Intel Corporation INTEL82802AC, INTEL82802AB Datasheet

Intel® 82802AB/82802AC
Firmware Hub (FWH)

Datasheet

November 2000

Document Number: 290658-004

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Intel® 82802AB/AC Firmware Hub

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2 Datasheet

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Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel

®

82802AB/AC Firmware Hub (FWH) may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

I

2

C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations

of the I

2

C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.

A

lert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

Intel Corporation

www.intel.com

or call 1-800-548-4725

*Third-party brands and names are the property of their respective owners.

Copyright © Intel Corporation 1999-2001

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Datasheet 3

Contents

1.

Architectural Overview ................................................................................................................. 9

1.1. Interface Overview........................................................................................................... 9

1.1.1. Intel Firmware Hub Interface....................................................................... 10

1.1.2. Address/Address-Multiplexed Interface ...................................................... 10

1.2. Nonvolatile Flash Memory Core .................................................................................... 10

2. Pinout Configurations ................................................................................................................. 13

2.1. Pin Descriptions............................................................................................................. 14

3. Interface Operation Description .................................................................................................17

3.1. Read 17

3.2. Write 17

3.3. Output Disable............................................................................................................... 17

3.4. Reset 17

3.5. Operational Effects of Hardware Write-Protect Pins TBL# and WP# ........................... 18

4. Functional Descriptions .............................................................................................................. 19

4.1. Read Array Command................................................................................................... 21

4.2. Read Identifier Codes Command.................................................................................. 21

4.3. Read Status Register Command................................................................................... 21

4.4. Clear Status Register Command................................................................................... 21

4.5. Block Erase Command ................................................................................................. 22

4.6. Program Command....................................................................................................... 22

4.7. Block Erase Suspend Command .................................................................................. 23

4.8. Program Suspend Comand ........................................................................................... 23

4.9. Register Based Locking, General-Purpose Input, and Random Number Generator
Registers 23

4.9.1. T_BLOCK_LK and T_MINUSxx_LK — Block-Locking Registers ............... 25

4.9.2. General-Purpose Input Register ................................................................. 26

4.9.2.1. GPI_REG — General-Purpose Input Register ............................... 26

4.9.3. Random Number Generator Registers ....................................................... 27

4.9.3.1. RNG Hardware Status Register ..................................................... 27

4.9.3.2. RNG Data Status Register ............................................................. 27

4.9.3.3. RNG Data Register......................................................................... 28

4.10. Using the Random Number Generator ......................................................................... 28

4.11. Detecting and Initializing the RNG Device..................................................................... 28

4.11.1. Detecting the RNG Device .......................................................................... 28

4.11.2. Initializing the RNG Device.......................................................................... 29

4.11.3. Selecting Appropriate FWH IDs and Densities ........................................... 29

4.11.4. Mapping FWH Devices onto Memory Map ................................................. 30

4.11.5. Paging FWH Devices for Greater Than 4 MB of FWH Memory ................. 30

4.11.6. Programming Multiple FWH Devices .......................................................... 30

4.12. CUI Automation Flowcharts........................................................................................... 31

5. Electrical Specifications ............................................................................................................. 33

5.1. Absolute Maximum Ratings........................................................................................... 33

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5.2.

Operating Conditions .....................................................................................................33

5.2.1. Interface DC Input/Output Specifications ....................................................34

5.2.2. Interface AC Input/Output Specifications.....................................................36

5.2.3. Intel FWH Interface AC Timing Specifications ............................................37

5.2.3.1. Clock Specification.......................................................................... 37

5.2.3.2. Signal Timing Parameters...............................................................38

5.3. Block Programming Times ............................................................................................40

5.4. Intel Firmware Hub Interface..........................................................................................40

5.4.1. Intel FWH Interface Cycles.......................................................................... 40

5.4.1.1. Read Cycle Sequence.....................................................................40

5.4.1.2. Single-Byte Read Waveforms.........................................................42

5.4.1.3. Write Cycle Sequence..................................................................... 42

5.4.1.4. Write W aveforms ............................................................................43

5.4.1.5. Response To Invalid Fields............................................................. 43

5.4.1.6. Abort Operations .............................................................................44

5.4.1.7. Intel FWH Cycle Timing Information ...............................................44

5.5. RNG Parameters ...........................................................................................................45

6. PROM Programming Specifications ........................................................................................... 47

6.1. Programming (“A/A Mux”) Mode Operation ...................................................................47

6.2. Bus Operation ................................................................................................................47

6.2.1. Output Disable/Enable.................................................................................47

6.2.2. Row/Column Addresses ..............................................................................47

6.2.3. Read Operation ...........................................................................................47

6.2.4. Read Identifier Codes Operation .................................................................48

6.2.5. Write Operation ...........................................................................................48

6.3. Command Definitions .................................................................................................... 48

6.4. Electrical Characteristics in A/A Mux Mode ...................................................................48

6.4.1. Reset Operations......................................................................................... 49

6.4.2. AC Waveforms for Reset Operations .......................................................... 49

6.4.3. A/A Mux Read-Only Operations

(1,3)

.............................................................49

6.4.4. A/A Mux Write Operations

(1,2)

.....................................................................51

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Datasheet 5

Figures

Figure 1. Simplified Block Diagram ..................................................................................... 8

Figure 2. Device Memory Map with Intel FWH Hardware Lock Architecture .................... 11

Figure 3. Intel FWH Boot-Configuration System Memory Map......................................... 11

Figure 4. 32-Lead PLCC Intel Firmware Hub Pinout......................................................... 13

Figure 5. 40-Lead TSOP Intel Firmware Hub Pinout ........................................................ 13

Figure 6. Automated Block Erase Flowchart..................................................................... 31

Figure 7. Clock Waveform ................................................................................................ 37

Figure 8. Output Timing Parameters................................................................................. 38

Figure 9. Input Timing Parameters ................................................................................... 39

Figure 10. FWH Single-Byte Read Waveforms .................................................................. 42

Figure 11. Write Waveforms ............................................................................................... 43

Figure 12. Intel FWH Output Timing Parameters ............................................................... 45

Figure 13. Intel FWH Input Timing Parameters .................................................................. 46

Figure 14. A/A Mux Read Timing Diagram ......................................................................... 50

Figure 15. A/A Mux Write Timing Diagram ......................................................................... 52

Tables

Table 1. Pin Descriptions ................................................................................................. 14

Table 2. Command Definitions......................................................................................... 19

Table 3. Status Register Definition .................................................................................. 20

Table 4. Identifier Codes.................................................................................................. 21

Table 5. Intel Firmware Hub Register Configuration Map................................................ 24

Table 6. Register-Based Locking Value Definitions......................................................... 25

Table 7. Temperature and VCC....................................................................................... 33

Table 8. Intel FWH Interface DC Input/Output Specifications.......................................... 34

Table 9. Power Supply Specifications — All Interfaces ................................................... 35

Table 10. Intel FWH Interface AC Input/Output Specifications.......................................... 36

Table 11. Clock Specification............................................................................................. 37

Table 12. Signal Timing Parameters.................................................................................. 38

Table 13. Interface Measurement Condition Parameters .................................................. 39

Table 14. AC Waveform for Reset Operation.................................................................... 39

Table 15. Programming Times .......................................................................................... 40

Table 16. FWH Read Cycle ............................................................................................... 41

Table 17. FWH Write Cycle ............................................................................................... 42

Table 18. Signal Timing Parameters.................................................................................. 44

Table 19. RNG Timing Characteristics .............................................................................. 45

Table 20. RNG Statistical Characteristics.......................................................................... 45

Table 21. Bus Operations .................................................................................................. 48

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Revision History

Rev. Draft/Changes Date

-001 • Initial Release April 1999

-002 • Added Chapter 6

• Updated programmer vendor/service provider information.

May 1999

-003 • Changed VIH min. spec to reflect actual value.

• Updated programmer vendor/service provider information.

• Clarification of part numbering.

• Spec now includes all known issues from all densities/lithographies.

• Included FWH memory cycle and RNG information.

May 2000

-004 • Removed All references to multi-byte read cycles

• Added DC Characteristics for A/A Mux mode

November 2000

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Datasheet 7

Intel® 82802AB/AC Firmware Hub
(FWH)

Product Features

§

Intel platform compatability

 Enables security-enhanced platform

infrastructure; facilitates option to remove ISA.

§

Firmware hub hardware interface mode

 5-Signal communication interface supporting

byte-at-a-time reads and writes

 Register-based read and write protection for

each code/data storage block

 Hardware write protect pins for the top boot

block and the remaining code/data storage
blocks

 5 Additional GPIs for platform design

flexibility

 Contains a hardware Random Number

Generator (RNG) for enhancing platform
security

 Integrated Command User Interface (CUI) for

requesting access to locking, programming, and
erasing options. The CUI also handles requests
for data residing in status, ID, and block-lock
registers.

 Operates with 33-MHz PCI clock and

3.3 V I/O.

§

Industry-standard packages
(40L TSOP or 32L PLCC)

§

Two configurable interfaces

 Firmware hub interface for platform

operation

 Address/Address-Multiplexed (A/A Mux)

interface for programming during
manufacturing

§

4 or 8 Mbits of flash memory for platform
code/data nonvolatile storage

 Symmetrically blocked, 64-KB memory

sections

 Available in 8-Mbit (Intel

®

82802AC) and 4-

Mbit (Intel

®

82802AB) densities

 Automated byte program and block erase via

an integrated Write State Machine (WSM)

§

Address/Address-Multiplexed (A/A Mux)
interface/mode

 11-Pin multiplexed address and 8-pin data

I/O interface

 Supports fast on-board or out-of-system

programming for manufacturing

§

Case temprature operating range

§

Power supply specifications

 Vcc: 3.3 V ± 0.3 V
 Vpp: 3.3 V and 12 V for fast programming,

(80 hours maximum)

The Intel® 82802 (FWH) firmware hub may contain design defects or errors known as errata that may cause the products to
deviate from published specifications. Current characterized errata are available upon request.

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8 Datasheet

Figure 1. Simplified Block Diagram

Processor

AC’97 Codec(s)

(optional)

LPC Interface

PCI Agent

PCI Bus

PCI Slot

Super I/O

Keyboard,

Mouse, FD,

PP, SP, IR

Memory

IDE (4 drives)

SMBus

IDE

AC’97

USB

SMBus Device(s)

GPIO

Memory

Controller

I/O

Controller

82802

ISA Bridge

(optional)

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Datasheet 9

1. Architectural Overview

The Intel

®

82802 Firmware Hub (FWH) discrete component is compatible with several Intel chipset
platforms and a variety of applications. The device operates under the LPC/FWH interface/protocol. The
hardware features of this device include a Random Number Generator (RNG), five General-Purpose
Inputs (GPIs), register-based block locking, and hardware-based locking. This combination of logic
features and non-volatile memory enables better protection for the storage and update of platform code
and data, adds platform flexibility through additional GPIs, and allows for quicker introduction of new
security/manageability features into current and future platforms. The platform RNG, accessed through
the Intel

®

Security Driver and third-party software, enables security features for the PC platform. See the

product features listed previously for a list of more key features that the Intel FWH provides.

1.1. Interface Overview

This device is equipped with two hardware interfaces. The state of the device’s “IC”
(InterfaceConfiguration) pin determines which interface is in use. The interface mode must be selected
prior topower-up or before return from reset (RST# or INIT# low-to-high transition). The Intel FWH
interface isdesigned to work with the Intel

family of I/O Controller Hubs (ICH) during platform
operation. The A/A Mux interface is designed as a programming interface for OEMs, for use during
motherboard manufacturing or component pre-programming. The A/A Mux interface is not intended for
use during regular personal computer operation. Such a configuration would cause the expected (Intel
FWH) interface to be disabled, and the system boot sequence would fail upon power-up.

An internal Command User Interface (CUI) serves as the internal control center for the
nonvolatilememory core in either of the two device interfaces (Intel FWH or A/A Mux). A single valid
commandsequence written to the CUI initiates an automated sequence of internal events to complete
various tasks. An internal Write State Machine (WSM) automatically executes the algorithms and
timings necessary for block erase and program operations.

Driving RST# or INIT# low resets the device, which resets the block-lock registers to their default
(write-locked) condition and clears the status register. A reset time (tPHQV A/A Mux) is required from
RST# or INIT# switching high until outputs are valid. Likewise, the device has a wake time (tPHRH A/A
Mux) from RST# or INIT# high until writes to the CUI are recognized. A reset latency will occur if a
reset procedure is performed during a programming or erase operation. Resetting the component will put
the component back into read-array mode.

Note: There is no chip enable (like CE#) in either interface. Stand-by current control in the Inel FWH interface

is enabled automatically, if the Intel FWH4 is high and the device is not working to complete a requested
activity.

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1.1.1. Intel Firmware Hub Interface

The Intel Firmware Hub (Intel FWH) interface consists primarily of a 5-signal communication interface
used to control the operation of the device in a system environment. The buffers for this interface were
designed to be PCI compliant. To ensure the effective delivery of security and manageability features, the
Intel FWH interface is the only way access the full feature set of the device. The Intel FWH interface is
equipped to operate at 33 MHz, synchronous with the PCI bus.

1.1.2. Address/Address-Multiplexed Interface

The A/A Mux refers to the multiplexed row and column addresses in this interface. This approach is
required so that the device can be tested and programmed quickly with automated test equipment (ATE)
or off-board PROM programmers in the OEM’s manufacturing flow. This interface also allows the
device to have an efficient programming interface with potentially large future densities, while still fitting
into a 32-pin package. Only basic reads, programming, and erasure of the nonvolatile memory blocks can
be performed through the A/A Mux interface. In this mode, the Intel FWH features, security features, and
registers are unavailable. A row/column (R/C#) pin determines which set of addresses (rows or columns)
is latched. See the A/A Mux pin description table for more information.

1.2. Nonvolatile Flash Memory Core

The primary feature of the Intel FWH component is a nonvolatile memory core based on Intel® Flash
Technology. This high-performance memory array is arranged in eight (4-Mbit device) or sixteen (8­Mbit device) 64-KB blocks.

Intel

®

Flash Technology enables fast factory programming and low-power designs. Specifically designed

for 3-V systems, this component supports read operations at 3.3 V V

CC

and block erase and program

operations at 3.3 V and 12 V V

PP

. The 12 V VPP option yields the fastest program performance, which
will increase factory throughput, but is not recommended for standard in-system FWH operation in the
platform, due to an 80-hr limit for 12 V on the V

PP

pin over the lifetime of the device, whether or not

programming is taking place. With the 3.3-V V

PP

option (recommended for in-system operation), VCC

and V

PP

may be tied together for a simple, low-power 3-V design. In addition to the voltage flexibility,

the dedicated V

PP

pin provides complete data protection when VPP ≤≤≤≤ V

PPLK

. Internal VPP detection
circuitry automatically configures the device for block erase and program operations. While current for
12-V programming will be drawn from V

PP

, 3.3-V programming solutions should design their board such

that V

PP

draws from the same supply as VCC, and should assume that full programming current may be

drawn from either pin.

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Datasheet 11

Figure 2. Device Memory Map with Intel FWH Hardware Lock Architecture

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

64-Kbyte Block

64-Kbyte Block

64-Kbyte Block

64-Kbyte Block

64-Kbyte Block

64-Kbyte Block

64-Kbyte Block

64-Kbyte Block

64-Kbyte Block

64-Kbyte Block

64-Kbyte Block

64-Kbyte Block

64-Kbyte Block

64-Kbyte Block

64-Kbyte Block

64-Kbyte Block

}

TBL# (8 Mb)

}

TBL# (4 Mb)

WP# (8 Mb)

Blocks 0-14

WP# (4 Mb)

mem_map_lock

0FFFFF

0F0000

0EFFFF

0E0000

0DFFFF

0D0000

0CFFFF

0C0000

0BFFFF

0B0000

0AFFFF

0A0000

09FFFF

090000

08FFFF

080000

07FFFF

070000

06FFFF

060000

05FFFF

050000

04FFFF

040000

03FFFF

030000

02FFFF

020000

01FFFF

010000

00FFFF

000000

Figure 3. Intel FWH Boot-Configuration System Memory Map

Sys_memmap_b oot

System Memory

(Top 4 MB)

FFF80000h

FFFFFFFFh

FFF00000h

FFC00000h

FWH

4 Mbit

FWH

8 Mbit

Block 7

Block0

Block 15

Block 0

Range for other

FWH devices

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This page is intentionally left blank.

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Datasheet 13

2. Pinout Configurations

Figure 4. 32-Lead PLCC Intel Firmware Hub Pinout

IntelFirmware Hub

(IntelFWH)

32-Lead PLCC

0.450" x 0.550"
Top View

RST# VPP

32 31 30

29

28

27

26

25

24

23

22

21

201917 18

123

4

5

6

7

8

9

10

11

12

13

141615

CLKVCC

FWH2 GND FWH3FWH1

FWH0

ID0

ID1

ID2

ID3

FGPI2 FGPI3 FGPI4

RFU RFU RFU

FGPI1

FGPI0

WP#

TBL#

A/A

Mux

A/A
Mu

x

A/A

Mu

x

A/A

Mux

WE#

IC(V

IH

)

DQ7

RY/BY#

OE#

GNDa

VCCa

GND

VCC

A5

VPP

A6

A4

VCC

DQ2 GND DQ3 DQ6DQ1 DQ5DQ4

DQ0

R/C#RST# A10A9A8

A7

A3

A2

A1

A0

FWH4

RFU

GNDa

GND

VCCa

IC (V

IL

)

INIT#

VCC

RFU

Figure 5. 40-Lead TSOP Intel Firmware Hub Pinout

RST#

NC

NC
NC

NC
NC

VCC

VPP

VCCa
FWH4

INIT#

GND
GND

RFU

RFU

RFU

ID0
ID1
ID2
ID3

FWH2

FWH3

FWH1
FWH0

VCC

RFU

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21

22

23

24

25

26

27

28

29

30

31

32

40
39
38
37
36
35
34
33

NC

Firmware Hub (FWH)

40-LEAD TSOP

10mm x 20mm

TOP VIEW

CLK

NC

WP#

TBL#

FGPI4

IC (V

IL

)

GNDa

NC

RFU

WE#

NC

NC

NC

IC (V

IH

)

NC

NC

A10

NC

NC

A9

A8

A7

A6

A5

A4

VCC

VPP

VCCa

RST#

OE#

RY/BY#

GND

GND

DQ6

DQ7

DQ5

A0

A1

A2

A3

DQ2

DQ3

DQ1

DQ0

GNDa

VCC

DQ4

NC

R/C#

A/A Mux A/A Mux

FGPI0

FGPI1

FGPI2

FGPI3

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14 Datasheet

2.1. Pin Descriptions

The pin descriptions table details the usage of each device pin. Most pins have dual functionality, with
functions in both the Intel Firmware Hub and A/A Mux interfaces. The A/A Mux functionality for pins is
shown bold italic in the description box for that pin. All pins are designed to be compliant with
VCC + 0.3 V max. unless otherwise noted.

Table 1. Pin Descriptions

Interface Symbol Type

Intel
FWH

A/A M ux

Name and Function

IC I X X Interface Configuration Pin. This pin determines which interface is

used to communicate with the device. When it is held low, the Intel
FWH interface is enabled. When it is held High, the A/A Mux
interface is enabled. This pin must be set at power-up or before
return from reset, and must not be changed during device operation.
This pin is pulled down with an internal resistor of between 20 and
100 kΩ. When the IC is High (A/A Mux mode), this pin will exhibit a
leakage current of approximately 200 µA. This pin may be floated,
which will select the Intel FWH mode.

RST# I X X Interface Reset. Valid for both A/A Mux and Intel FWH interface

operation. When driven low, RST# inhibits write operations to
provide data protection during power transitions, resets internal
automation, and tri-states pins FWH[3:0] (in Intel FWH interface
mode). RST#-high enables normal operation. When exiting from
reset, the device defaults to read array mode.

INIT# I X Processor Reset. This is a second reset pin for in-system use. This

pin is internally combined with the RST# pin. If this pin or RST# is
driven low, identical operation is exhibited. This signal is designed to
be connected to the chipset INIT signal (Max. voltage depends on
the processor. Do not use 3.3 V).

A/A Mux = OE#

CLK I X 33-MHz Clock for Intel FWH Interface. This input is the same as

that for the PCI clock and adheres to the PCI specification.

A/A Mux = R/C#

FWH[3:0] I/O X Intel FWH I/Os. I/O communication

A/A Mux = DQ[3:0]

FWH4 I X Intel FWH Input. Input communication

A/A Mux = WE#

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Datasheet 15

Interface Symbol Type

Intel

FWH

A/A M ux

Name and Function

ID[3:0] I X Identification Inputs. These four pins are part of the mechanism

that allows multiple parts to be attached to the same bus. The
strapping of these pins is used to identify the component. The boot
device must have ID[3:0] = 0000, and it is recommended that all
subsequent devices use sequential up-count strapping (

0001,

0010,0011,...

). These pins are pulled down with internal resistors, with
values between 20 and 100 kΩ, when in the Intel FW H mode. Any
ID pins pulled high will exhibit a leakage current of approximately
200 µA. Any pins intended to be low may be left to float. In a single
Intel FWH system, all may be left floating.

A/A Mux = A[3:0]

FGPI[4:0] I X

Intel FWH General Purpose Inputs. These individual inputs can be
used for additional board flexibility. The state of these pins can be
read immediately at boot, through Intel FWH registers. These inputs
should be at their desired state before the start of the PCI clock
cycle during which the read is attempted, and they should remain at
the same level until the end of the read cycle. They may only be
used for 3.3-V signals. Unused FGPI pins must not be floated.

A/A Mux = A[10:6]

TBL# I X

Top Block Lock. When low, it prevents programming or block erase
to the highest addressable block (7 in a 4-Mbit, 15 in an 8-Mbit
component), regardless of the state of the lock register. TBL#-high
disables hardware write protection for the top block, though register­based protection still applies. The status of TBL# does not affect the
status of block-locking registers.

A/A Mux = A4

WP# I X

Write Protect. When low, prevents programming or block erase to
all but the highest addressable block (0-6 in a 4-Mbit, 0-14 in an 8­Mbit component), regardless of the state of the corresponding lock
registers. WP#-high disables hardware write protection for these
blocks, though register-based protection still applies. The status of
TBL# does not affect the status of block-locking registers.

A/A Mux = A5

A[0:10] I X

Low-Order Address Inputs. Inputs for low-order addresses during
read and write operations. Addresses are internally latched during a
write cycle. For the A/A Mux interface, these addresses are latched
by R/C# and share the same pins as the high-order address inputs.

DQ[0:7] I/O X

Data Input/Outputs. These pins receive data and commands during
CUI write cycles and transmit data during memory array, status
register, and identifier code read cycles. Data pins float to high
impedance when outputs are disabled. Data is internally latched
during a write cycle.

OE# I X Output Enable. Gates the device’s outputs during a read cycle

R/C# I X

Row-Column Address Select. For the A/A Mux interface, this pin
determines whether the address pins are pointing to the row
addresses (A[0:10]) or the column addresses (A[11:19]).

WE# I X

Write Enable. Controls writes to the CUI and array blocks.
Addresses and data are latched on the rising edge of the WE#
pulse.

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16 Datasheet

Interface Symbol Type

Intel
FWH

A/A M ux

Name and Function

VPP PWR X X

Block Erase/Program Power Supply. For erasing array blocks or
programming data. V

PP

= 3.3 V or 12 V VPP. With VPP ≤ V

PPLK

,
memory contents cannot be altered. Attempting a block erase or
program with an invalid V

PP

(see DC Characteristics) will produce

spurious results and should not be attempted. V

PP

may only be held

at 12 V for 80 hours over the lifetime of the device.

VCC PWR X X

Device Power Supply. Internal detection automatically configures
the device for optimized read performance. Do not float any power
pins. With V

CC

≤ V

LKO

, all attempts to write to flash memory are

inhibited. Device operations at invalid V

CC

voltages (see DC
Characteristics) produce spurious results and should not be
attempted.

GND PWR X X Ground. Do not float any ground pins.

VCCa PWR X X

Analog Power Supply. This supply should share the same system
supply as V

CC

.

GNDa PWR X X Analog Ground. Should be tied to same plane as GND.

RFU X

Reserved For Future Use. These pins are reserved for future
generations of this product. They may be left disconnected or driven.
If they are driven, the voltage levels should satisfy V

IH

and VIL

requirements.

A/A M ux = D Q[ 7: 4]

NC X X

No Connect. Pin may be driven or floated. If it is driven, the voltage
levels should satisfy VIH and VIL. No connects appear only on the
40ld TSOP package.

Ry/By# 0 X

Ready/Busy. Valid only in A/A Mux Mode. This output pin is a
reflection of bit 7 in the Status Register. This pin is used to
determine block erase or program completion.