Intel Corporation GT28F160B3-B120 Datasheet
E
SMART 3 ADVANCED BOOT BLOCK
4-MBIT (256K X 16), 8-MBIT (512K X 16),
16-MBIT (1024K X 16)
FLASH MEMORY FAMILY
n
Flexible SmartVoltage Technology
2.7V–3.6V Program/Erase
2.7V–3.6V Read Operation
12V VPP Fast Production
Programming
n
2.7V or 1.8V I/O Option
Reduces Overall System Power
n
Optimized Block Sizes
Eight 4-KW Blocks for Data,
Top or Bottom Locations
Up to Thirty-One 32-KW Blocks for
Code
n
High Performance
2.7V–3.6V: 120 ns Max Access Time
n
Block Locking
VCC-Level Control through WP#
n
Low Power Consumption
20 mA Maximum Read Current
n
Absolute Hardware-Protection
VPP = GND Option
VCC Lockout Voltage
n
Extended Temperature Operation
–40°C to +85°C
WORD-WIDE
28F400B3, 28F800B3, 28F160B3
n
Supports Code Plus Data Storage
Optimized for FDI, Flash Data
Integrator Software
Fast Program Suspend Capability
Fast Erase Suspend Capability
n
Extended Cycling Capability
10,000 Block Erase Cycles
n
Automated Word Program and Block
Erase
Command User Interface
Status Registers
n
SRAM-Compatible Write Interface
n
Automatic Power Savings Feature
n
Reset/Deep Power-Down
1 µA ICCTypical
Spurious Write Lockout
n
Standard Surface Mount Packaging
48-Ball µBGA* Package
48-Lead TSOP Package
n
Footprint Upgradeable
Upgradeable from 2-, 4- and 8-Mbit
Boot Block
n
ETOX™ V (0.4 µ) Flash Technology
PRELIMINARY
The new Smart 3 Advanced Boot B lock , m anufac tured on I ntel’ s l ates t 0. 4µ tec hnology, represent s a feat urerich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability
(2.7V read, program and erase) with high-speed, low-power operation. Several new features have been
added, including the ability to drive the I /O at 1.8V, which significantly reduces system active power and
interfaces to 1.8V cont rollers. A new bloc king schem e enables code and data s torage within a si ngle device.
Add to this the Intel-dev eloped Flash Data Integrator (FDI) software and you hav e the most cost-effect ive,
monolithic code plus dat a storage solution on the market today . Smart 3 Advanced Boot B lock Word-Wide
products will be available in 48-lead TSOP and 48-ball µBGA* packages. Additional information on this
product family can be obtained by accessing Intel’s WWW page: http://www.intel.com/design/flcomp.
May 1997 Order Number: 290580-002
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
y
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F400B3, 28F800B3, 28F160B3 may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
or visit Intel’s website at http:\\www.intel.com
COPYRIGHT © INTEL CORPORATION 1996, 1997 CG-041493
*Third-part
brands and names are the property of their respective owners
E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE
CONTENTS
PAGE PAGE
1.0 INTRODUCTION .............................................5
1.1 Smart 3 Advanced Boot Block Flash
Memory Enhancements ..............................5
1.2 Product Overview.........................................6
2.0 PRODUCT DESCRIPTION..............................6
2.1 Package Pinouts..........................................7
2.2 Block Organization.....................................11
2.2.1 Parameter Blocks................................11
2.2.2 Main Blocks.........................................11
3.0 PRINCIPLES OF OPERATION .....................14
3.1 Bus Operation............................................14
3.1.1 Read....................................................15
3.1.2. Output Disable....................................15
3.1.3 Standby...............................................15
3.1.4 Deep Power-Down / Reset..................15
3.1.5 Write....................................................15
3.2 Modes of Operation....................................15
3.2.1 Read Array..........................................16
3.2.2 Read Intelligent Identifier.....................17
3.2.3 Read Status Register ..........................17
3.2.4 Program Mode.....................................18
3.2.5 Erase Mode.........................................19
3.3 Block Locking.............................................26
3.3.1 V
3.3.2 WP# = V
3.3.3 WP# = V
3.4 V
= VIL for Complete Protection .......26
PP
for Block Locking................26
IL
for Block Unlocking............26
IH
Program and Erase Voltages ..............26
PP
3.5 Power Consumption...................................26
3.5.1 Active Power .......................................26
3.5.2 Automatic Power Savings (APS) .........27
3.5.3 Standby Power....................................27
3.5.4 Deep Power-Down Mode.....................27
3.6 Power-Up/Down Operation.........................27
3.6.1 RP# Connected to System Reset ........27
3.6.2 V
3.7 Power Supply Decoupling ..........................28
3.7.1 V
4.0 ABSOLUTE MAXIMUM RATINGS................29
5.0 OPERATING CONDITIONS (V
3.6V).............................................................29
5.1 DC Characteristics: V
6.0 OPERATING CONDITIONS (V
2.2V).............................................................34
6.1 DC Characteristics: V
7.0 AC CHARACTERISTICS...............................39
7.1 Reset Operations .......................................43
APPENDIX A: Ordering Information .................45
APPENDIX B: Write State Machine
Current/Next States.....................................46
APPENDIX C: Access Speed vs. Capacitive
Load.............................................................47
APPENDIX D: Architecture Block Diagram ......48
APPENDIX E: Additional Information ...............49
, VPP and RP# Transitions.............27
CC
Trace On Printed Circuit Boards ...28
PP
= 2.7V–
CCQ
= 2.7V–3.6V.......30
CCQ
= 1.8V–
CCQ
= 1.8V–2.2V.......34
CCQ
PRELIMINARY
3
SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E
REVISION HISTORY
Number Description
-001 Original version
-002 Section 3.4,
Updated Figure 9: Automated Block Erase Flowchart
Updated Figure 10: Erase Suspend/Resume Flowchart (added program op. to table)
Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes)
maximum specification change from ±25 µA to ±50 µA
I
PPR
Program and Erase Suspend Latency specification change
Updated Appendix A: Ordering Information (included 8M and 4M information)
Updated Figure, Appendix D: Architecture Block Diagram (Block info. in Words not
bytes)
Minor wording changes
VPP Program and Erase Voltages
, added
4
PRELIMINARY
E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE
1.0 INTRODUCTION
This preliminary datasheet contains the
specifications for the Advanced Boot Block flash
memory family, which is optimized for low power,
portable systems. This family of products features
1.8V–2.2V or 2.7V–3.6V I /Os and a low V
operating range of 2.7V–3.6V for read and
program/erase operations. In addit ion thi s fam ily i s
capable of fast programming at 12V. Throughout
this document, the term “2.7V” refers to the full
voltage range 2.7V–3.6V (except where noted
otherwise) and “V
Section 1 and 2 provides an overv iew of the flash
memory family incl uding applications, pinouts and
pin descriptions. Section 3 desc ribes the memory
organization and operation for these products.
Finally, Sections 4, 5, 6 and 7 contain the
operating specifications.
= 12V” refers to 12V ±5%.
PP
CC/VPP
1.1 Smart 3 Advanced Boot Block Flash Memory Enhancements
The new 4-Mbit, 8-Mbit, and 16-Mbit Smart 3
Advanced Boot Block flash memory provides a
Table 1. Smart 3 Advanced Boot Block Feature Summary
Feature 28F160B3 Reference
VCC Read Voltage 2.7V– 3.6V Table 9, Table 12
V
I/O Voltage 1.8V–2.2V or 2.7V– 3.6V Table 9, Table 12
CCQ
VPP Program/Erase Voltage 2.7V– 3.6V or 11.4V– 12.6V Table 9, Table 12
Bus Width 16 bit Table 2
Speed 120 ns Table 15
Memory Arrangement 256-Kbit x 16 (4-Mbit), 512-Kbit x 16 (8-Mbit),
Blocking (top or bottom) Eight 4-Kword parameter blocks (4/8/16) &
Locking WP# locks/unlocks parameter blocks
Operating Temperature Extended: –40°C to +85°C Table 9, Table 12
Program/Erase Cycling 10,000 cycles Table 9, Table 12
Packages 48-Lead TSOP, 48-Ball µBGA* CSP Figures 1, 2, 3,
1024-Kbit x 16 (16-Mbit)
Seven 32-Kword blocks (4-Mbit)
Fifteen 32-Kword blocks (8-Mbit)
Thirty-one 32-Kword main blocks (16-Mbit)
All other blocks protected using V
convenient upgrade from and/or compatibility to
previous 4-Mbit and 8-Mbit Boot Block products.
The Smart 3 product functi ons are s imilar t o lower
density products in both command sets and
operation, providing simil ar pi nouts to ease density
upgrades.
The Smart 3 Advanced Boot Block flash memory
features
• Enhanced blocking for easy segmentation of
code and data or additional design flexibility
• Program Suspend command which permits
program suspend to read
• WP# pin to lock and unlock t he upper two (or
lower two, depending on location) 4-Kword
blocks
• V
• Maximum program time specification for
input for 1.8V–2.2V on all I/Os. See
CCQ
Figure 1-4 for pinout diagrams and V
location
improved data storage.
Section 2.2
Figures 5 and 6
switch
PP
Section 3.3
Table 8
and 4
CCQ
PRELIMINARY
5
SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E
1.2 Product Overview
Intel provides the most flexible voltage solution in
the flash industry, providing three discrete volt age
supply pins: V
swing, and V
Discrete supply pins allow system designers to use
the optimal voltage lev els for t heir design. All Sm art
3 Advanced Boot Block flash memory products
provide program/erase capability at 2.7V or 12V
and read with V
read from the flash memory a l arge percentage of
the time, 2.7V V
substantial power savings. The 12V V
maximizes program and erase performanc e during
production programming.
The Smart 3 Advanced Boot Block flash memory
products are high-performance devices with low
power operation. The available densi ties for wordwide devices (x16) are
a. 4-Mbit (4,194,304-bit) flash memory
organized as 256-Kwords of 16 bits each
b. 8-Mbit (8,388,608-bit) flash memory
organized as 512-Kwords of 16 bits each
c. 16-Mbit (16,777,216-bit) flash memory
organized as 1024-Kwords of 16 bits each.
For byte-wide devices (x8) see the
Advanced Boot Block Byte-Wide Flash Memory
Family
datasheet.
The parameter blocks are located at either the top
(denoted by -T suffix) or the bot tom (-B suffix) of the
address map in order to accommodate different
microprocessor protocols for kernel code location.
The upper two (or lower two) parameter blocks can
be locked to provide complete code security for
system initialization code. Locking and unlocking is
controlled by WP# (see Section 3.3 for details).
The Command User Interface (CUI) s erves as the
interface between the microprocessor or
microcontroller and the internal operation of the
flash memory. The internal Write State Machine
(WSM) automatically executes the algorithms and
timings necessary for program and erase
operations, including verification, thereby
unburdening the microprocessor or microcontroller.
The status register indicates the status of the WSM
by signifying block erase or word program
completion and status.
for read operation, V
CC
for program and erase operation.
PP
at 2.7V. Since many designs
CC
operation can provide
CC
for output
CCQ
PP
option
Smart 3
Program and erase automation allows program and
erase operations to be executed using an indust rystandard two-write command sequence t o the CUI.
Data writes are performed in word increments.
Each word in the flash memory can be program m ed
independently of other memory locations; every
erase operation erases all locations within a bl ock
simultaneously. Program suspend allows system
software to suspend the program comm and in order
to read from any other block. Erase suspend allows
system software to suspend the block erase
command in order to read from or program data to
any other block.
The Smart 3 Advanced Boot B lock flas h memory is
also designed with an Automatic Power Savings
(APS) feature which minimizes system current
drain, allowing for very low power designs. This
mode is entered immediately following the
completion of a read cycle.
When the CE# and RP# pins are at V
CC
, the I
CC
CMOS standby mode is enabled. A deep powerdown mode is enabled when the RP# pin is at
GND, minimizing power consum ption and providing
write protection. I
1 µA typical (2.7V V
t
is required from RP# switching high until
PHQV
current in deep power-down is
CC
). A minimum reset time of
CC
outputs are valid to read attempts. With RP# at
GND, the WSM is reset and Status Register is
cleared. Section 3.5 c ontains additional inf ormation
on using the deep power-down feature, along wi th
other power consumption issues.
The RP# pin provides additional protection agai nst
unwanted command writes that may occur during
system reset and power-up/down sequences due to
invalid system bus conditions (see Section 3.6).
Refer to the DC Characteristi cs Table, Sec tions 5.1
and 6.1, for complete current and voltage
specifications. Refer to the AC Characteristics
Table, Section 7.0, for read, program and erase
performance specifications.
2.0 PRODUCT DESCRIPTION
This section explains device pin description and
package pinouts.
6
PRELIMINARY
E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE
2
2.1 Package Pinouts
The Smart 3 Advanced Boot B lock flas h memory is
available in 48-lead TSOP (see Figure 1) and 48ball µBGA packages (see Figures 2-4). In Figure 1,
pin changes from one density to the next are
circled. Both pack ages, 48-lead TSOP and 48-ball
*
µBGA
package, are 16-bits wide and fully
upgradeable across product densities (f rom 4 Mb to
16 Mb).
8F400B3
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
NC
NC
WE#
RP#
V
PP
WP#
NC
NC
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
28F800B3
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
NC
NC
WE#
RP#
VPPV
WP#
NC
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
A
A
A
A
A
A
A
NC
NC
WE#
RP#
WP#
A
A
A
A
A
A
A
A
A
A
28F400B328F800B3
A
16
V
CCQ
GND
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V
CC
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
OE#
GND
CE#
A
0
A
16
V
CCQ
GND
DQ
15
15
DQ
7
7
DQ
14
14
DQ
6
6
DQ
13
13
DQ
5
5
DQ
12
12
DQ
4
4
V
CC
DQ
11
11
DQ
3
3
DQ
10
10
DQ
2
2
DQ
9
9
DQ
1
1
DQ
8
8
DQ
0
0
OE#
GND
CE#
A
0
0580_01
A
15
14
13
12
11
10
9
8
PP
19
18
17
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
16-Mbit
Advanced Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
16
V
CCQ
GND
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V
CC
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
OE#
GND
CE#
A
0
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
Figure 1. 48-Lead TSOP Package
PRELIMINARY
7
SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E
1234 567 8
A
A
A
13
B
A
A
14
C
A
A
15
D
A
D
16
E
V
CCQ
D
A
11
WE# RP# NC A
10
12
14
15
V
8
PP
A
9
D
D
5
11
D
D
6
12
WP# NC A
17
A
6
D
D
2
8
D
D
3
9
7
A
5
A
3
CE# A
D
0
A
A
A
GND
4
2
1
0
GND D
F
D
7
D
V
13
4
D
CC
D
10
OE#
1
NOTE:
Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades.
Routing is not recommended in this area.
Figure 2. 4-Mbit 48-Ball µBGA* Chip Size Package
1234 567 8
A
A
A
13
B
A
A
14
C
A
A
15
D
A
D
16
E
V
GND D
F
CCQ
D
A
11
10
12
14
15
8
WE# RP# A
A
9
D
5
D
6
D
7
13
V
WP# NC A
PP
D
11
D
12
D
V
4
A
7
4
A
18
D
2
D
3
D
CC
A
D
D
17
6
8
9
10
A
5
A
3
CE# A
D
0
D
1
A
A
GND
OE#
2
1
0
NOTE:
Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades.
Routing is not recommended in this area.
Figure 3. 8-Mbit 48-Ball µBGA* Chip Size Package
8
PRELIMINARY
0580_02
0580_03
E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE
12345678
A
B
C
D
E
F
A
13
A
14
A
15
A
16
V
CCQ
GND D
A
11
A
WE# RP# A
10
A
12
D
D
D
14
D
15
D
7
A
V
D
D
D
PP
11
12
4
WP# A
18
D
2
D
3
V
CC
A
A
D
D
D
8
A
9
5
6
13
19
17
6
8
9
10
A
7
A
5
A
3
CE# A
D
0
D
1
A
A
A
GND
OE#
4
2
1
0
NOTE:
Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades.
Routing is not recommended in this area.
Figure 4. 16-Mbit 48-Ball µBGA* Chip Size Package
(Top View, Ball Down)
0580_04
PRELIMINARY
9
SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E
The pin descriptions table details the usage of each device pin.
Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions
Symbol Type Name and Function
A0–A
19
DQ0–DQ7INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
DQ8–DQ15INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
CE# INPUT CHIP ENABLE: Activates the internal control logic, input buffers,
OE# INPUT OUTPUT ENABLE: Enables the device’s outputs through the data
WE# INPUT WRITE ENABLE: Controls writes to the Command Register and memory
RP# INPUT RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to
WP# INPUT WRITE PROTECT: Provides a method for locking and unlocking the two
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a program or erase cycle.
28F400B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19]
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, Intelligent Identifier and Status Register
data. The data pins float to tri-state when the chip is de-selected or the
outputs are disabled.
WE# cycle during a Program command. Data is internally latched.
Outputs array and intelligent identifier data. The data pins float to tri-state
when the chip is de-selected.
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels. If
CE# and RP# are high, but not at a CMOS high level, the standby
current will increase due to current flow through the CE# and RP# inputs.
buffers during an array or status register read. OE# is active low.
array. WE# is active low. Addresses and data are latched on the rising
edge of the second WE# pulse.
control reset/deep power-down mode.
When RP# is at logic low, the device is in reset/deep power-down
mode, which drives the outputs to High-Z, resets the Write State
Machine, and draws minimum current.
When RP# is at logic high, the device is in standard operation.
When RP# transitions from logic-low to logic-high, the device defaults to
the read array mode.
lockable parameter blocks.
When WP# is at logic low, the lockable blocks are locked,
preventing program and erase operations to those blocks. If a program
or erase operation is attempted on a locked block, SR.1 and either SR.4
[program] or SR.5 [erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked and
can be programmed or erased.
See Section 3.3 for details on write protection.
10
PRELIMINARY
E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE
K
Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions (Continued)
Symbol Type Name and Function
VCCQ INPUT OUTPUT VCC: Enables all outputs to be driven to 2.0V ±10% while the
V
CC
V
PP
GND GROUND: For all internal circuitry. All ground inputs must be
NC NO CONNECT: Pin may be driven or left floating.
V
is at 2.7V. When this mode is used, the VCC should be regulated to
CC
2.7V–2.85V to achieve lowest power operation (see Section 6.1: DC
Characteristics: V
This input may be tied directly to V
See the DC Characteristics for further details.
DEVICE POWER SUPPLY: 2.7V–3.6V
PROGRAM/ERASE POWER SUPPLY: For erasing memory array
blocks or programming data in each block, a voltage of either 2.7V–3.6V
or 12V ± 5% must be applied to this pin. When V
are locked and protected against Program and Erase commands.
Applying 11.4V-12.6V to V
cycles on the main blocks and 2500 cycles on the parameter blocks.
V
may be connected to 12V for a total of 80 hours maximum (see
PP
Section 3.4 for details).
connected.
= 1.8V–2.2V).
CCQ
(2.7V–3.6V).
CC
< V
PP
can only be done for a maximum of 1000
PP
PPL
all blocks
2.2 Block Organization
The Smart 3 Advanced Boot Block is an
asymmetrically-blocked architecture that enables
system integration of code and data within a single
flash device. Each block can be erased
independently of the others up t o 10,000 times . For
the address locations of each block, see the
memory maps in Figure 5 (top boot blocking) and
Figure 6 (bottom boot blocking).
PRELIMINARY
2.2.1 PARAMETER BLOCKS
The Smart 3 Advanced Boot Block flash memory
architecture includes parameter blocks to facilitate
storage of frequently updated small parameters
(e.g., data that would normally be stored in an
EEPROM). By using software techniques, t he wordrewrite functionality of EEPROMs can be emulated.
Each 4-/8-/16-Mbit device contai ns eight parameter
blocks of 4-Kwords (4,096-words) each.
2.2.2 MAIN BLOCKS
After the parameter blocks, the remainder of the
array is divided into equal size main blocks for data
or code storage. Each 16-Mbit device contains
thirty-one 32-Kword (32,768-word) blocks. Each
8-Mbit device contains fifteen 32-Kword blocks.
Each 4-Mbit device contains seven 32-Kword
blocks.
11
SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E
16-Mbit Advanced Boot
FFFFF
FF000
FEFFF
FE000
FDFFF
FD000
FCFFF
FC000
FBFFF
FB000
FAFFF
FA000
F9FFF
F9000
F8FFF
F8000
F7FFF
F0000
EFFFF
E8000
E7FFF
E0000
DFFFF
D8000
D7FFF
D0000
CFFFF
C8000
C7FFF
C0000
BFFFF
B8000
B7000
B0000
AFFFF
A8000
A7FFF
A0000
9FFFF
98000
97FFF
90000
8FFFF
88000
87FFF
80000
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
8-Mbit Advanced Boot
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
7FFFF
7F000
7EFFF
7E000
7DFFF
7D000
7CFFF
7C000
7BFFF
7B000
7AFFF
7A000
79FFF
79000
78FFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
4-Mbit Advanced Boot
3FFFF
3F000
3EFFF
3E000
3DFFF
3D000
3CFFF
3C000
3BFFF
3B000
3AFFF
3A000
39FFF
39000
38FFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0580_05
12
Figure 5. 4-/8-/16-Mbit Advanced Boot Block Word-Wide Top Boot Memory Maps
PRELIMINARY
E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE
16-Mbit Advanced Boot
FFFFF
F8000
F7FFF
F0000
EFFFF
E8000
E7FFF
E0000
DFFFF
D8000
D7FFF
D0000
CFFFF
C8000
C7FFF
C0000
BFFFF
B8000
B7FFF
B0000
AFFFF
A8000
A7FFF
A0000
9FFFF
98000
97FFF
90000
8FFFF
88000
87FFF
80000
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
07000
06FFF
06000
05FFF
05000
04FFF
04000
03FFF
03000
02FFF
02000
01FFF
01000
00FFF
00000
Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
8-Mbit Advanced Boot
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
07000
06FFF
06000
05FFF
05000
04FFF
04000
03FFF
03000
02FFF
02000
01FFF
01000
00FFF
00000
Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
4-Mbit Advanced Boot
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
07000
06FFF
06000
05FFF
05000
04FFF
04000
03FFF
03000
02FFF
02000
01FFF
01000
00FFF
00000
Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
32-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
4-Kword Block
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0580_06
Figure 6. 4-/8-/16-Mbit Advanced Boot Block Word-Wide Top Boot Memory Maps
PRELIMINARY
13
SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E
3.0 PRINCIPLES OF OPERATION
Flash memory combines EEPROM functionality
with in-circuit electrical program and erase
capability. The Smart 3 Advanc ed Boot Block flash
memory family utilizes a Command User Interface
(CUI) and automated algorithms to s impli fy program
and erase operations. The CUI allows for 100%
CMOS-level control inputs, fixed power supplies
during erasure and programming, and maximum
EEPROM compatibility.
When V
following commands successfully: Read Array,
Read Status Register, Clear Status Register and
Read Intelligent Identifier. The device provides
standard EEPROM read, standby and output
disable operations. Manufac turer identification and
device identification data c an be accessed through
the CUI. In addition, 2.7V or 12V on V
program and erase of the device. All functions
Read 1,2,3 V
Output Disable 2 V
Standby 2 V
Deep Power-Down 2,9 V
Intelligent Identifier (Mfr.) 2,4 V
Intelligent Identifier (Dvc.) 2,4,5 V
Write 2,6,7,8V
< V
PP
, the device will only execute the
PPLK
allows
PP
Table 3. Bus Operations for Word-Wide Mode
Mode Notes RP# CE# OE# WE# WP# A0V
V
IH
V
IH
V
IH
X X X X X X High Z
IL
V
IH
V
IH
V
IH
associated with altering memory contents, namely
program and erase, are accessible via the CUI.
The internal Write State Mac hi ne (WS M) completely
automates program and erase operati ons while the
CUI signals the start of an operation and the stat us
register reports status . The CUI handles the WE#
interface to the data and address latches, as well
as system status requests during WSM operation.
3.1 Bus Operation
Smart 3 Advanced Boot Block flash memory
devices read, program and erase in-system via the
local CPU or microcontroller. All bus cycles to or
from the flash memory conform to standard
microcontroller bus cycles. Four control pins dictate
the data flow in and out of the flash component:
CE#, OE#, WE# and RP#. These bus operations
are summarized in Table 3.
V
IL
V
IL
IH
V
IL
V
IL
V
IL
V
IL
IH
IH
V
IH
XXXD
X X X High Z
X X X X X High Z
V
IL
IL
IH
IH
V
IH
V
IL
XVILX 0089 H
XVIHX See Table 5
XXV
PP
PPH
DQ
D
0–15
OUT
IN
NOTES:
1. Refer to DC Characteristics.
2. X must be V
3. See DC Characteristics for V
4. Manufacturer and device codes may also be accessed via a CUI write sequence, A
5. See Table 5 for device IDs.
6. Refer to Table 6 for valid D
7. Command writes for block erase or word program are only executed when V
8. To program or erase the lockable blocks, hold WP# at V
9. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.
, VIH for control pins and addresses, V
IL
, V
PPH1
, V
PPH2
PPLK
during a write operation.
IN
PPLK
voltages.
, V
or V
PPH1
PPH2
. See Section 3.3.
IH
for VPP.
PP
= V
1–A19
PPH1
14
= X
or V
.
PPH2
PRELIMINARY
E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE
3.1.1 READ
The flash memory has three read modes av ailable:
read array, read identifier, and read status. These
modes are accessible independent of the V
voltage. The appropriate read mode c om m and must
be issued to the CUI to enter the corresponding
mode. Upon initial device power-up or after exit
from deep power-down mode, the device
automatically defaults to read array mode.
CE# and OE# must be driven active to obtain dat a
at the outputs. CE# is the device s election control;
when active it enables the flash memory device.
OE# is the data output (DQ
drives the selected m emory data onto the I/O bus.
For all read modes, WE# and RP# must be at V
Figure 15 illustrates a read cycle.
3.1.2 OUTPUT DISABLE
With OE# at a logic-high level (V
outputs are disabled. Output pins DQ
placed in a high-impedance state.
3.1.3 STANDBY
Deselecting the device by bri nging CE# to a logichigh level (V
which substantially reduces device power
consumption. In standby, outputs DQ
placed in a high-impedance state independent of
OE#. If deselected during program or erase
operation, the device cont inues to consume active
power until the program or erase operation is
complete.
) places the device in standby mode,
IH
–DQ15) control and it
0
), the device
IH
–DQ15 are
0
–DQ
0
15
IH
are
After return from power-down, a time t
required until the initial mem ory access out puts are
valid. A delay (t
return from power-down before a write sequence
can be initiated. After this wake-up interval, normal
PP
operation is restored. The CUI resets t o read array
mode, and the status register is set to 80H (ready).
If RP# is taken low for time t
or erase operation, the operation will be aborted
and the memory contents at the aborted location
are no longer valid. After returni ng from an aborted
operation, time t
before a read or write operation is initiated
respectively.
.
3.1.5 WRITE
A write is any command t hat alters the content s of
the memory array. There are two write c ommands:
Program (40H) and Erase (20H). Writing either of
these commands to the internal Command User
Interface (CUI) initiates a sequence of internallytimed functions that culminate in the c ompletion of
the requested task (unless that operat ion is aborted
by either RP# being driven to V
appropriate suspend command).
The Command User Interface does not occupy an
addressable memory location. Instead, commands
are written into the CUI using standard
microprocessor write timings when WE# and CE#
are low, OE# = V
data (command) are presented. The command is
latched on the rising edge of the f irst WE# or CE#
pulse, whichever occurs first. Figure 16 illustrates a
write operation.
or t
PHWL
or t
PHQV
, and the proper address and
IH
) is required after
PHEL
during a program
PLPH
PHWL/tPHEL
IL
PHQV
must be met
for t
PLRH
is
or an
3.1.4 DEEP POWER-DOWN / RESET
RP# at V
sometimes referred to as reset mode.
From read mode, RP# going low for time t
accomplishes the following:
1. deselects the memory
2. places output drivers in a high-impedance
initiates the deep power-down mode,
IL
state
PLPH
PRELIMINARY
Device operations are selected by writing specific
commands into the CUI. Table 4 defines the
available commands. A ppendix B provides det ailed
information on moving between t he different modes
of operation.
3.2 Modes of Operation
The flash memory has three read modes and two
write modes. The read modes are read array, read
identifier, and read status. The write modes are
program and block erase. Three additional modes
15
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