Intel Corporation GT28F032B3BA95 Datasheet
E
PRELIMINARY
July 1998 Order Number: 290580-005
n
Flexible SmartVoltage Technology
2.7 V–3.6 V Read/Program/Erase
12 V VPP Fast Production
Programming
n
2.7 V or 1.65 V I/O Option
Reduces Overall System Power
n
High Performance
2.7 V–3.6 V: 90 ns Max Access Time
3.0 V–3.6 V: 80 ns Max Access Time
n
Optimized Block Sizes
Eight 8-KB Blocks for Data,
Top or Bottom Locations
Up to Sixty-Three 64-KB Blocks for
Code
n
Block Locking
VCC-Level Control through WP#
n
Low Power Consumption
10 mA Typical Read Current
n
Absolute Hardware-Protection
VPP = GND Option
VCC Lockout Voltage
n
Extended Temperature Operation
–40 °C to +85 °C
n
Flash Data Integrator Software
Flash Memory Manager
System Interrupt Manager
Supports Parameter Storage,
Streaming Data (e.g., Voice)
n
Automated Program and Block Erase
Status Registers
n
Extended Cycling Capability
Minimum 100,000 Block Erase
Cycles Guaranteed
n
Automatic Power Savings Feature
Typical I
CCS
after Bus Inactivity
n
Standard Surface Mount Packaging
48-Ball µBGA* Package
48-Lead TSOP Package
40-Lead TSOP Package
n
Footprint Upgradeable
Upgrade Path for 4-, 8-, 16-, and 32Mbit Densities
n
ETOX™ VI (0.25 µ) Flash Technology
The Smart 3 Advanced Boot Block, manuf actured on Intel’s latest 0. 25 µ technology, represents a featurerich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability
(2.7 V read, program and erase) with high-speed, low-power operation. Several new features have been
added, including the ability to drive the I/O at 1.65 V, which significantly reduces system active power and
interfaces to 1.65 V controllers. A new blocking scheme enables code and data storage within a single
device. Add to this t he Intel-developed Flash Data Integrat or (FDI) software, and you have a c ost-effective,
monolithic code plus data storage solution. Smart 3 Advanced Boot Block products will be available in 40lead and 48-lead TSOP and 48-ball µBGA* packages. Additional i nformation on this product family c an be
obtained by accessing Intel’s WWW page: http://www.intel.com/design/flash.
SMART 3 ADVANCED BOOT BLOCK
4-, 8-, 16-, 32-MBIT
FLASH MEMORY FAMILY
28F400B3, 28F800B3, 28F160B3, 28F320B3
28F008B3, 28F016B3, 28F032B3
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided i n Intel’s Terms and Conditi ons of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F400B3, 28F800/008B3, 28F160/016B3, 38F320/032B3 may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel’s Website at http://www.intel.com
COPYRIGHT © INTEL CORPORATION 1996, 1997,1998 CG-041493
*Third-part
y
brands and names are the property of their respective owners
E SMART 3 ADVANCED BOOT BLOCK
3
PRELIMINARY
CONTENTS
PAGE PAGE
1.0 INTRODUCTION .............................................5
1.1 Smart 3 Advanced Boot Block Flash
Memory Enhancements ..............................5
1.2 Product Overview.........................................6
2.0 PRODUCT DESCRIPTION..............................6
2.1 Package Pinouts..........................................6
2.2 Block Organization.....................................11
2.2.1 Parameter Blocks................................11
2.2.2 Main Blocks.........................................11
3.0 PRINCIPLES OF OPERATION .....................11
3.1 Bus Operation............................................12
3.1.1 Read....................................................13
3.1.2 Output Disable.....................................13
3.1.3 Standby...............................................13
3.1.4 Deep Power-Down / Reset..................13
3.1.5 Write....................................................13
3.2 Modes of Operation....................................14
3.2.1 Read Array..........................................14
3.2.2 Read Identifier.....................................15
3.2.3 Read Status Register ..........................16
3.2.4 Program Mode.....................................16
3.2.5 Erase Mode.........................................17
3.3 Block Locking.............................................20
3.3.1 WP# = V
IL
for Block Locking................20
3.3.2 WP# = V
IH
for Block Unlocking............20
3.4 V
PP
Program and Erase Voltages ..............20
3.4.1 V
PP
= VIL for Complete Protection .......20
3.5 Power Consumption...................................20
3.5.1 Active Power .......................................21
3.5.2 Automatic Power Savings (APS) .........21
3.5.3 Standby Power....................................21
3.5.4 Deep Power-Down Mode.....................21
3.6 Power-Up/Down Operation.........................21
3.6.1 RP# Connected to System Reset ........21
3.6.2 V
CC
, VPP and RP# Transitions.............21
3.7 Power Supply Decoupling ..........................22
4.0 ELECTRICAL SPECIFICATIONS..................23
4.1 Absolute Maximum Ratings........................23
4.2 Operating Conditions..................................24
4.3 Capacitance...............................................24
4.4 DC Characteristics .....................................25
4.5 AC Characteristics—Read Operations .......28
4.6 AC Characteristics—Write Operations........30
4.7 Program and Erase Timings.......................31
5.0 RESET OPERATIONS ..................................33
6.0 ORDERING INFORMATION..........................34
7.0 ADDITIONAL INFORMATION.......................36
APPENDIX A: Write State Machine
Current/Next States.....................................37
APPENDIX B: Access Time vs.
Capacitive Load...........................................38
APPENDIX C: Architecture Block Diagram ......39
APPENDIX D: Word-Wide Memory Map
Diagrams......................................................40
APPENDIX E: Byte Wide Memory Map
Diagrams......................................................43
APPENDIX F: Program and Erase Flowcharts.45
SMART 3 ADVANCED BOOT BLOCK E
4
PRELIMINARY
REVISION HISTORY
Number Description
-001 Original version
-002 Section 3.4,
VPP Program and Erase Voltages
, added
Updated Figure 9:
Automated Block Erase Flowchart
Updated Figure 10:
Erase Suspend/Resume Flowchart
(added program to table)
Updated Figure 16:
AC Waveform: Program and Erase Operations
(updated notes)
I
PPR
maximum specification change from ±25 µA to ±50 µA
Program and Erase Suspend Latency specification change
Updated Appendix A:
Ordering Information
(included 8 M and 4 M information)
Updated Figure, Appendix D:
Architecture Block Diagram
(Block info. in words not
bytes)
Minor wording changes
-003 Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V V
PP
read specification (Section 3.4)
Removed 120 ns and 150 ns speed offerings
Moved
Ordering Information
from Appendix to Section 6.0; updated information
Moved
Additional Information
from Appendix to Section 7.0
Updated figure Appendix B,
Access Time vs. Capacitive Load
Updated figure Appendix C,
Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated
Program Flowchart
Updated
Program Suspend/Resume Flowchart
Minor text edits throughout.
-004 Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A
1–A20
= 0 when in read identifier mode (Section 3.2.2)
Status register clarification for SR3 (Table 7)
V
CC
and V
CCQ
absolute maximum specification = 3.7 V (Section 4.1)
Combined I
PPW
and I
CCW
into one specification (Section 4.4)
Combined I
PPE
and I
CCE
into one specification (Section 4.4)
Max Parameter Block Erase Time (t
WHQV2/tEHQV2
) reduced to 4 sec (Section 4.7)
Max Main Block Erase Time (t
WHQV3/tEHQV3
) reduced to 5 sec (Section 4.7)
Erase suspend time @ 12 V (t
WHRH2/tEHRH2
) changed to 5 µs typical and 20 µs
maximum (Section 4.7)
Ordering Information
updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
-005 µBGA package diagrams corrected (Figures 3 and 4)
I
PPD
test conditions corrected (Section 4.4)
32-Mbit ordering information corrected (Section 6)
µBGA package top side mark information added (Section 6)
E SMART 3 ADVANCED BOOT BLOCK
5
PRELIMINARY
1.0 INTRODUCTION
This datasheet contains the specifications for the
Advanced Boot Block flas h mem ory fam ily , whic h is
optimized for low power, portable systems. This
family of products f eatures 1.65 V–2.5 V or 2.7 V–
3.6 V I/Os and a low V
CC/VPP
operating range of
2.7 V–3.6 V for read, program, and erase
operations. In addition this family is capable of fast
programming at 12 V. Throughout this document,
the term “2.7 V” refers to the full voltage range
2.7 V–3.6 V (except where noted otherwise) and
“V
PP
= 12 V” refers to 12 V ±5%. Section 1.0 and
2.0 provide an overview of the fl ash memory famil y
including applications, pinouts and pi n descriptions.
Section 3.0 describes t he mem ory organiz ation and
operation for these products. Sections 4.0 and 5.0
contain the operating specifications. Finally,
Sections 6.0 and 7.0 provide ordering and other
reference information.
1.1 Smart 3 Advanced Boot Block
Flash Memory Enhancements
The Smart 3 Advanced Boot Block flash memory
features
• Enhanced blocking for easy segmentation of
code and data or additional design flexibility
• Program Suspend to Read command
• V
CCQ
input of 1.65 V–2.5 V on all I/Os. See
Figures 1 through 4 for pinout diagrams and
V
CCQ
location
• Maximum program and erase time specifi cation
for improved data storage.
Table 1. Smart 3 Advanced Boot Block Feature Summary
Feature 28F008B3, 28F016B3,
28F032B3
(1)
28F400B3
(2),
28F800B3,
28F160B3, 28F320B3
Reference
VCC Read Voltage 2.7 V– 3.6 V Section 4.2, 4.4
V
CCQ
I/O Voltage 1.65 V–2.5 V or 2.7 V– 3.6 V Section 4.2, 4.4
VPP Program/Erase Voltage 2.7 V– 3.6 V or 11.4 V– 12.6 V Section 4.2, 4.4
Bus Width 8-bit 16 bit Table 3
Speed 80 ns, 90 ns, 100 ns, 110 ns Section 4.5
Memory Arrangement 1024 Kbit x 8 (8 Mbit),
2048 Kbit x 8 (16 Mbit),
4096 Kbit x 8 (32 Mbit)
256 Kbit x 16 (4 Mbit),
512 Kbit x 16 (8 Mbit),
1024 Kbit x 16 (16 Mbit)
2048 Kbit x 16 (32 Mbit)
Section 2.2
Blocking (top or bottom) Eight 8-Kbyte parameter blocks and
Seven 64-Kbyte blocks (4-Mbit) or
Fifteen 64-Kbyte blocks (8-Mbit) or
Thirty-one 64-Kbyte main blocks (16-Mbit)
Sixty-three 64-Kbyte main blocks (32-Mbit)
Section 2.2
Appendix D
Locking WP# locks/unlocks parameter blocks
All other blocks protected using V
PP
Section 3.3
Table 8
Operating Temperature Extended: –40 °C to +85 °C Section 4.2, 4.4
Program/Erase Cycling 100,000 cycles Section 4.2, 4.4
Packages 40-lead TSOP
(1)
, 48-Ball
µBGA* CSP
(2)
48-Lead TSOP, 48-Ball
µBGA CSP
(2)
Figure 3, Figure 4
NOTES:
1. 4-Mbit and 32-Mbit density not available in 40-lead TSOP.
2. 4-Mbit density not available in µBGA* CSP.
SMART 3 ADVANCED BOOT BLOCK E
6
PRELIMINARY
1.2 Product Overview
Intel provides the most flexible voltage solution in
the flash industry, prov iding three discrete voltage
supply pins: V
CC
for read operation, V
CCQ
for output
swing, and V
PP
for program and erase operation. All
Smart 3 Advanced Boot Block flash memory
products provide program/erase capability at 2.7 V
or 12 V [for fast production programming] and read
with V
CC
at 2.7 V. Since many designs read from
the flash memory a large percentage of the time,
2.7 V V
CC
operation can provide substant ial power
savings.
The Smart 3 Advanced Boot Block flash memory
products are available in either x8 or x16 pac kages
in the following densit ies: (see
Ordering Information
for availability.)
• 4-Mbit (4,194,304-bit) flash memory organized
as 256 Kwords of 16 bits each or 512 Kbytes of
8-bits each
• 8-Mbit (8,388,608-bit) flash memory organized
as 512 Kwords of 16 bits each or 1024 Kbytes
of 8-bits each
• 16-Mbit (16,777,216-bit) flash memory
organized as 1024 Kwords of 16 bits each or
2048 Kbytes of 8-bits each
• 32-Mbit (33,554,432-bit) flash memory
organized as 2048 Kwords of 16 bits each or
4096 Kbytes of 8-bits each
The parameter blocks are located at either the top
(denoted by -T suffix) or the bot t om (-B suffix) of t he
address map in order to accommodate different
microprocessor protocols for kernel code location.
The upper two (or lower two) parameter blocks can
be locked to provide complete code security for
system initialization code. Locking and unlocking is
controlled by WP# (see Section 3.3 for details).
The Command User Interface (CUI) s erves as the
interface between the microprocessor or
microcontroller and the internal operation of the
flash memory. The internal Write State Machine
(WSM) automatically executes the algorithms and
timings necessary for program and erase
operations, including verification, thereby unburdening the microprocessor or microcontroller.
The status register indicates t he status of the WSM
by signifying block erase or word program
completion and status.
The Smart 3 Advanced Boot Bl ock flash memory is
also designed with an Automatic Power Savings
(APS) feature which minimizes system current
drain, allowing for very low power designs. This
mode is entered following the completion of a read
cycle (approximately 300 ns later).
The RP# pin provides additional protection agains t
unwanted command writes that may occur during
system reset and power-up/down sequences due to
invalid system bus conditions (see Section 3.6).
Section 3.0 gives detailed explanation of the
different modes of operation. Complete c urrent and
voltage specifications can be found in the
DC
Characteristics
section. Refer to
AC Characteristics
for read, program and erase performance
specifications.
2.0 PRODUCT DESCRIPTION
This section explains device pin description and
package pinouts.
2.1 Package Pinouts
The Smart 3 Advanced Boot Bl ock flash memory is
available in 40-lead TSOP (x8, Figure 1), 48-lead
TSOP (x16, Figure 2) and 48-ball µBGA pac kages
(x8 and x16, Figure 3 and Figure 4 respectively ). In
all figures, pin changes necessary for density
upgrades have been circled.
E SMART 3 ADVANCED BOOT BLOCK
7
PRELIMINARY
A
17
GND
A
20
A
19
A
10
DQ
7
DQ
6
DQ
5
DQ
4
V
CCQ
V
CC
NC
DQ
3
DQ
2
DQ
1
DQ
0
OE#
GND
CE#
A
0
A
16
A
15
A
14
A
13
A
12
A
11
A
9
A
8
WE#
RP#
V
PP
WP#
A
18
A
7
A
6
A
5
A
4
A
3
A
2
A
1
16 M
8 M
Advanced Boot Block
40-Lead TSOP
10 mm x 20 mm
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
0580_01
NOTES:
1. 40-Lead TSOP available for 8- and 16-Mbit densities only.
2. Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pin 38.
Figure 1. 40-Lead TSOP Package for x8 Configurations
Advanced Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
16
V
CCQ
GND
DQ
15
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
NC
A
20
WE#
RP#
V
PP
WP#
A
19
A
18
A
17
A
7
A
6
A
5
21
22
23
24
OE#
GND
CE#
A
0
28
27
26
25
A
4
A
3
A
2
A
1
32 M
4 M
16 M
8 M
0580_02
NOTE:
Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pins 9 and 15.
Figure 2. 48-Lead TSOP Package for x16 Configurations
SMART 3 ADVANCED BOOT BLOCK E
8
PRELIMINARY
A
14
A
15
A
16
A
17
V
CCQ
A
12
A
10
A
13
NC
A
11
A
8
WE#
A
9
D
5
D
6
V
PP
RP#
NC
NC
WP#
A
19
A
21
D
2
D
3
A
20
A
18
A
6
NC
NC
A
7
A
5
A
3
CE#
D
0
A
4
A
2
A
1
A
0
GND
GND D
7
NC D
4
V
CC
NC D
1
OE#
A
B
C
D
E
F
13254768
16M
32M
8M
0580_04
NOTE:
1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address
solder balls. Routing is not recommended in this area. A
20
is the upgrade address for the 16-Mbit device. A
21
is the
upgrade address for the 32-Mbit device.
2. 4-Mbit density not available in µBGA* CSP.
Figure 3. x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down)
E SMART 3 ADVANCED BOOT BLOCK
9
PRELIMINARY
A
13
A
14
A
15
A
16
V
CCQ
A
11
A
10
A
12
D
14
D
15
A
8
WE#
A
9
D
5
D
6
V
PP
RP#
D
11
D
12
WP#
A
18
A
20
D
2
D
3
A
19
A
17
A
6
D
8
D
9
A
7
A
5
A
3
CE#
D
0
A
4
A
2
A
1
A
0
GND
GND D
7
D
13
D
4
V
CC
D
10
D
1
OE#
A
B
C
D
E
F
13254768
16M
32M
8M
0580_03
NOTES:
1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address
solder balls. Routing is not recommended in this area. A19 is the upgrade address for the 16-Mbit device. A20 is the
upgrade address for the 32-Mbit device.
2. 4-Mbit density not available in µBGA* CSP.
Figure 4. x16 48-Ball µBGA* Chip Size Package (Top View, Ball Down)
SMART 3 ADVANCED BOOT BLOCK E
10
PRELIMINARY
The pin descriptions table details the usage of each device pin.
Table 2. Smart 3 Advanced Boot Block Pin Descriptions
Symbol Type Name and Function
A0–A
21
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a program or erase cycle.
28F008B3: A[0-19], 28F016B3: A[0-20], 28F032B3: A[0-21],
28F800B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19],
28F320B3: A[0-20]
DQ0–DQ7INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, identifier and status register data. The
data pins float to tri-state when the chip is de-selected or the outputs are
disabled.
DQ8–DQ15INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE# cycle during a Program command. Data is internally latched.
Outputs array and identifier data. The data pins float to tri-state when the
chip is de-selected. Not included on x8 products.
CE# INPUT CHIP ENABLE: Activates the internal control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels.
OE# INPUT OUTPUT ENABLE: Enables the device’s outputs through the data
buffers during a read operation. OE# is active low.
WE# INPUT WRITE ENABLE: Controls writes to the Command Register and memory
array. WE# is active low. Addresses and data are latched on the rising
edge of the second WE# pulse.
RP# INPUT RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to
control reset/deep power-down mode.
When RP# is at logic low, the device is in reset/deep power-down
mode, which drives the outputs to High-Z, resets the Write State
Machine, and minimizes current levels (I
CCD
).
When RP# is at logic high, the device is in standard operation.
When RP# transitions from logic-low to logic-high, the device resets all
blocks to locked and defaults to the read array mode.
WP# INPUT WRITE PROTECT: Provides a method for locking and unlocking the two
lockable parameter blocks.
When WP# is at logic low, the lockable blocks are locked,
preventing program and erase operations to those blocks. If a program
or erase operation is attempted on a locked block, SR.1 and either SR.4
[program] or SR.5 [erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked and
can be programmed or erased.
See Section 3.3 for details on write protection.
E SMART 3 ADVANCED BOOT BLOCK
11
PRELIMINARY
Table 2. Smart 3 Advanced Boot Block Pin Descriptions (Continued)
Symbol Type Name and Function
V
CCQ
INPUT OUTPUT VCC: Enables all outputs to be driven to 1.8 V – 2.5 V while
the V
CC
is at 2.7 V–3.3 V. If the VCC is regulated to 2.7 V–2.85 V, V
CCQ
can be driven at 1.65 V–2.5 V to achieve lowest power operation (see
Section 4.4,
DC Characteristics
.
This input may be tied directly to V
CC
(2.7 V–3.6 V).
V
CC
DEVICE POWER SUPPLY: 2.7 V–3.6 V
V
PP
PROGRAM/ERASE POWER SUPPLY: Supplies power for program
and erase operations. V
PP
may be the same as VCC (2.7 V–3.6 V) for
single supply voltage operation. For fast programming at manufacturing,
11.4 V–12.6 V may be supplied to V
PP
. This pin cannot be left floating.
Applying 11.4 V–12.6 V to V
PP
can only be done for a maximum of 1000
cycles on the main blocks and 2500 cycles on the parameter blocks.
V
PP
may be connected to 12 V for a total of 80 hours maximum (see
Section 3.4 for details).
V
PP
< V
PPLK
protects memory contents against inadvertent or
unintended program and erase commands.
GND GROUND: For all internal circuitry. All ground inputs must be
connected.
NC NO CONNECT: Pin may be driven or left floating.
2.2 Block Organization
The Smart 3 Advanced Boot Block is an
asymmetrically-blocked architecture that enables
system integration of code and data within a single
flash device. Each block can be erased
independently of the others up to 100,000 times.
For the address locations of each block, see the
memory maps in Appendix D.
2.2.1 PARAMETER BLOCKS
The Smart 3 Advanced Boot Block flash memory
architecture includes parameter bl ocks to facilitate
storage of frequently updated small parameters
(e.g., data that would normally be stored in an
EEPROM). By using software techniques, the wordrewrite functionality of EEPROMs can be emulated.
Each device contains eight parameter blocks of
8-Kbytes/4-Kwords (8192 bytes/4,096 words) each.
2.2.2 MAIN BLOCKS
After the parameter blocks, the remainder of the
array is divided into equal si ze main blocks (65,536
bytes / 32,768 words) for data or c ode storage. The
4-Mbit device contains seven main blocks; 8-Mbit
device contains fifteen main blocks; 16-Mbit flash
has thirty-one main blocks; 32-Mbit has sixty-three
main blocks.
3.0 PRINCIPLES OF OPERATION
Flash memory combines EEPROM functionality
with in-circuit electrical program and erase
capability. The Smart 3 Advanc ed Boot Block f lash
memory family utilizes a Command User Interface
(CUI) and automated algorithms to si mpli fy program
and erase operations. The CUI allows for 100%
CMOS-level control inputs and fi xed power suppli es
during erasure and programming.
SMART 3 ADVANCED BOOT BLOCK E
12
PRELIMINARY
When VPP < V
PPLK
, the device will only execute the
following commands successfully: Read Array,
Read Status Register, Clear Status Register and
Read Identifier. The device provides standard
EEPROM read, standby and output disable
operations. Manufacturer identification and device
identification data can be accessed through the
CUI. All functions associated with altering m emory
contents, namely program and erase, are
accessible via the CUI. The internal Write State
Machine (WSM) completely automates program
and erase operations while the CUI si gnals the s tart
of an operation and the status register reports
status. The CUI handles t he WE# interface to the
data and address latches, as well as system status
requests during WSM operation.
3.1 Bus Operation
Smart 3 Advanced Boot Block flash memory
devices read, program and erase in-system via the
local CPU or microcontroller. All bus cycles to or
from the flash memory conform to standard
microcontroller bus cycles. Four control pins dictate
the data flow in and out of the flash component:
CE#, OE#, WE# and RP#. These bus operations
are summarized in Table 3.
Table 3. Bus Operations
(1)
Mode Note RP# CE# OE# WE# DQ
0–7
DQ
8–15
Read (Array, Status, or
Identifier)
2–4 V
IH
V
IL
V
IL
V
IH
D
OUT
D
OUT
Output Disable 2 V
IH
V
IL
V
IH
V
IH
High Z High Z
Standby 2 V
IH
V
IH
X X High Z High Z
Reset 2, 7 V
IL
X X X High Z High Z
Write 2, 5–7 V
IH
V
IL
V
IH
V
IL
D
IN
D
IN
NOTES:
1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15]
2. X must be V
IL
, VIH for control pins and addresses.
3. See
DC Characteristics
for V
PPLK
, V
PP1
, V
PP2
, V
PP3
, V
PP4
voltages.
4. Manufacturer and device codes may also be accessed in read identifier mode (A
1–A21
= 0). See Table 4.
5. Refer to Table 6 for valid D
IN
during a write operation.
6. To program or erase the lockable blocks, hold WP# at V
IH
.
7. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.
E SMART 3 ADVANCED BOOT BLOCK
13
PRELIMINARY
3.1.1 READ
The flash memory has four read modes available:
read array, read identifier, read status and read
query. These modes are accessibl e independent of
the V
PP
voltage. The appropriate Read Mode
command must be issued t o the CUI to enter the
corresponding mode. Upon initial dev ice power
-
up
or after exit from reset, the device automatically
defaults to read array mode.
CE# and OE# must be driven active to obtain dat a
at the outputs. CE# is the device sel ection control;
when active it enables the flash memory device.
OE# is the data output control and it drives the
selected memory data onto t he I/ O bus. For all read
modes, WE# and RP# must be at V
IH
. Figure 7
illustrates a read cycle.
3.1.2 OUTPUT DISABLE
With OE# at a logic
-
high level (VIH), the device
outputs are disabled. Output pins are placed in a
high
-
impedance state.
3.1.3 STANDBY
Deselecting the device by bri nging CE# to a logic
-
high level (VIH) places the device in standby mode,
which substantially reduces device power
consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a
high-impedance state independent of OE#. If
deselected during program or erase operat ion, the
device continues to c onsume active power unt il the
program or erase operation is complete.
3.1.4 DEEP POWER-DOWN / RESET
From read mode, RP# at V
IL
for time t
PLPH
deselects the memory, places output drivers in a
high
-
impedance state, and turns off all internal
circuits. After return from reset, a time t
PHQV
is
required until the initial read access outputs are
valid. A delay (t
PHWL
or t
PHEL
) is required after
return from reset before a write can be initiated.
After this wake
-
up interval, normal operation is
restored. The CUI resets to read array mode, and
the status register is set to 80H. This cas e is shown
in Figure 9A.
If RP# is taken low for time t
PLPH
during a program
or erase operation, the operation will be aborted
and the memory contents at the aborted location
(for a program) or block (for an erase) are no longer
valid, since the data may be partially erased or
written. The abort process goes through the
following sequence: When RP# goes low, the
device shuts down the operation in progress, a
process which takes time t
PLRH
to complete. After
this time t
PLRH
, the part will either reset to read
array mode (if RP# has gone high during t
PLRH
,
Figure 9B) or enter reset mode (if RP# is st ill logic
low after t
PLRH
, Figure 9C). In both cases, after
returning from an aborted operation, the relevant
time t
PHQV
or t
PHWL/tPHEL
must be waited before a
read or write operation is initiat ed, as discussed in
the previous paragraph. However, in this case,
these delays are referenced to the end of t
PLRH
rather than when RP# goes high.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, proc essor expec ts to read from
the flash memory. Automated flash memories
provide status information when read during
program or block erase operations. I f a CPU reset
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash
memory may be providing status information
instead of array data. Intel ’s Flash memories allow
proper CPU initialization following a system reset
through the use of the RP# input. In this applic at i on,
RP# is controlled by the same RESET# signal that
resets the system CPU.
3.1.5 WRITE
A write takes place when both CE# and WE# are
low and OE# is high. Commands are written to the
Command User Interface (CUI) using standard
microprocessor write timings to control flash
operations. The CUI does not occupy an
addressable memory location. The address and
data buses are latched on the rising edge of the
second WE# or CE# pulse, whichever occ urs first.
Figure 8 illustrates a program and erase operation.
The available commands are shown in Table 6, and
Appendix A provides detailed information on
moving between the different modes of operation
using CUI commands.
SMART 3 ADVANCED BOOT BLOCK E
14
PRELIMINARY
There are two commands that modify array data:
Program (40H) and Erase (20H). Writing either of
these commands to the internal Command User
Interface (CUI) initiates a sequence of internally
-
timed functions that culminate in the c ompletion of
the requested task (unless that operati on is aborted
by either RP# being driven to V
IL
for t
PLRH
or an
appropriate suspend command).
3.2 Modes of Operation
The flash memory has four read modes and two
write modes. The read modes are read array, read
identifier, read status and read query (see A ppendix
C). The write modes are program and block erase.
Three additional modes (erase suspend to program,
erase suspend to read and program suspend to
read) are available only during suspended
operations. These modes are reached using the
commands summarized in Table 4. A
comprehensive chart showing t he state transitions
is in Appendix A.
3.2.1 READ ARRAY
When RP# transitions from V
IL
(reset) to VIH, the
device defaults to read array mode and will res pond
to the read control inputs (CE#, address i nputs , and
OE#) without any additional CUI commands.
When the device is in read array mode, four control
signals control data output:
• WE# must be logic high (V
IH
)
• CE# must be logic low (V
IL
)
• OE# must be logic low (V
IL
)
• RP# must be logic high (V
IH
)
In addition, the address of the desired loc ati on mus t
be applied to the address pins. If the dev ice is not
in read array mode, as would be t he case after a
program or erase operation, the Read Array
command (FFH) must be written to the CUI before
array reads can take place.
Table 4. Command Codes and Descriptions
Code Device Mode Description
00,
01,
60,
2F,
C0,
98
Invalid/
Reserved
Unassigned commands that should not be used. Intel reserves the right to
redefine these codes for future functions.
FF Read Array Places the device in read array mode, such that array data will be output on the
data pins.
40 Program
Set-Up
This is a two-cycle command. The first cycle prepares the CUI for a program
operation. The second cycle latches addresses and data information and
initiates the WSM to execute the Program algorithm. The flash outputs status
register data when CE# or OE# is toggled. A Read Array command is required
after programming to read array data. See Section 3.2.4.
10 Alternate
Program Set-Up
(See 40H/Program Set-Up)
20 Erase
Set-Up
Prepares the CUI for the Erase Confirm command. If the next command is not
an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the
status register to a “1,” (b) place the device into the read status register mode,
and (c) wait for another command. See Section 3.2.5.
E SMART 3 ADVANCED BOOT BLOCK
15
PRELIMINARY
Table 4. Command Codes and Descriptions (Continued)
Code Device Mode Description
D0 Erase Confirm
Program / Erase
Resume
If the previous command was an Erase Set-Up command, then the CUI will
close the address and data latches, and begin erasing the block indicated on the
address pins. During erase, the device will only respond to the Read Status
Register and Erase Suspend commands. The device will output status register
data when CE# or OE# is toggled.
If a program or erase operation was previously suspended, this command will
resume that operation
B0 Program / Erase
Suspend
Issuing this command will begin to suspend the currently executing
program/erase operation. The status register will indicate when the operation
has been successfully suspended by setting either the program suspend (SR.2)
or erase suspend (SR.6) and the WSM status bit (SR.7) to a “1” (ready). The
WSM will continue to idle in the SUSPEND state, regardless of the state of all
input control pins except RP#, which will immediately shut down the WSM and
the remainder of the chip if it is driven to V
IL
. See Sections 3.2.4.1 and 3.2.5.1.
70 Read Status
Register
This command places the device into read status register mode. Reading the
device will output the contents of the status register, regardless of the address
presented to the device. The device automatically enters this mode after a
program or erase operation has been initiated. See Section 3.2.3.
50 Clear Status
Register
The WSM can set the block lock status (SR.1) , VPP status (SR.3), program
status (SR.4), and erase status (SR.5) bits in the status register to “1,” but it
cannot clear them to “0.” Issuing this command clears those bits to “0.”
90 Read Identifier Puts the device into the intelligent identifier read mode, so that reading the
device will output the manufacturer and device codes (A
0
= 0 for manufacturer,
A
0
= 1 for device, all other address inputs must be 0). See Section 3.2.2.
NOTE: See Appendix A for mode transition information.
3.2.2 READ IDENTIFIER
To read the manufacturer and device codes, the
device must be in read identif ier mode, which can
be reached by writing the Read Identif ier command
(90H). Once in read identifier mode, A
0
= 0 outputs
the manufacturer’s identification code and A
0
= 1
outputs the device identifier (see Table 5) Note:
A
1—A21
= 0. To return to read array mode, write t he
Read Array command (FFH).
Table 5. Read Identifier Table
Device Identifier
Size Mfr. ID -T
(Top Boot)-B(Bot. Boot)
28F400B3 0089H 8894H 8895H
28F008B3 0089H D2 D3
28F800B3 8892H 8893H
28F016B3 0089H D0 D1
28F160B3 8890H 8891H
28F032B3 0089H D6 D7
28F320B3 8896 8897
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