Intel Corporation G28F016SC-150, G28F016SC-120, G28F008SC-150, G28F008SC-120 Datasheet
E
December 1997
SmartVoltage FlashFile™ MEMORY FAMILY
4, 8, AND 16 MBIT
28F004SC, 28F008SC, 28F016SC
Includes Commercial and Extended Temperature Specifications
n
SmartVoltage Technology
2.7 V (Read-Only), 3.3 V or 5 V V
and 3.3 V, 5 V, or 12 V V
n
High-Performance
4, 8 Mbit 85 ns Read Access Time
16 Mbit 95 ns Read Access Time
n
Enhanced Data Protection Features
Absolute Protection with V
Flexible Block Locking
Block Write Lockout during Power
Transitions
n
Enhanced Automated Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n
Industry-Standard Packaging
40-Lead TSOP, 44-Lead PSOP
and 40 Bump µBGA* CSP
PP
PP
BYTE-WIDE
n
CC
n
= GND
n
n
n
n
PRELIMINARY
High-Density 64-Kbyte Symmetrical
Erase Block Architecture
4 Mbit: Eight Blocks
8 Mbit: Sixteen Blocks
16 Mbit: Thirty-Two Blocks
Extended Cycling Capability
100,000 Block Erase Cycles
Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases I
Automated Program and Block Erase
Command User Interface
Status Register
SRAM-Compatible Write Interface
ETOX™ V Nonvolatile Flash
Technology
in Static Mode
CC
Intel’s byte-wide SmartVolt age FlashFile™ memory family renders a variet y of density offeri ngs in the same
package. The 4-, 8-, and 16-Mbit byte-wide FlashFile memories provide high-density, low-cost, nonv olatile,
read/write storage solutions for a wide range of applications. Thei r symmetrically-blocked architecture, fl exible
voltage, and extended cy cling provide highly flexible components suitable for resident flash arrays , SIMMs,
and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage
applications. For secure code storage applications, such as networking, where code is either directly
executed out of flash or downl oaded to DRAM, the 4-, 8-, and 16-Mbit FlashFile mem ories offer three lev els
of protection: absolute protection with V
block locking. These alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They come in
industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged
44-lead PSOP. Based on the 28F008S A architecture, the byte-wide SmartVol tage FlashFile memory family
enables quick and easy upgrades for designs that demand state-of-the-art technology.
at GND, selective hardware block locking, or flexible software
PP
Order Number: 290600-003
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F004SC, 28F008SC, 28F016SC may contain design defects or errors known as errata. Current characterized errata are
available on request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel’s Website at http://www.intel.com
COPYRIGHT © INTEL CORPORATION 1996, 1997 CG-041493
E BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
CONTENTS
PAGE PAGE
1.0 INTRODUCTION .............................................5
1.1 New Features...............................................5
1.2 Product Overview.........................................5
1.3 Pinout and Pin Description...........................6
2.0 PRINCIPLES OF OPERATION .....................12
2.1 Data Protection ..........................................13
3.0 BUS OPERATION.........................................13
3.1 Read..........................................................13
3.2 Output Disable...........................................13
3.3 Standby......................................................13
3.4 Deep Power-Down.....................................13
3.5 Read Identifier Codes Operation................14
3.6 Write ..........................................................14
4.0 COMMAND DEFINITIONS............................14
4.1 Read Array Command................................17
4.2 Read Identifier Codes Command...............17
4.3 Read Status Register Command................17
4.4 Clear Status Register Command................17
4.5 Block Erase Command ..............................17
4.6 Program Command....................................18
4.7 Block Erase Suspend Command................18
4.8 Program Suspend Command.....................19
4.9 Set Block and Master Lock-Bit Commands 19
4.10 Clear Block Lock-Bits Command..............20
6.0 ELECTRICAL SPECIFICATIONS..................30
6.1 Absolute Maximum Ratings........................30
6.2 Commercial Temperature Operating
Conditions.................................................30
6.3 Capacitance...............................................30
6.4 DC Characteristics—Commercial
Temperature..............................................31
6.5 AC Characteristics—Read-Only
Operations—Commercial Temperature.....35
6.6 AC Characteristics—Write Operations—
Commercial Temperature..........................37
6.7 Block Erase, Program, and Lock-Bit
Configuration Performance—Commercial
Temperature..............................................39
6.8 Extended Temperature Operating
Conditions.................................................40
6.9 DC Characteristics—Extended
Temperature..............................................40
6.10 AC Characteristics—Read-Only Operations
— Extended Temperature.........................40
7.0 ORDERING INFORMATION..........................41
8.0 ADDITIONAL INFORMATION.......................42
5.0 DESIGN CONSIDERATIONS........................28
5.1 Three-Line Output Control..........................28
5.2 RY/BY# Hardware Detection......................28
5.3 Power Supply Decoupling..........................28
Trace on Printed Circuit Boards...........28
5.4 V
PP
, VPP, RP# Transitions .........................28
5.5 V
CC
5.6 Power-Up/Down Protection........................28
Program and Erase Voltages on Sub-
5.7 V
PP
0.4µ SC Memory Family............................29
PRELIMINARY
3
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E
REVISION HISTORY
Number Description
-001 Original version
-002 Table 3 revised to reflect change in abbreviations from “W” for write to “P” for program.
-003 Added µBGA* CSP pinout and corrected error in PSOP pinout.
Ordering information graphic (Appendix A) corrected: from PB = Ext. Temp. 44-Lead
PSOP to TB = Ext. Temp. 44-Lead PSOP.
Corrected nomenclature table (Appendix A) to reflect actual Operating Temperature/
Package information
Updated Ordering Information and table
Correction to table, Section 6.2.3. Under I
or GND, corrected to V
= VCC or GND
OUT
Test Conditions, previously read VIN = V
LO
Section 6.2.7, modified Program and Block Erase Suspend Latency Times
Added Design Consideration for V
Program and Erase Voltages on future sub-0.4µ
PP
devices.
CC
4
PRELIMINARY
E BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
Voltage Combinations
1.0 INTRODUCTION
This datasheet contains 4-, 8-, and 16-Mbit
SmartVoltage FlashFile memory specifications.
Section 1.0 provides a flash memory overview.
Sections 2.0, through 5.0 describe the memory
organization and functionality. Section 6.0 covers
electrical specifications for commercial and
extended temperature product offerings. Section
7.0 contains ordering informat ion. Finally, the by tewide SmartVoltage FlashFile memory family
documentation also incl udes application notes and
design tools which are referenced in Section 8.0.
1.1 New Features
The byte-wide SmartVoltage FlashFile memory
family maintains backwards-compatibility with
Intel’s 28F008SA and 28F008SA-L. Key
enhancements include:
• SmartVoltage Technology
• Enhanced Suspend Capabilities
• In-System Block Locking
They share a compatible status register, software
commands, and pinouts. These similarities enable
a clean upgrade from the 28F008SA and
28F008SA-L to byte-wide SmartVoltage FlashFile
products. When upgrading, it is important to note
the following differences:
• Because of new feature and density options,
the devices have different device identifier
codes. This allows for software optimization.
• V
• To take advantage of SmartVoltage tech-
For more details see application note
28F008SC Compatibility with 28F008SA
number 292180)
has been lowered from 6.5 V to 1.5 V to
PPLK
support low V
program, and lock-bit configuration operations.
Designs that switch V
operations should transition V
nology, allow V
voltages during block erase,
PP
off during read
PP
to GND.
PP
connection to 3.3 V or 5 V.
PP
.
AP-625,
(order
1.2 Product Overview
The byte-wide SmartVoltage FlashFile memory
family provides density upgrades with pinout
compatibility for the 4-, 8-, and 16-Mbit densities.
The 28F004SC, 28F008SC, and 28F016SC are
high-performance memories arranged as
512 Kbyte, 1 Mbyte, and 2 Mbyte of 8 bits. This
data is grouped in eight, sixteen, and thirty-two
64-Kbyte blocks which are individually erasable,
lockable, and unlockable in-system. Figure 4
illustrates the memory organization.
SmartVoltage technology enables fast factory
programming and low-power designs. These
components support read operations at 2. 7 V (readonly), 3.3 V, and 5 V V
program operations at 3.3 V, 5 V, and 12 V V
The 12 V V
and erase performance which will increase your
factory throughput. With the 3.3 V and 5 V V
option, VCC and VPP can be tied together for a
simple and voltage flexible design. This voltage
flexibility is key for removable media that need to
operate in a 3 V to 5 V system. In addition, the
dedicated V
when V
NOTE:
1. Block erase, program, and lock-bit configuration
operation with V
Internal VCC and VPP detection circuitry
automatically configures the device for optimum
performance.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
configuration operations.
option renders the fastest program
PP
pin gives complete data protection
PP
≤ V
PP
V
CC
VCC Voltage VPP Voltage
2.7 V
.
PPLK
Table 1. SmartVoltage Flash
and V
PP
(1)
3.3 V 3.3 V, 5 V, 12 V
5 V 5 V, 12 V
, 3.0 V are not supported.
CC
and block erase and
CC
PP
PP
.
PRELIMINARY
5
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E
A block erase operation erases one of the device’s
64-Kbyte blocks typically within 1 second
(5 V V
, 12 V VPP), independent of other blocks.
CC
Each block can be independently erased 100,000
times (1.6 million block erases per device). A block
erase suspend operation allows system software to
suspend block erase to read data f rom or write data
to any other block.
Data is programmed in byte increments typically
within 6 µs (5 V V
, 12 V VPP). A program
CC
suspend operation permits system software to read
data or execute code from any other flash memory
array location.
To protect programmed data, each block can be
locked. This block locking mechanism uses a
combination of bits, block lock-bits and a master
lock-bit, to lock and unlock individual blocks. The
block lock-bits gate block erase and program
operations, while the master lock-bit gates block
lock-bit configuration operations. Lock-bit configuration operations (Set Bloc k Lock-Bit, Set M aster
Lock-Bit, and Clear Bloc k Loc k-Bit s c ommands) set
and clear lock-bits.
The status register and RY/BY# output indicate
whether or not the device is busy executing or
ready for a new command. Polling the status
register, system software retrieves WSM feedback.
The RY/BY# output gives an additional indicator of
WSM activity by provi ding a hardware st atus s ignal.
Like the status register, RY/BY#-low indicates that
the WSM is performing a bl ock erase, program, or
lock-bit configuration operation. RY/BY#-high
indicates that the WSM is ready for a new
command, block erase is s uspended (and program
is inactive), program i s suspended, or t he device i s
in deep power-down mode.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in stati c mode (addresses not switching).
In APS mode, the typical I
5 V V
.
CC
When CE# and RP# pins are at V
current is 1 mA at
CCR
CC
, the
component enters a CMOS s tandby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (t
PHQV
) is
required from RP# switching high until output s are
valid. Likewise, t he device has a wake time (t
PHEL
from RP#-high until writes to the CUI are
recognized.
1.3 Pinout and Pin Description
The family of devices is avail able in 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick) and
44-lead PSOP (Plastic Small Outline Pac kage) and
40-bump µ BGA* CSP (28F008SC and 28F016SC
only). Pinouts are shown in Figures 2, 3 and 4.
)
6
PRELIMINARY
E BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
DQ - DQ
07
Input
Buffer
Command
Register
Write State
Machine
I/O Logic
Program/Erase
Voltage Switch
V
CC
CE#
WE#
OE#
RP#
RY/BY#
V
PP
V
CC
GND
4-Mbit: A - A ,
0
18
8-Mbit: A - A ,
19
0
16-Mbit: A - A
020
Input
Buffer
Address
Latch
Address
Counter
Y
Decoder
X
Decoder
Output
Buffer
Identifier
Register
Status
Register
Data
Comparator
Y Gating
4-Mbit: Eight
8-Mbit: Sixteen
16-Mb it: Thirty-Two
64-Kbyte Blocks
Figure 1. Block Diagram
Table 2. Pin Descriptions
Sym Type Name and Function
A0–A
DQ0–DQ7INPUT/
INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations.
20
Addresses are internally latched during a write cycle.
4 Mbit → A
16 Mbit → A0–A
8 Mbit → A0–A
–A
0
20
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles;
OUTPUT
outputs data during memory array, status register, and identifier code read cycles.
Data pins float to high-impedance when the chip is deselected or outputs are
disabled. Data is internally latched during a write cycle.
CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE#-high deselects the device and reduces power consumption to
standby levels.
RP# INPUT RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations
which provides data protection during power transitions, puts the device in deep
power-down mode, and resets internal automation. RP#-high enables normal
operation. Exit from deep power-down sets the device to read array mode.
RP# at V
lock-bits when the master lock-bit is set. RP# = V
enables setting of the master lock-bit and enables configuration of block
HH
overrides block lock-bits,
HH
thereby enabling block erase and program operations to locked memory blocks.
Block erase, program, or lock-bit configuration with V
< RP# < VHH produce
IH
spurious results and should not be attempted.
OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
PRELIMINARY
7
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E
Table 3. Pin Descriptions (Continued)
Sym Type Name and Function
WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data
RY/BY# OUTPUT READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is
V
PP
V
CC
SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:
SUPPLY DEVICE POWER SUPPLY: Internal detection automatically configures the device
GND SUPPLY GROUND: Do not float any ground pins.
NC NO CONNECT: Lead is not internally connected; it may be driven or floated.
are latched on the rising edge of the WE# pulse.
performing an internal operation (block erase, program, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase or
program is suspended, or the device is in deep power-down mode. RY/BY# is
always active.
For erasing array blocks, programming data, or configuring lock-bits.
SmartVoltage Flash → 3.3 V, 5 V, and 12 V V
With VPP ≤ V
, memory contents cannot be altered. Block erase, program, and
PPLK
lock-bit configuration with an invalid V
(see
DC Characteristics
PP
PP
) produce spurious
results and should not be attempted.
for optimized read performance. Do not float any power pins.
SmartVoltage Flash → 2.7 V (Read-Only), 3.3 V, and 5 V V
With VCC ≤ V
, all write attempts to the flash memory are inhibited. Device
LKO
operations at invalid V
voltages (see
CC
DC Characteristics
) produce spurious
CC
results and should not be attempted. Block erase, program, and lock-bit
configuration operations with V
< 3.0 V are not supported.
CC
8
PRELIMINARY
E BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
28F016SC
28F008SC
28F004SC
A
19A19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
CE#
V
CC
V
PP
RP#
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
A
A
A
A
A
A
CE#
V
V
RP#
A
A
A
A
A
A
A
A
NC
A
18
18
A
17
17
A
16
16
A
15
15
A
14
14
A
13
13
A
12
12
CE#
V
CC
CC
V
PP
PP
RP#
A
11
11
A
10
10
A
9
9
A
8
8
A
7
7
A
6
6
A
5
5
A
4
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40-LEAD TSOP
STANDARD PINOUT
10 mm x 20 mm
TOP VIEW
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
WE#
OE#
RY/BY#
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
GND
GND
DQ
3
DQ
2
DQ
1
DQ
0
A
0
A
1
A
2
A
3
WE#
OE#
RY/BY#
DQ
DQ
DQ
DQ
V
GND
GND
DQ
DQ
DQ
DQ
Figure 2. TSOP 40-Lead Pinout
NC
NC
A
A
A
A
A
20
NC
WE#
OE#
RY/BY#
DQ
7
7
DQ
6
6
DQ
5
5
DQ
4
4
V
CC
CC
GND
GND
DQ
3
3
DQ
2
2
DQ
1
1
DQ
0
0
A
0
0
A
1
1
A
2
2
A
3
3
PRELIMINARY
9
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E
10
Figure 3. PSOP 44-Lead Pinout
PRELIMINARY
E BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
87654321
A
A
Pin #1
Indicator
A
B
C
D
E
A
7
A
6
A
4
A
2
A
1
12345678
A
17
A
18
NC RY/BY# A
WE#
OE# D
RP# V
9
A
A
10
A
5
A
0
D
D
0
PP
CE# A
11
3
1
2
8
D3GNDD
GND D
Bottom View - Bump Side Up
A
A
15
A
16
D
6
7
V
12
CC
A
D
14
19
4
5
13
NC A
GNDD
V
CC
V
CC
13
NCA
V
CC
A
12
A
14
A
19
D
4
5
V
PP
CE#A
8
D
3
GND D
A
A
A
RY/BY#A
17
15
A
18
16
A
20
D6WE#
OE#D
7
RP# A
A
9
A
A
A
D
10
11
A
3
5
A
0
1
D
2
0
B
C
D
E
7
A
6
A
4
A
2
A
1
Top View - Bump Side Down
This is the view of the package as surface mounted on the board.
Note that the signals are mirror images of bottom view.
NOTES:
1. Figures are not drawn to scale.
2. Address A20 is not included in the 28F008SC.
3. More information on µBGA* packages is available by contacting your Intel/Distribution sales office.
Figure 4. µBGA* CSP 40-Ball Pinout (28F008SC and 28F016SC)
PRELIMINARY
11
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E
2.0 PRINCIPLES OF OPERATION
The byte-wide SmartVoltage FlashFile memories
include an on-chip WSM to manage block erase,
program, and lock-bit configuration functions. It
allows for: 100% TTL-level control inputs, fixed
power supplies during block erasure, program, and
lock-bit configuration, and minimal processor
overhead with RAM-like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the
device defaults to read array mode. Mani pulation of
external memory control pins allow array read,
standby, and output disable operations.
Status register and identifier codes can be
accessed through the CUI independent of the V
PP
voltage. High voltage on VPP enables successful
block erasure, program, and lock-bit c onfiguration.
All functions associated with altering memory
contents—block erase, program, lock-bit
configuration, status, and identifier codes—are
accessed via the CUI and verified through the
status register.
Commands are written using standard microprocessor write timings . The CUI c ontents s erve as
input to the WSM that controls block erase,
program, and lock-bit configuration operat ions. The
internal algorithms are regulated by the WSM,
including pulse repetition, internal verification, and
margining of data. Addresses and data are
internally latched during write cycles. Writing the
appropriate command outputs array data, acces ses
the identifier codes, or outputs status register data.
Interface software that initiates and polls progress
of block erase, program, and lock-bit configuration
can be stored in any block. This code is c opied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system
software to suspend a block erase to read or write
data from any other block. Program sus pend allows
system software to suspend a program to read data
from any other flash memory array location.
1FFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1A0000
19FFFF
190000
18FFFF
180000
17FFFF
170000
16FFFF
160000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
000000
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
4-Mbit
3
2
1
0
16-Mbit
8-Mbit
12
Figure 5. Memory Map
PRELIMINARY
E BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
2.1 Data Protection
Depending on the application, the system designer
may choose to make the V
switchable (available only when memory block
erases, programs, or lock-bit configurations are
required) or hardwired to V
accommodates either design practice and
encourages optimization of the processor-memory
interface.
When V
altered. When high voltage is applied to V
two-step block erase, program, or lock-bit
configuration command sequences provides protection from unwanted operations. All write
functions are disabled when V
the write lockout voltage V
V
IL
additional protection from i nadvertent code or data
alteration by gating erase and program operations.
≤ V
PP
. The device’s block locking capability provides
, memory contents cannot be
PPLK
power supply
PP
. The device
PPH1/2/3
voltage is below
CC
or when RP# is at
LKO
PP
, the
3.0 BUS OPERATION
The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
3.1 Read
3.2 Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ
placed in a high-impedance state.
–DQ7 are
0
3.3 Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ
in a high-impedance state independent of OE#. If
deselected during block erase, program, or
lock-bit configuration, the device continues
functioning and consuming active power until the
operation completes.
–DQ7 outputs are placed
0
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read mode, RP#-low deselects the memory,
places output drivers in a high-impedance state,
and turns off all internal c ircuits. RP# mus t be held
low for time t
return from power-down until initial m emory access
outputs are valid. After this wake-up interval,
normal operation is restored. The CUI resets to
read array mode, and the status register is set to
80H.
PLPH
. Time t
is required after
PHQV
Block information, i dentifier codes, or stat us register
can be read independent of the V
can be at either V
The first task is to write the appropri ate read-mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep powerdown mode, the device automati cally resets to read
array mode. Four control pins dictate the data flow
in and out of the component: CE#, OE#, WE#, and
RP#. CE# and OE# must be driven active to obtai n
data at the outputs. CE# is the device selection
control, and when active enables the selected
memory device. OE# is the data out put (DQ
control and when active drives the selected
memory data onto the I/O bus . WE # mus t be at V
and RP# must be at VIH or VHH. Figure 18
illustrates a read cycle.
or VHH.
IH
voltage. RP#
PP
0
–DQ7)
PRELIMINARY
During block erase, program, or lock-bit
configuration, RP#-low will abort the operation.
RY/BY# remains low until the reset operation is
complete. Memory contents being altered are no
longer valid; the data may be partially erased or
written. Time t
logic-high (V
written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, i t ex pect s t o read from t he flas h
memory. Automated flash memori es provide status
information when accessed during block erase,
program, or lock-bit confi guration modes. If a CPU
reset occurs with no flash memory reset, proper
CPU initialization m ay not occur because the flas h
IH
memory may be providing status information
instead of array data. Int el’s flash memories allow
proper CPU initialization following a system reset
through the use of the RP# input. In this application,
RP# is controlled by the same RESET# signal that
resets the system CPU.
is required after RP# goes to
PHWL
) before another command can be
IH
13
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