Intel Corporation FW82371AB Datasheet
E
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
© INTEL CORPORATION 1997 April 1997 Order Number: 290562-001
Supported Kits for both Pentium® and
Pentium
®
II Microprocessors
82430TX ISA Kit
82440LX ISA/DP Kit
Multifunction PCI to ISA Bridge
Supports PCI at 30 MHz and 33 MHz
Supports PCI Rev 2.1 Specification
Supports Full ISA or Extended I/O
(EIO) Bus
Supports Full Positive Decode or
Subtractive Decode of PCI
Supports ISA and EIO at 1/4 of PCI
Frequency
Supports both Mobile and Desktop
Deep Green Environments
3.3V Operation with 5V Tolerant
Buffers
Ultra-low Power for Mobile
Environments Support
Power-On Suspend, Suspend to
RAM, Suspend to Disk, and SoftOFF System States
All Registers Readable and
Restorable for Proper Resume
from 0.V Suspend
Power Management Logic
Global and Local Device
Management
Suspend and Resume Logic
Supports Thermal Alarm
Support for External
Microcontroller
Full Support for Advanced
Configuration and Power Interface
(ACPI) Revision 1.0 Specification
and OS Directed Power
Management
Integrated IDE Controller
Independent Timing of up to
4 Drives
PIO Mode 4 and Bus Master IDE
Transfers up to 14 Mbytes/sec
Supports “Ultra DMA/33”
Synchronous DMA Mode Transfers
up to 33 Mbytes/sec
Integrated 16 x 32-bit Buffer for IDE
PCI Burst Transfers
Supports Glue-less “Swap-Bay”
Option with Full Electrical Isolation
Enhanced DMA Controller
Two 82C37 DMA Controllers
Supports PCI DMA with 3 PC/PCI
Channels and Distributed DMA
Protocols (Simultaneously)
Fast Type-F DMA for Reduced PCI
Bus Usage
Interrupt Controller Based on Two
82C59
15 Interrupt Support
Independently Programmable for
Edge/Level Sensitivity
Supports Optional I/O APIC
Serial Interrupt Input
Timers Based on 82C54
System Timer, Refresh Request,
Speaker Tone Output
USB
Two USB 1.0 Ports for Serial
Transfers at 12 or 1.5 Mbit/sec
Supports Legacy Keyboard and
Mouse Software with USB-based
Keyboard and Mouse
Supports UHCI Design Guide
SMBus
Host Interface Allows CPU to
Communicate Via SMBus
Slave Interface Allows External
SMBus Master to Control Resume
Events
Real-Time Clock
256-byte Battery-Back CMOS SRAM
Includes Date Alarm
Two 8-byte Lockout Ranges
Microsoft Win95* Compliant
324 mBGA Package
82371AB PCI-TO-ISA / IDE
XCELERATOR (PIIX4)
82371AB (PIIX4) E
2
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
The 82371AB PCI ISA IDE Xcelerator (PIIX4) is a multi-function PCI device implementing a PCI-to-ISA bridge
function, a PCI IDE function, a Universal Serial Bus host/hub function, and an Enhanced Power Management
function. As a PCI-to-ISA bridge, PIIX4 integrates many common I/O functions found in ISA-based PC
systems—two 82C37 DMA Controllers, two 82C59 Interrupt Controllers, an 82C54 Timer/Counter, and a Real
Time Clock. In addition to compatible transfers, each DMA channel supports Type F transfers. PIIX4 also
contains full support for both PC/PCI and Distributed DMA protocols implementing PCI-based DMA. The
Interrupt Controller has Edge or Level sensitive programmable inputs and fully supports the use of an external
I/O Advanced Programmable Interrupt Controller (APIC) and Serial Interrupts. Chip select decoding is provided
for BIOS, Real Time Clock, Keyboard Controller, second external microcontroller, as well as two Programmable
Chip Selects. PIIX4 provides full Plug and Play compatibility. PIIX4 can be configured as a Subtractive Decode
bridge or as a Positive Decode bridge. This allows the use of a subtractive decode PCI-to-PCI bridge such as
the Intel 380FB PCIset which implements a PCI/ISA docking station environment.
PIIX4 supports two IDE connectors for up to four IDE devices providing an interface for IDE hard disks and CD
ROMs. Up to four IDE devices can be supported in Bus Master mode. PIIX4 contains support for “Ultra DMA/33”
synchronous DMA compatible devices.
PIIX4 contains a Universal Serial Bus (USB) Host Controller that is Universal Host Controller Interface (UHCI)
compatible. The Host Controller’s root hub has two programmable USB ports.
PIIX4 supports Enhanced Power Management, including full Clock Control, Device Management for up to
14 devices, and Suspend and Resume logic with Power On Suspend, Suspend to RAM or Suspend to Disk. It
fully supports Operating System Directed Power Management via the Advanced Configuration and Power
Interface (ACPI) specification. PIIX4 integrates both a System Management Bus (SMBus) Host and Slave
interface for serial communication with other devices.
Information in this document is provided in conjunction with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as provided in
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express
or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
The 82371AB PIIX4 may contain design defects or errors known as errata. Current characterized errata are available
on request.
Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this
specification. Intel does not warrant or represent that such use will not infringe such rights.
I2C is a two-wire communication bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was
developed by Intel. Implementation of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various
entities, including Philips Electronics N.V. and North American Philips Corporation.
Third-party brands and names are the property of their respective owners.
E 82371AB (PIIX4)
3
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
PCICL
K
AD[31:0]
C/BE[3:0]#
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
SERR#
PAR
IDSEL
PHOLD#
PHLKA#
CLKR
UN#
RCIN#
PWROK
CPURST
RSTDRV
INIT
PCIRST#
IRQ0//GPO14
IRQ8#/GPI6
IRQ12/M
INTR
NMI
IRQ[15,14,11:9,7:3,1]
SERIRQ/GPI7
PRIQ[A:C]
PIRQD
IRQ9OUT#/GPO29
SMI#
STPCLK#
EXTSMI#
SLP#
SUSCLK
BATLOW#/GPI9
THRM#/GPI8
LID//GPI10
RI#/GPI12
RSMRST#
PWRBTN#
SUSA#
SUSB#/GPO15
SUSC#/GPO16
ZZ/GPO19
PCIREQ[D:A]#
SPKR
OSC
DREQ[7:5,3:0]
DACK[7:5,3:0]#
TC
REFRESH#
REQ[A:C]#/GPI[2:4]
GNT[A:C]#/GPO[9:11]
CLK48
USBPO±
USBP1±
OC[1:0]#
CONFIG[2:1]
TEST#
PCI Bus
Interface
ISA Bus
Interface
System
Reset
Interrupt
Primary
IDE
Interface
Secondary
IDE
Interface
System
Power
Mgmt.
X-Bus
Support
Logic
Timers/
Counters
DMA
I/O APIC
Support
Logic
Universal
Serial
Bus
RTC
SMBUS
General
Purpose
Inputs
and
Outputs
Test
SD[15:0]
IOCS16#
MEMCS16#
MEMR#
MEMW#
AEN
IOCHRDY
IOCHK#/GPI0
SYSCLK
BALE
IOR#
IOW#
SMEMR#
SMEMW#
ZEROWS#
SA[19:0]
LA[23:17]/GPO[7:1]
SBHE#
PDCS1#
PDCS3#
PDA[2:0]
PDD[15:0]
PDDACK#
PDDREQ
PDIOIR#
PDIOW#
PIORDY
SDCS1#
SDCS3#
SDA[2:0]
SDD[15:0]
SDDACK#
SDDREQ
SDIOR#
SDIOW#
SIORDY
PCS[1:0]#
XDIR#/GPO22
XOE#/GPO23
RTCALE/GPO25
FERR#
IGNNE#
BIOSCS#
RTCCS#/GPO24
KBCCS#/GPO26
A20M#
A20GATE
MCCS#
APICCS#/GPO13
APICACK#/GPO12
APCIREQ#/GPI5
RTCX[2:1]
SMBALERT#
SMBCLK
SMBDATA
GPI[21:13,1]
GPI[12:2,0] (Multiplexed)
GPO[30,28:27,8,0]
GPO[29,26:9,7:1] (Multiplexed)
Pix4_blk
Simplified Block Diagram
82371AB (PIIX4) E
4
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
CONTENTS
PAGE
1.0. ARCHITECTURAL OVERVIEW....................................................................................................................12
2.0. SIGNAL DESCRIPTION................................................................................................................................15
2.1. PIIX4 Signals ..............................................................................................................................................16
2.1.1. PCI Bus Interface.................................................................................................................................16
2.1.2. ISA Bus Interface.................................................................................................................................18
2.1.3. X-Bus Interface....................................................................................................................................21
2.1.4. DMA Signals........................................................................................................................................23
2.1.5. Interrupt Controller/APIC Signals.........................................................................................................24
2.1.6. CPU Interface Signals .........................................................................................................................26
2.1.7. Clocking Signals..................................................................................................................................28
2.1.8. IDE Signals..........................................................................................................................................28
2.1.9. Universal Serial Bus Signals ...............................................................................................................33
2.1.10. Power Management Signals..............................................................................................................33
2.1.11. General Purpose Input and Output Signals.......................................................................................35
2.1.12. Other System and Test Signals.........................................................................................................39
2.1.13. Power and Ground Pins.....................................................................................................................39
2.2. Power Planes..............................................................................................................................................40
2.3. Power Sequencing Requirements..............................................................................................................41
3.0. REGISTER ADDRESS SPACE.....................................................................................................................42
3.1. PCI/ISA Bridge Configuration.....................................................................................................................42
3.1.1. PCI Configuration Registers (Function 0)............................................................................................43
3.1.2. IO Space Registers .............................................................................................................................44
3.2. IDE Configuration........................................................................................................................................47
3.2.1. PCI Configuration Registers (Function 1)............................................................................................47
3.2.2. IO Space Registers .............................................................................................................................48
3.3. Universal Serial Bus (USB) Configuration..................................................................................................48
3.3.1. PCI Configuration Registers (Function 2)............................................................................................48
3.3.2. IO Space Registers .............................................................................................................................49
3.4. Power Management Configuration .............................................................................................................50
3.4.1. IO Space Registers .............................................................................................................................51
4.0. PCI TO ISA/EIO BRIDGE REGISTER DESCRIPTIONS..............................................................................53
4.1. PCI to ISA/EIO Bridge PCI Configuration Space Registers (PCI Function 0)............................................53
4.1.1. VID—Vendor Identification Register (Function 0)................................................................................53
4.1.2. DID—Device Identification Register (Function 0)................................................................................53
4.1.3. PCICMD—PCI Command Register (Function 0) ................................................................................54
4.1.4. PCISTS—PCI Device Status Register (Function 0)............................................................................55
4.1.5. RID—Revision Identification Register (Function 0).............................................................................55
E 82371AB (PIIX4)
5
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
4.1.6. CLASSC—Class Code Register (Function 0).....................................................................................56
4.1.7. HEDT—Header Type Register (Function 0)........................................................................................56
4.1.8. IORT—ISA I/O Recovery Timer Register (Function 0).......................................................................56
4.1.9. XBCS—X-Bus Chip Select Register (Function 0)...............................................................................57
4.1.10. PIRQRC[A:D]—PIRQX Route Control Registers (Function 0) .........................................................59
4.1.11. SERIRQC—Serial IRQ Control Register (Function 0) ......................................................................59
4.1.12. TOM—Top of Memory Register (Function 0)....................................................................................60
4.1.13. MSTAT—Miscellaneous Status Register (Function 0)......................................................................61
4.1.14. MBDMA[1:0]—Motherboard Device DMA Control Registers (Function 0)........................................61
4.1.15. APICBASE—APIC Base Address Relocation Register (Function 0)................................................62
4.1.16. DLC—Deterministic Latency Control Register (Function 0)..............................................................62
4.1.17. PDMACFG—PCI DMA Configuration Register (Function 0).............................................................63
4.1.18. DDMABP—Distributed DMA Slave Base Pointer Registers (Function 0).........................................64
4.1.19. GENCFG—General Configuration Register (Function 0) .................................................................65
4.1.20. RTCCFG—Real Time Clock Configuration Register (Function 0)....................................................67
4.2. PCI to ISA/EIO Bridge IO Space Registers (IO) ........................................................................................68
4.2.1. DMA Registers.....................................................................................................................................68
4.2.1.1. DCOM—DMA Command Register (IO)........................................................................................68
4.2.1.2. DCM—DMA Channel Mode Register (IO)....................................................................................69
4.2.1.3. DR—DMA Request Register (IO).................................................................................................70
4.2.1.4. WSMB—Write Single Mask Bit (IO) .............................................................................................70
4.2.1.5. RWAMB—Read/Write All Mask Bits (IO).....................................................................................71
4.2.1.6. DS—DMA Status Register (IO)....................................................................................................71
4.2.1.7. DBADDR—DMA Base and Current Address Registers (IO).......................................................72
4.2.1.8. DBCNT—DMA Base and Current Count Registers (IO)..............................................................72
4.2.1.9. DLPAGE—DMA Low Page Registers (IO)...................................................................................73
4.2.1.10. DCBP—DMA Clear Byte Pointer Register (IO)..........................................................................73
4.2.1.11. DMC—DMA Master Clear Register (IO) ....................................................................................73
4.2.1.12. DCLM—DMA Clear Mask Register (IO).....................................................................................74
4.2.2. Interrupt Controller Registers...............................................................................................................74
4.2.2.1. ICW1—Initialization Command Word 1 Register (IO) ..................................................................74
4.2.2.2. ICW2—Initialization Command Word 2 Register (IO) ..................................................................75
4.2.2.3. ICW3—Initialization Command Word 3 Register (IO) ..................................................................75
4.2.2.4. ICW3—Initialization Command Word 3 Register (IO) ..................................................................76
4.2.2.5. ICW4—Initialization Command Word 4 Register (IO) ..................................................................76
4.2.2.6. OCW1—Operational Control Word 1 Register (IO)......................................................................77
4.2.2.7. OCW2—Operational Control Word 2 Register (IO)......................................................................77
4.2.2.8. OCW3— Operational Control Word 3 Register (IO).....................................................................78
4.2.2.9. ELCR1—Edge/Level Control Register (IO)..................................................................................79
4.2.2.10. ELCR2—Edge/Level Control Register (IO)................................................................................79
4.2.3. Counter/Timer Registers......................................................................................................................80
4.2.3.1. TCW—Timer Control Word Register (IO).....................................................................................80
4.2.3.2. TMRSTS—Timer Status Registers (IO).......................................................................................82
82371AB (PIIX4) E
6
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
4.2.3.3. TMRCNT—Timer Count Registers (IO) .......................................................................................82
4.2.4. NMI Registers......................................................................................................................................83
4.2.4.1. NMISC—NMI Status and Control Register (IO)...........................................................................83
4.2.4.2. NMIEN—NMI Enable Register (Shared with Real-Time Clock Index Register) (IO)...................84
4.2.5. Real Time Clock Registers..................................................................................................................84
4.2.5.1. RTCI—Real-Time Clock Index Register (Shared with NMI Enable Register) (IO) ......................84
4.2.5.2. RTCD—Real-Time Clock Data Register (IO)...............................................................................85
4.2.5.3. RTCEI—Real-Time Clock Extended Index Register (IO).............................................................85
4.2.5.4. RTCED—Real-Time Clock Extended Data Register (IO)............................................................85
4.2.6. Advanced Power Management (APM) Registers................................................................................86
4.2.6.1. APMC—Advanced Power Management Control Port (IO)...........................................................86
4.2.6.2. APMS—Advanced Power Management Status Port (IO) ............................................................86
4.2.7. X-Bus, Coprocessor, and Reset Registers .........................................................................................86
4.2.7.1. RIRQ—Reset X-Bus IRQ12/M and IRQ1 Register (IO)...............................................................86
4.2.7.2. P92—Port 92 Register (IO)...........................................................................................................87
4.2.7.3. CERR—Coprocessor Error Register (IO) ....................................................................................87
4.2.7.4. RC—Reset Control Register (IO).................................................................................................88
5.0. IDE CONTROLLER REGISTER DESCRIPTIONS (PCI FUNCTION 1) ......................................................89
5.1. IDE Controller PCI Configuration Registers (PCI Function 1)....................................................................89
5.1.1. VID—Vendor Identification Register (Function 1)................................................................................89
5.1.2. DID—Device Identification Register (Function 1)................................................................................89
5.1.3. PCICMD—PCI Command Register (Function 1) ................................................................................89
5.1.4. PCISTS—PCI Device Status Register (Function 1)............................................................................90
5.1.5. RID—Revision Identification Register (Function 1).............................................................................91
5.1.6. CLASSC—Class Code Register (Function 1).....................................................................................91
5.1.7. MLT—Master Latency Timer Register (Function 1)............................................................................91
5.1.8. HEDT—Header Type Register (Function 1)........................................................................................92
5.1.9. BMIBA—Bus Master Interface Base Address Register (Function 1)..................................................92
5.1.10. IDETIM—IDE Timing Register (Function 1) ......................................................................................93
5.1.11. SIDETIM—Slave IDE Timing Register (Function 1)..........................................................................95
5.1.12. UDMACTL—Ultra DMA/33 Control Register (Function 1) ................................................................96
5.1.13. UDMATIM—Ultra DMA/33 Timing Register (Function 1)..................................................................96
5.2. IDE Controller IO Space Registers.............................................................................................................99
5.2.1. BMICX—Bus Master IDE Command Register (IO).............................................................................99
5.2.2. BMISX—Bus Master IDE Status Register (IO) .................................................................................100
5.2.3. BMIDTPX—Bus Master IDE Descriptor Table Pointer Register (IO)................................................101
6.0. USB HOST CONTROLLER REGISTER DESCRIPTIONS (PCI FUNCTION 2)........................................102
6.1. USB Host Controller PCI Configuration Registers (PCI Function 2)........................................................102
6.1.1. VID—Vendor Identification Register (Function 2)..............................................................................102
6.1.2. DID—Device Identification Register (Function 2)..............................................................................102
6.1.3. PCICMD—PCI Command Register (Function 2) ..............................................................................103
6.1.4. PCISTS—PCI Device Status Register (Function 2)..........................................................................103
E 82371AB (PIIX4)
7
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
6.1.5. RID—Revision Identification Register (Function 2)...........................................................................104
6.1.6. CLASSC—Class Code Register (Function 2)...................................................................................104
6.1.7. MLT—Master Latency Timer Register (Function 2)..........................................................................105
6.1.8. HEDT—Header Type Register (Function 2)......................................................................................105
6.1.9. INTLN—Interrupt Line Register (Function 2).....................................................................................105
6.1.10. INTPN—Interrupt Pin (Function 2) ..................................................................................................106
6.1.11. SBRNUM—Serial Bus Release Number (Function 2) ....................................................................106
6.1.12. LEGSUP—Legacy Support Register (Function 2)..........................................................................107
6.1.13. USBBA—USB I/O Space Base Address Register (Function 2)......................................................108
6.1.14. MISCSUP—Miscellaneous Support Register (Function 2).............................................................109
6.2. USB Host Controller IO Space Registers.................................................................................................109
6.2.1. USBCMD—USB Command Register (IO) ........................................................................................109
6.2.2. USBSTS—USB Status Register (IO)................................................................................................111
6.2.3. USBINTR—USB Interrupt Enable Register (IO)...............................................................................112
6.2.4. FRNUM—Frame Number Register (IO)............................................................................................113
6.2.5. FLBASEADD—Frame List Base Address Register (IO)...................................................................113
6.2.6. SOFMOD—Start Of Frame (SOF) Modify Register (IO)...................................................................114
6.2.7. PORTSC—Port Status and Control Register (IO).............................................................................115
7.0. POWER MANAGEMENT REGISTER DESCRIPTIONS............................................................................117
7.1. Power Management PCI Configuration Registers (PCI Function 3) ........................................................117
7.1.1. VID—Vendor Identification Register (Function 3)..............................................................................117
7.1.2. DID—Device Identification Register (Function 3)..............................................................................117
7.1.3. PCICMD—PCI Command Register (Function 3) ..............................................................................117
7.1.4. PCISTS—PCI Device Status Register (Function 3)..........................................................................118
7.1.5. RID—Revision Identification Register (Function 3)...........................................................................119
7.1.6. CLASSC—Class Code Register (Function 3)...................................................................................119
7.1.7. HEDT—Header Type Register (Function 3)......................................................................................119
7.1.8. INTLN—Interrupt Line Register (Function 3).....................................................................................120
7.1.9. INTPN—Interrupt Pin (Function 3) ....................................................................................................120
7.1.10. PMBA—Power Management Base Address (Function 3)...............................................................120
7.1.11. CNTA—Count A (Function 3)..........................................................................................................121
7.1.12. CNTB—Count B (Function 3)..........................................................................................................121
7.1.13. GPICTL—General Purpose Input Control (Function 3)...................................................................123
7.1.14. DEVRESD—Device Resource D (Function 3)................................................................................123
7.1.15. DEVACTA—Device Activity A (Function 3) ....................................................................................125
7.1.16. DEVACTB—Device Activity B (Function 3) ....................................................................................126
7.1.17. DEVRESA—Device Resource A (Function 3)................................................................................127
7.1.18. DEVRESB—Device Resource B (Function 3)................................................................................129
7.1.19. DEVRESC—Device Resource C (Function 3)................................................................................130
7.1.20. DEVRESE—Device Resource E (Function 3)................................................................................131
7.1.21. DEVRESF—Device Resource F (Function 3).................................................................................131
7.1.22. DEVRESG—Device Resource G (Function 3) ...............................................................................132
82371AB (PIIX4) E
8
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
7.1.23. DEVRESH—Device Resource H (Function 3)................................................................................133
7.1.24. DEVRESI—Device Resource I (Function 3)...................................................................................133
7.1.25. DEVRESJ
Device Resource J (Function 3) .................................................................................134
7.1.26. PMREGMISC
Miscellaneous Power Management (Function 3)..................................................134
7.1.27. SMBBA—SMBUS Base Address (Function 3)................................................................................135
7.1.28. SMBHSTCFG
SMBUS Host Configuration (Function 3)..............................................................135
7.1.29. SMBSLVC
SMBUS Slave Command (Function 3).......................................................................135
7.1.30. SMBSHDW1
SMBUS Slave Shadow Port 1 (Function 3)............................................................136
7.1.31. SMBSHDW2
SMBUS Slave Shadow Port 2 (Function 3)............................................................136
7.1.32. SMBREV
SMBUS Revision Identification (Function 3) ................................................................136
7.2. Power Management IO Space Registers.................................................................................................137
7.2.1. PMSTS
Power Management Status Register (IO) .........................................................................137
7.2.2. PMEN
Power Management Resume Enable Register (IO)............................................................138
7.2.3. PMCNTRL
Power Management Control Register (IO)...................................................................138
7.2.4. PMTMR
Power Management Timer Register (IO)..........................................................................139
7.2.5. GPSTS
General Purpose Status Register (IO) ..............................................................................139
7.2.6. GPEN
General Purpose Enable Register (IO) ...............................................................................140
7.2.7. PCNTRL
Processor Control Register (IO)......................................................................................141
7.2.8. PLVL2
Processor Level 2 Register (IO) .........................................................................................142
7.2.9. PLVL3
Processor Level 3 Register (IO) ........................................................................................142
7.2.10. GLBSTS
Global Status Register (IO) ...........................................................................................143
7.2.11. DEVSTS
Device Status Register (IO) ..........................................................................................144
7.2.12. GLBEN
Global Enable Register (IO) ............................................................................................144
7.2.13. GLBCTL
Global Control Register (IO)..........................................................................................145
7.2.14. DEVCTL
Device Control Register (IO).........................................................................................146
7.2.15. GPIREG
General Purpose Input Register (IO).............................................................................147
7.2.16. GPOREG
General Purpose Output Register (IO)........................................................................148
7.3. SMBus IO Space Registers......................................................................................................................148
7.3.1. SMBHSTSTS
SMBus Host Status Register (IO)............................................................................148
7.3.2. SMBSLVSTS
SMBus Slave Status Register (IO) ..........................................................................149
7.3.3. SMBHSTCNT
SMBus Host Control Register (IO)..........................................................................150
7.3.4. SMBHSTCMD
SMBus Host Command Register (IO)....................................................................150
7.3.5. SMBHSTADD
SMBus Host Address Register (IO)........................................................................151
7.3.6. SMBHSTDAT0
SMBus Host Data 0 Register (IO).........................................................................151
7.3.7. SMBHSTDAT1
SMBus Host Data 1 Register (IO).........................................................................151
7.3.8. SMBBLKDAT
SMBus Block Data Register (IO).............................................................................152
7.3.9. SMBSLVCNT
SMBus Slave Control Register (IO).........................................................................152
7.3.10. SMBSHDWCMD
SMBus Shadow Command Register (IO).........................................................153
7.3.11. SMBSLVEVT
SMBus Slave Event Register (IO) .........................................................................153
7.3.12. SMBSLVDAT
SMBus Slave Data Register (IO)...........................................................................153
8.0. PCI/ISA BRIDGE FUNCTIONAL DESCRIPTION ......................................................................................154
8.1. Memory and IO Address Map...................................................................................................................154
E 82371AB (PIIX4)
9
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
8.1.1. I/O Accesses .....................................................................................................................................154
8.1.2. Memory Address Map........................................................................................................................154
8.1.3. BIOS Memory....................................................................................................................................155
8.2. PCI Interface.............................................................................................................................................157
8.2.1. Transaction Termination....................................................................................................................157
8.2.2. Parity Support....................................................................................................................................157
8.2.3. PCI Arbitration....................................................................................................................................157
8.3. ISA/EIO Interface......................................................................................................................................158
8.4. DMA Controller .........................................................................................................................................158
8.4.1. DMA Transfer Modes.........................................................................................................................159
8.4.2. DMA Transfer Types .........................................................................................................................160
8.4.3. DMA Timings .....................................................................................................................................161
8.4.4. DMA Buffer for Type F Transfers ......................................................................................................161
8.4.5. DREQ and DACK# Latency Control..................................................................................................161
8.4.6. Channel Priority .................................................................................................................................162
8.4.7. Register Functionality........................................................................................................................162
8.4.8. Address Compatibility Mode..............................................................................................................162
8.4.9. Summary of DMA Transfer Sizes......................................................................................................163
8.4.9.1. Address Shifting When Programmed for 16-Bit I/O Count by Words.........................................163
8.4.10. Autoinitialize.....................................................................................................................................163
8.4.11. Software Commands.......................................................................................................................164
8.4.12. ISA Refresh Cycles .........................................................................................................................164
8.5. PCI DMA...................................................................................................................................................165
8.5.1. PC/PCI DMA......................................................................................................................................165
8.5.2. Distributed DMA.................................................................................................................................168
8.6. Interrupt Controller....................................................................................................................................171
8.6.1. Programming the Interrupt Controller ................................................................................................172
8.6.2. End-of-Interrupt Operation.................................................................................................................173
8.6.3. Modes of Operation ...........................................................................................................................173
8.6.4. Cascade Mode...................................................................................................................................175
8.6.5. Edge and Level Triggered Mode........................................................................................................175
8.6.6. Interrupt Masks..................................................................................................................................176
8.6.7. Reading the Interrupt Controller Status.............................................................................................176
8.6.8. Interrupt Steering...............................................................................................................................177
8.7. Serial Interrupts.........................................................................................................................................178
8.7.1. Protocol..............................................................................................................................................178
8.8. Timer/Counters.........................................................................................................................................180
8.8.1. Programming the Interval Timer ........................................................................................................180
8.9. Real Time Clock .......................................................................................................................................183
8.9.1. RTC Registers and RAM...................................................................................................................183
8.9.1.1. Control Register A.......................................................................................................................185
8.9.1.2. Control Register B.......................................................................................................................186
8.9.1.3. Control Register C ......................................................................................................................187
82371AB (PIIX4) E
10
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
8.9.1.4. Control Register D ......................................................................................................................187
8.9.2. RTC Update Cycle.............................................................................................................................188
8.9.3. RTC Interrupts...................................................................................................................................188
8.9.4. Lockable RAM Ranges......................................................................................................................188
8.9.5. RTC External Connections................................................................................................................188
8.10. X-Bus Support ........................................................................................................................................188
8.11. Reset Support.........................................................................................................................................189
8.12. Stand-Alone I/O APIC Support...............................................................................................................190
9.0. IDE CONTROLLER FUNCTIONAL DESCRIPTION ..................................................................................191
9.1. IDE Signal Configuration...........................................................................................................................191
9.2. ATA Register Block Decode.....................................................................................................................192
9.3. PIO IDE Transactions...............................................................................................................................193
9.4. Bus Master Function.................................................................................................................................195
9.5. “Ultra DMA/33” Synchronous DMA Operation..........................................................................................197
10.0. USB HOST CONTROLLER FUNCTIONAL DESCRIPTION ...................................................................199
11.0. POWER MANAGEMENT FUNCTIONAL DESCRIPTION .......................................................................201
11.1. Power Management Overview ...............................................................................................................201
11.2. Clock Control..........................................................................................................................................202
11.2.1. Host Clock Control Mechanisms.....................................................................................................202
11.2.2. Stop Clock and Deep Sleep State Example Sequence...................................................................208
11.2.3. PCI Clock Control............................................................................................................................210
11.3. Peripheral Device Management .............................................................................................................210
11.3.1. Device Idle Timer.............................................................................................................................211
11.3.2. Device Trap .....................................................................................................................................212
11.3.3. Peripheral Device Management Sequence.....................................................................................212
11.3.4. Device Location on PCI Bus or ISA Bus .........................................................................................212
11.3.5. Device Specific Details....................................................................................................................215
11.3.5.1. Device 0: IDE Primary Drive 0..................................................................................................215
11.3.5.2. Device 1: IDE Primary Drive 1..................................................................................................216
11.3.5.3. Device 2: IDE Secondary Drive 0.............................................................................................216
11.3.5.4. Device 3: IDE Secondary Drive 1.............................................................................................217
11.3.5.5. Device 4: Audio.........................................................................................................................218
11.3.5.6. Device 5: Floppy Disk Drive .....................................................................................................219
11.3.5.7. Device 6: Serial Port A..............................................................................................................220
11.3.5.8. Device 7: Serial Port B..............................................................................................................221
11.3.5.9. Device 8: LPT (Parallel Port)....................................................................................................222
11.3.5.10. Device 9: Generic I/O Device 0..............................................................................................223
11.3.5.11. Device 10: Generic I/O Device 1............................................................................................224
11.3.5.12. Device 11: User Interface (Keyboard, Mouse, Video)............................................................225
11.3.5.13. Device 12: Cardbus Slot (or Generic I/O and MEM Device)..................................................226
11.3.5.14. Device 13: Cardbus Slot (or Generic I/O and MEM Device)..................................................227
E 82371AB (PIIX4)
11
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
11.4. Suspend/Resume and Power Plane Control..........................................................................................228
11.4.1. System Suspend..............................................................................................................................228
11.4.2. System Resume ..............................................................................................................................230
11.4.3. System Suspend and Resume Control Signaling............................................................................232
11.4.3.1. Power Supply Timings..............................................................................................................232
11.4.3.2. Power Level Active Status Signal Timings...............................................................................233
11.4.3.3. Power Management Signal Timings (Powered From Suspend Power Well) ...........................234
11.4.3.4. PCI Clock Stop and Start Timing Relationships.......................................................................235
11.4.3.5. Power Management Signal Timings (Powered From PIIX4 Main Core Well) ..........................236
11.4.3.6. Power Management Signal Timings (Powered From PIIX4 Main Core Well) ..........................238
11.4.3.7. Mechanical Off to On Condition Timings..................................................................................240
11.4.3.8. On State to Power On Suspend State Timing..........................................................................242
11.4.3.9. Power On Suspend to On Timing (With a Full System Reset).................................................244
11.4.3.10. System Transition From Power On Suspend to On (With Only Processor Reset)................246
11.4.3.11. Power On Suspend to On Timing (With No Resets)..............................................................248
11.4.3.12. On State to Suspend to RAM State Timing............................................................................250
11.4.3.13. Suspend-To-RAM to On Timing (With Full System Reset)....................................................252
11.4.3.14. On State to Suspend to Disk/Soft Off State Timings..............................................................254
11.4.3.15. Suspend-To-Disk to On (With Full System Reset).................................................................256
11.4.4. Shadow Registers............................................................................................................................258
11.5. System Management..............................................................................................................................262
11.5.1. SMI Operation..................................................................................................................................262
11.5.2. SMI# Generation Events..................................................................................................................263
11.5.3. Global Standby Timer Operation.....................................................................................................265
11.5.4. SMBus Functional Description ........................................................................................................266
11.5.4.1. SMBus Host Interface...............................................................................................................266
11.5.4.2. SMBus Slave Interface.............................................................................................................267
11.6. ACPI Support..........................................................................................................................................268
11.6.1. SCI Generation................................................................................................................................268
11.6.2. Power Management Timer...............................................................................................................268
11.6.3. Global Lock......................................................................................................................................269
12.0. PINOUT INFORMATION...........................................................................................................................270
13.0. PIIX4 PACKAGE INFORMATION.............................................................................................................274
14.0. TESTABILITY ............................................................................................................................................277
14.1. Test Mode Description............................................................................................................................277
14.2. Tri-state Mode.........................................................................................................................................278
14.3. NAND Tree Mode...................................................................................................................................278
82371AB (PIIX4) E
12
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
1.0. ARCHITECTURAL OVERVIEW
PIIX4 is a multi-function PCI device that integrates many system-level functions. Figure 1 shows an example
system block diagram using PIIX4.
PCI Bus (3.3V or 5V, 30/33 MHz)
Main
Memory
(DRAM)
Processor
Host Bus
Second Level
Cache
Host-to-PCI
Bridge
BMI IDE
Ultra DMA/33
CD ROM
Hard
Disk
ISA/EIO Bus
(3.3V; 5V Tolerant)
USB 2
USB 1
82371AB
(PIIX4)
GP[I,O] (30+)
SMBus
Audio
KBD
SP, PP,
FDC, IR
BIOS
PCI Slots
Hard
Disk
pix4_sys
Figure 1. PIIX4 System Block Diagram
PCI to ISA/EIO Bridge
PIIX4 is compatible with the PCI Rev 2.1 specification, as well as the IEEE 996 specification for the ISA (AT)
bus. On PCI, PIIX4 operates as a master for various internal modules, such as the USB controller, DMA
controller, IDE bus master controller, distributed DMA masters, and on behalf of ISA masters. PIIX4 operates as
a slave for its internal registers or for cycles that are passed to the ISA or EIO buses. All internal registers are
positively decoded.
E 82371AB (PIIX4)
13
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
PIIX4 can be configured for a full ISA bus or a subset of the ISA bus called the Extended IO (EIO) bus. The use
of the EIO bus allows unused signals to be configured as general purpose inputs and outputs. PIIX4 can directly
drive up to five ISA slots without external data or address buffering. It also provides byte-swap logic, I/O
recovery support, wait-state generation, and SYSCLK generation. X-Bus chip selects are provided for Keyboard
Controller, BIOS, Real Time Clock, a second microcontroller, as well as two programmable chip selects.
PIIX4 can be configured as either a subtractive decode PCI to ISA bridge or as a positive decode bridge. This
gives a system designer the option of placing another subtractive decode bridge in the system (e.g., an Intel
380FB Dock Set).
IDE Interface (Bus Master capability and synchronous DMA Mode)
The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks and CD ROMs.
Each IDE device can have independent timings. The IDE interface supports PIO IDE transfers up to 14
Mbytes/sec and Bus Master IDE transfers up to 33 Mbytes/sec. It does not consume any ISA DMA resources.
The IDE interface integrates 16x32-bit buffers for optimal transfers.
PIIX4’s IDE system contains two independent IDE signal channels. They can be electrically isolated
independently, allowing for the implementation of a “glueless” Swap Bay. They can be configured to the standard
primary and secondary channels (four devices) or primary drive 0 and primary drive 1 channels (two devices).
This allows flexibility in system design and device power management.
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven independently
programmable channels. Channels [0:3] are hardwired to 8-bit, count-by-byte transfers, and channels [5:7] are
hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA channels can be programmed to
support fast Type-F transfers. The DMA controller also generates the ISA refresh cycles.
The DMA controller supports two separate methods for handling legacy DMA via the PCI bus. The PC/PCI
protocol allows PCI-based peripherals to initiate DMA cycles by encoding requests and grants via three PC/PCI
REQ#/GNT# pairs. The second method, Distributed DMA, allows reads and writes to 82C37 registers to be
distributed to other PCI devices. The two methods can be enabled concurrently. The serial interrupt scheme
typically associated with Distributed DMA is also supported.
The timer/counter block contains three counters that are equivalent in function to those found in one 82C54
programmable interval timer. These three counters are combined to provide the system timer function, refresh
request, and speaker tone. The 14.31818-MHz oscillator input provides the clock source for these three
counters.
PIIX4 provides an ISA-Compatible interrupt controller that incorporates the functionality of two 82C59 interrupt
controllers. The two interrupt controllers are cascaded so that 14 external and two internal interrupts are
possible. In addition, PIIX4 supports a serial interrupt scheme. PIIX4 provides full support for the use of an
external IO APIC.
All of the registers in these modules can be read and restored. This is required to save and restore system state
after power has been removed and restored to the circuit.
Enhanced Universal Serial Bus (USB) Controller
The PIIX4 USB controller provides enhanced support for the Universal Host Controller Interface (UHCI). This
includes support that allows legacy software to use a USB-based keyboard and mouse.
82371AB (PIIX4) E
14
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
RTC
PIIX4 contains a Motorola* MC146818A-compatible real-time clock with 256 bytes of battery-backed RAM. The
real-time clock performs two key functions: keeping track of the time of day and storing system data, even when
the system is powered down. The RTC operates on a 32.768-kHz crystal and a separate 3V lithium battery that
provides up to 7 years of protection.
The RTC also supports two lockable memory ranges. By setting bits in the configuration space, two 8-byte
ranges can be locked to read and write accesses. This prevents unauthorized reading of passwords or other
system security information.
The RTC also supports a date alarm, that allows for scheduling a wake up event up to 30 days in advance,
rather than just 24 hours in advance.
GPIO and Chip Selects
Various general purpose inputs and outputs are provided for custom system design. The number of inputs and
outputs varies depending on PIIX4 configuration. Two programmable chip selects are provided which allows the
designer to place devices on the X-Bus without the need for external decode logic.
Pentium
®
and Pentium® II Processor Interface
The PIIX4 CPU interface allows connection to all Pentium and Pentium II processors. The Sleep mode for the
Pentium II processors is also supported.
Enhanced Power Management
PIIX4’s power management functions include enhanced clock control, local and global monitoring support for 14
individual devices, and various low-power (suspend) states, such as Power-On Suspend, Suspend-to-DRAM,
and Suspend-to-Disk. A hardware-based thermal management circuit permits software-independent entrance to
low-power states. PIIX4 has dedicated pins to monitor various external events (e.g., interfaces to a notebook lid,
suspend/resume button, battery low indicators, etc.). PIIX4 contains full support for the Advanced Configuration
and Power Interface (ACPI) Specification.
System Management Bus (SMBus)
PIIX4 contains an SMBus Host interface that allows the CPU to communicate with SMBus slaves and an SMBus
Slave interface that allows external masters to activate power management events.
Configurability
PIIX4 provides a wide range of system configuration options. This includes full 16-bit I/O decode on internal
modules, dynamic disable on all the internal modules, various peripheral decode options, and many options on
system configuration.
E 82371AB (PIIX4)
15
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
2.0. SIGNAL DESCRIPTION
This section provides a detailed description of each signal. The signals are arranged in functional groups
according to their associated interface.
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is
at a low voltage level. When “#” is not present after the signal name, the signal is asserted when at the high
voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a
mixture of “active low” and “active high” signal. The term assert, or assertion indicates that a signal is active,
independent of whether that level is represented by a high or low voltage. The term negate, or negation indicates
that a signal is inactive.
Certain signals have different functions, depending on the configuration programmed in the PCI configuration
space. The signal whose function is being described is in bold font. Some of the signals are multiplexed with
General Purpose Inputs and Outputs. The default configuration and control bits for each are described in Table 1
and Table 2.
Each output signal description includes the value of the signal During Reset, After Reset, and During POS.
During Reset refers to when the PCIRST# signal is asserted. After Reset is immediately after negation of
PCIRST# and the signal may change value anytime thereafter. The term High-Z means tri-stated. The term
Undefined means the signal could be high, low, tri-stated, or in some in-between level. Some of the power
management signals are reset with the RSMRST# input signal. The functionality of these signals during
RSMRST# assertion is described in the Suspend/Resume and Power Plane Control section.
The I/O buffer types are shown below:
Buffer Type Description
I input only signal
O totem pole output
I/O bi-direction, tri-state input/output pin
s/t/s sustained tri-state
OD open drain
I/OD input/open drain output is a standard input buffer with an open drain output
V This is not a standard signal. It is a power supply pin.
3.3V/2.5V Indicates the buffer is 3.3V or 2.5V only, depending on the voltage (3.3V or 2.5V) connected to
V
CCX pins.
3.3V/5V Indicates that the output is 3.3V and input is 3.3V receiver with 5V tolerance.
5V Indicates 3.3V receiver with 5V tolerance.
All 3V output signals can drive 5V TTL inputs. Most of the 3V input signals are 5V tolerant. The 3V input signals
which are powered via the RTC or Suspend power planes should not exceed their power supply voltage (see
Power Planes chapter for additional information). The open drain (OD) CPU interface signals should be pulled up
to the CPU interface signal voltage.
82371AB (PIIX4) E
16
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
2.1. PIIX4 Signals
2.1.1. PCI BUS INTERFACE
Name Type Description
AD[31:0] I/O PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During the first
clock of a transaction, AD[31:0] contain a physical byte address (32 bits). During
subsequent clocks, AD[31:0] contain data.
A PIIX4 Bus transaction consists of an address phase followed by one or more data
phases. Little-endian byte ordering is used. AD[7:0] define the least significant byte
(LSB) and AD[31:24] the most significant byte (MSB).
When PIIX4 is a Target, AD[31:0] are inputs during the address phase of a transaction.
During the following data phase(s), PIIX4 may be asked to supply data on AD[31:0] for
a PCI read, or accept data for a PCI write.
As an Initiator, PIIX4 drives a valid address on AD[31:2] and 0 on AD[1:0] during the
address phase, and drives write or latches read data on AD[31:0] during the data
phase.
During Reset: High-Z After Reset: High-Z During POS: High-Z
C/BE#[3:0] I/O BUS COMMAND AND BYTE ENABLES. The command and byte enable signals are
multiplexed on the same PCI pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are used as
Byte Enables. The Byte Enables determine which byte lanes carry meaningful data.
C/BE0# applies to byte 0, C/BE1# to byte 1, etc. PIIX4 drives C/BE[3:0]# as an Initiator
and monitors C/BE[3:0]# as a Target.
During Reset: High-Z After Reset: High-Z During POS: High-Z
CLKRUN# I/O CLOCK RUN#. This signal is used to communicate to PCI peripherals that the PCI
clock will be stopped. Peripherals can assert CLKRUN# to request that the PCI clock
be restarted or to keep it from stopping. This function follows the protocol described in
the PCI Mobile Design Guide, Revision 1.0.
During Reset: Low After Reset: Low During POS: High
DEVSEL# I/O DEVICE SELECT. PIIX4 asserts DEVSEL# to claim a PCI transaction through positive
decoding or subtractive decoding (if enabled). As an output, PIIX4 asserts DEVSEL#
when it samples IDSEL active in configuration cycles to PIIX4 configuration registers.
PIIX4 also asserts DEVSEL# when an internal PIIX4 address is decoded or when PIIX4
subtractively or positively decodes a cycle for the ISA/EIO bus or IDE device. As an
input, DEVSEL# indicates the response to a PIIX4 initiated transaction and is also
sampled when deciding whether to subtractively decode the cycle. DEVSEL# is tristated from the leading edge of PCIRST#. DEVSEL# remains tri-stated until driven by
PIIX4 as a target.
During Reset: High-Z After Reset: High-Z During POS: High-Z
FRAME# I/O CYCLE FRAME. FRAME# is driven by the current Initiator to indicate the beginning and
duration of an access. While FRAME# is asserted data transfers continue. When
FRAME# is negated the transaction is in the final data phase. FRAME# is an input to
PIIX4 when it is the Target. FRAME# is an output when PIIX4 is the initiator. FRAME#
remains tri-stated until driven by PIIX4 as an Initiator.
During Reset: High-Z After Reset: High-Z During POS: High-Z
E 82371AB (PIIX4)
17
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Name Type Description
IDSEL I INITIALIZATION DEVICE SELECT. IDSEL is used as a chip select during PCI
configuration read and write cycles. PIIX4 samples IDSEL during the address phase of
a transaction. If IDSEL is sampled active, and the bus command is a configuration read
or write, PIIX4 responds by asserting DEVSEL# on the next cycle.
IRDY# I/O INITIATOR READY. IRDY# indicates PIIX4’s ability, as an Initiator, to complete the
current data phase of the transaction. It is used in conjunction with TRDY#. A data
phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During
a write, IRDY# indicates PIIX4 has valid data present on AD[31:0]. During a read, it
indicates PIIX4 is prepared to latch data. IRDY# is an input to PIIX4 when PIIX4 is the
Target and an output when PIIX4 is an Initiator. IRDY# remains tri-stated until driven by
PIIX4 as a master.
During Reset: High-Z After Reset: High-Z During POS: High-Z
PAR O CALCULATED PARITY SIGNAL. PAR is “even” parity and is calculated on 36 bits;
AD[31:0] plus C/BE[3:0]#. “Even” parity means that the number of “1”s within the
36 bits plus PAR are counted and the sum is always even. PAR is always calculated on
36 bits regardless of the valid byte enables. PAR is generated for address and data
phases and is only guaranteed to be valid one PCI clock after the corresponding
address or data phase. PAR is driven and tri-stated identically to the AD[31:0] lines
except that PAR is delayed by exactly one PCI clock. PAR is an output during the
address phase (delayed one clock) for all PIIX4 initiated transactions. It is also an
output during the data phase (delayed one clock) when PIIX4 is the Initiator of a PCI
write transaction, and when it is the Target of a read transaction.
During Reset: High-Z After Reset: High-Z During POS: High-Z
PCIRST# O PCI RESET. PIIX4 asserts PCIRST# to reset devices that reside on the PCI bus. PIIX4
asserts PCIRST# during power-up and when a hard reset sequence is initiated through
the RC register. PCIRST# is driven inactive a minimum of 1 ms after PWROK is driven
active. PCIRST# is driven for a minimum of 1 ms when initiated through the RC register.
PCIRST# is driven asynchronously relative to PCICLK.
During Reset: Low After Reset: High During POS: High
PHOLD# O PCI HOLD. An active low assertion indicates that PIIX4 desires use of the PCI Bus.
Once the PCI arbiter has asserted PHLDA# to PIIX4, it may not negate it until PHOLD#
is negated by PIIX4. PIIX4 implements the passive release mechanism by toggling
PHOLD# inactive for one PCICLK.
During Reset: High-Z After Reset: High During POS: High
PHLDA# I PCI HOLD ACKNOWLEDGE. An active low assertion indicates that PIIX4 has been
granted use of the PCI Bus. Once PHLDA# is asserted, it cannot be negated unless
PHOLD# is negated first.
SERR# I/O SYSTEM ERROR. SERR# can be pulsed active by any PCI device that detects a
system error condition. Upon sampling SERR# active, PIIX4 can be programmed to
generate a non-maskable interrupt (NMI) to the CPU.
During Reset: High-Z After Reset: High-Z During POS: High-Z
82371AB (PIIX4) E
18
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Name Type Description
STOP# I/O STOP. STOP# indicates that PIIX4, as a Target, is requesting an initiator to stop the
current transaction. As an Initiator, STOP# causes PIIX4 to stop the current transaction.
STOP# is an output when PIIX4 is a Target and an input when PIIX4 is an Initiator.
STOP# is tri-stated from the leading edge of PCIRST#. STOP# remains tri-stated until
driven by PIIX4 as a slave.
During Reset: High-Z After Reset: High-Z During POS: High-Z
TRDY# I/O TARGET READY. TRDY# indicates PIIX4’s ability to complete the current data phase
of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is
completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY#
indicates that PIIX4, as a Target, has place valid data on AD[31:0]. During a write, it
indicates PIIX4, as a Target is prepared to latch data. TRDY# is an input to PIIX4 when
PIIX4 is the Initiator and an output when PIIX4 is a Target. TRDY# is
tri-stated from the leading edge of PCIRST#. TRDY# remains tri-stated until driven
by PIIX4 as a slave.
During Reset: High-Z After Reset: High-Z During POS: High-Z
NOTES:
All of the signals in the host interface are described in the Pentium Processor data sheet. The preceding table
highlights PIIX4 specific uses of these signals.
2.1.2. ISA BUS INTERFACE
Name Type Description
AEN O ADDRESS ENABLE. AEN is asserted during DMA cycles to prevent I/O slaves from
misinterpreting DMA cycles as valid I/O cycles. When negated, AEN indicates that an
I/O slave may respond to address and I/O commands. When asserted, AEN informs
I/O resources on the ISA bus that a DMA transfer is occurring. This signal is also
driven high during PIIX4 initiated refresh cycles.
During Reset: High-Z After Reset: Low During POS: Low
BALE O BUS ADDRESS LATCH ENABLE. BALE is asserted by PIIX4 to indicate that the
address (SA[19:0], LA[23:17]) and SBHE# signal lines are valid. The LA[23:17]
address lines are latched on the trailing edge of BALE. BALE remains asserted
throughout DMA and ISA master cycles.
During Reset: High-Z After Reset: Low During POS: Low
IOCHK#/
GPI0
I I/O CHANNEL CHECK. IOCHK# can be driven by any resource on the ISA bus.
When asserted, it indicates that a parity or an uncorrectable error has occurred for
a device or memory on the ISA bus. A NMI will be generated to the CPU if the NMI
generation is enabled. If the EIO bus is used, this signal becomes a general purpose
input.
E 82371AB (PIIX4)
19
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Name Type Description
IOCHRDY I/O I/O CHANNEL READY. Resources on the ISA Bus negate IOCHRDY to indicate that
wait states are required to complete the cycle. This signal is normally high. IOCHRDY
is an input when PIIX4 owns the ISA Bus and the CPU or a PCI agent is accessing an
ISA slave, or during DMA transfers. IOCHRDY is output when an external ISA Bus
Master owns the ISA Bus and is accessing DRAM or a PIIX4 register. As a PIIX4
output, IOCHRDY is driven inactive (low) from the falling edge of the ISA commands.
After data is available for an ISA master read or PIIX4 latches the data for a write
cycle, IOCHRDY is asserted for 70 ns. After 70 ns, PIIX4 floats IOCHRDY. The 70 ns
includes both the drive time and the time it takes PIIX4 to float IOCHRDY. PIIX4 does
not drive this signal when an ISA Bus master is accessing an ISA Bus slave.
During Reset: High-Z After Reset: High-Z During POS: High-Z
IOCS16# I 16-BIT I/O CHIP SELECT. This signal is driven by I/O devices on the ISA Bus to
indicate support for 16-bit I/O bus cycles.
IOR# I/O I/O READ. IOR# is the command to an ISA I/O slave device that the slave may drive
data on to the ISA data bus (SD[15:0]). The I/O slave device must hold the data valid
until after IOR# is negated. IOR# is an output when PIIX4 owns the ISA Bus. IOR# is
an input when an external ISA master owns the ISA Bus.
During Reset: High-Z After Reset: High During POS: High
IOW# I/O I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave may latch
data from the ISA data bus (SD[15:0]). IOW# is an output when PIIX4 owns the ISA
Bus. IOW# is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z After Reset: High During POS: High
LA[23:17]/
GPO[7:1]
I/O ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory on the
ISA Bus up to 16 Mbytes. LA[23:17] are outputs when PIIX4 owns the ISA Bus. The
LA[23:17] lines become inputs whenever an ISA master owns the ISA Bus.
If the EIO bus is used, these signals become a general purpose output.
During Reset: High-Z After Reset: Undefined During POS: Last LA/GPO
MEMCS16# I/O MEMORY CHIP SELECT 16. MEMCS16# is a decode of LA[23:17] without any
qualification of the command signal lines. ISA slaves that are 16-bit memory devices
drive this signal low. PIIX4 ignores MEMCS16# during I/O access cycles and refresh
cycles. MEMCS16# is an input when PIIX4 owns the ISA Bus. PIIX4 drives this signal
low during ISA master to PCI memory cycles.
During Reset: High-Z After Reset: High-Z During POS: High-Z
MEMR# I/O MEMORY READ. MEMR# is the command to a memory slave that it may drive data
onto the ISA data bus. MEMR# is an output when PIIX4 is a master on the ISA Bus.
MEMR# is an input when an ISA master, other than PIIX4, owns the ISA Bus. This
signal is also driven by PIIX4 during refresh cycles. For DMA cycles, PIIX4, as a
master, asserts MEMR#.
During Reset: High-Z After Reset: High During POS: High
82371AB (PIIX4) E
20
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Name Type Description
MEMW# I/O MEMORY WRITE. MEMW# is the command to a memory slave that it may latch data
from the ISA data bus. MEMW# is an output when PIIX4 owns the ISA Bus. MEMW#
is an input when an ISA master, other than PIIX4, owns the ISA Bus. For DMA cycles,
PIIX4, as a master, asserts MEMW#.
During Reset: High-Z After Reset: High During POS: High
REFRESH# I/O REFRESH. As an output, REFRESH# is used by PIIX4 to indicate when a refresh
cycle is in progress. It should be used to enable the SA[7:0] address to the row
address inputs of all banks of dynamic memory on the ISA Bus. Thus, when MEMR#
is asserted, the entire expansion bus dynamic memory is refreshed. Memory slaves
must not drive any data onto the bus during refresh. As an output, this signal is driven
directly onto the ISA Bus. This signal is an output only when PIIX4 DMA refresh
controller is a master on the bus responding to an internally generated request for
refresh.
As an input, REFRESH# is driven by 16-bit ISA Bus masters to initiate refresh cycles.
During Reset: High-Z After Reset: High During POS: High
RSTDRV O RESET DRIVE. PIIX4 asserts RSTDRV to reset devices that reside on the ISA/EIO
Bus. PIIX4 asserts this signal during a hard reset and during power-up. RSTDRV is
asserted during power-up and negated after PWROK is driven active. RSTDRV is
also driven active for a minimum of 1 ms if a hard reset has been programmed in the
RC register.
During Reset: High After Reset: Low During POS: Low
SA[19:0] I/O SYSTEM ADDRESS[19:0]. These bi-directional address lines define the selection
with the granularity of 1 byte within the 1-Megabyte section of memory defined by the
LA[23:17] address lines. The address lines SA[19:17] that are coincident with
LA[19:17] are defined to have the same values as LA[19:17] for all memory cycles.
For I/O accesses, only SA[15:0] are used, and SA[19:16] are undefined. SA[19:0] are
outputs when PIIX4 owns the ISA Bus. SA[19:0] are inputs when an external ISA
Master owns the ISA Bus.
During Reset: High-Z After Reset: Undefined During POS: Last SA
SBHE# I/O SYSTEM BYTE HIGH ENABLE. SBHE# indicates, when asserted, that a byte is
being transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated
during refresh cycles. SBHE# is an output when PIIX4 owns the ISA Bus. SBHE# is
an input when an external ISA master owns the ISA Bus.
During Reset: High-Z After Reset: Undefined During POS: High
SD[15:0] I/O SYSTEM DATA. SD[15:0] provide the 16-bit data path for devices residing on the ISA
Bus. SD[15:8] correspond to the high order byte and SD[7:0] correspond to the low
order byte. SD[15:0] are undefined during refresh.
During Reset: High-Z After Reset: Undefined During POS: High-Z
SMEMR# O STANDARD MEMORY READ. PIIX4 asserts SMEMR# to request an ISA memory
slave to drive data onto the data lines. If the access is below the 1-Mbyte range
(00000000h–000FFFFFh) during DMA compatible, PIIX4 master, or ISA master
cycles, PIIX4 asserts SMEMR#. SMEMR# is a delayed version of MEMR#.
During Reset: High-Z After Reset: High During POS: High
E 82371AB (PIIX4)
21
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Name Type Description
SMEMW# O STANDARD MEMORY WRITE. PIIX4 asserts SMEMW# to request an ISA memory
slave to accept data from the data lines. If the access is below the 1-Mbyte range
(00000000h–000FFFFFh) during DMA compatible, PIIX4 master, or ISA master
cycles, PIIX4 asserts SMEMW#. SMEMW# is a delayed version of MEMW#.
During Reset: High-Z After Reset: High During POS: High
ZEROWS# I ZERO WAIT STATES. An ISA slave asserts ZEROWS# after its address and
command signals have been decoded to indicate that the current cycle can be
shortened. A 16-bit ISA memory cycle can be reduced to two SYSCLKs. An 8-bit
memory or I/O cycle can be reduced to three SYSCLKs. ZEROWS# has no effect
during 16-bit I/O cycles.
If IOCHRDY is negated and ZEROWS# is asserted during the same clock, then
ZEROWS# is ignored and wait states are added as a function of IOCHRDY.
2.1.3. X-BUS INTERFACE
Name Type Description
A20GATE I ADDRESS 20 GATE. This input from the keyboard controller is logically combined with
bit 1 (FAST_A20) of the Port 92 Register, which is then output via the A20M# signal.
BIOSCS# O BIOS CHIP SELECT. This chip select is driven active during read or write accesses to
enabled BIOS memory ranges. BIOSCS# is driven combinatorially from the ISA
addresses SA[16:0] and LA[23:17], except during DMA cycles. During DMA cycles,
BIOSCS# is not generated.
During Reset: High After Reset: High During POS: High
KBCCS#/
GPO26
O KEYBOARD CONTROLLER CHIP SELECT. KBCCS# is asserted during I/O read or
write accesses to KBC locations 60h and 64h. It is driven combinatorially from the ISA
addresses SA[19:0] and LA[23:17].
If the keyboard controller does not require a separate chip select, this signal can be
programmed to a general purpose output.
During Reset: High After Reset: High During POS: High/GPO
MCCS# O MICROCONTROLLER CHIP SELECT. MCCS# is asserted during I/O read or write
accesses to IO locations 62h and 66h. It is driven combinatorially from the ISA
addresses SA[19:0] and LA[23:17].
During Reset: High After Reset: High During POS: High
PCS0#
PCS1#
O PROGRAMMABLE CHIP SELECTS. These active low chip selects are asserted for
ISA I/O cycles which are generated by PCI masters and which hit the programmable
I/O ranges defined in the Power Management section. The X-Bus buffer signals (XOE#
and XDIR#) are enabled while the chip select is active. (i.e., it is assumed that the
peripheral which is selected via this pin resides on the X-Bus.)
During Reset: High After Reset: High During POS: High
RCIN# I RESET CPU. This signal from the keyboard controller is used to generate an INIT
signal to the CPU.
82371AB (PIIX4) E
22
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Name Type Description
RTCALE/
GPO25
O REAL TIME CLOCK ADDRESS LATCH ENABLE. RTCALE is used to latch the
appropriate memory address into the RTC. A write to port 70h with the appropriate RTC
memory address that will be written to or read from causes RTCALE to be asserted.
RTCALE is asserted on falling IOW# and remains asserted for two SYSCLKs.
If the internal Real Time Clock is used, this signal can be programmed as a general
purpose output.
During Reset: Low After Reset: Low During POS: Low/GPO
RTCCS#/
GPO24
O REAL TIME CLOCK CHIP SELECT. RTCCS# is asserted during read or write I/O
accesses to RTC location 71h. RTCCS# can be tied to a pair of external OR gates to
generate the real time clock read and write command signals. If the internal Real Time
Clock is used, this signal can be programmed as a general purpose output.
During Reset: High After Reset: High During POS: High/GPO
XDIR#/
GPO22
O X-BUS TRANSCEIVER DIRECTION. XDIR# is tied directly to the direction control of a
74’245 that buffers the X-Bus data, XD[7:0]. XDIR# is asserted (driven low) for all I/O
read cycles regardless if the accesses is to a PIIX4 supported device. XDIR# is
asserted for memory cycles only if BIOS or APIC space has been decoded. For PCI
master initiated read cycles, XDIR# is asserted from the falling edge of either IOR# or
MEMR# (from MEMR# only if BIOS or APIC space has been decoded), depending on
the cycle type. For ISA master-initiated read cycles, XDIR# is asserted from the falling
edge of either IOR# or MEMR# (from MEMR# only if BIOS space has been decoded),
depending on the cycle type. When the rising edge of IOR# or MEMR# occurs, PIIX4
negates XDIR#. For DMA read cycles from the X-Bus, XDIR# is driven low from
DACKx# falling and negated from DACKx# rising. At all other times, XDIR# is negated
high.
If the X-Bus not used, then this signal can be programmed to be a general purpose
output.
During Reset: High After Reset: High During POS: High/GPO
XOE#/
GPO23
O X-BUS TRANSCEIVER OUTPUT ENABLE. XOE# is tied directly to the output enable
of a 74’245 that buffers the X-Bus data, XD[7:0], from the system data bus, SD[7:0].
XOE# is asserted anytime a PIIX4 supported X-Bus device is decoded, and the devices
decode is enabled in the X-Bus Chip Select Enable Register (BIOSCS#, KBCCS#,
RTCCS#, MCCS#) or the Device Resource B (PCCS0#) and Device Resource C
(PCCS1#). XOE# is asserted from the falling edge of the ISA commands (IOR#, IOW#,
MEMR#, or MEMW#) for PCI Master and ISA master-initiated cycles. XOE# is negated
from the rising edge of the ISA command signals for PCI Master initiated cycles and the
SA[16:0] and LA[23:17] address for ISA master-initiated cycles. XOE# is not generated
during any access to an X-Bus peripheral in which its decode space has been disabled.
If an X-Bus not used, then this signal can be programmed to be a general purpose
output.
During Reset: High After Reset: High During POS: High/GPO
E 82371AB (PIIX4)
23
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
2.1.4. DMA SIGNALS
Name Type Description
DACK[0,1,2,3]#
DACK[5,6,7]#
O DMA ACKNOWLEDGE. The DACK# output lines indicate that a request for DMA
service has been granted by PIIX4 or that a 16-bit master has been granted the
bus. The active level (high or low) is programmed via the DMA Command
Register. These lines should be used to decode the DMA slave device with the
IOR# or IOW# line to indicate selection. If used to signal acceptance of a bus
master request, this signal indicates when it is legal to assert MASTER#. If the
DREQ goes inactive prior to DACK# being asserted,
the DACK# signal will not be asserted.
During Reset: High After Reset: High During POS: High
DREQ[0,1,2,3]
DREQ[5,6,7]
I DMA REQUEST. The DREQ lines are used to request DMA service from PIIX4’s
DMA controller or for a 16-bit master to gain control of the ISA expansion bus. The
active level (high or low) is programmed via the DMA Command Register. All
inactive to active edges of DREQ are assumed to be asynchronous. The request
must remain active until the appropriate DACKx# signal is asserted.
REQ[A:C]#/
GPI[2:4]
I PC/PCI DMA REQUEST. These signals are the DMA requests for PC/PCI
protocol. They are used by a PCI agent to request DMA services and follow the
PCI Expansion Channel Passing protocol as defined in the PCI DMA section.
If the PC/PCI request is not needed, these pins can be used as general-purpose
inputs.
GNT[A:C]#/
GPO[9:11]
O PC/PCI DMA ACKNOWLEDGE. These signals are the DMA grants for PC/PCI
protocol. They are used by a PIIX4 to acknowledge DMA services and follow the
PCI Expansion Channel Passing protocol as defined in the PCI DMA section.
If the PC/PCI request is not needed, these pins can be used as general-purpose
outputs.
During Reset: High After Reset: High During POS: High/GPO
TC O TERMINAL COUNT. PIIX4 asserts TC to DMA slaves as a terminal count
indicator. PIIX4 asserts TC after a new address has been output, if the byte count
expires with that transfer. TC remains asserted until AEN is negated, unless AEN
is negated during an autoinitialization. TC is negated before AEN is negated during
an autoinitialization.
During Reset: Low After Reset: Low During POS: Low
82371AB (PIIX4) E
24
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
2.1.5. INTERRUPT CONTROLLER/APIC SIGNALS
Name Type Description
APICACK#/
GPO12
O APIC ACKNOWLEDGE. This active low output signal is asserted by PIIX4 after its
internal buffers are flushed in response to the APICREQ# signal. When the I/O APIC
samples this signal asserted it knows that PIIX4’s buffers are flushed and that it can
proceed to send the APIC interrupt. The APICACK# output is synchronous to
PCICLK.
If the external APIC is not used, then this is a general-purpose output.
During Reset: High After Reset: High During POS: High/GPO
APICCS#/
GPO13
O APIC CHIP SELECT. This active low output signal is asserted when the APIC Chip
Select is enabled and a PCI originated cycle is positively decoded within the
programmed I/O APIC address space.
If the external APIC is not used, this pin is a general-purpose output.
During Reset: High After Reset: High During POS: High/GPO
APICREQ#/
GPI5
I APIC REQUEST. This active low input signal is asserted by an external APIC
device prior to sending an interrupt over the APIC serial bus. When PIIX4 samples
this pin active it will flush its F-type DMA buffers pointing towards PCI. Once the
buffers are flushed, PIIX4 asserts APICACK# which indicates to the external APIC
that it can proceed to send the APIC interrupt. The APICREQ# input must be
synchronous to PCICLK.
If the external APIC is not used, this pin is a general-purpose input.
INTR OD INTERRUPT. See CPU Interface Signals.
IRQ0/
GPO14
O INTERRUPT REQUEST 0. This output reflects the state of the internal IRQ0 signal
from the system timer.
If the external APIC is not used, this pin is a general-purpose output.
During Reset: Low After Reset: Low During POS: IRQ0/GPO
IRQ1 I INTERRUPT REQUEST 1. IRQ1 is always edge triggered and can not be modified
by software to level sensitive. A low to high transition on IRQ1 is latched by PIIX4.
IRQ1 must remain asserted until after the interrupt is acknowledged. If the input goes
inactive before this time, a default IRQ7 is reported in response to the interrupt
acknowledge cycle.
E 82371AB (PIIX4)
25
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Name Type Description
IRQ 3:7, 9:11,
14:15
I INTERRUPT REQUESTS 3:7, 9:11, 14:15. The IRQ signals provide both system
board components and ISA Bus I/O devices with a mechanism for asynchronously
interrupting the CPU. These interrupts may be programmed for either an edge
sensitive or a high level sensitive assertion mode. Edge sensitive is the default
configuration.
An active IRQ input must remain asserted until after the interrupt is acknowledged. If
the input goes inactive before this time, a default IRQ7 is reported in response to the
interrupt acknowledge cycle.
IRQ8#/
GPI6
I/O IRQ 8#. IRQ8# is always an active low edge triggered interrupt and can not be
modified by software.
IRQ8# must remain asserted until after the interrupt is acknowledged. If the input
goes inactive before this time, a default IRQ7 is reported in response to the interrupt
acknowledge cycle.
If using the internal RTC, then this can be programmed as a general-purpose input. If
enabling an APIC, this signal becomes an output and must not be programmed as a
general purpose input.
IRQ9OUT#/
GPO29
O IRQ9OUT#. IRQ9OUT# is used to route the internally generated SCI and SMBus
interrupts out of the PIIX4 for connection to an external IO APIC. If APIC is disabled,
this signal pin is a General Purpose Output.
During Reset: High After Reset: High During POS: IRQ9OUT#/GPO
IRQ 12/M I INTERRUPT REQUEST 12. In addition to providing the standard interrupt function
as described in the pin description for IRQ[3:7,9:11,14:15], this pin can also be
programmed to provide the mouse interrupt function.
When the mouse interrupt function is selected, a low to high transition on this signal
is latched by PIIX4 and an INTR is generated to the CPU as IRQ12. An internal
IRQ12 interrupt continues to be generated until a Reset or an I/O read access to
address 60h (falling edge of IOR#) is detected.
PIRQ[A:D]# I/OD
PCI
PROGRAMMABLE INTERRUPT REQUEST. The PIRQx# signals are active low,
level sensitive, shareable interrupt inputs. They can be individually steered to ISA
interrupts IRQ [3:7,9:12,14:15]. The USB controller uses PIRQD# as its output
signal.
SERIRQ/
GPI7
I/O SERIAL INTERRUPT REQUEST. Serial interrupt input decoder, typically used in
conjunction with the Distributed DMA protocol.
If not using serial interrupts, this pin can be used as a general-purpose input.
82371AB (PIIX4) E
26
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
2.1.6. CPU INTERFACE SIGNALS
Name Type Description
A20M# OD ADDRESS 20 MASK. PIIX4 asserts A20M# to the CPU based on combination of Port
92 Register, bit 1 (FAST_A20), and A20GATE input signal.
During Reset: High-Z After Reset: High-Z During POS: High-Z
CPURST OD CPU RESET. PIIX4 asserts CPURST to reset the CPU. PIIX4 asserts CPURST during
power-up and when a hard reset sequence is initiated through the RC register.
CPURST is driven inactive a minimum of 2 ms after PWROK is driven active. CPURST
is driven active for a minimum of 2 ms when initiated through the RC register. The
inactive edge of CPURST is driven synchronously to the rising edge of PCICLK. If a
hard reset is initiated through the RC register, PIIX4 resets its internal registers (in both
core and suspend wells) to their default state.
This signal is active high for Pentium processor and active-low for Pentium II processor
as determined by CONFIG1 signal.
For values During Reset, After Reset, and During POS, see the Suspend/Resume
and Resume Control Signaling section.
FERR# I NUMERIC COPROCESSOR ERROR. This pin functions as a FERR# signal supporting
coprocessor errors. This signal is tied to the coprocessor error signal on the CPU. If
FERR# is asserted, PIIX4 generates an internal IRQ13 to its interrupt controller unit.
PIIX4 then asserts the INT output to the CPU. FERR# is also used to gate the IGNNE#
signal to ensure that IGNNE# is not asserted to the CPU unless FERR# is active.
IGNNE# OD IGNORE NUMERIC EXCEPTION. This signal is connected to the ignore numeric
exception pin on the CPU. IGNNE# is only used if the PIIX4 coprocessor error reporting
function is enabled. If FERR# is active, indicating a coprocessor error,
a write to the Coprocessor Error Register (F0h) causes the IGNNE# to be asserted.
IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted when the
Coprocessor Error Register is written, the IGNNE# signal is not asserted.
During Reset: High-Z After Reset: High-Z During POS: High-Z
INIT OD INITIALIZATION. INIT is asserted in response to any one of the following conditions.
When the System Reset bit in the Reset Control Register is reset to 0 and the Reset
CPU bit toggles from 0 to 1, PIIX4 initiates a soft reset by asserting INIT. PIIX4 also
asserts INIT if a Shut Down Special cycle is decoded on the PCI Bus, if the RCIN#
signal is asserted, or if a write occurs to Port 92h, bit 0. When asserted, INIT remains
asserted for approximately 64 PCI clocks before being negated.
This signal is active high for Pentium processor and active-low for Pentium II processor
as determined by CONFIG1 signal.
Pentium Processor:
During Reset: Low After Reset: Low During POS: Low
Pentium II Processor:
During Reset: High After Reset: High During POS: High
INTR OD CPU INTERRUPT. INTR is driven by PIIX4 to signal the CPU that an interrupt request
is pending and needs to be serviced. It is asynchronous with respect to SYSCLK or
PCICLK and is always an output. The interrupt controller must be programmed following
PCIRST# to ensure that INTR is at a known state.
During Reset: Low After Reset: Low During POS: Low
E 82371AB (PIIX4)
27
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Name Type Description
NMI OD NON-MASKABLE INTERRUPT. NMI is used to force a nonmaskable interrupt to the
CPU. PIIX4 generates an NMI when either SERR# or IOCHK# is asserted, depending
on how the NMI Status and Control Register is programmed. The CPU detects an NMI
when it detects a rising edge on NMI. After the NMI interrupt routine processes the
interrupt, the NMI status bits in the NMI Status and Control Register are cleared by
software. The NMI interrupt routine must read this register to determine the source of
the interrupt. The NMI is reset by setting the corresponding NMI source enable/disable
bit in the NMI Status and Control Register. To enable NMI interrupts, the two NMI
enable/disable bits in the register must be set to 0, and the NMI mask bit in the NMI
Enable/Disable and Real Time Clock Address Register must be set to 0. Upon
PCIRST#, this signal is driven low.
During Reset: Low After Reset: Low During POS: Low
SLP# OD SLEEP. This signal is output to the Pentium II processor in order to put it into Sleep
state. For Pentium processor it is a No Connect.
During Reset: High-Z After Reset: High-Z During POS: High-Z
SMI# OD SYSTEM MANAGEMENT INTERRUPT. SMI# is an active low synchronous output that
is asserted by PIIX4 in response to one of many enabled hardware or software events.
The CPU recognizes the falling edge of SMI# as the highest priority interrupt in the
system, with the exception of INIT, CPURST, and FLUSH.
During Reset: High-Z After Reset: High-Z During POS: High-Z
STPCLK# OD STOP CLOCK. STPCLK# is an active low synchronous output that is asserted by PIIX4
in response to one of many hardware or software events. STPCLK# connects directly to
the CPU and is synchronous to PCICLK.
During Reset: High-Z After Reset: High-Z During POS: High-Z
82371AB (PIIX4) E
28
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
2.1.7. CLOCKING SIGNALS
Name Type Description
CLK48 I 48-MHZ CLOCK. 48-MHz clock used by the internal USB host controller. This signal
may be stopped during suspend modes.
PCICLK I FREE-RUNNING PCI CLOCK. A clock signal running at 30 or 33 MHz, PCICLK
provides timing for all transactions on the PCI Bus. All other PCI signals are sampled on
the rising edge of PCICLK, and all timing parameters are defined with respect to this
edge. Because many of the circuits in PIIX4 run off the PCI clock, this signal MUST be
kept active, even if the PCI bus clock is not active.
OSC I 14.31818-MHZ CLOCK. Clock signal used by the internal 8254 timer. This clock signal
may be stopped during suspend modes.
RTCX1,
RTCX2
I/O RTC CRYSTAL INPUTS: These connected directly to a 32.768-kHz crystal. External
capacitors are required. These clock inputs are required even if the internal RTC is not
being used.
SUSCLK O SUSPEND CLOCK. 32.768-kHz output clock provided to the Host-to-PCI bridge used
for maintenance of DRAM refresh. This signal is stopped during Suspend-to-Disk and
Soft Off modes. For values During Reset, After Reset, and During POS, see the
Suspend/Resume and Resume Control Signaling section.
SYSCLK O ISA SYSTEM CLOCK. SYSCLK is the reference clock for the ISA bus. It drives the ISA
bus directly. The SYSCLK is generated by dividing PCICLK by 4. The SYSCLK
frequencies supported are 7.5 MHz and 8.33 MHz. For PCI accesses to the ISA bus,
SYSCLK may be stretched low to synchronize BALE falling to the rising edge of
SYSCLK.
During Reset: Running After Reset: Running During POS: Low
2.1.8. IDE SIGNALS
Name Type Description
PDA[2:0] O PRIMARY DISK ADDRESS[2:0]. These signals indicate which byte in either the ATA
command block or control block is being addressed.
If the IDE signals are configured for Primary and Secondary, these signals are
connected to the corresponding signals on the Primary IDE connector.
If the IDE signals are configured for Primary 0 and Primary 1, these signals are used for
the Primary 0 connector.
During Reset: High-Z After Reset: Undefined
1
During POS: PDA
PDCS1# O PRIMARY DISK CHIP SELECT FOR 1F0H−−1F7H RANGE. For ATA command register
block. If the IDE signals are configured for Primary and Secondary, this output signal is
connected to the corresponding signal on the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is
used for the Primary Master connector.
During Reset: High After Reset: High During POS: High
E 82371AB (PIIX4)
29
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Name Type Description
PDCS3# O PRIMARY DISK CHIP SELECT FOR 3F0−−3F7 RANGE. For ATA control register block.
If the IDE signals are configured for Primary and Secondary, this output signal is
connected to the corresponding signal on the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is
used for the Primary Master connector.
During Reset: High After Reset: High During POS: High
PDD[15:0] I/O PRIMARY DISK DATA[15:0]. These signals are used to transfer data to or from the IDE
device. If the IDE signals are configured for Primary and Secondary, these signals are
connected to the corresponding signals on the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is
used for the Primary Master connector.
During Reset: High-Z After Reset: Undefined
1
During POS: PDD
PDDACK# O PRIMARY DMA ACKNOWLEDGE. This signal directly drives the IDE device DMACK#
signal. It is asserted by PIIX4 to indicate to IDE DMA slave devices that a given data
transfer cycle (assertion of PDIOR# or PDIOW#) is a DMA data transfer cycle. This
signal is used in conjunction with the PCI bus master IDE function. It is not associated
with any AT compatible DMA channel.
If the IDE signals are configured for Primary and Secondary, this signal is connected to
the corresponding signal on the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is
used for the Primary Master connector.
During Reset: High After Reset: High During POS: High
PDDREQ I PRIMARY DISK DMA REQUEST. This input signal is directly driven from the IDE
device DMARQ signal. It is asserted by the IDE device to request a data transfer, and
used in conjunction with the PCI bus master IDE function. It is not associated with any
AT compatible DMA channel.
If the IDE signals are configured for Primary and Secondary, this signal is connected to
the corresponding signal on the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is
used for the Primary Master connector.
82371AB (PIIX4) E
30
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
PRELIMINARY
Name Type Description
PDIOR# O PRIMARY DISK IO READ. In normal IDE this is the command to the IDE device that it
may drive data onto the PDD[15:0] lines. Data is latched by PIIX4 on the negation edge
of PDIOR#. The IDE device is selected either by the ATA register file chip selects
(PDCS1#, PDCS3#) and the PDA[2:0] lines, or the IDE DMA slave arbitration signals
(PDDACK#).
In an Ultra DMA/33 read cycle, this signal is used as DMARDY# which is negated by the
PIIX4 to pause Ultra DMA/33 transfers. In an Ultra DMA/33 write cycle, this signal is
used as the STROBE signal, with the drive latching data on rising and falling edges of
STROBE.
If the IDE signals are configured for Primary and Secondary, this signal is connected to
the corresponding signal on the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is
used for the Primary Master connector.
During Reset: High After Reset: High During POS: High
PDIOW# O PRIMARY DISK IO WRITE. In normal IDE mode, this is the command to the IDE device
that it may latch data from the PDD[15:0] lines. Data is latched by the IDE device on the
negation edge of PDIOW#. The IDE device is selected either by the ATA register file
chip selects (PDCS1#, PDCS3#) and the PDA[2:0] lines, or the IDE DMA slave
arbitration signals (PDDACK#).
For Ultra DMA/33 mode, this signal is used as the STOP signal, which is used to
terminate an Ultra DMA/33 transaction. If the IDE signals are configured for Primary and
Secondary, this signal is connected to the corresponding signal on the Primary IDE
connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is
used for the Primary Master connector.
During Reset: High After Reset: High During POS: High-Z
PIORDY I PRIMARY IO CHANNEL READY. In normal IDE mode, this input signal is directly
driven by the corresponding IDE device IORDY signal.
In an Ultra DMA/33 read cycle, this signal is used as STROBE, with the PIIX4 latching
data on rising and falling edges of STROBE. In an Ultra DMA/33 write cycle, this signal
is used as the DMARDY# signal which is negated by the drive to pause Ultra DMA/33
transfers.
If the IDE signals are configured for Primary and Secondary, this signal is connected to
the corresponding signal on the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is
used for the Primary Master connector.
This is a Schmitt triggered input.
Loading...