Intel Corporation FV75, FV200, FV166, FV150, FV133 Datasheet

E

June 1997 Order Number 241997-010

Max. Operating Frequency

75

MHz

90

MHz

100

MHz

120

MHz

133

MHz

150

MHz

166

MHz

200

MHz

iCOMP® Index 2.0 Rating 67 81 90 100 111 114 127 142

Note: Contact Intel Corporation for more information about iCOMP®Index 2.0 ratings.

n

Compatible with Large Software Base

 MS-DOS*, Windows*, OS/2*, UNIX*

n

32-Bit CPU with 64-Bit Data Bus

n

Superscalar Architecture

 Two Pipelined Integer Units Are Capable

of 2 Instructions/Clock

 Pipe-lined Floating Point Unit

n

Separate Code and Data Caches

 8-Kbyte Code, 8-Kbyte Write Back Data
 MESI Cache Protocol

n

Advanced Design Features

 Branch Prediction
 Virtual Mode Extensions

n

3.3V BiCMOS Silicon Technology

n

4-Mbyte Pages for Increased TLB Hit Rate

n

IEEE 1149.1 Boundary Scan

n

Dual Processing Configuration

n

Functional Redundancy Checking Support

n

Internal Error Detection Features

n

Multi-Processor Support

 Multiprocessor Instructions
 Support for Second Level Cache

n

On-Chip Local APIC Controller

 MP Interrupt Management
 8259 Compatible

n

Upgradable with a Pentium® OverDrive

®

Processor

n

Power Management Features

 System Management Mode
 Clock Control

n

Fractional Bus Operation

 200-MHz Core/66-MHz Bus
 166-MHz Core/66-MHz Bus
 150-MHz Core/60-MHz Bus
 133-MHz Core/66-MHz Bus
 120-MHz Core/60-MHz Bus
 100-MHz Core/66-MHz Bus
 100-MHz Core/50-MHz Bus
 90-MHz Core/60-MHz Bus
 75-MHz Core/50-MHz Bus

The Pentium

®

processor 75/90/100/120/133/150/166/200 extends the Pentium processor family, providing
performance needed for mains tream des k top applic ations as w ell as for works tations and s erv ers . The Pentium
process or is compatible with the entire installed base of applications for DOS*, W indows*, OS/2* , and UNIX*.
The Pentium process or 75/90/100/120/133/150/166/200 superscalar architecture can execute two instructions
per clock c y c le. B ranc h predic tion and s epar ate c ac hes als o inc reas e per formanc e. The pipelined floating point
unit delivers workstation level performance. Separate code and data caches reduce cache conflicts while
remaining software transparent. The Pentium processor 75/90/100/120/133/150/166/200 has 3.3 million
transistors and is built on Intel’s advanced 3.3V BiCMOS silicon technology. The Pentium processor
75/90/100/120/133/150/166/200 has on-chip dual process ing support, a loc al multiproces sor interr upt controller,
and SL power management features. The Pentium process or may contain design defec ts or errors know n as
errata which may cause the produc t to deviate from published s pecifications. Current c haracterized errata are
available upon request.

PENTIUM® PROCESSOR

CONTENTS

PAGE PAGE

1.0. MICROPROCESSOR ARCHITECTURE

OVERVIEW .......................................................3

1.1. Pentium® Processor Family Architecture......3

1.2. Pentium® Processor

75/90/100/120/133/150/166/200....................6

2.0. PINOUT..............................................................8

2.1. Pinout and Pin Descriptions...........................8

2.2. Design Notes................................................12

2.3. Quick Pin Reference....................................12

2.4. Pin Reference Tables...................................22

2.5. Pin Grouping According to Function............26

3.0. ELECTRICAL SPECIFICATIONS ..................27

3.1. Electrical Differences Between Pentium®
Processor 75/90/100/120/133/150/166/200

and Pentium Processor 60/66......................27

3.2. Absolute Maximum Ratings..........................28

3.3. DC Specifications.........................................28

3.4. AC Specifications.........................................31

4.0. MECHANICAL SPECIFICATIONS.................56

5.0. THERMAL SPECIFICATIONS........................62

5.1. Measuring Thermal Values..........................62

6.0. OverDrive® PROCESSOR SOCKET

SPECIFICATION.............................................69

6.1. Introduction...................................................69

6.2. Socket 5.......................................................69

6.3. Socket 7.......................................................70

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products , Intel assumes no liability w hats oeve r, and Intel disc laims any expres s or implied warranty , relating to
sale and/or use of Intel products including liability or warr anties re lating to fitnes s fo r a par tic ular pur pose, me rchantabilit y, or
infringement of any patent, copyright or other intellectual property right. Intel produc ts are not intended for us e in medical, life
saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not r ely on the absence or c haracteristics of any features or instruc tions marked "reser ved" or "undefined."

Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them.

The Pentium

®

processor may contain design defects or errors know n as errata whic h may caus e the product to deviate from

published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which hav e an ordering number and are refer enced in this document, or other Intel literatur e, may be

obtained from:

Intel Corporation
P.O. Box 7641
Mt. Prospect IL 60056-7641

or call 1-800-879-4683

or visit Intel’s website at http:\\www.intel.com
Copyright © Intel Corporation 1993, 1996, 1997.

* Third-party brands and names are the property of their respective owners.

E

PENTIUM® PROCESSO R 75/ 90/100/120/133/150/ 166/ 200

3

1.0. MICROPROCESSOR

ARCHITECTURE OVERVIEW

The Pentium® processor 75/90/100/120/133/
150/166/200 extends the Intel Pentium family of
microprocessors. It is binary compatible with the
8086/88, 80286, Intel386™ DX CPU, Intel386 SX
CPU, Intel486™ DX CPU, Intel486 SX CPU,
Intel486 DX2 CPU, and Pentium processor 60/66.

The Pentium processor family consists of the
following products.

• Described in this document (product code

80502). The name “Pentium processor

75/90/100/120/133/150/166/200” will be us ed to

refer to these products:

– Pentium processor at 200 MHz, iCOMP

®

Index 2.0 rating = 142

– Pentium processor at 166 MHz, iCOMP

Index 2.0 rating = 127

– Pentium processor at 150 MHz, iCOMP

Index 2.0 rating = 114

– Pentium processor at 133 MHz, iCOMP

Index 2.0 rating = 111

– Pentium processor at 120 MHz, iCOMP

Index 2.0 rating = 100

– Pentium processor at 100 MHz, iCOMP

Index 2.0 rating = 90

– Pentium processor at 90 MHz, iCOMP

Index 2.0 rating = 81

– Pentium processor at 75 MHz, iCOMP

Index 2.0 rating = 67

• Original Pentium processor. The name

“Pentium process or 60/66” will be used to refer

to the original 60 and 66 MHz version products:

– Pentium processor at 66 MHz, iCOMP

Index 2.0 rating = 57

– Pentium processor at 60 MHz, iCOMP

Index 2.0 rating = 51

The Pentium proces sor f amily arc hitectur e c ontains
all of the features of the Intel486 CPU family, and
provides significant enhancements and additions
including the following:

• Superscalar Architecture

• Dynamic Branch Prediction

• Pipelined Floating-Point Unit

• Improved Instruction Execution Time

• Separate 8K Code and 8K Data Caches

• Writeback MESI Protocol in the Data Cache

• 64-Bit Data Bus

• Bus Cycle Pipelining

• Address Parity

• Internal Parity Checking

• Functional Redundancy Checking

• Execution Tracing

• Performance Monitoring

• IEEE 1149.1 Boundary Scan

• System Management Mode

• Virtual Mode Extensions

In addition to the features listed abov e, the Pentium
processor 75/90/100/120/133/150/166/200 offers
the following enhancements over Pentium
processor 60/66:

• Fractional bus operation allowing higher core
frequency operation

• Dual processing support

• SL power management features

• On-chip local APIC device

1.1. Pentium® Processor Family

Architecture

The application instruction set of the Pentium
processor family includes the complete Intel486
CPU family instruction set with extensions to
accommodate s ome of t he additional func tionalit y of
the Pentium processors. All application software
written for the Intel386 and Intel486 family
microproc es s ors will run on the Pentium proc es s ors
without modification. The on-chip memory
management unit (MMU) is completely compatible
with the Intel386 family and Intel486 family of CPUs.

The Pentium processors implement several
enhancements to increase performance. The two
instruction pipelines and floating-point unit on
Pentium processors are capable of independent
operation. Each pipeline issues frequently used

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

E

4

instructions in a single clock. Together, the dual
pipes can issue two integer instructions in one
clock , or one floating point ins t ruc tion ( under c er tain
circumstances, two floating-point instructions) in
one clock.

Branch prediction is implemented in the Pentium
processors. To support this, Pentium processors
implement two prefetch buffers, one to prefetch
code in a linear fashion, and one that prefetches
code according to the BTB so the needed code is
almost always prefetched before it is needed for
execution.

The floating-point unit has been completely
redesigned over the Intel486 CPU. Faster
algorithms prov ide up to 10X speed- up for common
operations including add, multiply, and load.

Pentium processors include separate code and data
caches integrated on-chip to meet performance
goals. Each cache is 8 Kbytes in size, with a 32­byte line size and is 2-way set associative. Each
cache has a dedicated Translation Lookaside Buffer
(TLB) to translate linear addresses to physical
addresses. The data cache is configurable to be
write back or write through on a line-by-line basis
and follows the MES I prot oc ol. The data cache t ags
are triple ported to support two data trans fers and
an inquire cycle in the same clock. The code cache
is an inherently write-protected cache. The code
cache tags are also triple ported to support
snooping and split line ac cesses. Individual pages
can be configured as cacheable or non-cacheable
by software or hardware. The caches can be
enabled or disabled by software or hardware.

The Pentium processors have increased the data
bus to 64 bits to improve the data transfer rate.
Burst read and burst write back cycles are
supported by the Pentium processors. In addition,
bus cycle pipelining has been added to allow two
bus cycles to be in progress simultaneously. The
Pentium processors' Memory Management Unit

contains optional extensions to the architecture
which allow 2-Mbyte and 4-Mbyte page sizes.

The Pentium processors have added significant
data integrity and error detection capability. Data
parity chec king is still s upported on a byte-by -byte
basis. Address parity checking, and internal parity
checking features have been added along with a
new exception, the machine check exception.

In addition, the Pentium processors have
implemented functional redundancy checking to
provide maximum error detection of the processor
and the interface to the proc ess or. When func tional
redundancy chec king is us ed, a second proc essor,
the “checker” is us ed to execute in loc k step w ith
the “master” processor. The checker samples the
master's outputs and compares those values with
the values it computes internally, and asserts an
error signal if a mismatch occurs.

As more and more functions ar e integrated on c hip,
the complexity of board level testing is increased.
To address this, the Pentium processors have
increased test and debug capability. The Pentium
processors implement IEEE Boundary Scan
(Standard 1149.1). In addition, the Pentium
processors have specified 4 breakpoint pins that
correspond to each of the debug registers and
externally indicate a breakpoint match. Execution
tracing provides external indications when an
instruc tion has completed ex ecution in either of the
two internal pipelines, or when a branch has been
taken.

System Management Mode (SMM) has been
implemented along with some extensions to the
SMM architecture. Enhancements to the virtual
8086 mode have been made to increase
performance by reduc ing the number of times it is
necessary to trap to a virtual 8086 monitor.

Figure 1 shows a block diagram of the Pentium
processor 75/90/100/120/133/150/166/200.

E

PENTIUM® PROCESSO R 75/ 90/ 100/ 120/ 133/ 150/ 166/ 200

5

Branch

Target
Buffer

Code Cache

8 KBytes

ROM

Control Unit

Generate

Address

Generate

Data Cache

8 KBytes

256

TLB

TLB

Prefetch

Address

Prefetch Buffers

Instruction Decode

Instruction

Pointer

Integer Register File

ALU

Barrel Shifter

32

32

32
32

32

32

Page

Unit

Bus
Unit

64-Bit

Data

Bus

32-Bit

Address

Bus

Control

64-Bit

Data

Bus

32-Bit
Addr.
Bus

64

Control

Register File

Add

Multiply

Divide

Floating

Point

Unit

Pentium® Processor (75/90/100/120/133/150/166/200 MHz)

Control

80

80

Address

(U Pipeline) (V Pipeline)

(U Pipeline)

(V Pipeline)

ALU

Branch Verification
and Target Address

32

DP
Logic

Control

APIC

Data

Control

199718

Figure 1. Pentium® Processor Block Diagram

The block diagram shows the two instruction
pipelines, the "u” pipe and the "v” pipe. The u-pipe
can execute all integer and floating point
instructions. The v-pipe can execute simple integer
instructions and the FXCH floating-point
instructions.

The separate code and data caches are shown.
The data cache has two port s, one for eac h of the
two pipes (the tags are triple ported to allow
simultaneous inquir e cycles). The data cache has
a dedicated Trans lation Lookaside Buff er (TLB) t o

translate linear addresses to the physical
addresses used by the data cache.

The code cache, br anch target buf fer and prefetc h
buffers are responsible for getting raw instr uctions
into the execut ion units of the Pentium proc essor.
Instructions are fetched from the code cache or
from the external bus. Branch addresses are
remembered by the branc h t arget buf fer. The c ode
cache TLB trans lates linear addres ses to phy sical
addresses used by the code cache.

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

E

6

The decode unit decodes the prefetched
instructions so the Pentium processors can
execute the ins truc tion. The cont rol ROM cont ains
the microcode which controls the sequence of
operations that must be performed to implement
the Pentium processor architecture. The control
ROM unit has direct control over both pipelines.

The Pentium processors contain a pipelined
floating-point unit that provides a significant
floating-point performance advantage over
previous generations of processors.

The architectural features introduced in this
chapter are more fully described in the

Pentium

®

Processor Family Developer’s Manual, Volume 1

(Order Number 241428).

1.2. Pentium® Processor
75/90/100/120/133/150/166/200

In addition to the architec ture desc ribed above for
the Pentium processor family, the Pentium
processor 75/90/100/120/133/150/166/200 has
additional features which are described in this
section.

The Pentium processor 75/90/100/120/133/
150/166/200 offers higher perfor mance and higher
operating frequencies than the Pentium process or
60/66.

Symmetric dual processing in a system is
supported with two Pentium processor
75/90/100/120/133/150/166/200. The two
processors appear to the system as a single
Pentium processor 75/90/100/120/133/150
/166/200. Operating systems with dual processing
support properly schedule computing tasks
between the two processors. This scheduling of
tasks is transparent to software applications and
the end-user. Logic built into the processors
support a “glueless” interface for easy system
design. Through a private bus, the two Pentium
processor 75/90/100/120/133/150/166/200
arbitrate for the external bus and maintain cache
coherency. Dual processing is supported in a
system only if both processors are operating at
identical core and bus frequencies.

In this document, in order to distinguish between
two Pentium processor 75/90/100/120/133/
150/166/200 in dual processing mode, one CPU
will be designated as the “Primary” processor and
the other as the “Dual” pr oces sor. N ote that this is
a different concept than that of “master” and
“checker” processors described above in the
discussion on functional redundancy.

Due to the advanc ed 3.3V BiC MOS pr oc es s that it
is produced on, the Pentium processor
75/90/100/120/133/150/166/200 dissipates less
power than the Pentium processor 60/66. In
addition to the SMM features des cr ibed above, the
Pentium processor 75/90/100/120/133/150/
166/200 supports cloc k c ontrol. When the cloc k to
the Pentium processor 75/90/100/120/133/150/
166/200 is stopped, power dissipation is virtually
eliminated. The combination of these
improvements makes the Pentium processor
75/90/100/120/133/150/166/200 a good choic e for
energy-efficient desktop designs.
Supporting an upgrade soc ket (Sock et 5/7) in the
system will provide end-user upgradability by the
addition of a Pentium OverDrive processor. Typical
applications will realize a 40%–70% performance
increase by addition of a Pentium OverDrive
processor.

Socket 7 has been defined as the upgrade soc ket
for the Pentium proc essor 75/90/100/120/133/150/
166/200. The flexibility of the Socket 7 definition
makes it backward compatible with Soc ket 5 and
should be used for all new Pentium processor­based system designs.

The Pentium processor 75/90/100/120/133/
150/166/200 supports fractional bus operation.
This allows the internal proces sor core to operate
at high frequencies, while communic ating with the
external bus at lower frequencies.

The Pentium processor 75/90/100/120/133/
150/166/200 contains an on-chip Advanced
Programmable Interrupt Controller (APIC). This
APIC implementation supports multiprocessor
interrupt management (with symmetric interrupt
distribution across all processors), multiple I/O
subsystem support, 8259A compatibility, and inter­processor interrupt support.

E

PENTIUM® PROCESSO R 75/ 90/100/120/133/150/ 166/ 200

7

1.3. Pentium® Processors with
Voltage Reduction
Technology

Currently, Intel's Pentium processor with Voltage
Reduction Tec hnology family cons ists of two s ets
of products. Please reference the appropriate
datasheets f or c orr ec t pinout, mec hanic al, ther mal,
and electrical specifications. Detailed information
on Mobile Pentium processors based on 0.6 µm
process technology (75, 90, and 100 MHz) is

available in the datasheet

Pentium® Processors at

iComp

®

Index 1000\120, 735\90, 610\75 MHz with

Voltage Reduction Technology

(Order Number

242973). For detailed information on Mobile
Pentium processors based on 0.35 µm process
technology (100, 120, and 133 MHz), see Intel
datasheet

Pentium® Processors at iComp® Index
1110\133, 1000\120, 815\100 MHz with Voltage
Reduction Technology

(Order Number 242557).

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

E

8

2.0. PINOUT

2.1. Pinout and Pin Descriptions

2.1.1. PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200 PINOUT

199719

Figure 2. Pentium® Processor 75/90/100/120/133/150/166/200 SPGA and PPGA Package Pinout

(Top Side View)

E

PENTIUM® PROCESSO R 75/ 90/100/120/133/150/ 166/ 200

9

199703

Figure 3. Pentium® Processor 75/90/100/120/133/150/166/200 SPGA and PPGA Package Pinout

(Pin Side View)

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

E

10

2.1.2. PIN CROSS REFERENCE TABLE FOR PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

Table 1. Pin Cross Reference by Pin Name

A3 AL35 A9 AK30 A15 AK26 A21 AF34 A27 AG33
A4 AM34 A10 AN31 A16 AL25 A22 AH36 A28 AK36
A5 AK32 A11 AL31 A17 AK24 A23 AE33 A29 AK34
A6 AN33 A12 AL29 A18 AL23 A24 AG35 A30 AM36
A7 AL33 A13 AK28 A19 AK22 A25 AJ35 A31 AJ33
A8 AM32 A14 AL27 A20 AL21 A26 AH34

Data

D0 K34 D13 B34 D26 D24 D39 D10 D52 E03
D1 G35 D14 C33 D27 C21 D40 D08 D53 G05
D2 J35 D15 A35 D28 D22 D41 A05 D54 E01
D3 G33 D16 B32 D29 C19 D42 E09 D55 G03
D4 F36 D17 C31 D30 D20 D43 B04 D56 H04
D5 F34 D18 A33 D31 C17 D44 D06 D57 J03
D6 E35 D19 D28 D32 C15 D45 C05 D58 J05
D7 E33 D20 B30 D33 D16 D46 E07 D59 K04
D8 D34 D21 C29 D34 C13 D47 C03 D60 L05

D9 C37 D22 A31 D35 D14 D48 D04 D61 L03
D10 C35 D23 D26 D36 C11 D49 E05 D62 M04
D11 B36 D24 C27 D37 D12 D50 D02 D63 N03
D12 D32 D25 C23 D38 C09 D51 F04

E

PENTIUM® PROCESSO R 75/ 90/100/120/133/150/ 166/ 200

11

Table 1. Pin Cross Reference by Pin Name

(Continued)

Control

A20M# AK08 BRDYC# Y03 FLUSH# AN07 PEN# Z34
ADS# AJ05 BREQ AJ01 FRCMC# Y35 PM0/BP0 Q03
ADSC# AM02 BUSCHK# AL07 HIT# AK06 PM1/BP1 R04
AHOLD V04 CACHE# U03 HITM# AL05 PRDY AC05
AP AK02 CPUTYP Q35 HLDA AJ03 PWT AL03
APCHK# AE05 D/C# AK04 HOLD AB04 R/S# AC35
BE0# AL09 D/P# AE35 IERR# P04 RESET AK20
BE1# AK10 DP0 D36 IGNNE# AA35 SCYC AL17
BE2# AL11 DP1 D30 INIT AA33 SMI# AB34
BE3# AK12 DP2 C25 INTR/LINT0 AD34 SMIACT# AG03
BE4# AL13 DP3 D18 INV U05 TCK M34
BE5# AK14 DP4 C07 KEN# W05 TDI N35
BE6# AL15 DP5 F06 LOCK# AH04 TDO N33
BE7# AK16 DP6 F02 M/IO# T04 TMS P34
BOFF# Z04 DP7 N05 NA# Y05 TRST# Q33
BP2 S03 EADS# AM04 NMI/LINT1 AC33 W/R# AM06
BP3 S05 EWBE# W03 PCD AG05 WB/WT# AA05
BRDY# X04 FERR# Q05 PCHK# AF04

APIC Clock Control Dual Processor Private Interface

PICCLK H34 CLK AK18 PBGNT# AD04
PICD0 J33 BF0 Y33 PBREQ# AE03
[DPEN#] BF1 X34 PHIT# AA03
PICD1 L35 STPCLK# V34 PHITM# AC03
[APICEN]

V

CC

A07 A19 E37 L33 S01 W01 AC01 AN09 AN21
A09 A21 G01 L37 S37 W37 AC37 AN11 AN23
A11 A23 G37 N01 T34 Y01 AE01 AN13 AN25
A13 A25 J01 N37 U01 Y37 AE37 AN15 AN27
A15 A27 J37 Q01 U33 AA01 AG01 AN17 AN29
A17 A29 L01 Q37 U37 AA37 AG37 AN19

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

E

12

Table 1. Pin Cross Reference by Pin Name

(Continued)

Control

V

SS

B06 B22 M02 U35 AB36 AM08 AM24
B08 B24 M36 V02 AD02 AM10 AM26
B10 B26 P02 V36 AD36 AM12 AM28
B12 B28 P36 X02 AF02 AM14 AM30
B14 H02 R02 X36 AF36 AM16 AN37
B16 H36 R36 Z02 AH02 AM18
B18 K02 T02 Z36 AJ37 AM20
B20 K36 T36 AB02 AL37 AM22

NC/INC

1

A03 C01 S35 W35 AL01 AN01 AN05
A37 R34 W33 AL19 AN03 AN35
B02 S33

NOTE:

1. Please refer to socket 5 and socket 7 specifications if using socket 5 or socket 7.

2.2. Design Notes

For reliable operation, always c onnect unus ed inputs
to an appropriate signal level. Unused active low
inputs should be connected to V

CC

. Unused active

HIGH inputs should be connected to GND.
No Connect (NC) pins must remain unconnected.

Connection of NC pins may result in component
failure or incompatibility with processor steppings.

2.3. Quick Pin Reference

This section gives a brief functional description of
each of the pins. For a detailed descript ion, see the
“Hardware Interface” chapter in the

Pentium

®

Processor Family Developer’s Manual

, Volume 1.

Note

All input pins must meet their AC/DC
specifications to guarantee proper functional
behavior.

The # symbol at the end of a signal name indicates
that the active, or asserted state occurs when the
signal is at a low voltage. When a # symbol is not
present after t he signal name, the s ignal is ac tive, or
asserted at the high voltage level.

The following pins exist on the Pentium processor
60/66 but have been removed from the Pentium
processor 75/90/100/120/133/150/166/200:

• IBT, IU, IV, BT0-3
The following pins become I/O pins when two

Pentium processors 75/90/100/120/133/150/166/200
are operating in a dual processing environment:

• ADS#, CACHE#, HIT#, HITM#, HLDA#, LOCK#,
M/IO#, D/C#, W/R#, SCYC

E

PENTIUM® PROCESSO R 75/ 90/100/120/133/150/ 166/ 200

13

Table 2. Quick Pin Reference

Symbol Type* Name and Function

A20M# I When the

address bit 20 mask

pin is asserted, the Pentium® processor
75/90/100/120/133/150/166/200 emulates the address wraparound at 1 Mbyte
which occurs on the 8086 by masking physical address bit 20 (A20) before
performing a lookup to the internal caches or driving a memory cycle on the bus.
The effect of A20M# is undefined in protected mode. A20M# must be asserted
only when the processor is in real mode.

A20M# is internally masked by the Pentium processor 75/90/100/120/133/150/
166/200 when configured as a Dual processor.

A31-A3 I/O As outputs, the

address

lines of the processor along with the byte enables define
the physical area of memory or I/O accessed. The external system drives the
inquire address to the processor on A31-A5.

ADS# O The

address status

indicates that a new valid bus cycle is currently being driven

by the Pentium processor 75/90/100/120/133/150/166/200.

ADSC# O ADSC# is functionally identical to ADS#.
AHOLD I In response to the assertion of

address hold

, the Pentium processor
75/90/100/120/133/150/166/200 will stop driving the address lines (A31-A3), and
AP in the next clock. The rest of the bus will remain active so data can be returned
or driven for previously issued bus cycles.

AP I/O

Address parity

is driven by the Pentium processor
75/90/100/120/133/150/166/200 with even parity information on all Pentium
processor 75/90/100/120/133/150/166/200 generated cycles in the same clock
that the address is driven. Even parity must be driven back to the Pentium
processor 75/90/100/120/133/150/166/200 during inquire cycles on this pin in the
same clock as EADS# to ensure that correct parity check status is indicated by
the Pentium processor 75/90/100/120/133/150/166/200.

APCHK# O The

address parity check

status pin is asserted two clocks after EADS# is
sampled active if the Pentium processor 75/90/100/120/133/150/166/200 has
detected a parity error on the address bus during inquire cycles. APCHK# will
remain active for one clock each time a parity error is detected (including during
dual processing private snooping).

[APICEN]
PICD1

I

Advanced Programmable Interrupt Controller Enable

enables or disables the
on-chip APIC interrupt controller. If sampled high at the falling edge of RESET, the
APIC is enabled. APICEN shares a pin with the PICD1 signal.

BE7#-BE5#
BE4#-BE0#

O

I/O

The

byte enable

pins are used to determine which bytes must be written to
external memory, or which bytes were requested by the CPU for the current cycle.
The byte enables are driven in the same clock as the address lines (A31-3).

Additionally, the lower 4-byte enables (BE3#-BE0#) are used on the Pentium
processor 75/90/100/120/133/150/166/200 as APIC ID inputs and are sampled at
RESET.

In dual processing mode, BE4# is used as an input during Flush cycles.

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

E

14

Table 2. Quick Pin Reference

(Continued)

Symbol Type* Name and Function

BF[1:0] I

Bus Frequency

determines the bus-to-core frequency ratio. BF[1:0] are sampled
at RESET, and cannot be changed until another non-warm (1 ms) assertion of
RESET. Additionally, BF[1:0] must not change values while RESET is active. See
Table 3 for Bus Frequency Selections.

BOFF# I The

backoff

input is used to abort all outstanding bus cycles that have not yet
completed. In response to BOFF#, the Pentium processor 75/90/100/120/133/150/
166/200 will float all pins normally floated during bus hold in the next clock. The
processor remains in bus hold until BOFF# is negated, at which time the Pentium
processor 75/90/100/120/133/150/166/200 restarts the aborted bus cycle(s) in
their entirety.

BP[3:2]
PM/BP[1:0]

O The

breakpoint

pins (BP3-0) correspond to the debug registers, DR3-DR0.
These pins externally indicate a breakpoint match when the debug registers are
programmed to test for breakpoint matches.

BP1 and BP0 are multiplexed with the

performance monitoring

pins (PM1 and
PM0). The PB1 and PB0 bits in the Debug Mode Control Register determine if the
pins are configured as breakpoint or performance monitoring pins. The pins come
out of RESET configured for performance monitoring.

BRDY# I The

burst ready

input indicates that the external system has presented valid data
on the data pins in response to a read or that the external system has accepted
the Pentium processor 75/90/100/120/133/150/166/200 data in response to a write
request. This signal is sampled in the T2, T12 and T2P bus states.

BRDYC# I This signal has the same functionality as BRDY#.
BREQ O The

bus request

output indicates to the external system that the Pentium
processor 75/90/100/120/133/150/166/200 has internally generated a bus request.
This signal is always driven whether or not the Pentium processor
75/90/100/120/133/150/166/200 is driving its bus.

BUSCHK# I The

bus check

input allows the system to signal an unsuccessful completion of a
bus cycle. If this pin is sampled active, the Pentium processor
75/90/100/120/133/150/166/200 will latch the address and control signals in the
machine check registers. If, in addition, the MCE bit in CR4 is set, the Pentium
processor 75/90/100/120/133/150/166/200 will vector to the machine check
exception.

NOTE:

To assure that BUSCHK# will always be recognized, STPCLK# must be
deasserted any time BUSCHK# is asserted by the system, before the system
allows another external bus cycle. If BUSCHK# is asserted by the system for a
snoop cycle while STPCLK# remains asserted, usually (if MCE=1) the processor
will vector to the exception after STPCLK# is deasserted. But if another snoop to
the same line occurs during STPCLK# assertion, the processor can lose the
BUSCHK# request.

E

PENTIUM® PROCESSO R 75/ 90/100/120/133/150/ 166/ 200

15

Table 2. Quick Pin Reference

(Continued)

Symbol Type* Name and Function

CACHE# O For Pentium processor 75/90/100/120/133/150/166/200 -initiated cycles the

cache

pin indicates internal cacheability of the cycle (if a read), and indicates a burst
write back cycle (if a write). If this pin is driven inactive during a read cycle, the
Pentium processor 75/90/100/120/133/150/166/200 will not cache the returned
data, regardless of the state of the KEN# pin. This pin is also used to determine
the cycle length (number of transfers in the cycle).

CLK I The

clock

input provides the fundamental timing for the Pentium processor
75/90/100/120/133/150/166/200. Its frequency is the operating frequency of the
Pentium processor 75/90/100/120/133/150/166/200 external bus, and requires
TTL levels. All external timing parameters except TDI, TDO, TMS, TRST#, and
PICD0-1 are specified with respect to the rising edge of CLK.

NOTE:

It is recommended that CLK begin toggling within 150 ms after V

CC

reaches its
proper operating level. This recommendation is to ensure long-term reliability of
the device.

CPUTYP I

CPU type

distinguishes the Primary processor from the Dual processor. In a
single processor environment, or when the Pentium processor 75/90/100/120/133/
150/166/200 is acting as the Primary processor in a dual processing system,
CPUTYP should be strapped to V

SS

. The Dual processor should have CPUTYP

strapped to V

CC

. For the Pentium OverDrive processor, CPUTYP will be used to
determine whether the bootup handshake protocol will be used (in a dual socket
system) or not (in a single socket system).

D/C# O The

data/code

output is one of the primary bus cycle definition pins. It is driven
valid in the same clock as the ADS# signal is asserted. D/C# distinguishes
between data and code or special cycles.

D/P# O The

dual/primary

processor indication. The Primary processor drives this pin low
when it is driving the bus, otherwise it drives this pin high. D/P# is always driven.
D/P# can be sampled for the current cycle with ADS# (like a status pin). This pin
is defined only on the Primary processor. Dual processing is supported in a
system only if both processors are operating at identical core and bus
frequencies. Within these restrictions, two processors of different steppings may
operate together in a system.

D63-D0 I/O These are the 64

data lines

for the processor. Lines D7-D0 define the least
significant byte of the data bus; lines D63-D56 define the most significant byte of
the data bus. When the CPU is driving the data lines, they are driven during the
T2, T12, or T2P clocks for that cycle. During reads, the CPU samples the data
bus when BRDY# is returned.

DP7-DP0 I/O These are the

data parity

pins for the processor. There is one for each byte of the
data bus. They are driven by the Pentium processor 75/90/100/120/133/150/166/
200 with even parity information on writes in the same clock as write data. Even
parity information must be driven back to the Pentium processor 75/90/100/120/
133/150/166/200 on these pins in the same clock as the data to ensure that the
correct parity check status is indicated by the Pentium processor 75/90/100/120/
133/150/166/200. DP7 applies to D63-56, DP0 applies to D7-0.

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

E

16

Table 2. Quick Pin Reference

(Continued)

Symbol Type* Name and Function

[DPEN#]
PICD0

I/O

Dual processing enable

is an output of the Dual processor and an input of the
Primary processor. The Dual processor drives DPEN# low to the Primary
processor at RESET to indicate that the Primary processor should enable dual
processor mode. DPEN# may be sampled by the system at the falling edge of
RESET to determine if the dual-processor socket is occupied. DPEN# shares a
pin with PICD0.

EADS# I This signal indicates that a valid

external address

has been driven onto the
Pentium processor 75/90/100/120/133/150/166/200 address pins to be used for an
inquire cycle.

EWBE# I The

external write buffer empty

input, when inactive (high), indicates that a write
cycle is pending in the external system. When the Pentium processor 75/90/100/
120/133/150/166/200 generates a write, and EWBE# is sampled inactive, the
Pentium processor 75/90/100/120/133/150/166/200 will hold off all subsequent
writes to all E- or M-state lines in the data cache until all write cycles have
completed, as indicated by EWBE# being active.

FERR# O The

floating point error

pin is driven active when an unmasked floating point
error occurs. FERR# is similar to the ERROR# pin on the Intel387™ math
coprocessor. FERR# is included for compatibility with systems using DOS type
floating point error reporting. FERR# is never driven active by the Dual processor.

FLUSH# I When asserted, the

cache flush

input forces the Pentium processor 75/90/100/
120/133/150/166/200 to write back all modified lines in the data cache and
invalidate its internal caches. A Flush Acknowledge special cycle will be
generated by the Pentium processor 75/90/100/120/133/150/166/200 indicating
completion of the write back and invalidation.

If FLUSH# is sampled low when RESET transitions from high to low, tristate test
mode is entered.

If two Pentium processor 75/90/100/120/133/150/166/200 are operating in dual
processing mode and FLUSH# is asserted, the Dual processor will perform a flush
first (without a flush acknowledge cycle), then the Primary processor will perform
a flush followed by a flush acknowledge cycle.

NOTE:

If the FLUSH# signal is asserted in dual processing mode, it must be deasserted
at least one clock prior to BRDY# of the FLUSH Acknowledge cycle to avoid DP
arbitration problems.

E

PENTIUM® PROCESSO R 75/ 90/100/120/133/150/ 166/ 200

17

Table 2. Quick Pin Reference

(Continued)

Symbol Type* Name and Function

FRCMC# I The

functional redundancy checking master/checker

mode input is used to
determine whether the Pentium processor 75/90/100/120/133/150/166/200 is
configured in master mode or checker mode. When configured as a master, the
Pentium processor 75/90/100/120/133/150/166/200 drives its output pins as
required by the bus protocol. When configured as a checker, the Pentium
processor 75/90/100/120/133/150/166/200 tristates all outputs (except IERR# and
TDO) and samples the output pins.

The configuration as a master/checker is set after RESET and may not be
changed other than by a subsequent RESET.

HIT# O The

hit

indication is driven to reflect the outcome of an inquire cycle. If an inquire
cycle hits a valid line in either the Pentium processor 75/90/100/120/133/150/166/
200 data or instruction cache, this pin is asserted two clocks after EADS# is
sampled asserted. If the inquire cycle misses the Pentium processor 75/90/100/
120/133/150/166/200 cache, this pin is negated two clocks after EADS#. This pin
changes its value only as a result of an inquire cycle and retains its value between
the cycles.

HITM# O The

hit to a modified line

output is driven to reflect the outcome of an inquire
cycle. It is asserted after inquire cycles which resulted in a hit to a modified line in
the data cache. It is used to inhibit another bus master from accessing the data
until the line is completely written back.

HLDA O The

bus hold acknowledge

pin goes active in response to a hold request driven
to the processor on the HOLD pin. It indicates that the Pentium processor 75/90/
100/120/133/150/166/200 has floated most of the output pins and relinquished the
bus to another local bus master. When leaving bus hold, HLDA will be driven
inactive and the Pentium processor 75/90/100/120/133/150/166/200 will resume
driving the bus. If the Pentium processor 75/90/100/120/133/150/166/200 has a
bus cycle pending, it will be driven in the same clock that HLDA is de-asserted.

HOLD I In response to the

bus hold request

, the Pentium processor 75/90/100/120/133/
150/166/200 will float most of its output and input/output pins and assert HLDA
after completing all outstanding bus cycles. The Pentium processor 75/90/100/
120/133/150/166/200 will maintain its bus in this state until HOLD is de-asserted.
HOLD is not recognized during LOCK cycles. The Pentium processor 75/90/100/
120/133/150/166/200 will recognize HOLD during reset.

IERR# O The

internal error

pin is used to indicate two types of errors, internal parity errors
and functional redundancy errors. If a parity error occurs on a read from an
internal array, the Pentium processor 75/90/100/120/133/150/166/200 will assert
the IERR# pin for one clock and then shutdown. If the Pentium processor
75/90/100/120/133/150/166/200 is configured as a checker and a mismatch
occurs between the value sampled on the pins and the corresponding value
computed internally, the Pentium processor 75/90/100/120/133/150/166/200 will
assert IERR# two clocks after the mismatched value is returned.

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

E

18

Table 2. Quick Pin Reference

(Continued)

Symbol Type* Name and Function

IGNNE# I Th i s i s t h e

ignore numeric error

input. This pin has no effect when the NE bit in CR0 is
set to 1. When the CR0.NE bit is 0, and the IGNNE# pin is asserted, the Pentium
processor 75/90/100/120/133/150/166/200 will ignore any pending unmasked numeric
exception and continue executing floating-point instructions for the entire duration that
this pin is asserted. When the CR0.NE bit is 0, IGNNE# is not asserted, a pending
unmasked numeric exception exists (SW.ES = 1), and the floating point instruction is
one of FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, or FSETPM,
the Pentium processor 75/90/100/120/133/150/166/200 will execute the instruction in
spite of the pending exception. When the CR0.NE bit is 0, IGNNE# is not asserted, a
pending unmasked numeric exception exists (SW.ES = 1), and the floating-point
instruction is one other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI,
FDISI, or FSETPM, the Pentium processor 75/90/100/120/133/
150/166/200 will stop execution and wait for an external interrupt.

IGNNE# is internally masked when the Pentium processor 75/90/100/120/133/150/
166/200 is configured as a Dual processor.

INIT I The Pentium processor 75/90/100/120/133/150/166/200

initialization

input pin
forces the Pentium proces s or 75/90/100/120/133/150/166/200 to begin execution
in a known state. The processor state after INIT is the same as the state after
RESET except that the internal caches, write buffers, and floating point registers
retain the values they had prior to INIT. INIT may NOT be used in lieu of RESET
after power-up.

If INIT is sampled high when RESET transitions from high to low, the Pentium
proces s or 75/90/100/120/133/150/166/200 will perform built-in self test prior to the
start of program execution.

INTR/LINT0 I An active

maskable interrupt

input indicates that an external interrupt has been
generated. If the IF bit in the EFLAGS register is set, the Pentium processor
75/90/100/120/133/150/166/200 will generate two locked interrupt acknowledge
bus cycles and vector to an interrupt handler after the current instruction execution
is completed. INTR must remain active until the first interrupt acknowledge cycle
is generated to assure that the interrupt is recognized.

If the local APIC is enabled, this pin becomes LINT0.

INV I The

invalidation

input determines the final cache line state (S or I) in case of an
inquire cycle hit. It is sampled together with the address for the inquire cycle in the
clock EADS# is sampled active.

KEN# I The

cache enable

pin is used to determine whether the current cycle is cacheable
or not and is consequently used to determine cycle length. When the Pentium
processor 75/90/100/120/133/150/166/200 generates a cycle that can be cached
(CACHE# asserted) and KEN# is active, the cycle will be transformed into a burst
line fill cycle.

LINT0/INTR I If the APIC is enabled, this pin is

local interrupt 0

. If the APIC is disabled, this pin

is INTR.

LINT1/NMI I If the APIC is enabled, this pin is

local interrupt 1

. If the APIC is disabled, this pin

is NMI.

E

PENTIUM® PROCESSO R 75/ 90/100/120/133/150/ 166/ 200

19

Table 2. Quick Pin Reference

(Continued)

Symbol Type* Name and Function

LOCK# O The

bus lock

pin indicates that the current bus cycle is locked. The Pentium
proces s or 75/90/100/120/133/150/166/200 will not allow a bus hold when LOCK#
is asserted (but AHOLD and BOFF# are allowed). LOCK# goes active in the first
clock of the first locked bus cycle and goes inactive after the BRDY# is returned
for the last locked bus cycle. LOCK# is guaranteed to be de-asserted for at least
one clock between back-to-back locked cycles.

M/IO# O The

memory/input-output

is one of the primary bus cycle definition pins. It is
driven valid in the same clock as the ADS# signal is asserted. M/IO# distinguishes
between memory and I/O cycles.

NA# I An active

next address

input indicates that the external memory system is ready
to accept a new bus cycle although all data transfers for the current cycle have
not yet completed. The Pentium process or 75/90/100/120/133/150/166/200 will
issue ADS# for a pending cycle two clocks after NA# is asserted. The Pentium
proces s or 75/90/100/120/133/150/166/200 supports up to 2 outstanding bus
cycles.

NMI/LINT1 I Th e

non-maskable interrupt

request signal indicates that an external non-maskable

interrupt has been generated.
If the local APIC is enabled, this pin becomes LINT1.

PBGNT# I/O

Private bus grant

is the grant line that is used when two Pentium processor
75/90/100/120/133/150/166/200 are configured in dual processing mode, in order
to perform private bus arbitration. PBGNT# should be left unconnected if only one
Pentium processor 75/90/100/120/133/150/166/200 exists in a system.

PBREQ# I/O

Private bus request

is the request line that is used when two Pentium processor
75/90/100/120/133/150/166/200 are configured in dual processing mode, in order
to perform private bus arbitration. PBREQ# should be left unconnected if only one
Pentium processor 75/90/100/120/133/150/166/200 exists in a system.

PCD O The

page cache disable

pin reflects the state of the PCD bit in CR3, the Page
Directory Entry, or the Page Table Entry. The purpose of PCD is to provide an
external cacheability indication on a page by page basis.

PCHK# O The

parity check

output indicates the result of a parity check on a data read. It is
driven with parity status two clocks after BRDY# is returned. PCHK# remains low
one clock for each clock in which a parity error was detected. Parity is checked
only for the bytes on which valid data is returned.

When two Pentium process or 75/90/100/120/133/150/166/200 are operating in
dual processing mode, PCHK# may be driven two or three clocks after BRDY# is
returned.

PEN# I The

parity enable

input (along with CR4.MCE) determines whether a machine
check exception will be taken as a result of a data parity error on a read cycle. If
this pin is sampled active in the clock a data parity error is detected, the Pentium
proces s or 75/90/100/120/133/150/166/200 will latch the address and control
signals of the cycle with the parity error in the machine check registers. If, in
addition, the machine check enable bit in CR4 is set to “1”, the Pentium proces s or
75/90/100/120/133/150/166/200 will vector to the machine check exception before
the beginning of the next instruction.

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

E

20

Table 2. Quick Pin Reference

(Continued)

Symbol Type* Name and Function

PHIT# I/O

Private hit

is a hit indication used when two Pentium proces s or 75/90/100/120/
133/150/166/200 are configured in dual processing mode, in order to maintain
local cache coherency. PHIT# should be left unconnected if only one Pentium
processor 75/90/100/120/133/150/166/200 exists in a system.

PHITM# I/O

Private modified hit

is a hit indication used when two Pentium processor
75/90/100/120/133/150/166/200 are configured in dual processing mode, in order
to maintain local cache coherency. PHITM# should be left unconnected if only one
Pentium processor 75/90/100/120/133/150/166/200 exists in a system.

PICCLK I The APIC interrupt controller serial data bus clock is driven into the

programmable interrupt controller clock

input of the Pentium process or

75/90/100/120/133/150/166/200.

PICD0-1
[DPEN#]
[APICEN]

I/O

Programmable interrupt controller data lines 0-1

of the Pentium process or
75/90/100/120/133/150/166/200 comprise the data portion of the APIC 3-wire bus.
They are open-drain outputs that require external pull-up resistors. These signals
share pins with DPEN# and APICEN respectively.

PM/BP[1:0] O These pins function as part of the performance monitoring feature.

The breakpoint 1-0 pins are multiplexed with the

performance monitoring 1-0

pins. The PB1 and PB0 bits in the Debug Mode Control Register determine if the
pins are configured as breakpoint or performance monitoring pins. The pins come
out of RESET configured for performance monitoring.

PRDY O The

probe ready

output pin indicates that the processor has stopped normal

execution in response to the R/S# pin going active, or Probe Mode being entered.

PWT O The

page write through

pin reflects the state of the PWT bit in CR3, the page
directory entry, or the page table entry. The PWT pin is used to provide an
external write back indication on a page-by-page basis.

R/S# I The

run/stop

input is an asynchronous, edge-sensitive interrupt used to stop the
normal execution of the processor and place it into an idle state. A high to low
transition on the R/S# pin will interrupt the processor and cause it to stop
execution at the next instruction boundary.

RESET I

RESET

forces the Pentium process or 75/90/100/120/133/150/166/200 to begin
execution at a known state. All the Pentium proces s or 75/90/100/120/133/150/
166/200 internal caches will be invalidated upon the RESET. Modified lines in the
data cache are not written back. FLUSH#, FRCMC# and INIT are sampled when
RESET transitions from high to low to determine if tristate test mode or checker
mode will be entered, or if BIST will be run.

SCYC O The

split cycle

output is asserted during misaligned LOCKed transfers to indicate
that more than two cycles will be locked together. This signal is defined for locked
cycles only. It is undefined for cycles which are not locked.

SMI# I The

system management interrupt

causes a system management interrupt
request to be latched internally. When the latched SMI# is recognized on an
instruction boundary, the processor enters System Management Mode.

E

PENTIUM® PROCESSO R 75/ 90/ 100/ 120/ 133/ 150/ 166/ 200

21

Table 2. Quick Pin Reference

(Continued)

Symbol Type* Name and Function

SMIACT# O An active

system management interrupt active

output indicates that the

processor is operating in System Management Mode.

STPCLK# I Assertion of the

stop clock

input signifies a request to stop the internal clock of
the Pentium proces s or 75/90/100/120/133/150/166/200 thereby causing the core to
consume less power. When the CPU recognizes STPCLK#, the processor will
stop execution on the next instruction boundary, unless superseded by a higher
priority interrupt, and generate a stop grant acknowledge cycle. When STPCLK#
is asserted, the Pentium proces s or 75/90/100/120/133/150/166/200 will still
respond to interprocessor and external snoop requests.

TCK I The

testability clock

input provides the clocking function for the Pentium
processor 75/90/100/120/133/150/166/200 boundary scan in accordance with the
IEEE Boundary Scan interface (Standard 1149.1). It is used to clock state
information and data into and out of the Pentium process or 75/90/100/120/133/150/
166/200 during boundary scan.

TDI I The

test data input

is a serial input for the test logic. TAP instructions and data
are shifted into the Pentium process or 75/90/100/120/133/150/166/200 on the TDI
pin on the rising edge of TCK when the TAP controller is in an appropriate state.

TDO O The

test data output

is a serial output of the test logic. TAP instructions and data
are shifted out of the Pentium process or 75/90/100/120/133/150/166/200 on the
TDO pin on TCK's falling edge when the TAP controller is in an appropriate state.

TMS I The value of the

test mode select

input signal sampled at the rising edge of TCK

controls the sequence of TAP controller state changes.

TRST# I When asserted, the

test reset

input allows the TAP controller to be

asynchronously initialized.

V

CC

I The Pentium processor 75/90/100/120/133/150/166/200 has 53 3.3V

power

inputs.

V

SS

I The Pentium processor 75/90/100/120/133/150/166/200 has 53

ground

inputs.

W/R# O

Write/read

is one of the primary bus cycle definition pins. It is driven valid in the
same clock as the ADS# signal is asserted. W/R# distinguishes between write
and read cycles.

WB/WT# I The

write back/write through

input allows a data cache line to be defined as
write back or write through on a line-by-line basis. As a result, it determines
whether a cache line is initially in the S or E state in the data cache.

NOTE:

•

The pins are classified as Input or Output based on their function in Master Mode. See the Functional Redundancy
Checking section in the “Error Detection” chapter of the

Pentium

®

Processor Family Developer’s Manual

, Volume 1, for

further information.