Intel Corporation F28F020-90, F28F020-150 Datasheet
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changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
November 1995COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 290245-007
28F020
2048K (256K x 8) CMOS FLASH MEMORY
Y
Flash Electrical Chip-Erase
Ð 2 Second Typical Chip-Erase
Y
Quick-Pulse Programming Algorithm
Ð10 ms Typical Byte-Program
Ð 4 Second Chip-Program
Y
100,000 Erase/Program Cycles
Y
12.0Vg5% V
PP
Y
High-Performance Read
Ð 70 ns Maximum Access Time
Y
CMOS Low Power Consumption
Ð 10 mA Typical Active Current
Ð50 mA Typical Standby Current
Ð 0 Watts Data Retention Power
Y
Integrated Program/Erase Stop Timer
Y
Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
Y
Noise Immunity Features
Ð
g
10% VCCTolerance
Ð Maximum Latch-Up Immunity
through EPI Processing
Y
ETOXTMNonvolatile Flash Technology
Ð EPROM-Compatible Process Base
Ð High-Volume Manufacturing
Experience
Y
JEDEC-Standard Pinouts
Ð 32-Pin Plastic Dip
Ð 32-Lead PLCC
Ð 32-Lead TSOP
(See Packaging Spec., OrderÝ231369)
Y
Extended Temperature Options
Intel’s 28F020 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F020 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; onboard during subassembly test; in-system during final test; and in-system after-sale. The 28F020 increases
memory flexibility, while contributing to time-and cost-savings.
The 28F020 is a 2048-kilobit nonvolatile memory organized as 262,144 bytes of 8 bits. Intel’s 28F020 is
offered in 32-pin plastic DIP, 32-lead PLCC, and 32-lead TSOP packages. Pin assignments conform to JEDEC
standards for byte-wide EPROMs.
Extended erase and program cycling capability is designed into Intel’s ETOX (EPROM Tunnel Oxide) process
technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field combine to
extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V V
PP
supply, the 28F020 performs
100,000 erase and program cyclesÐwell within the time limits of the Quick-Pulse Programming and QuickErase algorithms.
Intel’s 28F020 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low
power consumption, and immunity to noise. Its 70 ns access time provides zero wait-state performance for a
wide range of microprocessors and microcontrollers. Maximum standby current of 100 mA translates into
power savings when the device is deselected. Finally, the highest degree of latch-up protection is achieved
through Intel’s unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA on address
and data pins, from
b
1V to V
CC
a
1V.
With Intel’s ETOX process base, the 28F020 builds on years of EPROM experience to yield the highest levels
of quality, reliability, and cost-effectiveness.
28F020
290245– 1
Figure 1. 28F020 Block Diagram
Table 1. Pin Description
Symbol Type Name and Function
A0–A
17
INPUT ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
DQ0–DQ7INPUT/OUTPUT DATA INPUT/OUTPUT: Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active high
and float to tri-state OFF when the chip is deselected or the outputs
are disabled. Data is internally latched during a write cycle.
CE
Ý
INPUT CHIP ENABLE: Activates the device’s control logic, input buffers,
decoders and sense amplifiers. CE
Ý
is active low; CEÝhigh
deselects the memory device and reduces power consumption to
standby levels.
OE
Ý
INPUT OUTPUT ENABLE: Gates the devices output through the data buffers
during a read cycle. OE
Ý
is active low.
WE
Ý
INPUT WRITE ENABLE: Controls writes to the control register and the array.
Write enable is active low. Addresses are latched on the falling edge
and data is latched on the rising edge of the WE
Ý
pulse.
Note: With V
PP
s
6.5V, memory contents cannot be altered.
V
PP
ERASE/PROGRAM POWER SUPPLY for writing the command
register, erasing the entire array, or programming bytes in the array.
V
CC
DEVICE POWER SUPPLY (5Vg10%)
V
SS
GROUND
2
28F020
290245– 2
290245– 3
290245– 4
290245– 5
Figure 2. 28F020 Pin Configurations
3
28F020
APPLICATIONS
The 28F020 flash memory provides nonvolatility
along with the capability to perform over 100,000
electrical chip-erasure/reprogram cycles. These features make the 28F020 an innovative alternative to
disk, EEPROM, and battery-backed static RAM.
Where periodic updates of code and data-tables are
required, the 28F020’s reprogrammability and nonvolatility make it the obvious and ideal replacement
for EPROM.
Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption Ð a consideration particularly important in portable equipment. Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and application code. With updatable code, system manufacturers can easily accommodate last-minute changes as
revisions are made.
In diskless workstations and terminals, network traffic reduces to a minimum and systems are instanton. Reliability exceeds that of electromechanical
media. Often in these environments, power interruptions force extended re-boot periods for all networked terminals. This mishap is no longer an issue
if boot code, operating systems, communication protocols and primary applications are flash-resident in
each terminal.
For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, the 28F020 flash memory offers a solid
state alternative in a minimal form factor. The
28F020 provides higher performance, lower power
consumption, instant-on capability, and allows an
‘‘execute in place’’ memory hierarchy for code and
data table reading. Additionally, the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause
disk-based systems to fail.
The need for code updates pervades all phases of a
system’s life Ð from prototyping to system manufacture to after-sale service. The electrical chip-erasure
and reprogramming ability of the 28F020 allows incircuit alterability; this eliminates unnecessary handling and less-reliable socketed connections, while
adding greater test, manufacture, and update flexibility.
Material and labor costs associated with code
changes increases at higher levels of system integration Ð the most costly being code updates after
sale. Code ‘‘bugs’’, or the desire to augment system
functionality, prompt after-sale code updates. Field
revisions to EPROM-based code requires the removal of EPROM components or entire boards. With
the 28F020, code updates are implemented locally
via an edge-connector, or remotely over a communcations link.
For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory’s inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.
Flash memory’s electrical chip erasure, byte programmability and complete nonvolatility fit well with
data accumulation and recording needs. Electrical
chip-erasure gives the designer a ‘‘blank slate’’ in
which to log or record data. Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new ‘‘blank slate’’.
A high degree of on-chip feature integration simplifies memory-to-processor interfacing. Figure 4 depicts two 28F020s tied to the 80C186 system bus.
The 28F020’s architecture minimizes interface circuitry needed for complete in-circuit updates of
memory contents.
The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1.2 mm thickness. With standard and reverse pin configurations, TSOP reduces
the number of board layers and overall volume necessary to layout multiple 28F020s. TSOP is particularly suited for portable equipment and applications
requiring large amounts of flash memory. Figure 3
illustrates the TSOP Serpentine layout.
With cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility,
the 28F020 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straight-forward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today’s designs.
4
28F020
Figure 3. TSOP Serpentine Layout
290245– 20
5
28F020
290245– 6
Figure 4. 28F020 in a 80C186 System
PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F020 introduces a command register to manage
this new functionality. The command register allows
for 100% TTL-level control inputs, fixed power supplies during erasure and programming, and maximum EPROM compatibility.
In the absence of high voltage on the V
PP
pin, the
28F020 is a read-only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and Intelligent Identifier operations.
The same EPROM read, standby, and output disable
operations are available when high voltage is applied to the V
PP
pin. In addition, high voltage on V
PP
enables erasure and programming of the device. All
functions associated with altering memory contentsÐIntelligent Identifier, erase, erase verify, program, and program verifyÐare accessed via the
command register.
Commands are written to the register using standard
microprocessor write timings. Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for programming or erase operations. With
the appropriate command written to the register,
standard microprocessor read timings output array
data, access the Intelligent Identifier codes, or output data for erase and program verification.
Integrated Stop Timer
Successive command write cycles define the durations of program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing
specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or erase operation, the device enters an inactive state and remains inactive until receiving the appropriate verify or reset command.
Write Protection
The command register is only active when VPPis at
high voltage. Depending upon the application, the
system designer may choose to make the V
PP
power supply switchableÐavailable only when memory
updates are desired. When V
PP
e
V
PPL
, the contents of the register default to the read command,
making the 28F020 a read-only memory. In this
mode, the memory contents cannot be altered.
6
28F020
Table 2. 28F020 Bus Operations
Mode V
PP
(1)
A0A9CEÝOEÝWEÝDQ0–DQ
7
Read V
PPLA0A9
V
IL
V
IL
VIHData Out
Output Disable V
PPL
XXVILV
IHVIH
Tri-State
READ-ONLY Standby V
PPL
XXVIHX X Tri-State
Intelligent Identifier (Mfr)
(2)
V
PPLVILVID
(3)
V
IL
V
IL
VIHDatae89H
Intelligent Identifier (Device)
(2)
V
PPLVIHVID
(3)
V
IL
V
IL
VIHDataeBDH
Read V
PPHA0A9
V
IL
V
IL
VIHData Out
(4)
READ/WRITE Output Disable V
PPH
XXVILV
IHVIH
Tri-State
Standby
(5)
V
PPH
XXVIHX X Tri-State
Write V
PPHA0A9
V
IL
V
IHVIL
Data In
(6)
NOTES:
1. Refer to DC Characteristics. When V
PP
e
V
PPL
memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All
other addresses low.
3. V
ID
is the Intelligent Identifier high voltage. Refer to DC Characteristics.
4. Read operations with V
PP
e
V
PPH
may access array data or the Intelligent Identifier codes.
5. With V
PP
at high voltage, the standby current equals I
CC
a
IPP(standby).
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be V
IL
or VIH.
Or, the system designer may choose to ‘‘hardwire’’
V
PP
, making the high voltage supply constantly
available. In this case, all Command Register functions are inhibited whenever V
CC
is below the write
lockout voltage V
LKO
. (See Power Up/Down Protection.) The 28F020 is designed to accommodate either design practice, and to encourage optimization
of the processor-memory interface.
The two step program/erase write sequence to the
Command Register provides additional software
write protection.
BUS OPERATIONS
Read
The 28F020 has two control functions, both of which
must be logically active, to obtain data at the outputs. Chip-Enable (CE
Ý
) is the power control and
should be used for device selection. Output-Enable
(OE
Ý
) is the output control and should be used
to gate data from the output pins, independent of
device selection. Refer to AC read timing
waveforms.
When V
PP
is high (V
PPH
), the read operation can be
used to access array data, to output the Intelligent
Identifier codes, and to access data for program/
erase verification. When V
PP
is low (V
PPL
), the read
operation can only access the array data.
Output Disable
With OE
Ý
at a logic-high level (VIH), output from the
device is disabled. Output pins are placed in a highimpedance state.
Standby
With CE
Ý
at a logic-high level, the standby operation disables most of the 28F020’s circuitry and substantially reduces device power consumption. The
outputs are placed in a high-impedance state, independent of the OE
Ý
signal. If the 28F020 is deselected during erasure, programming, or program/
erase verification, the device draws active current
until the operation is terminated.
7
28F020
Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manufacturer code (89H) and device code (BDH). Programming equipment automatically matches the device with its proper erase and programming algorithms.
With CE
Ý
and OEÝat a logic low level, raising A9
to high voltage V
ID
(see DC Characteristics) activates the operation. Data read from locations 0000H
and 0001H represent the manufacturer’s code and
the device code, respectively.
The manufacturer- and device-codes can also be
read via the command register, for instances where
the 28F020 is erased and reprogrammed in the target system. Following a write of 90H to the command register, a read from address location 0000H
outputs the manufacturer code (89H). A read from
address 0001H outputs the device code (BDH).
Write
Device erasure and programming are accomplished
via the command register, when high voltage is applied to the V
PP
pin. The contents of the register
serve as input to the internal state-machine. The
state-machine outputs dictate the function of the
device.
The command register itself does not occupy an addressable memory location. The register is a latch
used to store the command, along with address and
data information needed to execute the command.
The command register is written by bringing WE
Ý
to
a logic-low level (V
IL
), while CEÝis low. Addresses
are latched on the falling edge of WE
Ý
while data is
latched on the rising edge of the WE
Ý
pulse. Stan-
dard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing
parameters.
COMMAND DEFINITIONS
When low voltage is applied to the V
PP
pin, the contents of the command register default to 00H, enabling read-only operations.
Placing high voltage on the VPPpin enables read/
write operations. Device operations are selected by
writing specific data patterns into the command register. Table 3 defines these 28F020 register
commands.
Table 3. Command Definitions
Cycles
Req’d
Bus
First Bus Cycle Second Bus Cycle
Command
Operation
(1)
Address
(2)
Data
(3)
Operation
(1)
Address
(2)
Data
(3)
Read Memory 1 Write X 00H
Read Intelligent Identifier Codes
(4)
3 Write IA 90H Read IA ID
Set-up Erase/Erase
(5)
2 Write X 20H Write X 20H
Erase Verify
(5)
2 Write EA A0H Read X EVD
Set-up Program/Program
(6)
2 Write X 40H Write PA PD
Program Verify
(6)
2 Write X C0H Read X PVD
Reset
(7)
2 Write X FFH Write X FFH
NOTES:
1. Bus operations are defined in Table 2.
2. IA
e
Identifier address: 00H for manufacturer code, 01H for device code.
EA
e
Erase Address: Address of memory location to be read during erase verify.
PA
e
Program Address: Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. ID
e
Identifier Address: Data read from location IA during device identification (Mfre89H, DeviceeBDH).
EVD
e
Erase Verify Data: Data read from location EA during erase verify.
PD
e
Program Data: Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD
e
Program Verify Data: Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read Intelligent ID command, two read operations access manufacturer and device codes.
5. Figure 6 illustrates the Quick-Erase Algorithm.
6. Figure 5 illustrates the Quick-Pulse Programming Algorithm.
7. The second bus cycle must be followed by the desired command register write.
8
28F020
Read Command
While VPPis high, for erasure and programming,
memory contents can be accessed via the read
command. The read operation is initiated by writing
00H into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register contents are altered.
The default contents of the register upon V
PP
power-up is 00H. This default value ensures that no spurious alteration of memory contents occurs during
the V
PP
power transition. Where the VPPsupply is
hard-wired to the 28F020, the device powers-up and
remains enabled for reads until the command-register contents are changed. Refer to the AC Read
Characteristics and Waveforms for specific timing
parameters.
Intelligent Identifier Command
Flash-memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides in the target system. PROM programmers typically access signature
codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a desired system-design practice.
The 28F020 contains an Intelligent Identifier operation to supplement traditional PROM-programming
methodology. The operation is initiated by writing
90H into the command register. Following the command write, a read cycle from address 0000H retrieves the manufacturer code of 89H. A read cycle
from address 0001H returns the device code of
BDH. To terminate the operation, it is necessary to
write another valid command into the register.
Set-up Erase/Erase Commands
Set-up Erase is a command-only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register.
To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
WE
Ý
pulse and terminates with the rising edge of
the next WE
Ý
pulse (i.e., Erase-Verify Command).
This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when
high voltage is applied to the V
PP
pin. In the absence
of this high voltage, memory contents are protected
against erasure. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.
Erase-Verify Command
The erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing A0H into the command register. The address
for the byte to be verified must be supplied as it is
latched on the falling edge of the WE
Ý
pulse. The
register write terminates the erase operation with the
rising edge of its WE
Ý
pulse.
The 28F020 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.
In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set-up) to the command
register. Figure 6, the Quick-Erase algorithm, illustrates how commands and bus operations are combined to perform electrical erasure of the 28F020.
Refer to AC Erase Characteristics and Waveforms
for specific timing parameters.
Set-up Program/Program Commands
Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into the command register performs the set-up
operation.
Once the program set-up operation is performed,
the next WE
Ý
pulse causes a transition to an active
programming operation. Addresses are internally
latched on the falling edge of the WE
Ý
pulse. Data
is internally latched on the rising edge of the WE
Ý
pulse. The rising edge of WEÝalso begins the programming operation. The programming operation
terminates with the next rising edge of WE
Ý
used to
write the program-verify command. Refer to AC Programming Characteristics and Waveforms for specific timing parameters.
9
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