Intel Corporation E28F400CV-T80 Datasheet

E

PRELIMINARY

July 1997 Order Number: 290530-005

n

Intel SmartVoltage Technology



5V or 12V Program/Erase



2.7V, 3.3V or 5V Read Operation



Increased Programming Throughput
at 12V V

PP

n

Very High-Performance Read



5V: 60/80/120 ns Max. Access Time,
30/40 ns Max. Output Enable Time



3V: 110/150/180 ns Max Access
65/90 ns Max. Output Enable Time



2.7V: 120 ns Max Access 65 ns Max.
Output Enable Time

n

Low Power Consumption



Max 60 mA Read Current at 5V



Max 30 mA Read Current at

2.7V–3.6V

n

x8/x16-Selectable Input/Output Bus



28F400 for High Performance 16- or
32-bit CPUs

n

x8-Only Input/Output Architecture



28F004B for Space-Constrained
8-bit Applications

n

Optimized Array Blocking Architecture



One 16-KB Protected Boot Block



Two 8-KB Parameter Blocks



One 96-KB Main Block



Three 128-KB Main Blocks



Top or Bottom Boot Locations

n

Absolute Hardware-Protection for Boot
Block

n

Software EEPROM Emulation with
Parameter Blocks

n

Extended Temperature Operation



–40°C to +85°C

n

Extended Cycling Capability



100,000 Block Erase Cycles
(Commercial Temperature)



10,000 Block Erase Cycles
(Extended Temperature)

n

Automated Word/Byte Program and
Block Erase



Industry-Standard Command User
Interface



Status Registers



Erase Suspend Capability

n

SRAM-Compatible Write Interface

n

Automatic Power Savings Feature



1 mA Typical ICC Active Current in
Static Operation

n

Reset/Deep Power-Down Input



0.2 µA ICCTypical



Provides Reset for Boot Operations

n

Hardware Data Protection Feature



Write Lockout during Power
Transitions

n

Industry-Standard Surface Mount
Packaging



40-Lead TSOP



44-Lead PSOP: JEDEC ROM
Compatible



48-Lead TSOP



56-Lead TSOP

n

Footprint Upgradeable from 2-Mbit and
to 8-Mbit Boot Block Flash Memories

n

ETOX™ IV Flash Technology

4-MBIT (256K X 16, 512K X 8)

SmartVoltage BOOT BLOCK FLASH

MEMORY FAMILY

28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B

28F400CE-T/B, 28F004BE-T/B

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provi ded in Intel ’s Terms and Condi tions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B, 28F400CE-T/B, 28F004BE-T/B may contain design defects or errors

known as errata which may cause the product to deviate from published specifications. Current characterized errata are
available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

or visit Intel’s Website at http:\\www.intel.com

COPYRIGHT © INTEL CORPORATION, 1997 CG-041493
*Third-party brands and names are the property of their respective owners.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

3

PRELIMINARY

CONTENTS

PAGE PAGE

1.0 PRODUCT FAMILY OVERVIEW .................... 5

1.1 New Features in the SmartVoltage

Products .....................................................5

1.2 Main Features..............................................5

1.3 Applications .................................................7

1.4 Pinouts.........................................................7

1.5 Pin Descriptions.........................................11

2.0 PRODUCT DESCRIPTION............................13

2.1 Memory Blocking Organization ..................13

2.1.1 Boot Block........................................... 13

2.1.2 Parameter Blocks................................ 13

2.1.3 Main Blocks.........................................13

3.0 PRODUCT FAMILY PRINCIPLES OF

OPERATION................................................ 15

3.1 Bus Operations..........................................15

3.2 Read Operations........................................15

3.2.1 Read Array.......................................... 15

3.2.2 Intelligent Identifiers ............................17

3.3 Write Operations........................................17

3.3.1 Command User Interface (CUI)...........17

3.3.2 Status Register ...................................20

3.3.3 Program Mode ....................................21

3.3.4 Erase Mode.........................................21

3.4 Boot Block Locking ....................................22

3.4.1 V

PP

= VIL for Complete Protection....... 22

3.4.2 WP# = V

IL

for Boot Block Locking .......22

3.4.3 RP# = V

HH

or WP# = VIH forr Boot Block

Unlocking...........................................22

3.4.4 Upgrade Note for 8-Mbit 44-PSOP

Package............................................. 22

3.5 Power Consumption...................................26

3.5.1 Active Power.......................................26

3.5.2 Automatic Power Savings (APS) .........26

3.5.3 Standby Power....................................26

3.5.4 Deep Power-Down Mode.....................26

3.6 Power-Up/Down Operation.........................26

3.6.1 RP# Connected to System Reset........26

3.6.2 V

CC

, VPP and RP# Transitions.............27

3.7 Power Supply Decoupling..........................27

3.7.1 V

PP

Trace on Printed Circuit Boards....27

4.0 ABSOLUTE MAXIMUM RATINGS................28

5.0 COMMERCIAL OPERATING CONDITIONS.29

5.1 Applying V

CC

Voltages...............................29

5.2 DC Characteristics.....................................30

5.3 AC Characteristics .....................................34

6.0 EXTENDED OPERATING CONDITIONS......44

6.1 Applying V

CC

Voltages...............................44

6.2 DC Characteristics.....................................45

6.3 AC Characteristics .....................................51

APENDIX A: Additional Information.................56

APPENDIX B: Additional Information...............57

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

4

PRELIMINARY

REVISION HISTORY

Number Description

-001 Initial release of datasheet.

-002 Status changed from Product Preview to Preliminary
28F400CV/CE/BE references and information added throughout.

2.7V CE/BE specs added throughout.

The following sections have been changed or rewritten: 1.1, 3.0, 3.2.1, 3.2.2, 3.3.1,

3.3.1.1, 3.3.2, 3.3.2.1, 3.3.3, 3.3.4, 3.6.2.
Note 2 added to Figure 3 to clarify 28F008B pinout vs. 28F008SA.
Sentence about program and erase WSM timeout deleted from Section 3.3.3, 3.3.4.
Erroneous arrows leading out of error states deleted from flowcharts in Figs. 9, 10.
Sections 5.1, 6.1 changed to “Applying V

CC

Voltages.” These sections completely

changed to clarify V

CC

ramp requirements.

I

PPD

3.3V Commercial spec changed from 10 to 5 µA.
Capacitance tables added after commercial and extended DC Characteristics tables.
Test and slew rate notes added to Figs. 12, 13, 19, 20, 21.
Test configuration drawings (Fig. 14, 22) consolidated into one, with component

values in table. (Component values also rounded off).

t

ELFL

, t

ELFH

, t

AVFL

changed from 7 to 5 ns for 3.3V BV-60 commercial and 3.3V

TBV-80 extended, 10 to 5 ns for 3.3V BV-80 and BV-120 commercial.

t

WHAX

and t

EHAX

changed from 10 to 0 ns.

t

PHWL

changed from 1000 ns to 800 ns for 3.3V BV-80, BV-120 commercial.

t

PHEL

changed from 1000 ns to 800 ns for 3.3V BV-60, BV-80, and BV-120 commercial.

-003 28F400BE row removed from Table 1
Applying V

CC

voltages (Sections 5.1 and 6.1) rewritten for clarity.

Minor cosmetic changes/edits.

-004 Corrections: Spec typographical error “t

QWL

” corrected to read “t

QVVL

.”
Intel386™ EX Microprocessor block diagram updated because latest Intel386 CPU
specs require less glue logic.
Spec t

ELFL

and t

ELFH

changed from 5 ns (max) to 0 ns (min).

New specs t

PLPH

and t

PLQX

added from Specification Update document (297595).

Specs t

EHQZ

and t

GHQZ

improved on most voltage/speed combinations.

-005 Correction: Appendix A, Ordering information fixed order numbers from TE27F400BVT80
to TE28F400BVT80 and TE27F400BVB80 to TE28F400BVB80.
Updated disclaimer.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

5

PRELIMINARY

1.0 PRODUCT FAMILY OVERVIEW

This datasheet contains the specifications for the
two branches of products in the SmartVoltage
4-Mbit boot block flash mem ory f amily : t he -BE /CE
suffix products f eature a low V

CC

operating range

of 2.7V–3.6V; the -BV/CV suffix products offer

3.0V–3.6V operation. Both BE/CE and BV/CV
products also operate at 5V for high-s peed acces s
times. Throughout this datasheet, the 28F400
refers to all x8/x16 4-Mbit products, while
28F004B refers to all x8 4-Mbit boot block
products. Also, t he term “2.7V” generally refers to
the full voltage range 2.7V–3.6V. Section 1
provides an overview of the flash mem ory family
including applications, pinouts and pin
descriptions. Sections 2 and 3 describe the
memory organization and operation for these
products. Finally, Sections 4 and 5 contain the
family’s operating specifications.

1.1 New Features in the
SmartVoltage Products

The SmartVoltage boot block flash memory family
offers identical operation with the BX/BL 12V
program products, except for the dif ferences lis ted
below. All other functions are equivalent t o current
products, including signatures, write commands,
and pinouts.

• WP# pin has replaced a DU (Don’t Use) pin.

Connect the WP# pin to control signal or to
V

CC

or GND (in this case, a logic -level signal
can be placed on DU pin). See Tables 2 and
9 to see how the WP# pin works.

• 5V program/erase operation has been added.
If switching V

PP

for write protection, swi tch to
GND (not 5V) for complete write prot ect ion. To
take advantage of 5V write-capability , allow for
connecting 5V to V

PP

and disconnecting 12V

from V

PP

line.

• Enhanced circuits optimize low V

CC

performance, allowing operation down to
V

CC

= 2.7V (using the BE product).

If you are using BX/BL 12V V

PP

boot block
products today, you should account for the
differences listed above and also allow for
connecting 5V to V

PP

and disconnecting 12V from

V

PP

line, if 5V writes are desired.

1.2 Main Features

Intel’s SmartVoltage technology is the most
flexible voltage solution in the flash industry,
providing two discrete volt age s upply pi ns: V

CC

for

read operation, and V

PP

for program and erase
operation. Discrete supply pins allow system
designers to use the optimal voltage levels for
their design. The 28F400BV/CV, 28F004BV,
28F400CE and 28F004BE provide program/eras e
capability at 5V or 12V. The 28F400BV/CV and
28F004BV allow reads with V

CC

at 3.3 ± 0.3V or
5V, while the 28F400CE and 28F004BE allow
reads with V

CC

at 2.7V–3.6V or 5V. Since many
designs read from the flash memory a large
percentage of the time, read operation using the

2.7V or 3.3V ranges can provide great power
savings. If read performance is an issue, however,
5V V

CC

provides faster read access times.

Table 1. SmartVoltage Provides Total Voltage Flexibility

Product Bus V

CC

V

PP

Name Width 2.7V–3.6V 3.3 ± 0.3V 5V ± 5%

5V ± 10%

5V ± 10% 12V ± 5%

28F004BV-T/B x8 √√√√
28F400BV-T/B x8 or x16 √√√√
28F400CV-T/B x8 or x16 √√√√
28F004BE-T/B x8 √√√√
28F400CE-T/B x8 or x16 √√√√

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

6

PRELIMINARY

For program and erase operations, 5V V

PP

operation eliminates the need for i n system voltage
converters, while 12V V

PP

operation provides faster
program and erase for situations where 12V is
available, such as manuf acturing or designs where
12V is in-system. For design simplicity, however,
just hook up V

CC

and VPP to the same 5V ± 10%

source.
The 28F400/28F004B boot block flash memory

family is a high-performanc e, 4-Mbit (4,194,304 bit)
flash memory family organized as either
256 Kwords of 16 bits each (28F400 only) or
512 Kbytes of 8 bits each (28F400 and 28F004B).

Separately erasable blocks, including a hardware­lockable boot block (16,384 by tes), two parameter
blocks (8,192 bytes each) and main blocks (one
block of 98,304 bytes and three blocks of 131,072
bytes), define the boot block flash family
architecture. See Figures 7 and 8 for memory
maps. Each block can be independently eras ed and
programmed 100,000 times at commercial
temperature or 10,000 times at extended
temperature.

The boot block is located at either the top (denot ed
by -T suffix) or the bottom (-B suff ix) of the addres s
map in order to accommodate different
microprocessor protocols for boot code location.
The hardware-lockable boot block provides
complete code security for the k ernel code required
for system initialization. Locking and unlocking of
the boot block is controlled by WP# and/or RP#
(see Section 3.4 for details).

The Command User Interface (CUI) s erves as the
interface between the microprocessor or
microcontroller and the internal operation of the
boot block flash memory products. The internal
Write State Machine (WSM) automati cally exec utes
the algorithms and timings necessary for program
and erase operations, including verifications,
thereby unburdening the microprocessor or
microcontroller of these tasks. The Status Register
(SR) indicates the status of the WSM and whether i t
successfully completed the desired program or
erase operation.

Program and Erase Automation al l ows program and
erase operations to be executed using an indust ry­standard two-write command sequence t o the CUI.
Data writes are performed in word (28F400 family)
or byte (28F400 or 28F004B families) increment s.

Each byte or word in the flash memory can be
programmed independently of other memory
locations, unlike erases, which erase all locations
within a block simultaneously.

The 4-Mbit SmartVoltage boot block flash memory
family is also designed with an Automatic Power
Savings (APS) feature which minimizes system
battery current drain, allowing for very low power
designs. To provide even greater power savings,
the boot block family includes a deep power-down
mode which minimizes power consumption by
turning most of the flash memory’s circuitry off.
This mode is controlled by the RP# pin and its
usage is discussed in Sec tion 3.5, along with other
power consumption issues.

Additionally, the RP# pin provides protection
against unwanted command writes due to invalid
system bus conditions that may occur during
system reset and power-up/down sequences. For
example, when the flash memory powers-up, it
automatically default s to the read array mode, but
during a warm system reset, where power
continues uninterrupted to the system components,
the flash memory could rem ain in a non-read mode,
such as erase. Consequently, the system Reset
signal should be tied to RP# to reset the mem ory to
normal read mode upon activation of the Reset
signal. See Section 3.6.

The 28F400 provides both byte-wide or word-wide
input/output, which is controll ed by the BYTE# pin.
Please see Table 2 and Figure 16 for a detailed
description of BYTE# operations, especially the
usage of the DQ

15/A–1

pin.

The 28F400 products are available in a
ROM/EPROM-compatible pinout and hous ed in the
44-lead PSOP (Plastic Small Outline) pack age, the
48-lead TSOP (Thin Small Outline, 1.2 mm thick)
package and the 56-lead TSOP as shown in
Figures 4, 5 and 6, respectively. The 28F004
products are available in the 40-lead TSOP
package as shown in Figure 3.

Refer to the DC Characteristics Table, Section 5.2
(commercial temperature) and Section 6.2
(extended temperature), for complete current and
voltage specifications. Refer to the AC
Characteristics Table, Section 5.3 (commercial
temperature) and Section 6.3 (extended
temperature), for read, write and erase performance
specifications.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

7

PRELIMINARY

1.3 Applications

The 4-Mbit boot block flash memory family
combines high-density, low-power, high­performance, cost-effective flash memories with
blocking and hardware protection capabilit ies. Their
flexibility and versatility reduce c ost s throughout t he
product life cycle. Flash memory is ideal for Just-In­Time production flow, reducing system inventory
and costs, and eliminating component handling
during the production phase.

When your product is in the end-user’s hands, and
updates or feature enhancements become
necessary, flash m emory reduces t he update cost s
by allowing user-performed code changes instead
of costly product returns or technician calls.

The 4-Mbit boot block flas h memory f ami ly prov ides
full-function, block ed flash memories suitable for a
wide range of applications. These applications
include extended PC BIOS and ROM-able
applications storage, di gital cellular phone program
and data storage, telecommunication boot/firmware,
printer firmware/font storage and various other
embedded applications where program and data
storage are required.

Reprogrammable systems, such as personal
computers, are ideal applications for the 4-Mbit
flash memory products. Increasing software
sophistication greatens the probability that a code
update will be required after the PC is shipped. For
example, the emerging of “plug and play” standard
in desktop and portable PCs enables auto­configuration of ISA and PCI add-in cards.
However, since the “plug and play” specification
continues to evolve, a flash BIOS provides a cost­effective capability to update existing PCs. In
addition, the parameter blocks are ideal for storing
the required auto-configuration parameters,
allowing you to integrate the BIOS PROM and
parameter storage EEPROM into a single
component, reducing parts costs while increasing
functionality.

The 4-Mbit flash memory products are also
excellent design solutions for di gital cellular phone
and telecommunication switching applications
requiring very low power consumption, high­performance, high-density storage capability,
modular software designs, and a small form factor
package. The 4-Mbit’s bloc king scheme allows for
easy segmentation of the embedded code with
16 Kbytes of hardware-protected boot code, four
main blocks of program code and two parameter
blocks of 8 Kbytes each for frequently updated data
storage and diagnostic messages (e.g., phone
numbers, authorization codes).

Intel’s boot block architecture provides a flexible
voltage solution for the different design needs of
various applications. The asymmetrically-blocked
memory map allows the integration of several
memory components into a singl e flash dev ice. The
boot block provides a secure boot PROM; the
parameter blocks can emulate EEPROM
functionality for parameter store with proper
software techniques; and the main blocks provide
code and data storage with access times fast
enough to execute code in plac e, decreasing RAM
requirements.

1.4 Pinouts

Intel’s SmartVoltage Boot Block architecture
provides upgrade paths in every pac kage pinout to
the 8-Mbit density. The 28F004B 40-lead TSOP
pinout for space-constrained designs is shown in
Figure 3. The 28F400 44-lead PSOP pinout f ollows
the industry-standard ROM/EPROM pinout, as
shown in Figure 4. For designs that require x16
operation but have space concerns, refer to the
48-lead pinout in Figure 5. Furtherm ore, the 28F400
56-lead TSOP pinout shown in Figure 6 provides
density upgrades to future higher dens it y boot bloc k
memories.

Pinouts for the corresponding 2-Mbit and 8-Mbit
components are also provided for convenient
reference. 4-Mbit pinouts are given on the chip
illustration in the center, with 2-Mbit and 8-Mbit
pinouts going outward from the center.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

8

PRELIMINARY

A[18:1]

CS#

RD#

WR#

D[0:15]

A[0:17]

CE#

OE#

WE#

DQ[0:15]

28F400BV-60

RP#

i386™ EX CPU

(25 MHz)

RESET

RESET

0530_01

NOTE:

A data bus buffer may be needed for processor speeds above 25 MHz.

Figure 1. 28F400 Interface to Intel386™ EX Microprocessor

UCS#

80C188EB

-A15A

8

ALE

P1.X

WR#

RD#

RESIN#

System Reset

WE#
OE#

V

PP

ADDRESS

LATCHES

LE

ADDRESS

LATCHES

LE

CE#

A

0-A18

RP#

28F004-T

-AD

7AD0

A[16:18]

DQ

0

-DQ

7

WP#

V

CC

10K

Ω

P1.X

V

CC

0530_02

Figure 2. 28F004B Interface to Intel80C188EB 8-Bit Embedded Microprocessor

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

9

PRELIMINARY

28F004B

Boot Block

40-Lead TSOP

10 mm x 20 mm

TOP VIEW

32
31
30
29
28
27
26
25
24
23
22
21

33

34

35

36

37

38

39

40

20

19

17
18

1
2
3
4
5
6
7
8

9
10
11
12
13
14

16

15

A

1

A

2

A

3

RP#

WE#

V

PP

A

16

A

15

A

7

A

6

A

5

A

4

A

14

A

13

A

8

A

9

A

11

A

12

WP#

DQ

7

CE#

OE#

GND

A

0

DQ

6

DQ

5

DQ

4

DQ

2

DQ

1

DQ

0

V

CC

DQ

3

A

17

GND

NC

A

10

NC

NC

NC

28F002B 28F002B

28F008B 28F008B

DQ

7

CE#

OE#

GND

A

0

DQ

6

DQ

5

DQ

4

DQ

2

DQ

1

DQ

0

V

CC

V

CC

DQ

3

A

17

GND

NC

A

10

NC

A

1

A

2

A

3

RP#

WE#

V

PP

A

16

A

15

A

7

A

6

A

5

A

4

A

14

A

13

A

8

A

9

A

11

A

12

WP#

A

1

A

2

A

3

RP#

WE#

V

PP

A

16

A

15

A

7

A

6

A

5

A

4

A

14

A

13

A

8

A

9

A

11

A

12

WP#

A

18

A

18

A

19

DQ

7

CE#

OE#

GND

A

0

DQ

6

DQ

5

DQ

4

DQ

2

DQ

1

DQ

0

V

CC

DQ

3

A

17

GND

NC

A

10

NC

NC

V

CC

V

CC

0530_03

Figure 3. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained Applications

PA28F400

Boot Block

44-Lead PSOP

0.525" x 1.110"

TOP VIEW

32
31
30
29
28
27
26
25
24
23

33

34

35

36

37

38

39

40

41

42

43

44

22

21

20

19

17
18

1
2
3
4
5
6
7
8

9
10
11
12
13
14

16

15

RP#
WE#

A

A

A

A
A

A

A

A
A
BYTE#
GND
DQ /A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V

8
9
10
11
12
13
14
15
16

15
7
14
6
13
5
12
4

CC

-1

28F800 28F200

V

PP

WP#

NC
A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

CE#
GND
OE#

DQ

0

DQ

8

DQ

1

DQ

9

DQ

2

DQ

10

DQ

3

DQ

11

V

PP

A

17

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

CE#
GND
OE#

DQ

0

DQ

8

DQ

1

DQ

9

DQ

2

DQ

10

DQ

3

DQ

11

A

18

V

PP

WP#

A

17

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

CE#
GND
OE#

DQ

0

DQ

8

DQ

1

DQ

9

DQ

2

DQ

10

DQ

3

DQ

11

RP#
WE#

A

A

A

A
A

A

A

A
A
BYTE#
GND
DQ /A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V

8
9
10
11
12
13
14
15
16

15
7
14
6
13
5
12
4

CC

-1

RP#
WE#

A

A

A

A
A

A

A

A
A
BYTE#
GND
DQ /A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V

8
9
10
11
12
13
14
15
16

15
7
14
6
13
5
12
4

CC

-1

28F80028F200

0530_04

NOTE: Pin 2 is WP# on 2- and 4-Mbit devices but A18 on the 8-Mbit because no other pins were available for the high order
address. Thus, the 8-Mbit in the 44-lead PSOP cannot unlock the boot block without RP# = VHH (12V). To allow upgrades to
the 8 Mbit from 2/2 Mbit in this package, design pin 2 to control WP# at the 2/4 Mbit level and A18 at the 8-Mbit density. See
Section 3.4 for details.

Figure 4. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM Standards

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

10

PRELIMINARY

28F400

Boot Block

48-Lead TSOP

12 mm x 20 mm

TOP VIEW

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

17
18

1
2
3
4
5
6
7
8

9
10
11
12
13
14

16

15

25

26

27

28

29

30

31

32

16

15 -1
7
14
6
13

5
12

4

A
BYTE#
GND
DQ /A
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ

V
DQ

DQ
DQ
DQ
DQ
DQ
DQ
OE#
GND
CE#
A

CC

11
3
10

2
9
1
8

0

0

16

15 -1
7
14
6
13

5
12

4

A
BYTE#
GND
DQ /A
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ

V
DQ

DQ
DQ
DQ
DQ
DQ
DQ
OE#
GND
CE#
A

CC

11
3
10

2
9
1
8

0

0

28F80028F200

16

15 -1

7
14
6
13

5
12

4

A
BYTE#
GND
DQ /A
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
OE#
GND
CE#
A

V

CC

11
3
10

2
9
1
8
0

0

28F20028F800

A
A
A

A

A
A
A
A

NC

NC

WE#

RP#

WP#

NC
A

A
A
A
A
A
A
A

17

7
6
5
4
3
2
1

15
14
13
12
11
10
9
8

A
A
A

A

A
A
A
A

NC

NC

WE#

RP#

WP#

NC

NC
A

A
A
A
A
A
A

7
6
5
4
3
2
1

15
14
13
12
11
10
9
8

A
A
A

A

A
A
A
A

NC

NC

WE#

RP#

WP#

NC

NC
A
A
A
A
A
A
A
A

17
7
6
5
4
3
2
1

15
14
13
12
11
10
9
8

V

PPVPPVPP

A

18

NC

0530_05

Figure 5. The 48-Lead TSOP Offers the Smallest Form Factor for x16 Operation

28F400

56-Lead TSOP

Boot Block

14 mm x 20 mm

TOP VIEW

28

27

26

25

24

23

22

21

20

19

17
18

1
2
3
4
5
6
7
8

9
10
11
12
13
14

16

15

A

1

A

2

A

3

RP#

WE#

A

15

A

7

A

6

A

5

A

4

A

14

A

13

A

8

A

9

A

11

A

12

NC

V

PP

NC

NC

NC

NC

NC

NC

A

10

WP#

NC

NC

A

1

A

2

A

3

RP#

WE#

A

15

A

7

A

6

A

5

A

4

A

14

A

13

A

8

A

9

A

11

A

12

NC

V

PP

NC

NC

NC

NC

NC

NC

A

10

WP#

NC

DQ

7

CE#

OE#

GND

A

0

DQ

6

DQ

5

DQ

4

DQ

2

DQ

1

DQ

0

V

CC

V

CC

DQ

3

GND

NC

NC

DQ

9

DQ

10

DQ

11

DQ

8

BYTE#

DQ15/A

-1

DQ

14

DQ

13

DQ

12

A

16

NC

28F200 28F200

A

17

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

32
31

30
29

33

34

35

36

37

38

39

40

DQ

7

CE#

OE#

GND
A

0

DQ

6

DQ

5

DQ

4

DQ

2

DQ

1

DQ

0

V

CC

V

CC

DQ

3

GND

NC

NC

DQ

9

DQ

10

DQ

11

DQ

8

BYTE#

DQ15/A

-1

DQ

14

DQ

13

DQ

12

A

16

NC

0530_06

Figure 6. The 56-Lead TSOP Offers Compatibility between 2 and 4 Mbits

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

11

PRELIMINARY

1.5 Pin Descriptions

Table 2. 28F400/004 Pin Descriptions

Symbol Type Name and Function

A0–A

18

INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle. The 28F400 only has A

– A

pins, while the 28F004B

has A

0

– A18.

A

9

INPUT ADDRESS INPUT: When A9 is at VHH the signature mode is accessed. During

this mode, A

0

decodes between the manufacturer and device IDs. When BYTE#

is at a logic low, only the lower byte of the signatures are read. DQ

15/A–1

is a

don’t care in the signature mode when BYTE# is low.

DQ0–DQ

7

INPUT/

OUTPUT

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Inputs commands to the Command User Interface
when CE# and WE# are active. Data is internally latched during the write cycle.
Outputs array, Intelligent Identifier and Status Register data. The data pins float to
tri-state when the chip is de-selected or the outputs are disabled.

DQ8–DQ

15

INPUT/

OUTPUT

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Data is internally latched during the write cycle.
Outputs array data. The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide
mode DQ

15/A–1

becomes the lowest order address for data output on DQ0–DQ7.

The 28F004B does not include these DQ

8

–DQ

15

pins.

CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

sense amplifiers. CE# is active low. CE# high de-selects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow
through the CE# and RP# input stages.

OE# INPUT OUTPUT ENABLE: Enables the device’s outputs through the data buffers during

a read cycle. OE# is active low.

WE# INPUT WRITE ENABLE: Controls writes to the Command Register and array blocks.

WE# is active low. Addresses and data are latched on the rising edge of the WE#
pulse.

RP# INPUT RESET/DEEP POWER-DOWN: Uses three voltage levels (VIL, VIH, and VHH) to

control two different functions: reset/deep power-down mode and boot block
unlocking. It is backwards-compatible with the BX/BL/BV products.

When RP# is at logic low, the device is in reset/deep power-down mode,
which puts the outputs at High-Z, resets the Write State Machine, and draws
minimum current.

When RP# is at logic high, the device is in standard operation. When RP#
transitions from logic-low to logic-high, the device defaults to the read array mode.

When RP# is at V

HH

, the boot block is unlocked and can be programmed or

erased. This overrides any control from the WP# input.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

12

PRELIMINARY

Table 2. 28F400/004 Pin Descriptions (Continued)

Symbol Type Name and Function

WP# INPUT WRITE PROTECT: Provides a method for unlocking the boot block in a system

without a 12V supply.
When WP# is at logic low, the boot block is locked, preventing program and

erase operations to the boot block. If a program or erase operation is attempted
on the boot block when WP# is low, the corresponding status bit (bit 4 for
program, bit 5 for erase) will be set in the Status Register to indicate the operation
failed.

When WP# is at logic high, the boot block is unlocked and can be
programmed or erased.

NOTE: This feature is overridden and the boot block unlocked when RP# is at
V

HH

. See Section 3.4 for details on write protection.

BYTE# INPUT BYTE# ENABLE: Not available on 28F004B. Controls whether the device

operates in the byte-wide mode (x8) or the word-wide mode (x16). BYTE# pin
must be controlled at CMOS levels to meet the CMOS current specification in the
standby mode.

When BYTE# is at logic low, the byte-wide mode is enabled, where data is
read and programmed on DQ

0

–DQ7 and DQ15/A–1 becomes the lowest order

address that decodes between the upper and lower byte. DQ

8

–DQ14 are tri-stated

during the byte-wide mode.
When BYTE# is at logic high, the word-wide mode is enabled, where data is

read and programmed on DQ

0

–DQ15.

V

CC

DEVICE POWER SUPPLY: 5.0V ± 10%, 3.3 ± 0.3V, 2.7V–3.6V (BE/CE only)

V

PP

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block, a voltage either of 5V ± 10% or 12V ± 5% must
be applied to this pin. When V

PP

< V

PPL

K

all blocks are locked and protected

against Program and Erase commands.
GND GROUND: For all internal circuitry.
NC NO CONNECT: Pin may be driven or left floating.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

13

PRELIMINARY

2.0 PRODUCT DESCRIPTION

2.1 Memory Blocking Organization

This product family features an asymmetrically­blocked architecture providing system memory
integration. Each erase block can be erased
independently of the others up to 100,000 tim es for
commercial temperature or up to 10,000 tim es for
extended temperature. The block sizes have been
chosen to optimize their functionality for common
applications of nonvolat i l e storage. The combination
of block sizes in t he boot block architecture allow
the integration of several memories into a single
chip. For the address locations of t he blocks, see
the memory maps in Figures 4 and 5.

2.1.1 ONE 16-KB BOOT BLOCK

The boot block is intended to repl ace a dedicated
boot PROM in a microprocess or or microcontroller­based system. The 16-Kbyte (16,384 bytes) boot
block is located at either the top (denoted by -T
suffix) or the bottom (-B suffix) of the address m ap
to accommodate different microproces sor protocols
for boot code location. This boot block features
hardware controllable write-protection to protec t the
crucial microprocessor boot code from accidental
modification. The protection of the boot block is
controlled using a combinati on of the V

PP

, RP#, and

WP# pins, as is detailed in Section 3.4.

2.1.2 TWO 8-KB PARAMETER BLOCKS

The boot block architecture includes parameter
blocks to facilitate storage of frequently updated
small parameters that would normally require an
EEPROM. By using software techniques, the by te­rewrite functionality of EEPROMs can be emulated.

These techniques are detailed in Intel ’s application
note,

AP-604 Using Intel’s Boot Block Flash

Memory Parameter Blocks to Replace EEPROM

.
Each boot block component c ontains two parameter
blocks of 8 Kbytes (8,192 bytes) each. The
parameter blocks are not write-protectable.

2.1.3 ONE 96-KB + THREE 128-KB

MAIN BLOCKS

After the allocation of address space to the boot
and parameter blocks, the remainder is divided into
main blocks for data or code storage. Each 4-Mbit
device contains one 96-Kbyte (98,304 byte) block
and three 128-Kbyte (131,072 byte) blocks. See the
memory maps for each device for more information.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

14

PRELIMINARY

3FFFFH
3E000H

3DFFFH

3D000H

3CFFFH

3C000H

3BFFFH

30000H

20000H

1FFFFH

10000H

0FFFFH

00000H

2FFFFH

3FFFFH

30000H

2FFFFH

20000H

1FFFFH

10000H

0FFFFH

04000H

03FFFH

03000H

02FFFH

02000H

01FFFH

00000H

28F400-T

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

28F400-B

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

0530_07

NOTE: Address = A[17:0]. In x8 operation, the least significant system address should be connected to A-1. Memory maps are
shown for x16 operation.

Figure 7. Word-Wide x16-Mode Memory Maps

7FFFFH

7C000H

7BFFFH

7A000H

79FFFH

78000H

77FFFH

60000H

5FFFFH

40000H

3FFFFH

20000H

1FFFFH

00000H

28F004-T

128-Kbyte MAIN BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

7FFFFH

60000H

5FFFFH

40000H

3FFFFH

20000H

1FFFFH

08000H

07FFFH

06000H

05FFFH

04000H

03FFFH

00000H

28F004-B

128-Kbyte MAIN BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

0530_08

NOTE: Address = A[18:0]. These memory maps apply to the 28F004B or the 28F400 in x8 mode.

Figure 8. Byte-Wide x8-Mode Memory Maps

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

15

PRELIMINARY

3.0 PRODUCT FAMILY PRINCIPLES
OF OPERATION

Flash memory combines E PROM functionality with
in-circuit electrical wri te and erase. The boot block
flash family utilizes a Command User Interface
(CUI) and automated algorithms to simplify write
and erase operations. The CUI allows for 100%
TTL-level control inputs, fixed power supplies
during erasure and programming, and maximum
EPROM compatibility.

When V

PP

< V

PPLK

, the device will only successfully
execute the following commands: Read Array,
Read Status Register, Clear Status Register and
intelligent identifier mode. The device provides
standard EPROM read, standby and output disable
operations. Manufacturer identification and device
identification data c an be acc ess ed through t he CUI
or through the standard EPROM A

9

high voltage

access (V

ID

) for PROM programming equipment.

The same EPROM read, standby and output
disable functions are avai lable when 5V or 12V is
applied to the V

PP

pin. In addition, 5V or 12V on

V

PP

allows write and erase of the device. All
functions associ ated wit h alt ering mem ory c ontent s:
Program and Erase, Intelligent Identifier Read, and
Read Status are accessed via the CUI.

The internal Write State Machi ne (WSM) completely
automates program and erase, beginning operation
signaled by the CUI and reporting status through
the Status Register. The CUI handles the WE#
interface to the data and address latches, as well
as system status requests during WSM operation.

3.1 Bus Operations

Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles. These bus operations are summarized in
Tables 3 and 4.

3.2 Read Operations

3.2.1 READ ARRAY

When RP# transitions from V

IL

(reset) to VIH, the
device will be in the read array mode and will
respond to the read control inputs (CE#, address
inputs, and OE#) without any commands being
written to the CUI.

When the device is in the read array mode, five
control signals must be cont rolled to obtain data at
the outputs.

• RP# must be logic high (V

IH

)

• WE# must be logic high (V

IH

)

• BYTE# must be logic high or logic low

• CE# must be logic low (V

IL

)

• OE must be logic low (V

IL

)

In addition, the address of the desired l ocat ion mus t
be applied to the address pins. Refer to Figures 15
and 16 for the exact sequence and timing of these
signals.

If the device is not i n read array mode, as would be
the case after a program or erase operation, the
Read Mode command (FFH) must be written to t he
CUI before reads can take place.

During system design, consideration should be
taken to ensure address and control inputs meet
required input slew rates of <10 ns as defined in
Figures 12 and 13.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

16

PRELIMINARY

Table 3. Bus Operations for Word-Wide Mode (BYTE# = VIH)

Mode Notes RP# CE# OE# WE# A

9

A

0

V

PP

DQ

0–15

Read 1,2,3 V

IH

V

IL

V

IL

V

IH

XXX D

OUT

Output Disable V

IH

V

IL

V

IH

V

IH

X X X High Z

Standby V

IH

V

IH

XXXXXHigh Z

Deep Power-Down 9 V

IL

XXXXXXHigh Z

Intelligent Identifier
(Mfr)

4VIHV

IL

V

IL

V

IH

V

ID

V

IL

X 0089 H

Intelligent Identifier
(Device)

4,5 V

IH

V

IL

V

IL

V

IH

V

ID

V

IH

X See

Table 5

Write 6,7,8 V

IH

V

IL

V

IH

V

IL

XXX D

IN

Table 4. Bus Operations for Byte-Wide Mode (BYTE# = VIL)

Mode Notes RP# CE# OE# WE# A

9

A0A

–1

V

PP

DQ

0–7

DQ

8–14

Read 1,2,3 V

IH

V

IL

V

IL

V

IH

XXXXD

OUT

High Z

Output
Disable

V

IH

V

IL

V

IH

V

IH

XXXXHigh Z High Z

Standby V

IH

V

IH

XXXXXXHigh Z High Z

Deep Power­Down

9VILXXXXXXXHigh Z High Z

Intelligent
Identifier (Mfr)

4VIHV

IL

V

IL

V

IH

V

ID

V

IL

X X 89H High Z

Intelligent
Identifier
(Device)

4,5 V

IH

V

IL

V

IL

V

IH

V

ID

V

IH

X X See

Table

5

High Z

Write 6,7,8 V

IH

V

IL

V

IH

V

IL

XXXXDINHigh Z

NOTES:

1. Refer to DC Characteristics.

2. X can be V

IL

, VIH for control pins and addresses, V

PPLK

or V

PPH

for VPP.

3. See DC Characteristics for V

PPLK

, V

PPH1

, V

PPH2

, VHH, VID voltages.

4. Manufacturer and device codes may also be accessed via a CUI write sequence, A

1–A17

= X, A1–A18 = X.

5. See Table 5 for device IDs.

6. Refer to Table 7 for valid D

IN

during a write operation.

7. Command writes for block erase or word/byte program are only executed when V

PP

= V

PPH1

or V

PPH2

.

8. To write or erase the boot block, hold RP# at V

HH

or WP# at VIH. See Section 3.4.

9. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.

E 4-MBIT SmartVoltage BOOT BLOCK FAMILY

17

PRELIMINARY

3.2.2 INTELLIGENT IDENTIFIERS

To read the manufacturer and device codes, the
device must be in intelligent identifier read mode,
which can be reached using two methods: by
writing the intelligent identifier command (90H) or
by taking the A

9

pin to VID. Once in intelligent

identifier read mode, A

0

= 0 outputs the manu-

facturer’s identifi cation code and A

0

= 1 outputs the
device code. In byte-wi de m ode, onl y the lower byt e
of the above signatures is read (DQ

15/A–1

is a

“don’t care” in this mode). S ee Table 5 for product
signatures. To return to read array mode, write a
Read Array command (FFH).

Table 5. Intelligent Identifier Table

Product Mfr. ID Device ID

-T

(Top Boot)-B(Bottom Boot)

28F400 0089 H 4470 H 4471 H
28F004 89 H 78 H 79 H

3.3 Write Operations

3.3.1 COMMAND USER INTERFACE (CUI)

The Command User Interface (CUI) is t he interface
between the microprocessor and the internal chip
controller. Commands are writ ten to the CUI using
standard microprocessor write timings. The
available commands are Read Array, Read
Intelligent Identifier, Read Status Register, Clear
Status Register, Erase and Program (summarized
in Tables 6 and 7). The three read modes are read
array, intelligent identi fier read, and status register
read. For Program or Erase commands, the CUI
informs the Write State Machine (WS M) that a write
or erase has been requested. During the ex ecution
of a Program command, the WSM will control the
programming sequences and the CUI will only
respond to status reads. Duri ng an erase cycle, the
CUI will respond to status reads and erase
suspend. After the WSM has completed its task , it
will set the WSM Status bit to a “1” (ready), which
indicates that the CUI can respond to its full
command set. Note that after the WSM has
returned control to the CUI, the CUI will s tay in the
current command state until it receives another
command.

3.3.1.1 Command Function Description

Device operations are selected by writing specific
commands into the CUI. Tabl es 6 and 7 define the
available commands.

4-MBIT SmartVoltage BOOT BLOCK FAMILY E

18

PRELIMINARY

Table 6. Command Codes and Descriptions

Code Device Mode Decription

00 Invalid/

Reserved

Unassigned commands that should not be used. Intel reserves the right to redefine
these codes for future functions.

FF Read Array Places the device in read array mode, so that array data will be output on the data

pins.

40 Program

Set-Up

Sets the CUI into a state such that the next write will latch the Address and Data
registers on the rising edge and begin the program algorithm. The device then
defaults to the read status mode, where the device outputs Status Register data
when OE# is enabled. To read the array, issue a Read Array command.

To cancel a program operation after issuing a Program Set-Up command, write all

1’s (FFH for x8, FFFFH for x16)

to the CUI. This will return to read status register
mode after a standard program time without modifying array contents. If a program
operation has already been initiated to the WSM this command can not cancel that
operation in progress.

10 Alternate

Prog Set-Up

(See 40H/Program Set-Up)

20 Erase

Set-Up

Prepares the CUI for the Erase Confirm command. If the next command is not an
Erase Confirm command, then the CUI will set both the Program Status (SR.4) and
Erase Status (SR.5) bits of the Status Register to a “1,” place the device into the
read Status Register state, and wait for another command without modifying array
contents. This can be used to cancel an erase operation after the Erase Setup
command has been issued. If an operation has already been initiated to the WSM
this can not cancel that operation in progress.

D0 Erase

Resume/

Erase

Confirm

If the previous command was an Erase Set-Up command, then the CUI will latch
address and data, and begin erasing the block indicated on the address pins.
During erase, the device will respond only to the Read Status Register and Erase
Suspend commands and will output Status Register data when OE# is toggled low.
Status Register data is updated by toggling either OE# or CE# low.

B0 Erase

Suspend

Valid only while an erase operation is in progress and will be ignored in any other
circumstance. Issuing this command will begin to suspend erase operation. The
Status Register will indicate when the device reaches erase suspend mode. In this
mode, the CUI will respond only to the Read Array, Read Status Register, and
Erase Resume commands and the WSM will also set the WSM Status bit to a “1”
(ready). The WSM will continue to idle in the SUSPEND state, regardless of the
state of all input control pins except RP#, which will immediately shut down the
WSM and the remainder of the chip, if it is made active. During a suspend
operation, the data and address latches will remain closed, but the address pads
are able to drive the address into the read path. See Section 3.3.4.1.

70 Read Status

Register

Puts the device into the read Status Register mode, so that reading the device
outputs Status Register data, regardless of the address presented to the device.
The device automatically enters this mode after program or erase has completed.
This is one of the two commands that is executable while the WSM is operating.
See Section 3.3.2.