Intel Corporation E28F200CV-T80, E28F200CV-B80 Datasheet

E

December 1997

REFERENCE ONLY

2-MBIT SmartVoltage BOOT BLOCK

FLASH MEMORY FAMILY

28F200BV-T/B, 28F200CV-T/B, 28F002BV-T/B

n

Intel SmartVoltage Technology

 5 V or 12 V Program/Erase
 3.3 V or 5 V Read Operation

n

Very High-Performance Read

 5 V: 60 ns Access Time
 3 V: 110 ns Access Time

n

Low Power Consumption

 Max 60 mA Read Current at 5 V
 Max 30 mA Read Current at

3.3 V–3.6 V

n

x8/x16-Selectable Input/Output Bus

 28F200 for High Performance 16- or

32-bit CPUs

n

x8-Only Input/Output Architecture

 28F002B for Space-Constrained

8-bit Applications

n

Optimized Array Blocking Architecture

 One 16-KB Protected Boot Block
 Two 8-KB Parameter Blocks
 96-KB and 128-KB Main Blocks
 Top or Bottom Boot Locations

n

Extended Temperature Operation

 –40 °C to +85 °C

SEE NEW DESIGN RECOMMENDATIONS

n

Extended Block Erase Cycling

 100,000 Cycles at Commercial Temp
 10,000 Cycles at Extended Temp

n

Automated Word/Byte Program and
Block Erase

 Command User Interface
 Status Registers
 Erase Suspend Capability

n

SRAM-Compatible Write Interface

n

Automatic Power Savings Feature

n

Reset/Deep Power-Down Input

 0.2 µA I
 Provides Reset for Boot Operations

n

Hardware Data Protection Feature

 Absolute Hardware-Protection for

Boot Block

 Write Lockout during Power

Transitions

n

Industry-Standard Surface Mount
Packaging

 40-, 48-, 56-Lead TSOP
 44-Lead PSOP

n

Footprint Upgradeable to 4-Mbit and
8-Mbit Boot Block Flash Memories

n

ETOX™ IV Flash Technology

Typical

CC

New Design Recommendations:

For new 2.7 V–3.6 V VCC designs with this devi ce, Intel recommends using the Smart 3 Adv anced Boot
Block. Reference
order number 290580.

For new 5 V V

Smart 5 Flash Memory Family 2, 4, 8 Mbit

These documents are also available at Intel’s website, http://www.intel.com/design/flcomp.

Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family

designs with this devi ce, Int el rec ommends usi ng the 2-Mbi t S mart 5 Boot Bloc k. Ref erence

CC

datasheet, order number 290599.

Order Number: 290531-005

datasheet,

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F200BV-T/B, 28F200CV-T/B, 28F002BV-T/B may contain design defects or errors known as errata. Current

characterized errata are available on request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation
P.O. Box 5937
Denver, CO 8021-9808

or call 1-800-548-4725

or visit Intel’s website at http://www.intel.com

COPYRIGHT © INTEL CORPORATION, 1997 CG-041493

*Third-party brands and names are the property of their respective owners..

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

CONTENTS

PAGE PAGE

1.0 PRODUCT FAMILY OVERVIEW.....................5

1.1 New Features in the SmartVoltage Products5

1.2 Main Features..............................................5

1.3 Applications..................................................6

1.4 Pinouts.........................................................7

1.5 Pin Descriptions.........................................11

2.0 PRODUCT DESCRIPTION............................13

2.1 Memory Blocking Organization...................13

2.1.1 One 16-KB Boot Block.........................13

2.1.2 Two 8-KB Parameter Blocks................13

2.1.3 One 96-KB + One 128-KB Main Block.13

3.0 PRODUCT FAMILY PRINCIPLES OF

OPERATION ................................................15

3.1 Bus Operations ..........................................15

3.2 Read Operations........................................15

3.2.1 Read Array..........................................15

3.2.2 Intelligent Identifiers ............................17

3.3 Write Operations........................................17

3.3.1 Command User Interface (CUI)...........17

3.3.2 Status Register....................................20

3.3.3 Program Mode.....................................21

3.3.4 Erase Mode.........................................21

3.4 Boot Block Locking ....................................22

3.4.1 V

3.4.2 WP# = V

3.4.3 RP# = V

3.4.4 Upgrade Note for 8-Mbit 44-PSOP

3.5 Power Consumption...................................26

3.5.1 Active Power .......................................26

3.5.2 Automatic Power Savings (APS) .........26

3.5.3 Standby Power....................................26

3.5.4 Deep Power-Down Mode.....................26

= VIL for Complete Protection .......22

PP

for Boot Block Locking .......22

IL

or WP# = VIH for Boot Block

HH

Unlocking ...........................................22

Package.............................................22

3.6 Power-Up/Down Operation.........................26

3.6.1 RP# Connected To System Reset.......26

3.6.2 V

3.7 Power Supply Decoupling ..........................27

3.7.1 VPP Trace On Printed Circuit Boards..27

4.0 ELECTRICAL SPECIFICATIONS..................28

4.1 Absolute Maximum Ratings........................28

4.2 Commercial Operating Conditions..............28

4.2.1 Applying V

4.3 Capacitance...............................................29

4.4 DC Characteristics—Commercial...............30

4.5 AC Characteristics—Commercial...............34

4.6 AC Characteristics—WE#-Controlled Write

4.7 AC Characteristics—CE#-Controlled Write

4.8 Erase and Program Timings—Commercial.43

4.9 Extended Operating Conditions..................43

4.9.1 Applying V

4.10 Capacitance.............................................44

4.11 DC Characteristics—Extended

4.12 AC Characteristics—Read Only

4.13 AC Characteristics—WE#-Controlled Write

4.14 AC Characteristics—CE#-Controlled Write

4.15 Erase and Program Timings—Extended

5.0 ORDERING INFORMATION..........................54

6.0 ADDITIONAL INFORMATION.......................55

Related Intel Information..................................55

, VPP AND RP# Transitions............27

CC

Voltages.........................29

CC

Operations—Commercial..........................37

Operations—Commercial..........................40

Voltages.........................44

CC

Temperature Operations............................45

Operations—Extended Temperature.........49

Operations— Extended Temperature........50

Operations— Extended Temperature........52

Temperature..............................................53

SEE NEW DESIGN RECOMMENDATIONS

3

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

REVISION HISTORY

Number Description

-001 Initial release of datasheet.

-002 Status changed from Product Preview to Preliminary

-003 Applying VCC voltages (Sections 5.1 and 6.1) rewritten for clarity.

-004 Corrections: “This pin not available on 44-PSOP” inaccurate statement removed from pin

-005 Corrections: Figure 4, corrected pin designation 3 to “NC” from A17 on PA28F200.

28F200CV/CE/BE references and information added throughout.

2.7 V CE/BE specs added throughout.

The following sections have been changed or rewritten: 1.1, 3.0, 3.2.1, 3.2.2, 3.3.1,

3.3.1.1, 3.3.2, 3.3.2.1, 3.3.3, 3.3.4, 3.6.2.
Note 2 added to Figure 3 to clarify 28F008B pinout vs. 28F008SA.
Sentence about program and erase WSM timeout deleted from Section 3.3.3, 3.3.4.
Erroneous arrows leading out of error states deleted from flowcharts in Figs. 9, 10.
Sections 5.1, 6.1 changed to “Applying V

changed to clarify V

I

3.3 V Commercial spec changed from 10 to 5 µA.

PPD

ramp requirements.

CC

Voltages.” These sections completely

CC

Capacitance tables added after commercial and extended DC Characteristics tables.
Test and slew rate notes added to Figs. 12, 13, 19, 20, 21.
Test configuration drawings (Fig. 14, 22) consolidated into one, with component

values in table. (Component values also rounded off).

t

, t

, t

ELFL

ELFH

changed from 7 to 5 ns for 3.3 V BV-60 commercial and 3.3 V

AVFL

TBV-80 extended, 10 to 5 ns for 3.3 V BV-80 and BV-120 commercial.

t

and t

WHAX

t

changed from 1000 ns to 800 ns for 3.3 V BV-80, BV-120 commercial.

PHWL

t

changed from 1000 ns to 800 ns for 3.3 V BV-60, BV-80, and BV-120 commercial.

PHEL

changed from 10 to 0 ns.

EHAX

Minor cosmetic changes/edits.

description for WP# pin; Spec “t

” corrected to “t

QWL

” intelligent identifier values

QVVL;

corrected; Intel386™ EX block diagram updated because new 386 specs require less
glue logic.

Max program times for parameter and 96-KB main block added.
Specs t
Specs t
New specs t

Corrected typographical errors in

Added
Updated

ELFL
EHQZ

and t

and t

PLPH

changed from 5 ns (max) to 0 ns (min).

ELFH

improved.

HQZ

and t

added from Specification Update document (297612).

PLQZ

Ordering Information

New Design Recommendations

section to cover page.

Erase Suspend/Resume Flowchart

.

4

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

1.0 PRODUCT FAMILY OVERVIEW

This datasheet contains the specifications for the
two branches of products in the SmartVoltage
2-Mbit boot block flash memory family. These

-BV/CV suffi x produc ts off er 3.0 V–3. 6 V operation

and also operate at 5 V for high-speed access
times. Throughout this datasheet, the 28F200
refers to all x8/x16 2-Mbit products, while
28F002B refers to all x8 2-Mbit boot block
products. Section 1. 0 provides an overview of the
flash memory family including applications , pi nouts
and pin descriptions. Sections 2.0 and 3.0
describe the memory organization and operation
for these products. Section 4.0 contains the
family’s operating speci fications. Finally, Secti ons

5.0 and 6.0 provide ordering and document
reference information.

1.1 New Features in the SmartVoltage Products

The SmartVoltage boot block flash memory family
offers identical operation with the BX/BL 12 V
program products, except for the dif ferences lis ted
below. All other functi ons are equivalent t o current
products, including signatures, write commands,
and pinouts.

• WP# pin has replaced a DU (Don’t Use) pin.

Connect the WP# pin to control signal or to
V

or GND (in this case, a logic -level signal

CC

can be placed on DU pin). Refer to Tables 2
and 9 to see how the WP# pin works.

• 5 V program/erase operation has been added.

If switching V
GND (not 5 V) for complete write protection.
To take advantage of 5 V write-capability,
allow for connecting 5 V to V
disconnecting 12 V from V

for write protection, s witch to

PP

PP

PP

line.

and

• Enhanced circuits optimize low V
performance, allowing operation down to

= 3.0 V.

V

CC

If you are using BX/BL 12 V V
products today, you should account for the
differences listed above and also allow for
connecting 5 V to V
from V

line, if 5 V writes are desired.

PP

and disconnecting 12 V

PP

boot block

PP

CC

1.2 Main Features

Intel’s SmartVoltage technology is the most
flexible voltage solution in the flash industry,
providing two discrete vol tage s upply pins: V
read operation, and V
operation. Discrete supply pins allow system
designers to use the optimal voltage levels for
their design. This product family, specifically the
28F200BV/CV, and 28F002BV provide program/
erase capability at 5 V or 12 V. The 28F200BV /CV
and 28F002BV allow reads with V

0.3 V or 5 V. Since many designs read from t he

flash memory a large percentage of the time, read
operation using the 3.3 V ranges can provide great
power savings. If read performance is an issue,
however, 5 V V
times.

For program and erase operations, 5 V V
operation eliminates the need for in system
voltage converters, while 12 V V
provides faster program and erase for situations
where 12 V is available, s uch as manufacturi ng or
designs where 12 V is in-system. For design
simplicity, however, just hook up V
the same 5 V ± 10% source.

The 28F200/28F002B boot block flash memory
family is a high-performance, 2-Mbit (2,097,152
bit) flash memory family organized as either
256 Kwords of 16 bits each (28F200 only) or
512 Kbytes of 8 bits each (28F200 and 28F002B).

for program and erase

PP

at 3.3 V ±

CC

provides faster read access

CC

PP

and VPP to

CC

for

CC

operation

PP

Table 1. SmartVoltage Provides Total Voltage Flexibility

Product Bus V

Name Width 3.3 V ± 0.3 V 5 V ± 5%

28F002BV-T/B x8 √√√√
28F200BV-T/B x8 or x16 √√√√
28F200CV-T/B x8 or x16 √√√√

CC

5 V ± 10% 12 V ± 5%

5 V ± 10%

SEE NEW DESIGN RECOMMENDATIONS

V

PP

5

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

Separately erasable blocks, including a hardware­lockable boot block (16,384 by tes), two parameter
blocks (8,192 bytes each) and main blocks (one
block of 98,304 bytes and one block of 131,072
bytes), define the boot block flash family
architecture. See Figures 7 and 8 for memory
maps. Each block can be independently eras ed and
programmed 100,000 times at commercial
temperature or 10,000 times at extended
temperature.

The boot block is located at either the t op (denoted
by -T suffix) or the bottom (-B suff ix) of the addres s
map in order to accommodate different
microprocessor protocols for boot code location.
The hardware-lockable boot block provides
complete code security for t he kernel code required
for system initialization. Locking and unlocking of
the boot block is controlled by WP# and/or RP#
(see Section 3.4 for details).

The Command User Interface (CUI) s erves as the
interface between the microprocessor or
microcontroller and the internal operation of the
boot block flash memory products. The internal
Write State Machine (WSM) automati cally ex ecutes
the algorithms and timings necessary for program
and erase operations, including verifications,
thereby unburdening the microprocessor or
microcontroller of these tasks. The Status Register
(SR) indicates the st at us of the WSM and whether i t
successfully completed the desired program or
erase operation.

Program and Erase Automation allows program and
erase operations to be executed using an indust ry­standard two-write command sequence t o the CUI.
Data programming is performed in word (28F200
family) or byte (28F200 or 28F002B families)
increments. Each by te or word in the flash mem ory
can be programmed independently of other memory
locations, unlike erases, which erase all locations
within a block simultaneously.

The 2-Mbit SmartVoltage boot block flash memory
family is also designed with an Automatic Power
Savings (APS) feature which minimizes system
battery current drain, allowing for very low power
designs. To provide even greater power savings,
the boot block family includes a deep power-down
mode which minimizes power consumption by

turning most of the flash memory’s circuitry off. This
mode is controlled by the RP # pin and its usage is
discussed in Section 3.5, along with other power
consumption issues.

Additionally, the RP# pin provides protection
against unwanted command writes due to invalid
system bus conditions that may occur during
system reset and power-up/down sequences. For
example, when the flash memory powers-up, it
automatically defaul ts to the read array mode, but
during a warm system reset, where power
continues uninterrupted to t he system components,
the flash memory could rem ain in a non-read mode,
such as erase. Consequently, the system Reset
signal should be tied to RP# to reset the mem ory to
normal read mode upon activation of the Reset
signal. See Section 3.6.

The 28F200 provides both byte-wide or word-wide
input/output, which is control led by the BYTE# pin.
Please see Table 2 and Figure 16 for a detailed
description of BYTE# operations, especially the
usage of the DQ

The 28F200 products are available in a
ROM/EPROM-compatible pinout and hous ed in the
44-lead PSOP (Plastic Small Outline) pac kage, the
48-lead TSOP (Thin Small Outline, 1.2 mm thick)
package and the 56-lead TSOP as shown in
Figures 4, 5 and 6, respectively. The 28F002
products are available in the 40-lead TSOP
package as shown in Figure 3.

Refer to the
(commercial temperature) and Section 4.11
(extended temperature), for complete current and
voltage specifications. Refer to the

Characteristics

temperature) and Section 4.12 (extended
temperature), for read, write and erase performance
specifications.

pin.

15/A–1

DC Characteristics

, Section 4.4

AC

, Section 4.5 (commercial

1.3 Applications

The 2-Mbit boot block flash memory family
combines high-density, low-power, high­performance, cost-effective flash memories with
blocking and hardware protection c apabilities. Their
flexibility and versatility reduce c ost s throughout t he
product life cycle. Flash memory is ideal for Just-In­Time production flow, reducing system inventory
and costs, and eliminating component handling
during the production phase.

When your product is in the end-user’s hands, and
updates or feature enhancements become
necessary, flash m emory reduces t he update cos ts
by allowing user-performed code changes instead
of costly product returns or technician calls.

6

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

The 2-Mbit boot block flas h memory fami ly prov ides
full-function, bloc ked flash memories suitable for a
wide range of applications. These applications
include extended PC BIOS and ROM-able
applications storage, di gital cellular phone program
and data storage, telecommunication boot/firmware,
printer firmware/font storage and various other
embedded applications where program and data
storage are required.

Reprogrammable systems, such as personal
computers, are ideal applications for the 2-Mbit
flash memory products. Increasing software
sophistication greatens the probability that a code
update will be required after the PC is shipped. For
example, the emerging of “plug and play” standard

in desktop and portable PCs enables auto­configuration of ISA and PCI add-in cards.
However, since the plug and play specification
continues to evolve, a flash BIOS provides a cost­effective capability to update existing PCs. In
addition, the parameter blocks are ideal for storing
the required auto-configuration parameters,
allowing you to integrate the BIOS PROM and
parameter storage EEPROM into a single
component, reducing parts costs while increasing
functionality.

The 2-Mbit flash memory products are also
excellent design solutions f or digital cellular phone
and telecommunication switching applications
requiring very low power consumption, high­performance, high-density storage capability,
modular software designs, and a small form factor
package. The 2-Mbit’s bloc king scheme allows for
easy segmentation of the embedded code with
16 Kbytes of hardware-protected boot code, four

main blocks of program code and two parameter
blocks of 8 Kbytes each for frequently updated data
storage and diagnostic messages (e.g., phone
numbers, authorization codes).

Intel’s boot block architecture provides a flexible
voltage solution for the different design needs of
various applications. The asymmetrically-blocked
memory map allows the integration of several
memory components into a si ngle flash dev ice. The
boot block provides a secure boot PROM; the
parameter blocks can emulate EEPROM
functionality for parameter store with proper
software techniques; and the main blocks provide
code and data storage with access times fast
enough to execute code in plac e, decreasing RAM
requirements.

1.4 Pinouts

Intel’s SmartVoltage Boot Block architecture
provides upgrade paths in every pac kage pinout to
the 4 or 8-Mbit density. The 28F002B 40-lead
TSOP pinout for space-constrained designs is
shown in Figure 3. The 28F200 44-lead PSOP
pinout follows the industry-standard ROM/EPROM
pinout, as shown in Figure 4. For designs that
require x16 operation but have space concerns,
refer to the 48-lead pinout i n Figure 5. Furthermore,
the 28F200 56-lead TSOP pinout shown in Figure 6
provides compatibility with BX/BL family product
packages.

Pinouts for the corresponding 4-Mbit and 8-Mbit
components are also provided for convenient
reference. 2-Mbit pinouts are given on the chip
illustration in the center, with 4-Mbit and 8-Mbit
pinouts going outward from the center.

SEE NEW DESIGN RECOMMENDATIONS

7

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

A[17:1]

CS#

RD#

WR#

i386™ EX CPU

(25 MHz)

D[15:0]

RESET

RESET

NOTE:

A data bus buffer may be needed for processor speeds above 25 MHz.

Figure 1. 28F200 Interface to Intel386™ EX Microprocessor

A[16:17]

ADDRESS

LATCHES

LE

A[16:0]

CE#

OE#

WE#

28F200BV-60

D[15:0]

RP#

0530_01

80C188EB

-A15A

8

ALE

-AD

UCS#

WR#

RD#

RESIN#

P1.X

P1.X

7AD0

ADDRESS

LATCHES

LE

System Reset

V

CC

A

0-A17

28F002-T

-DQ

DQ

7

0

CE#

V

CC

10K

Ω

WE#
OE#

RP#

V

PP

WP#

0530_02

Figure 2. 28F002B Interface to Intel80C188EB 8-Bit Embedded Microprocessor

8

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

28F004B 28F004B

28F008B

A

A

A
A

A
A

A

A

A
A

WE#

RP#

V

WP#

A

A
A
A

A

A

A

A

16
15
14

13
12
11

PP

18

A

A
A

A

A

9
8

WE#

RP#

V

WP#

A

7
6
5

4

3

2

1

15

15

A

14

14

A

13

13

A

12

12

A

11

11

A

A
A

A
A
A

A

A

A

A

PP

18

9

9

A

8

8

WE#

RP#

V

PP

WP#

NC

A

7

7

A

6

6

A

5

5

A

4

4

A

3

3

A

2

2

A

1

1

16

16

A

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

28F002B

Boot Block

40-Lead TSOP

10 mm x 20 mm

TOP VIEW

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A

17

GND
NC

NC

A

10

DQ
DQ

DQ

DQ

V

CC

V

CC

NC

DQ
DQ
DQ
DQ

OE#

GND

CE#

A

0

7
6

5

4

3
2
1
0

A

17

GND
NC

NC

A

10

DQ
DQ

DQ

DQ

V

CC

V

CC

NC

DQ
DQ
DQ
DQ

OE#

GND

CE#

A

0

7
6

5

4

3
2
1
0

28F008B

A

17

GND
NC

A

19

A

10

DQ
DQ

DQ

DQ

V

CC

V

CC

NC

DQ
DQ
DQ
DQ

OE#

GND

CE#

A

0

Figure 3. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained Applications

28F800

V

PP

A

18

A

17

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

CE#
GND
OE#

DQ

0

DQ

8

DQ

1

DQ

9

DQ

2

DQ

10

DQ

3

DQ

11

28F400 28F400

WP#

CE#

GND

OE#

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

V

NC

PP

1
2
3
4

A

7

A

5

6

A

6

5

7

A

4

8

A

3

A

9

2

10

A

1

11

A

0

12
13
14
15

0

16

8

17

1

18

9

19

2

20

10

21

3

22

11

PA28F200
BOOT BLOCK
44-Lead PSOP

0.525" x 1.110"

TOP VIEW

44

RP#

43

WE#

42

A

8

41

A

9

40

A

10

39

A

11

38

A

12

37

A

13

A

36

14

35

A

15

34

A

16

33

BYTE#

32

GND

31

DQ

/A DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

V

CC

15 -1

7
14
6
13
5
12
4

30
29
28
27
26
25
24
23

RP#

WE#

A

8

A

9

A

10

A

11

A

12

A

13

A

14

A

15

A

16

BYTE#

GND

/A

15 -1

DQ
DQ
DQ
DQ
DQ
DQ
DQ

V

CC

7
14
6
13
5
12
4

V

WP#

A

A

A

A

A
A
A
A

A

CE#

GND

OE#

DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ

PP

17
7
6
5
4
3
2
1

0

0
8
1
9
2
10
3

11

NOTE: Pin 2 is WP# on 2- and 4-Mbit devices but A18 on the 8-Mbit because no other pins were available for the high order
address. Thus, the 8-Mbit in the 44-lead PSOP cannot unlock the boot block without RP# = VHH (12 V). To allow upgrades to
the 8 Mbit from 2/2 Mbit in this package, design pin 2 to control WP# at the 2/4 Mbit level and A18 at the 8-Mbit density. See
Section 3.4 for details.

28F800

RP#

WE#

A
A
A
A
A
A
A
A
A

BYTE#

GND

DQ

15 -1

DQ
DQ
DQ
DQ
DQ
DQ
DQ

V

CC

8
9
10
11
12
13
14
15
16

/A

7
14
6
13
5
12
4

Figure 4. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM Standards

SEE NEW DESIGN RECOMMENDATIONS

7
6

5

4

3
2
1
0

0530_03

0530_04

9

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

28F400 28F80028F40028F800

16

15

7

14

6
13
5
12

4

CC

11
3
10

2

9
1

8

0

0

NC

A

BYTE#

GND

DQ
DQ
DQ

DQ
DQ
DQ
DQ

DQ

V
V
DQ
DQ

DQ

DQ
DQ
DQ
DQ
DQ

OE#

GND

CE#

A

NC
NC

/A

16

CC

CC

0

A

BYTE#

GND

DQ

-1

DQ

DQ

DQ
DQ

DQ
DQ

DQ

V

CC

DQ
DQ
DQ

DQ

DQ
DQ

DQ

DQ

OE#

GND

CE#

A

15/A-1
7

14

6
13
5
12
4

11
3

10

2

9
1

8

0

A

16

0

16

BYTE#

GND

/A

-1

15
7

14

6
13
5
12

4

11
3
10

2

9
1

8

0

A

BYTE#

GND

DQ

DQ

DQ

DQ

DQ

DQ

DQ

DQ

V
V

DQ

DQ

DQ

DQ
DQ
DQ
DQ
DQ

OE#

GND

CE#

DQ

15

DQ

7

DQ

14

DQ

6

DQ

13

DQ

5

DQ

12

DQ

4

V

CC

DQ

11

DQ

3

DQ

10

DQ

2

DQ

9

DQ

1

DQ

8

DQ

0

OE#

GND

CE#

A

0

NC

16

15/A-1

7

14

6

13

5

12

4

CC

CC

11

3

10

2

9
1

8

0

A

0

NC

/A

0530_05

NC

0530_06

A

A
A

A

A

A

WE#

RP#

V

WP#

A

A

NC

NC

NC

A

A

15

15
14
13
12
11
10

A

9

A

8

WE#

RP#

PP

WP#

18
17

A

7

A

6

A

5

A

4

A

3

A

2

A

1

15

A

A

14

14

A

A

13

13

A

A

12

12

A

A

11

11

A

A

10

10

A

A

9

A

NC

NC

V

PP

NC
NC

A

A
A

A

A

A
A

A

9

A

8

8

NC

NC

WE#

RP#

V

PP

WP#

NC
NC

17

NC

A

7

7

A

6

6

A

5

5

A

4

4

A

3

3

A

2

2

A

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

28F200

Boot Block

48-Lead TSOP

12 mm x 20 mm

TOP VIEW

A

48
47

BYTE#

46

GND

45

DQ

44

DQ

43

DQ

42

DQ

41

DQ

40

DQ

39

DQ

38

DQ

37

V

36

DQ

35

DQ

34

DQ

33

DQ

32

DQ

31

DQ

30

DQ

29

DQ

28

OE#

27

GND

26

CE#

A

25

Figure 5. The 48-Lead TSOP Offers the Smallest Form Factor for x16 Operation

28F400 28F400

56
55

54

53
52

51
50
49
48
47
46
45

44

43
42
41
40
39
38
37
36
35
34
33

32

31

30
29

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

28

1
2
3
4
5
6
7
8
9

28F200

Boot Block

56-Lead TSOP

14 mm x 20 mm

TOP VIEW

NC

NC

A

15

A

14

A

13

A

12

A

11

A

10

A
A

NC

NC

WE#

RP#

NC
NC

V

PP

WP#

NC

A

17

A
A

A
A
A
A

A

NC

NC

NC

A

15

A

14

A

13

A

12

A

11

A

10

A
A

NC

NC

WE#

RP#

9

8

9

8

NC
NC

V

PP

WP#

NC
NC

A
A
A
A

A
A

A

NC

7
6
5
4
3
2

1

7
6

5
4
3
2

1

Figure 6. The 56-Lead TSOP Offers Compatibility between 2 and 4 Mbits

-1

10

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

1.5 Pin Descriptions

Table 2. 28F200/002 Pin Descriptions

Symbol Type Name and Function

A0–A

17

A

9

DQ0–DQ

DQ8–DQ

CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

OE# INPUT OUTPUT ENABLE: Enables the device’s outputs through the data buffers during

WE# INPUT WRITE ENABLE: Controls writes to the Command Register and array blocks.

RP# INPUT RESET/DEEP POWER-DOWN: Uses three voltage levels (VIL, VIH, and VHH) to

INPUT

INPUT ADDRESS INPUT: When A9 is at VHH the signature mode is accessed. During

INPUT/

7

OUTPUT

INPUT/

15

OUTPUT

ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle. The 28F200 only has A

the 28F002B has A

this mode, A
is at a logic low, only the lower byte of the signatures are read. DQ

don’t care in the signature mode when BYTE# is low.
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle

during a Program command. Inputs commands to the Command User Interface
when CE# and WE# are active. Data is internally latched during the write cycle.
Outputs array, Intelligent Identifier and status register data. The data pins float to
tri-state when the chip is de-selected or the outputs are disabled.

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Data is internally latched during the write cycle.
Outputs array data. The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide
mode DQ

The 28F002B does not include these DQ

sense amplifiers. CE# is active low. CE# high de-selects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow
through the CE# and RP# input stages.

a read cycle. OE# is active low.

WE# is active low. Addresses and data are latched on the rising edge of the WE#
pulse.

control two different functions: reset/deep power-down mode and boot block
unlocking. It is backwards-compatible with the BX/BL/BV products.

When RP# is at logic low, the device is in reset/deep power-down mode,
which puts the outputs at High-Z, resets the Write State Machine, and draws
minimum current.

When RP# is at logic high, the device is in standard operation. When RP#
transitions from logic-low to logic-high, the device defaults to the read array mode.

When RP# is at V

erased. This overrides any control from the WP# input.

15/A–1

– A17.

0

decodes between the manufacturer and device IDs. When BYTE#

0

becomes the lowest order address for data output on DQ0–DQ7.

, the boot block is unlocked and can be programmed or

HH

–DQ

8

0

– A

pins, while

16

pins.

15

15/A–1

is a

SEE NEW DESIGN RECOMMENDATIONS

11

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

Table 2. 28F200/002 Pin Descriptions

Symbol Type Name and Function

WP# INPUT WRITE PROTECT: Provides a method for unlocking the boot block in a system

BYTE# INPUT BYTE# ENABLE: Not available on 28F002B. Controls whether the device

V

CC

V

PP

GND GROUND: For all internal circuitry.
NC NO CONNECT: Pin may be driven or left floating.

without a 12 V supply.
When WP# is at logic low, the boot block is locked, preventing program and

erase operations to the boot block. If a program or erase operation is attempted
on the boot block when WP# is low, the corresponding status bit (bit 4 for
program, bit 5 for erase) will be set in the status register to indicate the operation
failed.

When WP# is at logic high, the boot block is unlocked and can be
programmed or erased.

NOTE: This feature is overridden and the boot block unlocked when RP# is at
V

. See Section 3.4 for details on write protection.

HH

operates in the byte-wide mode (x8) or the word-wide mode (x16). BYTE# pin
must be controlled at CMOS levels to meet the CMOS current specification in the
standby mode.

When BYTE# is at logic low, the byte-wide mode is enabled, where data is
read and programmed on DQ

address that decodes between the upper and lower byte. DQ

–DQ7 and DQ15/A–1 becomes the lowest order

0

–DQ14 are tri-stated

8

during the byte-wide mode.
When BYTE# is at logic high, the word-wide mode is enabled, where data is

read and programmed on DQ

–DQ15.

0

DEVICE POWER SUPPLY: 5.0 V ± 10%, 3.3 V ± 0.3 V, 2.7 V–3.6 V (BE/CE
only)

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block, a voltage either of 5 V ± 10% or 12 V ± 5% must
be applied to this pin. When V
against Program and Erase commands.

PP

< V

all blocks are locked and protected

PPLK

12

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

2.0 PRODUCT DESCRIPTION

2.1 Memory Blocking Organization

This product family features an asymmetrically­blocked architecture providing system memory
integration. Each erase block can be erased
independently of the others up to 100,000 tim es for
commercial temperature or up to 10,000 tim es for
extended temperature. The block sizes have been
chosen to optimize their functionality for common
applications of nonvolat i l e storage. The combination
of block sizes in the boot block architecture allow
the integration of several memories into a single
chip. For the address locations of the blocks, see
the memory maps in Figures 4 and 5.

2.1.1 ONE 16-KB BOOT BLOCK

The boot block is intended to repl ace a dedicated
boot PROM in a microprocess or or microcontroller­based system. The 16-Kbyte (16,384 bytes) boot
block is located at either the top (denoted by -T
suffix) or the bottom (-B suffix) of the address m ap
to accommodate different microproces sor protocols
for boot code location. This boot block features
hardware controllable write-protection to protec t the
crucial microprocessor boot code from accidental
modification. The protection of the boot block is
controlled using a combinat i on of the V
WP# pins, as is detailed in Section 3.4.

, RP#, and

PP

2.1.2 TWO 8-KB PARAMETER BLOCKS

The boot block architecture includes parameter
blocks to facilitate storage of frequently updated
small parameters that would normally require an
EEPROM. By using software techniques, the by te­rewrite functionality of EEPROMs can be emulated.

These techniques are detailed in Intel ’s application
note

AP-604, Using Intel’s Boot Block Flash

Memory Parameter Blocks to Replace EEPROM

Each boot block component contains two parameter
blocks of 8 Kbytes (8,192 bytes) each. The
parameter blocks are not write-protectable.

2.1.3 ONE 96-KB + ONE 128-KB MAIN

After the allocation of address space to the boot
and parameter blocks, the remainder is divided into
main blocks for data or code storage. Each 2-Mbit
device contains one 96-Kbyte (98,304 byte) block
and one 128-Kbyte (131,072 byte) block. See the
memory maps for each device for more information.

BLOCK

.

SEE NEW DESIGN RECOMMENDATIONS

13

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

1FFFFH

1E000H

1DFFFH

1D000H

1CFFFH

1C000H
1BFFFH

10000H

0FFFFH

00000H

28F200-T

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

1FFFFH

10000H

0FFFFH

04000H

03FFFH

03000H

02FFFH

02000H

01FFFH

00000H

8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK

28F200-B

128-Kbyte MAIN BLOCK

96-Kbyte MAIN BLOCK

16-Kbyte BOOT BLOCK

NOTE: In x8 operation, the least significant system address should be connected to A-1. Memory maps are shown for x16
operation.

Figure 7. Word-Wide x16-Mode Memory Maps

28F002-T 28F002-B

3FFFFH
3C000H

3BFFFH

3A000H

39FFFH

38000H

37FFFH

20000H

1FFFFH

00000H

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

3FFFFH

20000H

1FFFFH

08000H

07FFFH

06000H

05FFFH

04000H

03FFFH

00000H

128-Kbyte MAIN BLOCK

96-Kbyte MAIN BLOCK

8-Kbyte PARAMETER BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

NOTE: These memory maps apply to the 28F002B or the 28F200 in x8 mode.

Figure 8. Byte-Wide x8-Mode Memory Maps

0530_07

0530_08

14

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

3.0 PRODUCT FAMILY PRINCIPLES OF OPERATION

Flash memory combines E PROM functionality with
in-circuit electrical program and erase. The boot
block flash family utilizes a Command User
Interface (CUI) and automated algorithms to
simplify program and erase operations. The CUI
allows for 100% TTL-level control inputs, fixed
power supplies during erasure and programming,
and maximum EPROM compatibility.

When V
execute the following commands: Read Array,
Read Status Register, Clear Status Register and
intelligent identifier mode. The device provides
standard EPROM read, standby and output disable
operations. Manufacturer identification and device
identification data c an be acc ess ed through t he CUI
or through the standard EPROM A
access (V

The same EPROM read, standby and output
disable functions are avai lable when 5 V or 12 V is
applied to the V
V

PP

functions associ ated wit h alt ering mem ory c ontent s:
Program and Erase, Intelligent Identifier Read, and
Read Status are accessed via the CUI.

The internal Write State Mac hi ne (WS M) completely
automates program and erase, beginning operation
signaled by the CUI and reporting status through
the status register. The CUI handles the WE#
interface to the data and address latches, as well
as system status requests during WSM operation.

< V

PP

ID

allows program and erase of the device. All

, the device will only successfully

PPLK

high voltage

) for PROM programming equipment.

pin. In addition, 5 V or 12 V on

PP

9

3.2 Read Operations

3.2.1 READ ARRAY

When RP# transitions from V
device will be in the read array mode and will
respond to the read control inputs (CE#, address
inputs, and OE#) without any commands being
written to the CUI.

When the device is in the read array mode, five
control signals must be c ontrolled to obtain data at
the outputs.

• RP# must be logic high (V

• WE# must be logic high (V

• BYTE# must be logic high or logic low

• CE# must be logic low (V

• OE must be logic low (V

In addition, the address of the desired l ocat ion mus t
be applied to the address pins. Refer to Figures 15
and 16 for the exact sequenc e and timing of these
signals.

If the device is not in read array mode, as would be
the case after a program or erase operation, the
Read Mode command (FFH) must be written to t he
CUI before reads can take place.

During system design, consideration should be
taken to ensure address and control inputs meet
required input slew rates of <10 ns as defined in
Figures 12 and 13.

(reset) to VIH, the

IL

)

IH

)

IH

)

IL

)

IL

3.1 Bus Operations

Flash memory reads, erases and programs in­system via the local CPU. All bus cycles to or from
the flash memory conform to standard
microprocessor bus cycles. These bus operations
are summarized in Tables 3 and 4.

SEE NEW DESIGN RECOMMENDATIONS

15

2-MBIT SmartVoltage BOOT BLOCK FAMILY E

Table 3. Bus Operations for Word-Wide Mode (BYTE# = VIH)

Mode Notes RP# CE# OE# WE# A

Read 1,2,3 V
Output Disable V
Standby V
Deep Power-Down 9 V
Intelligent Identifier

4VIHV

(Mfr)
Intelligent Identifier

4,5 V

(Device)
Write 6,7,8 V

V

IH

V

IH

V

IH

IL

V

IH

V

IH

V

IL

V

IL

IH

V

IL

IH

IH

V

IH

XXXXXHigh Z

XXXXXXHigh Z

V

IL

V

IL

V

IL

V

IL

V

IL

V

IH

V

IH

V

IH

IL

Table 4. Bus Operations for Byte-Wide Mode (BYTE# = VIL)

Mode Notes RP# CE# OE# WE# A

Read 1,2,3 V
Output

Disable
Standby V
Deep Power-

9VILXXXXXXXHigh Z High Z

V

IH

V

IH

IH

V

IL

IL

V

V

IL

IH

V

XXXXXXHigh Z High Z

IH

V

IH

V

IH

A

9

0

XXXXD
XXXXHigh Z High Z

Down
Intelligent

Identifier (Mfr)
Intelligent

Identifier

4VIHV

4,5 V

IH

V

V

V

IL

IL

IH

V

V

IL

V

IL

IH

V

ID

IL

V

V

ID

IH

(Device)
Write 6,7,8 V

NOTES:

1. Refer to

2. X can be V

3. See

4. Manufacturer and device codes may also be accessed via a CUI write sequence, A

5. See Table 5 for device IDs.

6. Refer to Table 7 for valid D

7. Command writes for block erase or word/byte program are only executed when V

8. To program or erase the boot block, hold RP# at V

9. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.

DC Characteristics

, VIH for control pins and addresses, V

IL

DC Characteristics

.

for V

PPLK

during a write operation.

IN

V

V

IH

IL

, V

, V

PPH1

, VHH, VID voltages.

PPH2

V

IH

or V

PPLK

or WP# at VIH. See Section 3.4.

HH

XXXXDINHigh Z

IL

for VPP.

PPH

A

9

V

0

XXX D

PP

DQ

0–15

OUT

X X X High Z

V

ID

V

ID

XXX D

A

–1

IL

IH

V

PP

X 0089 H

X See

Table 5

IN

DQ

OUT

0–7

DQ

High Z

8–14

X X 89H High Z

X X See

High Z

Table

5

= X, A1–A17 = X.

1–A16

= V

or V

PP

PPH1

PPH2

.

16

SEE NEW DESIGN RECOMMENDATIONS

E 2-MBIT SmartVoltage BOOT BLOCK FAMILY

3.2.2 INTELLIGENT IDENTIFIERS

To read the manufacturer and device codes, the
device must be in intelligent identifier read mode,
which can be reached using two methods: by
writing the Intelligent Identifier command (90H) or
by taking the A
identifier read mode, A

facturer’s identifi cation code and A
device code. In byte-wi de m ode, only the lower byte
of the above signatures is read (DQ
“don’t care” in this mode). S ee Table 5 for product
signatures. To return to read array mode, write a
Read Array command (FFH).

Table 5. Intelligent Identifier Table

Product Mfr. ID Device ID

28F200 0089 H 2274 H 2275 H
28F002 89 H 7C H 7D H

pin to VID. Once in intelligent

9

= 0 outputs the manu-

0

(Top Boot)-B(Bottom Boot)

-T

= 1 outputs the

0

is a

15/A–1

3.3 Write Operations

3.3.1 COMMAND USER INTERFACE (CUI)

The Command User Interface (CUI) is t he interface
between the microprocessor and the internal chip
controller. Commands are wri tten to the CUI using
standard microprocessor write timings. The
available commands are Read Array, Read
Intelligent Identifier, Read Status Register, Clear
Status Register, Erase and Program (summarized
in Tables 6 and 7). The three read modes are read
array, intelligent identi fier read, and status register
read. For Program or Erase commands, the CUI
informs the Write State Machine (WSM) that a
program or erase has been requested. During the
execution of a Program command, the WSM will
control the programming sequences and the CUI
will only respond to status reads. During an erase
cycle, the CUI will respond to status reads and
erase suspend. After the WSM has completed its
task, it will set the WSM Status bit to a “1” (ready ),
which indicates that t he CUI can respond to it s full
command set. Note that after the WSM has
returned control to the CUI, the CUI will s tay in the
current command state until it receives another
command.

3.3.1.1 Command Function Description

Device operations are selected by writing specific
commands into the CUI. Tabl es 6 and 7 define the
available commands.

SEE NEW DESIGN RECOMMENDATIONS

17