Intel Corporation E28F016XD-95, E28F016XD-85 Datasheet

December 1996 Order Number: 290533-004

85 ns Access Time (t

RAC

)



Supports both Standard and FastPage-Mode Accesses

Multiplexed Address Bus



RAS# and CAS# Control Inputs

No-Glue Interface to Many Memory Controllers

SmartVoltage Technology



User-Selectable 3.3V or 5V V



User-Selectable 5V or 12V V

0.33 MB/sec Write Transfer Rate

x16 Architecture

56-Lead TSOP Type I Package

Backwards-Compatible with 28F008SA Command Set

2 µA Typical Deep Power-Down Current

1 mA Typical ICC Active Current in Static Mode

32 Separately-Erasable/Lockable 64-Kbyte Blocks

1 Million Erase Cycles per Block

State-of-the-Art 0.6 µm ETOX™ IV Flash Technology

Intel’s 28F016XD 16-Mbit fl ash memory is a revol utionary arc hitec ture which is the ideal choic e for designing truly revolutionary high-performance product s. Combining i ts DRAM-li ke read performance and int erface with the intrinsic nonvolatility of flash memory, the 28F016XD eliminates the traditional redundant memory paradigm of shadowing code from a slow nonvolati le storage source to a fas ter execution memory, such as DRAM, for improved system performance. The innovative capabilities of the 28F016X D enable the des ign of direct-execute code and mass storage data/file flash memory systems.

The 28F016XD’s DRAM-like interface with a mult iplexed address bus, f lexible V

and VPP voltages, power saving features, ext ended cycling, fast program and read performanc e, symmetrically-block ed architecture, and selective block lock ing prov ide a highl y f lexi ble mem ory c omponent suit able f or resident fl ash c omponent arrays on the system board or SIMMs. The DRAM-like i nterface with RAS# and CAS# control i nputs allows for easy migration to flash memory in existing DRAM-based systems. The 28F016XD’s dual read voltage allows the same component to operate at either 3.3V or 5.0V V

. Programming voltage at 5.0V V

minimizes external circ uitry in minimal-chip, space critical des igns, while the 12.0V V

option maximizes program/erase performance. The x16 arc hitecture allows opt imization of the memory-to-proc essor interface. Its high read performance combined with flexible block locking enable both storage and execution of operating systems/application software and fast ac cess to large data t ables. The 28F016XD is manufac tured on Intel’s 0.6 µm ETOX IV process technology.

28F016XD

16-MBIT (1 MBIT x 16)

DRAM-INTERFACE FLASH MEMORY

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provi ded in Intel ’s Terms and Condi tions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. The 28F016XD may contain design defects or errors known as errata. Current characterized errata are available upon request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

E 28F016XD FLASH MEMORY

CONTENTS

PAGE PAGE

1.0 INTRODUCTION.........................................5

1.1 Product Overview......................................5

2.0 DEVICE PINOUT.........................................6

2.1 Lead Descriptions.....................................9

3.0 MEMORY MAPS.......................................11

3.1 Extended Status Registers

Memory Map........................................12

4.0 BUS OPERATIONS, COMMANDS AND

STATUS REGISTER DEFINITIONS..........13

4.1 Bus Operations.......................................13

4.2 28F008SA—Compatible Mode

Command Bus Definitions.................... 14

4.3 28F016XD—Enhanced Command

Bus Definitions.....................................15

4.4 Compatible Status Register ....................16

4.5 Global Status Register............................17

4.6 Block Status Register.............................. 18

5.0 ELECTRICAL SPECIFICATIONS............. 19

5.1 Absolute Maximum Ratings.....................19

5.2 Capacitance............................................20

5.3 Transient Input/Output Reference

Waveforms...........................................21

5.4 DC Characteristics (V

= 3.3V ± 0.3V)..............................22

5.5 DC Characteristics (V

= 5.0V ± 0.5V)..............................25

5.6 AC Characteristics (V

= 3.3V ± 0.3V)..............................28

Read, Write, Read-Modify-Write and

Refresh Cycles (Common Parameters)....28

Read Cycle...............................................28

Write Cycle...............................................29

Read-Modify-Write Cycle..........................30

Fast Page Mode Cycle.............................30

Fast Page Mode Read-Modify-Write

Cycle........................................................30

Refresh Cycle...........................................31

Misc. Specifications..................................31

5.7 AC Characteristics (V

= 5.0V ± 0.5V)..............................33

Read, Write, Read-Modify-Write and

Refresh Cycles (Common Parameters)....33

Read Cycle...............................................34

Write Cycle...............................................35

Read-Modify-Write Cycle..........................35

Fast Page Mode Cycle.............................35

Fast Page Mode Read-Modify-Write

Cycle........................................................36

Refresh Cycle...........................................36

Misc. Specifications..................................37

5.8 AC Waveforms........................................38

5.9 Power-Up and Reset Timings..................50

5.10 Erase and Word Program Performance ..51

6.0 MECHANICAL SPECIFICATIONS............52

APPENDIX A: Device Nomenclature and

Ordering Information.....................................53

APPENDIX B: Additional Information...............54

28F016XD FLASH MEMORY E

REVISION HISTORY

Number Description

-001 Original Version

-002

Removed support of the following features:

• All page buffer operations (read, write, programming, Upload Device Information)

• Command queuing

• Software Sleep and Abort

• Erase All Unlocked Blocks

• Device Configuration command Changed definition of “NC.” Removed “No internal connection to die” from description.

Added “xx” to Upper Byte of Command (Data) Definition in Sections 4.2 and 4.3. Modified parameters “V” and “I” of Section 5.1 to apply to “NC” pins. Increased I

PPS

(VPP Read Current) for VPP > VCC to 200 µA at VCC = 3.3V/5.0V.

Changed V

= 5.0V DC Characteristics (Section 5.5) marked with Note 1 to indicate that these currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns and a TTL rise/fall time of <10 ns.

Corrected “RP# high to RAS# going low” to be a “Min” specification at V

= 3.3V/5.0V.

Increased Typical “Word/Block Program Times” (t

WHRH1/tWHRH3

) for VPP = 5.0V:

WHRH1

from 24.0 µs to 35.0 µs and t

WHRH3

from 0.8 sec to 1.2 sec at VCC = 3.3V

WHRH1

from 16.0 µs to 25.0 µs and t

WHRH3

from 0.6 sec to 0.85 sec at VCC = 5.0V

Changed “Time from Erase Suspend Command to WSM Ready” spec name to “Erase

Suspend Latency Time to Read;” modified typical values and added Min/Max values at V

=3.3/5.0V and VPP =5.0/12.0V (Section 5.10).

Minor cosmetic changes throughout document.

-003

Added 3/5# pin to Pinout Configuration (Figure 2), Product Overview (Section 1.1) and Lead Descriptions (Section 2.1)

Modified Block Diagram (Figure 1): Removed Address/Data Queues, Page Buffers, and Address Counter; Added 3/5# pin

Added 3/5# pin to Test Conditions of I

2 and ICC5 Specifications

Modified Power-Up and Reset Timings (Section 5.9) to include 3/5# pin: Removed t

5VPH

and t

3VPH

specifications; Added t

PLYL

, t

PLYH

, t

YLPH

, and t

YHPH

specifications Corrected TSOP Mechanical Specification A1 from 0.50 mm to 0.050 mm (Section 6.0) Minor cosmetic changes throughout document.

-004 Updated DC Specifications ICC3, ICC4, ICC6, ICC7, I

CCD

and I

PPES

Updated AC Specifications t

CAS

(min), t

RCD

(max) and t

CWD

(min)

E 28F016XD FLASH MEMORY

1.0 INTRODUCTION

The documentation of the Intel 28F016XD flash memory device includes this dat asheet, a detailed

user’s manual, and a number of applic ation notes and design tools, all of which are referenced in Appendix B.

The datasheet is intended to give an overview of the chip feature-set and of the operating AC/DC specifications.

The 16-Mbit Flash Product Family

User’s Manual

provides complete descriptions of the user modes, system interface examples and detailed descriptions of all principles of operation. It also contains the full list of software algorithm flowcharts, and a brief section on compatibility with the Intel 28F008SA.

Significant 28F016XD feature revisions occurred between datasheet revisions 290533-001 and 290533-002. These revisions center around removal of the following features:

• All page buffer operations (read, write,

programming, Upload Device Information)

• Command queuing

• Software Sleep and Abort

• Erase all Unlocked Blocks

• Device Configuration command

In addition, a significant 28F016XD change occurred between datasheet revis ions 290532-002 and 290532-003. This change centers around the

addition of a 3/5# pin to the device’s pinout configuration. Figure 2 shows the 3/5# pin assignment for the TSOP Type 1 package.

Intel recommends that all customers obtain the latest revisions of 28F016XD documentation.

1.1 Product Overview

The 28F016XD is a high-performance, 16-Mbit (16,777,216-bit) block erasable, nonvolatile random access memory, organized as 1 Mword x 16. The 28F016XD includes thirty-two 32-KW (32,768 word) blocks. A chip memory map is shown in Figure 3.

The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and result in greater product reliability and ease-of-use as compared t o

other flash memories. Significant features of the 28F016XD include:

• No-Glue Interface to Memory Controllers

• Improved Word Program Performance

• SmartVoltage Technology  Selectable 3.3V or 5.0V V

 Selectable 5.0V or 12.0V V

• Block Program/Erase Protection

The 28F016XD's multiplexed address bus with RAS# and CAS# inputs allows for a “No Glue” interface to many existing in-system memory controllers. As such, 28F016XD-based SIMMs (72-pin JEDEC Standard) offer attractive advantages over their DRAM c ount erparts in many applications. For more information on 28F016XDbased SIMM designs, see the application note referenced at the end of this datasheet.

The 28F016XD incorporates SmartVoltage technology, providing V

operation at both 3.3V

and 5.0V and program and erase capability at V

= 12.0V or 5.0V. Operating at VCC = 3.3V, the 28F016XD consumes less t han 60% of the power consumption at 5.0V V

, while 5.0V VCC provides

the highest read performance capability. V

5.0V operation eliminates the need for a separat e

12.0V converter, while V

= 12.0V maximizes program/erase performance. In addition to the flexible program and erase voltages , t he dedic ated V

gives complete code protection with VPP ≤

PPLK

A 3/5# input pin configures the device’s internal circuitry for optimal 3.3V or 5.0V read/program operation.

A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation.

Internal Algorithm Automation allows word programs and block erase operations to be executed using a Two-Write comm and sequence to the CUI in the same way as the 28F008SA 8Mbit FlashFile™ memory.

Software Locking of Memory Blocks is an added feature of the 28F016XD as compared to the 28F008SA. The 28F016XD provides selectable block locking to protect code or data such as direct-executable operating systems or applicati on code. Each block has an associated nonvolatile lock-bit which determines the lock status of the

28F016XD FLASH MEMORY E

block. In addition, the 28F016XD has a master Write Protect pin (WP#) which prevents any modifications to memory blocks whose lock-bits are set.

Writing of memory data is performed in word

increments typically within 6 µs (12.0V V

)—a

33% improvement

over the 28F008SA. A block erase operation erases one of the 32 blocks in typically 0.6 sec (12.0V V

), independent of the other blocks, which is about a 65% improvement over the 28F008SA.

Each block can be written and eras ed a minimum of 100,000 cycles. Systems can achieve one million Block Erase Cycles by providing wearleveling algorithms and gracef ul block retirement. These techniques have already been employ ed in many flash file systems and hard disk drive designs.

All operations are started by a sequence of Write commands to the device. Three types of Status Registers (described in detail later in this datasheet) and a RY/BY# output pin provide information on the progress of the requested operation.

The following Status Regist ers are us ed to provi de device and WSM information to the user :

• A Compatible Status Register (CSR) which is

100% compatible with the 28F008S A FlashFile memory Status Regist er. The CSR, when used alone, provides a straightforward upgrade capability to the 28F016XD from a 28F008SAbased design.

• A Global Status Register (GSR) which also

informs the system of overall Write State Machine (WSM) status.

• 32 Block Status Registers (BSRs) which

provide block-specific status information such as the block lock-bit status.

The GSR and BSR memory maps are shown in Figure 4.

The 28F016XD incorporates an open drain RY/BY# output pin. This feature al lows the user to OR-tie many RY/BY# pins together in a multiple memory configuration such as a Resident Flash Array.

The 28F016XD is specified for a maximum fast page mode cycle time of 65 ns (t

PC,R

) at 5.0V operation (4.75V to 5.25V) over the commercial temperature range (0°C to +70°C). A corresponding maximum fast page mode cycle time of 75 ns at 3.3V (3.0V to 3.6V and 0°C to +70°C) is achieved for reduced power consumption applications.

The 28F016XD incorporates an Automatic Power Saving (APS) feature, which substantially reduces the active current when the device is in static mode of operation (addresses not switching). In APS mode, the typical I

current is 1 mA at 5.0V

(3.0 mA at 3.3V). A deep power-down mode of operation is invoked

when the RP# (called PWD# on the 28F008SA) pin transitions low. This mode brings the device power consumption to less than 2.0 µA, typically, and provides additional write protection by acting as a device reset pin during power transit ions. A reset time of 300 ns (5.0V V

operation) is required from RP# switching high until dropping RAS#. In the deep power-down state, the WS M is reset (any current operation will abort) and the CSR, GSR and BSR registers are cleared.

A CMOS standby mode of operation is enabled when RAS# and CAS# transition high and RP# stays high with all input control pins at CMOS levels. In this mode, the dev ice typically draws an I

standby current of 70 µA at 5.0V VCC.

The 28F016XD is available in a 56-Lead, 1.2 mm thick, 14 mm x 20 mm TSOP Type I package. This form factor and pinout allow for very high board layout densities.

2.0 DEVICE PINOUT

The 28F016XD 56-Lead TSOP Type I pinout configuration is shown in Figure

E 28F016XD FLASH MEMORY

Output

Buffer

Output

Buffer

Input

Buffer

Input

Buffer

I/O Logic

CSR

ESRs

Data

Comparator

CUI

Decoder

64-Kbyte

Block 0

64-Kbyte

Block 1

64-Kbyte

Block 30

64-Kbyte

Block 31

WSM

Program/Erase Voltage Switch

Address Register

Input

Buffer/

Address

De-Mux

Y Gating/Sensing

Output Multiplexer

GND

8-15

0-7

RAS# CAS#

OE# WE#

WP#

RP#

RY/BY#

0-9

Data

RAS# CAS#

3/5#

0533_01

Figure 1. 28F016XD Block Diagram

Architectural Evolution Includes Multiplexed Address Bus,

SmartVoltage Technology, and Extended Registers

28F016XD FLASH MEMORY E

1 2 3

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

3/5#

GND

NC A

A A A A

V RAS# CAS#

56 55

52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35

NC NC

GND

RP#

NC NC NC NC

GND

NC NC A A A A A

WP# WE# OE# RY/BY# DQ DQ DQ DQ GND DQ DQ DQ DQ V GND DQ DQ DQ DQ V DQ DQ DQ DQ NC

NC NC

9 8 7 6 5

13 5 12 4

11 3 10 2

9 1 8

E28F016XD

56-LEAD TSOP PINOUT

14 mm x 20 mm

TOP VIEW

4 3 2 1 0

0533_02

Figure 2. 28F016XD 56-Lead TSOP Type I Pinout Configuration

E 28F016XD FLASH MEMORY

2.1 Lead Descriptions

Symbol Type Name and Function

A0–A

INPUT MULTIPLEXED ROW/COLUMN ADDRESSES: Selects a word within

one of thirty-two 32-Kword blocks. Row (upper) addresses are latched on the falling edge of RAS#, while column (lower) addresses are latched on the falling edge of CAS#.

DQ0–DQ15INPUT/OUTPUT DATA BUS: Inputs data and commands during CUI write cycles. Outputs

array, identifier or status data (DQ

0-7

) in the appropriate read mode.

Floated when the chip is de-selected or the outputs are disabled.

RAS# INPUT

ROW ADDRESS STROBE: Latches row address information on inputs A

when RAS# transitions low. A subsequent CAS# low transition

initiates 28F016XD read or program operations.

CAS# INPUT

COLUMN ADDRESS STROBE: Latches column address information on inputs A

when CAS# transitions low. When preceded by a RAS# low transition, CAS# low initiates 28F016XD read or program operations, along with OE# and WE#. Subsequent CAS# low transitions, with RAS# held low, enable fast page mode reads/programs

RP# INPUT

RESET/POWER-DOWN: RP# low places the device in a deep powerdown state. All circuits that consume static power, even those circuits enabled in standby mode, are turned off. When returning from deep power-down, a recovery time of 300 ns at 5.0V V

is required to allow these circuits to power-up. When RP# goes low, the current WSM operation is terminated, and the device is reset. All Status Registers return to ready (with all status flags cleared). Exit from deep power-down places the device in read array mode.

OE# INPUT

OUTPUT ENABLE: Gates device data through the output buffers when low in combination with RAS# and CAS# low. The outputs float to tri-state off when OE# is high. OE# can be tied to GND if not controlled by the system memory controller. RAS# and CAS# high override OE# low. WE# low also overrides OE# low.

WE# INPUT WRITE ENABLE: Controls access to the CUI, Data Register and Address

Register. WE# is active low and initiates programs in combination with RAS# and CAS# low. WE# low overrides OE# low. RAS# and CAS# high override WE# low.

RY/BY# OPEN DRAIN

OUTPUT

READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the WSM is busy performing an operation. RY/BY# floating indicates that the WSM is ready for new operations, erase is suspended, or the device is in deep power-down mode. This output is always active (i.e., not floated to tri-state off when OE#, RAS# or CAS# are high).

WP# INPUT WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile

lock-bit for each block. When WP# is low, those locked blocks as reflected by the Block-Lock Status bits (BSR.6), are protected from inadvertent data programs or erases. When WP# is high, all blocks can be written or erased regardless of the state of the lock-bits. The WP# input buffer is disabled when RP# transitions low (deep power-down mode).

28F016XD FLASH MEMORY E

2.1 Lead Descriptions (Continued)

Symbol Type Name and Function

3/5# INPUT 3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V

operation. 3/5# low configures internal circuits for 5.0V operation.

NOTE:

Reading the array with 3/5# high in a 5.0V system could damage the device. Reference the power-up and reset timings (Section 5.9) for 3/5# switching delay to valid data.

SUPPLY PROGRAM/ERASE POWER SUPPLY (12.0V ± 0.6V, 5.0V ± 0.5V): For

erasing memory array blocks or writing words into the flash array. V

5.0V ± 0.5V eliminates the need for a 12.0V converter, while connection to 12.0V ± 0.6V maximizes program/erase performance.

NOTE:

Successful completion of program and erase attempts is inhibited with V

at or below 1.5V. Program and erase attempts with V

between 1.5V and 4.5V, between 5.5V and 11.4V, and above 12.6V produce spurious results and should not be attempted.

SUPPLY

DEVICE POWER SUPPLY (3.3V ± 0.3V, 5.0V ± 0.5V):

To switch 3.3V to 5.0V (or vice versa), first ramp V

down to GND, and

then power to the new V

voltage.

Do not leave any power pins floating.

GND SUPPLY

GROUND FOR ALL INTERNAL CIRCUITRY:

Do not leave any ground pins floating.

NO CONNECT:

Lead may be driven or left floating.

E 28F016XD FLASH MEMORY

3.0 MEMORY MAPS

32-Kword Block

FFFFF

F8000

F7FFF

F0000

EFFFF

E8000

E7FFF

E0000

DFFFF

30 29 28 27

D8000

D7FFF

D0000

CFFFF

C8000

C7FFF

C0000

BFFFF

26 25 24 23

B8000

B7FFF

B0000

A8FFF

A8000

A7FFF

A0000

9FFFF

22 21 20 19

98000 97FFF

90000

8FFFF

88000 87FFF

80000

7FFFF

18 17 16 15

78000 77FFF

70000

6FFFF

68000 67FFF

60000

5FFFF

14 13 12 11

58000 57FFF

50000

4FFFF

48000 47FFF

40000

3FFFF

9 8 7

38000 37FFF

30000

2FFFF

28000 27FFF

20000

1FFFF

6 5 4 3

18000 17FFF

10000

0FFFF

08000 07FFF

00000

2 1 0

32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block

[19-0]

0533_03

NOTE:

The upper 10 bits (A

19–10

) reflect 28F016XD addresses A

9–0

, latched by RAS#.

The lower 10 bits (A

9–0

) reflect 28F016XD addresses A

9–0

, latched by CAS#.

Figure 3. 28F016XD Memory Map

28F016XD FLASH MEMORY E

3.1 Extended Status Registers Memory Map

RESERVED

GSR

RESERVED

BSR0

00002H

00001H RESERVED RESERVED

00000H

00003H

RESERVED

07FFFH

RESERVED

GSR

RESERVED

BSR31

F8002H

F8001H RESERVED RESERVED

F8000H

F8003H

RESERVED

FFFFFH

19-0

0533_04

NOTE:

The upper 10 bits (A

19–10

) reflect 28F016XD addresses A

9–0

, latched by RAS#.

The lower 10 bits (A

9–0

) reflect 28F016XD addresses A

9–0

, latched by CAS#.

Figure 4. Extended Status Registers Memory Map

E 28F016XD FLASH MEMORY

4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS

4.1 Bus Operations

Mode Notes RP# RAS# CAS# OE# WE# DQ

0–15

RY/BY#

Row Address Latch 1,2,9 V

↓ V

XX X X

Column Address Latch 1,2,9 V

↓ XX X X

Read 1,2,7 V

OUT

Output Disable 1,6,7 V

High Z X

Standby 1,6,7 V

X X High Z X

Deep Power-Down 1,3 V

XXXXHigh Z V

Manufacturer ID 4,8 V

0089H V

Device ID 4,8 V

66A8H V

Write 1,5,6 V

XVILD

NOTES:

1. X can be V

or V

for address or control pins except for RY/BY#, which is either V

or V

, or High Z or D

OUT

for data

pins depending on whether or not OE# is active.

2. RY/BY# output is open drain. When the WSM is ready, erase is suspended or the device is in deep power-down mode, RY/BY# will be at V

if it is tied to V

through a resistor. RY/BY# at VOH is independent of OE# while a WSM operation

is in progress.

3. RP# at GND ± 0.2V ensures the lowest deep power-down current.

4. A

(latched by CAS#) at VIL provides the Manufacturer ID code. A0 (latched by CAS#) at VIH provides the Device ID code.

All other addresses (row and column) should be set to zero.

5. Commands for erase, data program, or lock-block operations can only be completed successfully when V

= V

PPH1

= V

PPH2

6. While the WSM is running, RY/BY# stays at V

until all operations are complete. RY/BY# goes to VOH when the WSM is

not busy or in erase suspend mode.

7. RY/BY# may be at V

while the WSM is busy performing various operations (for example, a Status Register read during a

program operation).

8. The 28F016XD shares an identical device identifier with the 28F016XS.

9. Row (upper) addresses are latched via inputs A

0-9

on the falling edge of RAS#. Column (lower) addresses are latched via

inputs A

0-9

on the falling edge of CAS#. Row addresses must be latched before column addresses are latched.

28F016XD FLASH MEMORY E

4.2 28F008SA—Compatible Mode Command Bus Definitions

First Bus Cycle Second Bus Cycle

Command Notes Oper Addr Data

(4)

Oper Addr Data

(4)

Read Array Write X xxFFH Read AA AD Intelligent Identifier 1 Write X xx90H Read IA ID Read Compatible Status Register 2 Write X xx70H Read X CSRD Clear Status Register 3 Write X xx50H Word Program Write X xx40H Write PA PD Alternate Word Program Write X xx10H Write PA PD Block Erase/Confirm Write X xx20H Write BA xxD0H Erase Suspend/Resume Write X xxB0H Write X xxD0H

ADDRESS DATA

AA = Array Address AD = Array Data BA = Block Address CSRD = CSR Data IA = Identifier Address ID = Identifier Data PA = Program Address PD = Program Data

X = Don’t Care

NOTES:

1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes.

2. The CSR is automatically available after device enters data program, erase, or suspend operations.

3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSR.4 and BSR.2 bits. See Status Register definitions.

4. The upper byte of the data bus (D

8–15

) during command writes is a “Don’t Care.”

E 28F016XD FLASH MEMORY

4.3 28F016XD—Enhanced Command Bus Definitions

First Bus Cycle Second Bus Cycle

Command Notes Oper Addr Data

(3)

Oper Addr Data

(3)

Read Extended Status Register 1 Write X xx71H Read RA GSRD

BSRD Lock Block/Confirm Write X xx77H Write BA xxD0H Upload Status Bits/Confirm 2 Write X xx97H Write X xxD0H

ADDRESS DATA

BA = Block Address AD = Array Data RA = Extended Register Address BSRD = BSR Data PA = Program Address GSRD = GSR Data

X = Don’t Care

NOTES:

1. RA can be the GSR address or any BSR address. See Figure 4 for the Extended Status Register memory map.

2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the actual lock-bit status.

3. The upper byte of the data bus (D

8–15

) during command writes is a “Don’t Care.”

28F016XD FLASH MEMORY E

4.4 Compatible Status Register

WSMS ESS ES DWS VPPS R R R

76543210

NOTES:

CSR.7 = WRITE STATE MACHINE STATUS

1 = Ready 0 = Busy

RY/BY# output or WSMS bit must be checked to determine completion of an operation (erase, erase suspend, or data program) before the appropriate Status bit (ESS, ES or DWS) is checked for success.

CSR.6 = ERASE-SUSPEND STATUS

1 = Erase Suspended 0 = Erase In Progress/Completed

CSR.5 = ERASE STATUS

1 = Error In Block Erasure 0 = Successful Block Erase

If DWS and ES are set to “1” during an erase

attempt, an improper command sequence was entered. Clear the CSR and attempt the operation again.

CSR.4 = DATA-WRITE STATUS

1 = Error in Data Program 0 = Data Program Successful

CSR.3 = V

STATUS

1 = V

Error Detect, Operation Abort

0 = V

The VPPS bit, unlike an A/D converter, does not provide continuous indication of V

level. The

WSM interrogates V

’s level only after the Data Program or Erase command sequences have been entered, and informs the system if V

has not been switched on. VPPS is not guaranteed to report accurate feedback between V

PPL

(max)

and V

PPH1

(min), between V

PPH1

(max) and

PPH2

(min) and above V

PPH2

(max).

CSR.2–0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the CSR.

E 28F016XD FLASH MEMORY

4.5 Global Status Register

WSMS OSS DOS R R R R R

76543210

NOTES:

GSR.7 = WRITE STATE MACHINE STATUS

1 = Ready 0 = Busy

RY/BY# output or WSMS bit must be checked to determine completion of an operation (block lock, suspend, Upload Status Bits, erase or data program) before the appropriate Status bit (OSS or DOS) is checked for success.

GSR.6 = OPERATION SUSPEND STATUS

1 = Operation Suspended 0 = Operation in Progress/Completed

GSR.5 = DEVICE OPERATION STATUS

1 = Operation Unsuccessful 0 = Operation Successful or Currently

Running GSR.4–0 = RESERVED FOR FUTURE ENHANCEMENTS

These bits are reserved for future use; mask them out when polling the GSR.

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Intel Corporation E28F016XD-95, E28F016XD-85 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual