Intel Corporation E28F016SA-150, E28F016SA-120, E28F016SA-100, E28F016SA-080, E28F016SA-070 Datasheet

E







28F016SA 16-MBIT

(1 MBIT X 16, 2 MBIT X 8)

FlashFile™ MEMORY

Includes Commercial and Extended Temperature Specifications

n

User-Selectable 3.3V or 5V V

n

User-Configurable x8 or x16 Operation

n

70 ns Maximum Access Time

n

28.6 MB/sec Burst Write Transfer Rate

n

1 Million Typical Erase Cycles per
Block

n

56-Lead, 1.2 mm x 14 mm x 20 mm
TSOP Package

n

56-Lead, 1.8 mm x 16 mm x 23.7 mm
SSOP Package

Intel’s 28F016SA 16-Mbit FlashFile™ memory is a revolutionary architect ure which is the ideal choice f or
designing embedded direct-execut e code and mass s torage data/fi le flash mem ory systems. With innovative
capabilities, low-power, extended temperat ure operation and high read/program performance, the 28F016SA
enables the design of truly mobile, high-performance communications and computing products.

The 28F016SA is the highest dens ity, highest performance nonv olatile read/program sol ution for solid-s tate
storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit
FlashFile memory), extended cy cling, extended temperature operation, flexible V
performance and selectiv e block locking provide highly flexibl e memory components suitable for Resident
Flash Arrays, high-density mem ory cards and PCMCIA-ATA flas h drives. The 28F016SA dual read voltage
enables the design of memory cards which can be int erchangeably read/written i n 3.3V and 5.0V systems. Its
x8/x16 architecture al lows optimizat ion of the memory-t o-processor interfac e. Its high read perform ance and
flexible block locking enable both storage and execution of operating systems and application software.
Manufactured on Intel’s 0.6 µm ETOX IV process technology, the 28F016SA is the most cost-effective,
highest density monolithic 3.3V FlashFile memory.

CC

n

Revolutionary Architecture

Pipelined Command Execution
Program during Erase
Command Superset of Intel
28F008SA

n

1 mA Typical ICC in Static Mode

n

1 µA Typical Deep Power-Down

n

32 Independently Lockable Blocks

n

State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology

, fast program and read

CC

November 1996 Order Number: 290489-004

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F016SA may contain design defects or errors known as errata. Current characterized errata are available upon request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

COPYRIGHT © INTEL CORPORATION, 1996 CG-041493

E 28F016SA

CONTENTS

PAGE PAGE

1.0 INTRODUCTION.............................................5

1.1 Product Overview ........................................5

2.0 DEVICE PINOUT.............................................6

2.1 Lead Descriptions........................................8

3.0 MEMORY MAPS...........................................12

3.1 Extended Status Register Memory Map..... 13

4.0 BUS OPERATIONS, COMMANDS AND

STATUS REGISTER DEFINITIONS.............14

4.1 Bus Operations for Word-Wide Mode
(BYTE# = V

4.2 Bus Operations for Byte-Wide Mode
(BYTE# = V

4.3 28F008SA–Compatible Mode Command

Bus Definitions..........................................15

4.4 28F016SA–Performance Enhancement

Command Bus Definitions.........................16

4.5 Compatible Status Register ....................... 18

4.6 Global Status Register...............................19

4.7 Block Status Register ................................20

5.0 ELECTRICAL SPECIFICATIONS.................21

5.1 Absolute Maximum Ratings ....................... 21

5.2 Capacitance...............................................22

5.3 Timing Nomenclature................................. 23

5.4 DC Characteristics (V

5.5 DC Characteristics

= 5.0V ± 10%, 5.0V ± 5%)................29

(V

CC

)........................................... 14

IH

)...........................................14

IL

= 3.3V ± 10%)..... 26

CC

5.6 AC Characteristics–Read Only

Operations.................................................32

5.7 Power-Up and Reset Timings.....................37

5.8 AC Characteristics for WE#–Controlled

Command Write Operations......................38

5.9 AC Characteristics for CE#–Controlled

Command Write Operations......................42

5.10 AC Characteristics for Page Buffer Write

Operations.................................................46

5.11 Erase and Word/Byte Program
Performance, Cycling Performance and

Suspend Latency.......................................49

6.0 DERATING CURVES.....................................50

7.0 MECHANICAL SPECIFICATIONS FOR

TSOP............................................................52

8.0 MECHANICAL SPECIFICATIONS FOR

SSOP............................................................53

APPENDIX A: Device Nomenclature and

Ordering Information ..................................54

APPENDIX B: Additional Information...............55

3

28F016SA E

REVISION HISTORY

Number Description

-001 Original Version

-002 — Added 56-Lead SSOP Package

-003

-004

— Separated AC Reading Timing Specs t

Reads
— Modified Device Nomenclature
— Added Ordering Information
— Added Page Buffer Typical Program Performance numbers
— Added Typical Erase Suspend Latencies
— For I

(Deep Power-Down current) BYTE# must be at CMOS levels

CCD

— Added SSOP package mechanical specifications
— Revised document status from “Advanced Information” to “Preliminary”

— Section 5.11: Renamed specification “Erase Suspend Latency Time to Program” as
“Auto Erase Suspend Latency Time to Program”

— Section 5.7: Added specifications t
— TSOP dimension A1 = 0.05 mm (min)
— SSOP dimension B = 0.40 mm (max)
— Minor cosmetic changes

Update:
—Changed Deep Power Down Current
— Changed Standby Current
— Changed Sleep Mode Current
Combined Commercial and Extended Temperature information into single datasheet

PHEL3

AVEL

, t

, t

for Extended Status Register

AVGL

PHEL5

4

E 28F016SA

1.0 INTRODUCTION

The documentation of the Int el 28F016SA memory

device includes this datasheet, a detailed user’s
manual, and a number of application notes, all of
which are referenced at the end of this datasheet.

The datasheet is intended to give an overview of the
chip feature-set and of the operating AC/DC
specifications.

User’s Manual

the user modes, system interface examples and
detailed descriptions of all principles of operation. It
also contains the full list of software algorithm
flowcharts, and a brief sect ion on compatibility with
Intel 28F008SA.

The 16-Mbit Flash Product Family

provides complete descriptions of

1.1 Product Overview

The 28F016SA is a high-performance 16-Mbit
(16,777,216 bit) block erasable nonvolati le random
access memory organized as either 1 Mword x
16 or 2 Mbyte x 8. The 28F016SA i ncludes thirty­two 64-KB (65,536) blocks or thirty-two 32-KW
(32,768) blocks. A chip memory map is shown in
Figure 4.

The implementation of a new architecture, with
many enhanced features, will improve the device
operating characteristics and results in greater
product reliability and ease-of-use.

Among the significant enhancements on the
28F016SA:

• 3.3V Low Power Capability

• Improved Program Performance

• Dedicated Block Program/Erase Protection

A 3/5# input pin reconfigures the device internally
for optimized 3.3V or 5.0V read/program operation.

The 28F016SA will be available in a 56-lead,

1.2 mm thick, 14 mm x 20 mm TSOP type I
package or a 56-lead, 1.8 mm thick, 16 mm x

23.7 mm SSOP package. The TSOP form factor
and pinout allow for very high board layout
densities. SSOP packaging provides relaxed lead
spacing dimensions.

A Command User Interface (CUI) serves as the
system interface between the microprocessor or
microcontroller and the internal memory operation.

Internal algorithm automation allows word/byte
programs and block erase operations to be
executed using a two-write c ommand sequence to
the CUI in the same way as the 28F008SA 8-Mbit
FlashFile memory.

A superset of commands have been added to t he
basic 28F008SA command-set to achieve higher
program performance and provide additional
capabilities. These new commands and features
include:

• Page Buffer Writes to Flash

• Command Queueing Capability

• Automatic Data Programs during Erase

• Software Locking of Memory Blocks

• Two-Byte Successive Programs in 8-bit

Systems

• Erase All Unlocked Blocks
Writing of memory data is performed in either byte

or word increments typically within 6 µs, a 33%
improvement over the 28F008SA. A block erase
operation erases one of the 32 blocks in typically

0.6 sec, independent of the ot her blocks, which is a
65% improvement over the 28F008SA.

Each block can be writt en and erased a mini mum of
100,000 cycles. Systems can achieve typically one­million block erase cycles by providing wear-leveling
algorithms and graceful block retirement. These
techniques have already been employed in many
flash file systems. Additionally, wear leveling of
block erase cycles can be used to minimize the
program/erase performance differences across
blocks.

The 28F016SA incorporates two Page Buffers of
256 bytes (128 words) each to allow page data
writes. This feature can improve a system write
performance by up to 4.8 t imes over previ ous flash
memory devices.

All operations are started by a sequence of
command writes to the device. Three Status
Registers (described in detai l later) and a RY/BY#
output pin provide information on the progress of
the requested operation.

While the 28F008SA requires an operation to
complete before the next operation can be
requested, the 28F016SA allows queueing of the
next operation while the memory executes the
current operation. This elim inates system overhead

5

28F016SA E

when writing several bytes in a row to the array or
erasing several blocks at the same time. The
28F016SA can also perform program operations to
one block of memory while performing erase of
another block.

The 28F016SA provides user-selectable block
locking to protect code or data such as device
drivers, PCMCIA card i nformation, ROM -executable
O/S or application code. Each block has an
associated nonvolatil e loc k-bit whic h det ermines the
lock status of t he block. In addition, the 28F016SA
has a master Write Protect pin (WP#) which
prevents any modifications to memory blocks
whose lock-bits are set.

The 28F016SA contains three types of Status
Registers to accomplish various functions:

• A Compatible Status Register (CSR) which is
100% compatible with the 28F008SA FlashFile

memory’s Status Register. This register, when
used alone, provides a straight forward upgrade
capability to the 28F016SA from a 28F008SA­based design.

• A Global Status Regist er (GSR) which informs
the system of Command Queue status, Page
Buffer status, and ov erall Write State Machine
(WSM) status.

• 32 Block Status Regi s ters (BSRs) which provide
block-specific status information such as the
block lock-bit status.

The GSR and BSR memory maps for by te-wi de and
word-wide modes are shown in Figures 5
and 6.

The 28F016SA incorporates an open drain RY/BY #
output pin. This feature allows the user to OR-tie
many RY/BY# pins together in a multiple memory
configuration such as a Resident Flash Array.

Other configurations of t he RY/BY# pin are enabled
via special CUI commands and are described in
detail in the

16-Mbit Flash Product Family User’s

Manual.

The 28F016SA also incorporates a dual c hip-enable
function with two input pins, CE

# and CE1#. These

0

pins have exactly the same functionality as the
regular chip-enable pin CE# on the 28F008SA. For
minimum chip designs, CE
to use CE

# as the chip enable input. The

0

# may be tied to ground

1

28F016SA uses the logical combination of these
6

two signals to enable or disable the entire chip. Both
CE

# and CE1# must be active low to enable the

0

device and, if either one becomes i nactive, the c hip
will be disabled. This feature, along with the open
drain RY/BY# pin, allows the system designer to
reduce the number of control pins used in a large
array of 16-Mbit devices.

The BYTE# pin allows either x8 or x16
read/programs to the 28F016SA. BYTE# at logic
low selects 8-bit mode with address A

selecting

0

between low byte and high byte. On the other hand,
BYTE# at logic high enables 16-bit operation with
address A
address A

becoming the lowest order addres s and

1

is not used (don’t care). A device bl ock

0

diagram is shown in Figure 1.
The 28F016SA is specified f or a maximum access

time of 70 ns (t

) at 5.0V operation (4.75V to

ACC

5.25V) over the commercial temperature range
(0°C to +70°C). A corresponding m aximum access
time of 120 ns at 3.3V (3.0V to 3.6V and 0°C to
+70°C) is achieved for reduced power c onsumption
applications.

The 28F016SA incorporates an Automatic Power
Saving (APS) feature which substantially reduces
the active current when the device is in the static
mode of operation (addresses not switching).

In APS mode, the typical I

current is 1 mA at 5.0V

CC

(0.8 mA at 3.3V).
A deep power-down mode of operation is invoked

when the RP# (called PWD# on the 28F008SA) pin
transitions low. This mode brings the device power
consumption to less than 1.0 µA, typically, and
provides additional write protection by acting as a
device reset pin during power transitions. A reset
time is required from RP# switching high until
outputs are again valid. In the deep power-down
state, the WSM is reset (any current operation will
abort) and the CSR, GSR and BSR registers are
cleared.

A CMOS standby mode of operation is enabled
when either CE

# or CE1# transitions high and RP #

0

stays high with all input control pins at CMOS
levels. In this m ode, the device typically draws an
I

standby current of 50 µA.

CC

2.0 DEVICE PINOUT

The 28F016SA 56-lead TSOP Type I pinout
configuration is shown in
SSOP pinout configuration is shown in Figure 3.

Figure 2. The 56-lead

E 28F016SA

#

Output

Buffer

DQ

8-15

Output

Buffer

DQ

ID

Register

CSR

0-7

Input

Buffer

Data

Queue

Registers

Page

Buffers

Input

Buffer

I/O Logic

3/5#
BYTE#

Output Multiplexer

ESRs

0-20

A

Input

Buffer

Y

Decoder

Data

Comparator

Y Gating/Sensing

CUI

CE0

CE1#

OE#
WE#
WP#

RP#

Address

Queue

Latches

Address
Counter

X

Decoder

Program/Erase
Voltag e S witch

Block 1

Block 0

64-Kbyte

64-Kbyte

Block 30

Block 31

64-Kbyte

64-Kbyte

WSM

RY/BY#

V

3/5#

V

CC

GND

PP

Figure 1. 28F016SA Block Diagram

Architectural Evolution Includes Page Buffers, Queue Registers and Extended Status Registers

0489_01

7

28F016SA E

2.1 Lead Descriptions

Symbol Type Name and Function

A

0

A

1–A15

A

16–A20

DQ

0–DQ7

DQ

8–DQ15

CE0#,CE1# INPUT CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,

RP# INPUT RESET/POWER-DOWN: RP# low places the device in a deep power-

OE# INPUT OUTPUT ENABLE: Gates device data through the output buffers when

WE# INPUT WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue

INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when the

device is in x8 mode. This address is latched in x8 data programs. Not
used in x16 mode (i.e., the A

input buffer is turned off when BYTE# is

0

high).

INPUT WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block.

A

selects 1 of 1024 rows, and A

6–15

selects 16 of 512 columns. These

1–5

addresses are latched during data programs.

INPUT BLOCK-SELECT ADDRESSES: Select 1 of 32 erase blocks. These

addresses are latched during data programs, block erase and lock block
operations.

INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI write

cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is deselected or the outputs are
disabled.

INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 data program

operations. Outputs array, buffer or identifier data in the appropriate read
mode; not used for Status Register reads. Floated when the chip is
deselected or the outputs are disabled.

decoders and sense amplifiers. With either CE

# or CE1# high, the device

0

is deselected and power consumption reduces to standby levels upon
completion of any current data program or block erase operations. Both
CE

#, CE1# must be low to select the device.

0

All timing specifications are the same for both signals. Device selection
occurs with the latter falling edge of CE
CE

# or CE1# disables the device.

0

# or CE1#. The first rising edge of

0

down state. All circuits that burn static power, even those circuits enabled
in standby mode, are turned off. When returning from deep power-down,
a recovery time is required to allow these circuits to power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).

low. The outputs float to tri-state off when OE# is high.

NOTE:

CEx# overrides OE#, and OE# overrides WE#.

Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.

Page Buffer addresses are latched on the falling edge of WE#.

8

E 28F016SA

2.1 Lead Descriptions (Continued)

Symbol Type Name and Function

RY/BY# OPEN DRAIN

WP# INPUT WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile

BYTE# INPUT BYTE ENABLE: BYTE# low places device in x8 mode. All data is then

3/5# INPUT 3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V

V

PP

V

CC

GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY:

NC NO CONNECT:

OUTPUT

SUPPLY ERASE/PROGRAM POWER SUPPLY: For erasing memory array blocks

SUPPLY DEVICE POWER SUPPLY (3.3V ± 10%, 5.0V ± 10%, 5.0V ± 5%):

READY/BUSY: Indicates status of the internal WSM. When low, it
indicates that the WSM is busy performing an operation. RY/BY# high
indicates that the WSM is ready for new operations (or WSM has
completed all pending operations), or block erase is suspended, or the
device is in deep power-down mode. This output is always active (i.e., not
floated to tri-state off when OE# or CE
RY/BY# Pin Disable command is issued.

lock-bit for each block. When WP# is low, those locked blocks as
reflected by the Block-Lock Status bits (BSR.6), are protected from
inadvertent data programs or block erases. When WP# is high, all blocks
can be written or erased regardless of the state of the lock-bits. The WP#
input buffer is disabled when RP# transitions low (deep power-down
mode).

input or output on DQ
the high and low byte. BYTE# high places the device in x16 mode, and
turns off the A
address.

operation. 3/5# low configures internal circuits for 5.0V operation.

Reading the array with 3/5# high in a 5.0V system could damage the
device.
There is a significant delay from 3/5# switching to valid data.

or writing words/bytes/pages into the flash array.

Do not leave any power pins floating.

Do not leave any ground pins floating.

Lead may be driven or left floating.

input buffer. Address A1 then becomes the lowest order

0

, and DQ

0–7

#,CE1# are high), except if a

0

float. Address A

8–15

NOTES:

selects between

0

9

28F016SA E

28F032SA 28F016SV 28F032SA28F016SV

3/5#

CE #

1

CE #

2

A
A
A
A
A

V

CC

A
A
A
A

CE #

0

V

PP

RP#

A
A

A
A

GND

A
A
A
A
A
A
A

3/5#

3/5#

CE #

CE #

1

NCNC NC

NC

A
A
A
A
A
V

CC

A
A
A
A

CE #

V

RP#

A
A

A
A

GND

A
A
A
A
A
A
A

A

20

A

19

A

18

A

17

A

16

V
A

15

A

14

A

13

A

12

CE #

0

V

PP

RP#

A

11

A

10

9
8

GND

7
6
5
4
3
2
1

20
19
18
17
16

15
14
13
12

11
10

9
8

7
6
5
4
3
2
1

1
2

1

3

4

20

5

19

6

18

7

17

8

16

9

CC

10

15

11

14

12

13

13

12

14

0

15

PP

16
17

11

18

10

19

A

9

20

A

8

21
22

A

7

23

A

6

24

A

5

A

25

4

26

A

3

27

A

2

28

A

1

E28F016SA

56-LEAD TSOP PINOUT

1.2 mm x 14 mm x 20 mm
TOP VIEW

NOTE:

56-Lead TSOP Mechanical Diagrams and Dimensions are shown at the end of this specification.

Figure 2. TSOP Pinout Configuration

56

WP#

55

WE#

54

OE#

53

RY/BY#

52

DQ15DQ15DQ

51

DQ

50

DQ14DQ14DQ

49

DQ

48

GND

47

DQ

46

DQ5DQ5DQ

45

DQ

44

DQ4DQ4DQ

43

V

42

GND

41

DQ11DQ11DQ

40

DQ

39

DQ10DQ10DQ

38

DQ

37

V

36

DQ

35

DQ

34

DQ

33

DQ

32

A0A

31

BYTE#

30

NC

29

NC

WP#

WP#

WE#

WE#

OE#

OE#

RY/BY#

RY/BY#

15

DQ

DQ

7

DQ

6

GND
DQ

13

DQ

12

V

CC

GND
DQ

3

DQ

2

V

CC

DQ

9

DQ

1

DQ

8

DQ

0

BYTE#
NC
NC

7

7

14

DQ

6

6

GND
DQ

13

13

5

DQ

12

12
4

V

CC

CC

GND

11

DQ

3

3

10

DQ

2

2

V

CC

CC

DQ

9

9

DQ

1

1

DQ

8

8

DQ

0

0

A

0

0

BYTE#
NC
NC

0489_02

10

E 28F016SA

28F016SV

CE #

0

A

12

A

13

A

14

A

15

3/5#

CE #

1

NC

A

20

A

19

A

18

A

17

A

16

V

CC

GND

DQ

6

DQ

14

DQ

7

DQ

15

RY/BY#

OE#
WE#
WP#

DQ

13

DQ

5

DQ

12

DQ

4

V

CC

CE #

0

A

12

A

13

A

14

A

15

3/5#

CE #

1

NC
A

20

A

19

A

18

A

17

A

16

V

CC

GND

DQ
DQ

14

DQ
DQ

15

RY/BY#

OE#
WE#

WP#
DQ
DQ
DQ
DQ

V

CC

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

6

DA28F016SA
56-LEAD SSOP

STANDARD PINOUT

1.8 mm x 16 mm x 23.7 mm
TOP VIEW

17
18

7

19
20

21
22
23
24

13

25

5

26

12

27

4

28

56
55

54
53
52
51
50

49
48
47
46

45
44

43
42
41
40
39

38
37
36
35
34
33
32
31
30
29

V
RP#

A
A
A
A
A

A
A
A
A

A
GND

A
V
DQ
DQ
DQ

DQ
A
BYTE#
NC
NC
DQ

DQ
DQ
DQ
GND

V

PP

PP

RP#
A

11
10
9
1
2
3
4
5
6
7

11

A

10

A

9

A

1

A

2

A

3

A

4

A

5

A

6

A

7

GND
A

8

8

V

CC

CC

DQ
DQ
DQ
DQ
A

9
1
8
0

0

9
1
8
0

0

BYTE#

NC
NC

DQ
DQ

DQ
DQ

2
10
3
11

2
10
3
11

GND

0489_17

28F016SV

Figure 3. SSOP Pinout Configuration

11

28F016SA E

3.0 MEMORY MAPS

A

[20-0]

1FFFFF

1F0000

1EFFFF

1E0000

1DFFFF

1D0000

1CFFFF

1C0000

1BFFFF

1B0000

1AFFFF

1A0000

19FFFF

190000

18FFFF

180000

17FFFF

170000

16FFFF

160000

15FFFF

150000

14FFFF

140000

13FFFF

130000

12FFFF

120000

11FFFF

110000

10FFFF

100000

0FFFFF

0F0000

0EFFFF

0E0000

0DFFFF

0D0000

0CFFFF

0C0000

0BFFFF

0B0000

0AFFFF

0A0000

09FFFF

090000

08FFFF

080000

07FFFF

070000

06FFFF

060000

05FFFF

050000

04FFFF

040000

03FFFF

030000

02FFFF

020000

01FFFF

010000

00FFFF

000000

64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1
0

0489_03

12

Figure 4. 28F016SA Memory Map (Byte-Wide Mode)

E 28F016SA

3.1 Extended Status Register Memory Map

x8 MODE A[20-0]

RESERVED

GSR

RESERVED

BSR 31

RESERVED
RESERVED

1F0006H
1F0005H
1F0004H
1F0003H

1F0002H
1F0001H
1F0000H

.
.
.

010002H

RESERVED

000006H

RESERVED

GSR

RESERVED

BSR 0
RESERVED
RESERVED

000005H
000004H

000003H
000002H

000001H
000000H

0489_04

x16 MODE A[20-1]

RESERVED

GSR

RESERVED

BSR 31

RESERVED

RESERVED

F8003H

F8002H

F8001H

F8000H

.
.
.

08001H

RESERVED

00003H

RESERVED

GSR

RESERVED

BSR 0

RESERVED
RESERVED

00002H

00001H

00000H

0489_05

Figure 5. Extended Status Register Memory

Map (Byte-Wide Mode)

Figure 6. Extended Status Register Memory

Map (Word-Wide Mode)

13

28F016SA E

4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS

4.1 Bus Operations for Word-Wide Mode (BYTE# = V

Mode Notes RP# CE1#CE0# OE# WE# A

Read 1,2,7 V
Output Disable 1,6,7 V
Standby 1,6,7 V

Deep Power-Down 1,3 V
Manufacturer ID 4 V
Device ID 4 V
Write 1,5,6 V

V

IH

V

IH

V

IH

V
V

IL

V

IH

V

IH

V

IH

V

IL

V

IL

V

IL

V

IH

V

IH

V

IL
IL
IH

IL
IH

IL

V

IH

X X X High Z X

XXXXXHigh Z V

V

IL

V

IL

V

IL

V

IL
IL
IL

IL

V

IL

V

IH

)

IH

DQ

1

V

IH

V

IH

V

IH

V

IH

V

XD
X High Z X

V

IL

V

IH

XDINX

IL

OUT

0089H V
66A0H V

0–15

RY/BY#

X

OH
OH
OH

4.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL)

Mode Notes RP# CE1#CE0# OE# WE# A

Read 1,2,7 V
Output Disable 1,6,7 V
Standby 1,6,7 V

Deep Power-Down 1,3 V
Manufacturer ID 4 V
Device ID 4 V
Write 1,5,6 V

NOTES:

1. X can be V

2. RY/BY# output is open drain. When the WSM is ready, block erase is suspended or the device is in deep power-down
mode. RY/BY# will be at V
operation is in progress.

3. RP# at GND ± 0.2V ensures the lowest deep power-down current.

4. A

and A1 at VIL provide manufacturer ID codes in x8 and x16 modes, respectively. A0 and A1 at VIH provide device ID

0

codes in x8 and x16 modes, respectively. All other addresses are set to zero.

5. Commands for different block erase operations, data program operations or lock-block operations can only be successfully
completed when V

6. While the WSM is running, RY/BY# in level-mode (default) stays at V
V

OH

7. RY/BY# may be at V
data program operation.

or VIL for address or control pins except for RY/BY#, which is either VOL or VOH.

IH

if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM

OH

= V

.

PP

PPH

when the WSM is not busy or in erase suspend mode.

while the WSM is busy performing various operations; for example, a Status Register read during a

OL

V

IH

V

IH

V

IH

V
V

IL

V

IH

V

IH

V

IH

V

IL

V

IL

V

IL

V

IH

V

IH

V

IL

V

IL

IH

IL

IH

V

IL
IH

IH

V

IH

X X X High Z X

XXXXXHigh Z V

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

OL

V

IL
IL
IH

until all operations are complete. RY/BY# goes to

IH

V

IH

V

IL

DQ

0

XD

0–7

OUT

RY/BY#

X High Z X

V
V

IL

IH

89H V
A0H V

XDINX

X

OH
OH
OH

14

E 28F016SA

4.3 28F008SA–Compatible Mode Command Bus Definitions

First Bus Cycle Second Bus Cycle

Command Notes Oper Addr Data

Read Array Write X xxFFH Read AA AD
Intelligent Identifier 1 Write X xx90H Read IA ID
Read Compatible Status Register 2 Write X xx70H Read X CSRD
Clear Status Register 3 Write X xx50H
Word/Byte Program Write X xx40H Write PA PD
Alternate Word/Byte Program Write X xx10H Write PA PD
Block Erase/Confirm Write X xx20H Write BA xxD0H
Erase Suspend/Resume Write X xxB0H Write X xxD0H

ADDRESS DATA

A = Array Address AD = Array Data
BA = Block Address CSRD = CSR Data
IA = Identifier Address ID = Identifier Data
PA = Program Address PD = Program Data

X = Don’t Care

NOTES:

1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes.

2. The CSR is automatically available after device enters data program, block erase, or suspend operations.

3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits.

4. The upper byte of the data bus (DQ

) during command writes is a “Don’t Care” in x16 operation of the device.

8–15

(4)

Oper Addr Data

See Status Register definitions.

15

28F016SA E

4.4 28F016SA–Performance Enhancement Command Bus Definitions

First Bus Cycle Second Bus Cycle Third Bus Cycle

Command Mode Notes Oper Addr Data

Read Extended
Status Register

Page Buffer Swap 7 Write X xx72H
Read Page Buffer Write X xx75H Read PBA PD
Single Load to Page

Buffer
Sequential Load to

Page Buffer

Page Buffer Write to
Flash

Two-Byte Program x8 3 Write X xxFBH Write A0WD(L,H) Write PA WD(H,L)
Lock Block/Confirm Write X xx77H Write BA xxD0H
Upload Status

Bits/Confirm
Upload Device

Information
Erase All Unlocked

Blocks/Confirm
RY/BY# Enable to

Level-Mode
RY/BY# Pulse-On-

Write
RY/BY# Pulse-On-

Erase
RY/BY# Disable 8 Write X xx96H Write X xx04H
Sleep 11 Write X xxF0H
Abort Write X xx80H

x8 4,6,10 Write X xxE0H Write X BCL Write X BCH

x16 4,5,6,10 Write X xxE0H Write X WCL Write X WCH

x8 3,4,9,10 Write X xx0CH Write A0BC(L,H) Write PA BC(H,L)

x16 4,5,10 Write X xx0CH Write X WCL Write PA WCH

1 Write X xx71H Read RA GSRD

Write X xx74H Write PBA PD

2 Write X xx97H Write X xxD0H

Write X xx99H Write X xxD0H

Write X xxA7H Write X xxD0H

8 Write X xx96H Write X xx01H

8 Write X xx96H Write X xx02H

8 Write X xx96H Write X xx03H

(12)

Oper Addr Data

BSRD

(12)

Oper Addr Data

ADDRESS DATA

BA = Block Address AD = Array Data WC (L,H) = Word Count (Low, High)
PBA = Page Buffer Address PD = Page Buffer Data BC (L,H) = Byte Count (Low, High)
RA = Extended Register Address BSRD = BSR Data WD (L,H) = Write Data (Low, High)
PA = Program Address GSRD = GSR Data

X = Don’t Care

16

E 28F016SA

NOTES:

1. RA can be the GSR address or any BSR address. See Figures 5 and 6 for Extended Status Register Memory Maps.

2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.

3. A

is automatically complemented to load the second byte of data. BYTE# must be at VIL.

0

The A

value determines which WD/BC is supplied first: A

4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size and to avoid writing the

5. In x16 mode, only the lower byte DQ

6. PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.

7. This command allows the user to swap between available Page Buffers (0 or 1).

8. These commands reconfigure the RY/BY# output to one of two pulse-modes or enable and disable the RY/BY# function.

9. Program address, PA, is the destination address in the flash array which must match the source address in the Page

10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1.

11. To ensure that the 28F016SA’s power consumption during sleep mode reaches the deep power-down current level, the

12. The upper byte of the data bus (DQ

0

Page Buffer contents into more than one 256-byte segment within an array block. They are simply shown for future Page
Buffer expandability.

is used for WCL and WCH. The upper byte DQ

0–7

Buffer. Refer to the

system also needs to de-select the chip by taking either or both CE

16-Mbit Flash Product Family User’s Manual

) during command writes is a “Don’t Care” in x16 operation of the device.

8–15

= 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.

0

is a don’t care.

8–15

.

# or CE1# high.

0

17