Intel Corporation GT28F800F3T95, GT28F800F3T120, GT28F160F3T120, GT28F160F3B95, GT28F160F3B120 Datasheet
...
E
PRODUCT PREVIEW
May 1998 Order Number: 290644-001
n
High Performance
54 MHz Effective Zero Wait-State
Performance
Synchronous Burst-Mode Reads
Asynchronous Page-Mode Reads
n
SmartVoltage Technology
2.7 V−3.6 V Read and Write
Operations for Low Power Designs
12 V VPP Fast Factory Programming
n
Flexible I/O Voltage
1.65 V I/O Reduces Overall System
Power Consumption
5 V-Safe I/O Enables Interfacing to
5 V Devices
n
Enhanced Data Protection
Absolute Write Protection with
V
PP
= GND
Block Locking
Block Erase/Program Lockout
during Power Transitions
n
Density Upgrade Path
8- and 16-Mbit
n
Manufactured on ETOX™ V Flash
Technology
n
Supports Code Plus Data Storage
Optimized for Flash Data Integrator
(FDI) Software
Fast Program Suspend Capability
Fast Erase Suspend Capability
n
Flexible Blocking Architecture
Eight 4-Kword Blocks for Data
32-Kword Main Blocks for Code
Top or Bottom Configurations
Available
n
Extended Cycling Capability
Minimum 10,000 Block Erase Cycles
Guaranteed
n
Low Power Consumption
Automatic Power Savings Mode
Decreases Power Consumption
n
Automated Program and Block Erase
Algorithms
Command User Interface for
Automation
Status Register for System
Feedback
n
Industry-Standard Packaging
56-Lead SSOP
µBGA* CSP
Intel’s Fast Boot Bloc k memory famil y renders high perf ormance as ynchronous page-m ode and sync hronous
burst reads making it an ideal memory solution for burs t CPUs. Combining high read performance wit h the
intrinsic non-volatility of flas h memory, this flash memory f amily eliminates the traditional redundant memory
paradigm of shadowing code from a slow nonvolatile storage source to a faster execution memory for
improved system performance. Therefore, it reduces the total memory requirement which helps increase
reliability and reduce overall system power consumption and cost.
This family of product s is manufac tured on Intel’ s 0.4 µm ETOX ™ V process technology . They are available
in industry-standard packages: the µBGA* CSP, ideal for board-constrained applications, and the rugged
56-lead SSOP.
FAST BOOT BLOCK
FLASH MEMORY FAMILY
8 AND 16 MBIT
28F800F3, 28F160F3
Includes Extended and Automotive Temperature Specifications
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provi ded in Intel ’s Terms and Condi tions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F800F3, 28F160F3 may contain design defects or errors known as errata which may cause the product to devi ate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel’s Website at http://www.intel.com
COPYRIGHT © INTEL CORPORATION, 1998 CG-041493
*Third-party brands and names are the property of their respective owners
E FAST BOOT BLOCK DATASHEET
3
PRODUCT PREVIEW
CONTENTS
PAGE PAGE
1.0 INTRODUCTION .............................................5
1.2 Product Overview.........................................5
2.0 PRODUCT DESCRIPTION..............................6
2.1 Pinouts.........................................................6
2.2 Pin Description.............................................6
2.3 Memory Blocking Organization.....................9
2.3.1 Parameter Blocks..................................9
2.3.2 Main Blocks...........................................9
3.0 PRINCIPLES OF OPERATION .....................12
3.1 Bus Operations ..........................................12
3.1.1 Read....................................................12
3.1.2 Output Disable.....................................12
3.1.3 Standby...............................................12
3.1.4 Write....................................................12
3.1.5 Reset...................................................13
4.0 COMMAND DEFINITIONS............................13
4.1 Read Array Command................................15
4.2 Read Identifier Codes Command...............15
4.3 Read Status Register Command................15
4.4 Clear Status Register Command................15
4.5 Block Erase Command ..............................15
4.6 Program Command....................................17
4.7 Block Erase Suspend/Resume Command .17
4.8 Program Suspend/Resume Command.......17
4.9 Set Read Configuration Command.............19
4.9.1 Read Configuration..............................19
4.9.2 Frequency Configuration .....................20
4.9.3 Data Output Configuration...................20
4.9.4 WAIT# Configuration...........................20
4.9.5 Burst Sequence...................................20
4.9.6 Clock Configuration.............................20
4.9.7 Burst Length........................................20
5.0 DATA PROTECTION.....................................26
5.1 V
PP
= VIL for Complete Protection..............26
5.2 WP# = V
IL
for Block Locking ......................26
5.3 WP# = V
IH
for Block Unlocking...................26
6.0 V
PP
VOLTAGES............................................26
7.0 POWER CONSUMPTION..............................26
7.1 Active Power..............................................26
7.2 Automatic Power Savings ..........................26
7.3 Standby Power...........................................27
7.4 Power-Up/Down Operation.........................27
7.4.1 RST# Connection................................27
7.4.2 V
CC
, VPP and RST# Transitions...........27
7.5 Power Supply Decoupling ..........................27
7.5.1 V
PP
Trace on Printed Circuit Boards....27
8.0 ELECTRICAL SPECIFICATIONS .................28
8.1 Absolute Maximum Ratings........................28
8.2 Extended Temperature Operating
Conditions.................................................28
8.3 Capacitance...............................................29
8.4 DC Characteristics—Extended
Temperature..............................................30
8.5 AC Characteristics—Read-Only
Operations—Extended Temperature.........32
8.6 AC Characteristics—Write Operations—
Extended Temperature..............................38
8.7 AC Characteristics—Reset Operation—
Extended Temperature..............................40
8.8 Extended Temperature Block Erase and
Program Performance...............................41
8.9 Automotive Temperature Operating
Conditions.................................................41
FAST BOOT BLOCK DATASHEET E
4
PRODUCT PREVIEW
8.10 Capacitance.............................................42
8.11 DC Characteristics—Automotive
Temperature..............................................43
8.12 AC Characteristics—Read-Only
Operations—Automotive Temperature......44
8.13 Automotive Temperature Frequency
Configuration Settings...............................45
8.14 Automotive Temperature Block Erase and
Program Performance...............................45
9.0 ORDERING INFORMATION..........................46
10.0 ADDITIONAL INFORMATION.....................47
REVISION HISTORY
Date of
Revision
Version Description
05/12/98 -001 Original version
E FAST BOOT BLOCK DATASHEET
5
PRODUCT PREVIEW
1.0 INTRODUCTION
This datasheet contains 8- and 16-Mbit Fast Boot
Block memory informati on. Section 1.0 provides a
flash memory overview. Sections 2.0 through 8.0
describe the memory functionality and electrical
specifications for extended and automotive
temperature product offerings.
1.2 Product Overview
The Fast Boot Block flas h memory family provides
density upgrades with pinout compatibility for 8- and
16-Mbit densities. This family of products are high
performance, low voltage memories with a 16-bit
data bus and individually erasable blocks. These
blocks are optimally sized for code and data
storage. Eight 4-Kword parameter blocks are
positioned at either the top (denot ed by -T s uffix ) or
bottom (denoted by -B suffix) of the addres s map.
The rest of the device is grouped into
32-Kword main blocks. The upper two (or lower
two) parameter and all main blocks can be locked
for complete code protection.
The device’s optimized architecture and interface
dramatically increases read performance beyond
previously attainable levels. It supports
asynchronous page-mode and synchronous burst
reads from main blocks (parameter blocks support
single asynchronous and synchronous reads).
Upon initial power-up or return from reset, the
device defaults to a page-mode read conf iguration.
Page-mode read configuration is ideal for non-c lock
memory systems and is compatible with pagemode ROM. Synchronous burst reads are enabl ed
by writing to the read configuration register. In
synchronous burst mode, t he CLK input increm ents
an internal burst address generator, synchronizes
the flash memory with t he host CPU, and outputs
data on every rising (or falling) CLK edge up to
54 MHz (25 MHz for automotive temperature). An
output signal, WAIT#, is als o provided to eas e CPU
to flash memory communication and
synchronization during continuous burst operations.
In addition to the enhanced architecture and
interface, this family of products incorporates
SmartVoltage technology whi ch enables fast f actory
programming and low power designs. Specifically
designed for low voltage systems, Fast Boot Block
flash memory components support read operations
at 2.7 V (3.3 V for automoti ve temperature) V
CC
and
block erase and program operations at 2.7 V
(3.3 V for automotive temperature) and 12 V V
PP
.
The 12 V V
PP
option renders the fastest program
performance to increase factory programming
throughput. With the 2.7 V (3.3 V for automotive
temperature) V
PP
option, VCC and VPP can be tied
together for a simple, low power design. In addition
to the voltage flexibility, the dedicat ed V
PP
pin gives
complete data protection when V
PP
≤ V
PPLK
.
The flexible input/output (I/O) voltage capability
helps reduce system power consumption and
simplify interfacing to sub 2.7 V and 5 V CPUs.
Powered by V
CCQ
pins, the I/O buffers c an operate
at a lower voltage than the flash memory core. Wi th
V
CCQ
voltage at 1.65 V, the I/Os swing between
GND and 1.65 V, reducing I/O power cons umption
by 65% over standard 3 V flash memory
components. The low voltage and 5 V-safe feature
also helps ease CPU interfacing by adapting t o the
CPU’s bus voltage.
The device’s Command User Interface (CUI ) serv es
as the interface between t he system processor and
internal flash memory operation. A v alid command
sequence written to the CUI initiates device
automation. This automation is controlled by an
internal Write State Machine (WSM) which
automatically executes the algorithms and timings
necessary for block eras e and program operations.
The status register provides WSM feedback by
signifying block erase or program completion and
status.
Block erase and program automati on allows erase
and program operations to be executed using an
industry-standard two-write comm and sequence. A
block erase operation erases one bloc k at a time,
and data is programmed in word inc rements. Erase
suspend allows system software to suspend an
ongoing block erase operation in order to read from
or program data to any other block. Program
suspend allows system software to suspend an
ongoing program operation in order to read from
any other location.
Fast Boot Block flas h memory devi ces off er two low
power savings features: A utomatic Power Savings
(APS) and standby mode. The device automatically
enters APS mode following the completion of a read
cycle. Standby mode is initiated when the system
deselects the device by driving CE# inactive or
RST# active. RST# also res ets the device to read
array, provides write protection, and clears the
status register. Combined, these two features
significantly reduce power consumption.
FAST BOOT BLOCK DATASHEET E
6
PRODUCT PREVIEW
2.0 PRODUCT DESCRIPTION
This section describes the pinout and block
architecture of the device family.
2.1 Pinouts
Intel’s Fast Boot Block flash memory family
provides upgrade paths in each pack age pinout up
to the 16-Mbit density. The family is available in
µBGA CSP and 56-lead SSOP pac kages. Pinouts
for the 8- and 16-Mbit components are illus trated in
Figures 1 and 2.
2.2 Pin Description
The pin description table describes pin usage.
123456789
A
B
C
D
E
F
10
A
14
A15A
12
A
11
A
8
GND
A
20
WE#
CLK V
CC
A
19
V
PP
A17A
5
A
4
A13A
10
A
21
A
18A7
A
6
A
1
A
2
A
3
A
9
WP#RST#
ADV#
V
CCQ
DQ
7
DQ
12
DQ10DQ9DQ0CE#DQ
13
DQ
11
DQ
4
A16DQ15DQ
6
DQ2DQ1OE#
WAIT# GND DQ14GND
V
CCQ
DQ8GND
A
0
DQ
5
DQ
3
V
CC
16M
32M
64M
NOTES:
1. Shaded connections indicate upgrade address connections. Lower density devices will not have upper address solder
balls. Routing is not recommended in this area.
2. A20 and A21 are the upgrade address for potential 32-Mbit and 64-Mbit devices (currently not on road map).
3. Reference the
Micro Ball Grid Array Package Mechanical Specification and Media Information
on Intel’s World Wide Web
home page for detailed package specifications.
Figure 1. 56-Ball µBGA* Package Pinout (Top View, Ball Down)
E FAST BOOT BLOCK DATASHEET
7
PRODUCT PREVIEW
16-Mbit
WE# WE#
RST# RST#
V
PP
V
PP
WP# WP#
NC A
19
A
1
A
1
A
2
A
2
A
3
A
3
A
4
A
4
A
5
A
5
A
6
A
6
A
7
A
7
A
17
A
17
A
18
A
18
DQ
9
DQ
9
DQ
1
DQ
1
DQ
8
DQ
8
DQ
0
DQ
0
OE# OE#
GND GND
CE# CE#
A
0
A
0
NC NC
V
CCQ
V
CCQ
DQ
2
DQ
2
DQ
10
DQ
10
DQ
3
DQ
3
DQ
11
DQ
11
V
CC
V
CC
CLKCLK
ADV#ADV#
GNDGND
NCNC
A
15
A
15
A
14
A
14
A
13
A
13
A
12
A
12
A
11
A
11
A
10
A
10
A
9
A
9
A
8
A
8
NCNC
GNDGND
DQ
6
DQ
6
DQ
14
DQ
14
DQ
7
DQ
7
DQ
15
DQ
15
GNDGND
V
CCQ
V
CCQ
A
16
A
16
WAIT#WAIT#
DQ
13
DQ
13
DQ
5
DQ
5
DQ
12
DQ
12
DQ
4
DQ
4
V
CC
V
CC
56-Lead SSOP
16 mm x 23.7 mm
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
8-Mbit 8-Mbit 16-Mbit
Figure 2. SSOP Pinout
FAST BOOT BLOCK DATASHEET E
8
PRODUCT PREVIEW
Table 1. Pin Descriptions
Sym Type Name and Function
A0–A
19
INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during read and write cycles.
8-Mbit: A
0–18
, 16-Mbit: A
0–19
DQ0–
DQ
15
INPUT/
OUTPUT
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles, outputs
data during memory array, status register (DQ
0
–DQ7), and identifier code read
cycles. Data pins float to high-impedance when the chip is deselected or outputs
are disabled. Data is internally latched during a write cycle.
CLK INPUT CLOCK: Synchronizes the flash memory to the system operating frequency during
synchronous burst-mode read operations. When configured for synchronous burstmode reads, address is latched on the first rising (or falling, depending upon the
read configuration register setting) CLK edge when ADV# is active or upon a rising
ADV# edge, whichever occurs first. CLK is ignored during asynchronous pagemode read and write operations.
ADV# INPUT ADDRESS VALID: Indicates that a valid address is present on the address inputs.
Addresses are latched on the rising edge of ADV# during read and write
operations. ADV# may be tied active during asynchronous read and write
operations.
CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE#-high deselects the device and reduces power consumption
to standby levels.
RST# INPUT RESET: When driven low, RST# inhibits write operations which provides data
protection during power transitions, and it resets internal automation. RST#-high
enables normal operation. Exit from reset sets the device to asynchronous read
array mode.
OE# INPUT OUTPUT ENABLE: Gates data outputs during a read cycle.
WE# INPUT WRITE ENABLE: Controls writes to the CUI and array. Addresses and data are
latched on the rising edge of the WE# pulse.
WP# INPUT WRITE PROTECTION: Provides a method for locking and unlocking all main
blocks and two parameter blocks.
When WP# is at logic low, lockable blocks are locked. If a program or erase
operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5
[block erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked and can be
programmed or erased.
WAIT# OUTPUT WAIT: Provides data valid feedback when configured for synchronous burst-mode
and the burst length is set to continuous. This signal is gated by OE# and CE# and
is internally pull-up to V
CCQ
via a resistor. WAIT# from several components can be
tied together to form one system WAIT# signal.
E FAST BOOT BLOCK DATASHEET
9
PRODUCT PREVIEW
Table 1. Pin Descriptions
Sym Type Name and Function
V
PP
SUPPLY BLOCK ERASE AND PROGRAM POWER SUPPLY (2.7 V–3.6 V,
11.4 V–12.6 V): For erasing array blocks or programming data, a valid voltage
must be applied to this pin. With V
PP
≤ V
PPL
K
, memory contents cannot be altered.
Block erase and program with an invalid V
PP
voltage should not be attempted.
Applying 11.4 V–12.6 V to V
PP
can only be done for a maximum of 1000 cycles on
main blocks and 2500 cycles on the parameter blocks.
VPP
may be connected to
12 V for a total of 80 hours maximum (see Section 6.0 for details).
V
CC
SUPPLY DEVICE POWER SUPPLY (2.7 V–3.6 V): With VCC ≤ V
LKO
, all write attempts to
the flash memory are inhibited. Device operations at invalid V
CC
voltages should
not be attempted.
V
CCQ
SUPPLY OUTPUT POWER SUPPLY (1.65 V–2.5 V, 2.7 V–3.6 V): Enables all outputs to be
driven to 1.65 V to 2.5 V or 2.7 V to 3.6 V. When V
CCQ
equals 1.65 V–2.5 V, V
CC
voltage must not exceed 3.3 V and should be regulated to 2.7 V–2.85 V to achieve
lowest power operation (see
DC Characteristics
for detailed information).
This input may be tied directly to V
CC
.
GND SUPPLY GROUND: Do not float any ground pins.
NC NO CONNECT: Lead is not internally connected; it may be driven or floated.
2.3 Memory Blocking Organization
The Fast Boot Block flash memory family is an
asymmetrically-blocked architecture that enables
system integration of code and data within a single
flash device. For the address locations of each
block, see the memory m aps in Figure 3 (top boot
blocking) and Figure 4 (bottom boot blocking).
2.3.1 PARAMETER BLOCKS
The Fast Boot Block flash memory architecture
includes parameter blocks to facilitate storage of
frequently updated small parameters that would
normally be stored in an EEPROM. By using
software techniques, the word-rewrite functionality
of EEPROMs can be emulated. Each 8- and
16-Mbit device contains eight 4-Kwords
(4,096-words) parameter blocks.
2.3.2 MAIN BLOCKS
After the parameter blocks, the remainder of the
array is divided into equal si ze m ain blocks for code
and/or data storage. The 8-Mbit device contains
fifteen 32-Kword (32,768-word) main blocks, and
the 16-Mbit device contains thirty-one 32-Kword
(32,768-word) main blocks.
FAST BOOT BLOCK DATASHEET E
10
PRODUCT PREVIEW
32-KWord
32-KWord
32-KWord
Address Range
78000h - 78FFFh
70000h - 77FFFh
68000h - 6FFFFh
60000h - 67FFFh
58000h - 5FFFFh
50000h - 57FFFh
48000h - 4FFFFh
40000h - 47FFFh
38000h - 3FFFFh
30000h - 37FFFh
28000h - 2FFFFh
20000h - 27FFFh
18000h - 1FFFFh
10000h - 17FFFh
08000h - 0FFFFh
00000h - 07FFFh
8-Mbit
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
79000h - 79FFFh
7A000h - 7AFFFh
7B000h - 7BFFFh
7C000h - 7CFFFh
7D000h - 7DFFFh
7E000h - 7EFFFh
7F000h - 7FFFFh
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
32-KWord
32-KWord
32-KWord
Address Range
F8000h - F8FFFh
F0000h - F7FFFh
E8000h - EFFFFh
E0000h - E7FFFh
D8000h - DFFFFh
D0000h - D7FFFh
C8000h - CFFFFh
C0000h - C7FFFh
B8000h - BFFFFh
B0000h - B7FFFh
A8000h - AFFFFh
A0000h - A7FFFh
98000h - 9FFFFh
90000h - 97FFFh
88000h - 8FFFFh
80000h - 87FFFh
16-Mbit
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
Block 38
Block 37
Block 36
Block 35
Block 34
Block 33
Block 32
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
F9000h - F9FFFh
FA000h - FAFFFh
FB000h - FBFFFh
FC000h - FCFFFh
FD000h - FDFFFh
FE000h - FEFFFh
FF000h - FFFFFh
32-KWord
32-KWord 78000h - 7FFFFh
70000h - 77FFFh
68000h - 6FFFFh
60000h - 67FFFh
58000h - 5FFFFh
50000h - 57FFFh
48000h - 4FFFFh
40000h - 47FFFh
38000h - 3FFFFh
30000h - 37FFFh
28000h - 2FFFFh
20000h - 27FFFh
18000h - 1FFFFh
10000h - 17FFFh
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
08000h - 0FFFFh
00000h - 07FFFh
32-KWord
32-KWordBlock 1
Block 0
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
Figure 3. 8- and 16-Mbit Top Boot Memory Map
E FAST BOOT BLOCK DATASHEET
11
PRODUCT PREVIEW
Address Range
16-Mbit
32-KWord
32-KWord
32-KWord F8000h - FFFFFh
F0000h - F7FFFh
E8000h - EFFFFh
E0000h - E7FFFh
D8000h - DFFFFh
D0000h - D7FFFh
C8000h - CFFFFh
C0000h - C7FFFh
B8000h - BFFFFh
B0000h - B7FFFh
A8000h - AFFFFh
A0000h - A7FFFh
98000h - 9FFFFh
90000h - 97FFFh
88000h - 8FFFFh
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
Block 38
Block 37
Block 36
Block 35
Block 34
Block 33
Block 32
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
32-KWord
32-KWord 80000h - 87FFFh
78000h - 7FFFFh
70000h - 77FFFh
68000h - 6FFFFh
60000h - 67FFFh
58000h - 5FFFFh
50000h - 57FFFh
48000h - 4FFFFh
40000h - 47FFFh
38000h - 3FFFFh
30000h - 37FFFh
28000h - 2FFFFh
20000h - 27FFFh
18000h - 1FFFFh
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
Block 23
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
10000h - 17FFFh
32-KWordBlock 9
00000h - 00FFFh
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
01000h - 01FFFh
02000h - 02FFFh
03000h - 03FFFh
04000h - 04FFFh
05000h - 05FFFh
06000h - 06FFFh
07000h - 07FFFh
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
32-KWordBlock 8 08000h - 0FFFFh
32-KWord
32-KWord
32-KWord
Address Range
78000h - 7FFFFh
70000h - 77FFFh
68000h - 6FFFFh
60000h - 67FFFh
58000h - 5FFFFh
50000h - 57FFFh
48000h - 4FFFFh
40000h - 47FFFh
38000h - 3FFFFh
30000h - 37FFFh
28000h - 2FFFFh
20000h - 27FFFh
18000h - 1FFFFh
10000h - 17FFFh
08000h - 0FFFFh
8-Mbit
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
32-KWord
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0 00000h - 00FFFh
01000h - 01FFFh
02000h - 02FFFh
03000h - 03FFFh
04000h - 04FFFh
05000h - 05FFFh
06000h - 06FFFh
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
4-KWord
07000h - 07FFFh
Figure 4. 8- and 16-Mbit Bottom Boot Memory Map
FAST BOOT BLOCK DATASHEET E
12
PRODUCT PREVIEW
3.0 PRINCIPLES OF OPERATION
The Fast Boot Block flash memory components
include an on-chip WSM to manage block erase
and program. It allows for CMOS-level control
inputs, fixed power suppli es, and minim al proces sor
overhead with RAM-like interface timings.
3.1 Bus Operations
All bus cycles to and from flash memory conform to
standard microprocessor bus cycles.
3.1.1 READ
The flash memory has three read modes av ailable:
read array, identifier codes, and status register.
These modes are accessible independent of the
V
PP
voltage. The appropriate read command (Read
Array, Read Identifier Codes, or Read Status
Register) must be written to the CUI to enter the
requested read mode. Upon initial power-up or exit
from reset, the device defaults to read array mode.
When reading information from main blocks in read
array mode, the device supports two highperformance read configurations: asynchronous
page-mode and synchronous burst-mode.
Asynchronous page-mode is t he default state and
provides high data transfer rate for non-clocked
memory subsystems. In this state, data is internally
read and stored in a high-speed page buffer. A
1:0
addresses data in the page buffer. The page size i s
four words. The other read configuration,
synchronous burst-mode, is enabled by writing to
read configuration register. This register sets the
read configuration, burst order, frequency
configuration, and burst length. In synchronous
burst-mode, the device latches the initial address
then outputs a sequence of data wi th res pect to t he
input CLK and read configuration setting.
Read operations from the parameter blocks,
identifier codes and status register transpire as
single asynchronous or synchronous read cycles.
The read configuration register setting determines
whether or not read operations are asynchronous or
synchronous.
For all read operations, CE# mus t be driven act ive
to enable the devices, ADV# must be driven low to
open the internal address latch, and OE# must be
driven low to activate t he outputs. In async hronous
mode, the address is latc hed when ADV# is driven
high. In synchronous mode, the address is latched
by ADV# going high or ADV# low in conjunction
with a rising (falling) clock edge, whichever occurs
first. WE# must be at V
IH
. Figures 14 through 19
illustrate different read cycles.
3.1.2 OUTPUT DISABLE
With OE# at a logic-high level (V
IH
), the device
outputs are disabled. Output pins DQ
0
–DQ15 are
placed in a high-impedance state.
3.1.3 STANDBY
Deselecting the device by bringi ng CE# to a logichigh level (V
IH
) places the device in standby mode,
which substantially reduces device power
consumption. In standby, outputs are placed in a
high-impedance state independent of OE#. If
deselected during program or erase operat ion, the
device continues to c onsume active power unt il the
program or erase operation is complete.
3.1.4 WRITE
Commands are written to the CUI using standard
microprocessor write timings when ADV#, WE#,
and CE# are active and OE# inactive. The CUI
does not occupy an addressable m emory location.
The address is latched on the ris ing edge of ADV#,
WE#, or CE# (whichever occurs first) and data
needed to execute a command is latched on the
rising edge of WE# or CE# (whichever goes high
first). Write operations are asynchronous.
Therefore, CLK is ignored during write operations.
Figure 20 illustrates a write operation.
E FAST BOOT BLOCK DATASHEET
13
PRODUCT PREVIEW
3.1.5 RESET
The device enters a reset mode when RST# is
driven low. In reset mode, i nternal c irc uitry is t urned
off and outputs are placed in a high-impedance
state.
After return from reset, a time t
PHQV
is required until
outputs are valid, and a delay (t
PHWL
or t
PHEL
) is
required before a write sequence can be init iated.
After this wake-up interval, normal operation is
restored. The device defaults to read array mode,
the status register is set to 80H, and the read
configuration register defaults to asynchronous
page-mode reads.
If RP# is taken low during a block erase or program
operation, the operation will be aborted and the
memory contents at the aborted location are no
longer valid. See Figure 21 for detail ed information
regarding reset timings.
4.0 COMMAND DEFINITIONS
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.
Table 2. Bus Operations
Mode Notes RST# CE# ADV# OE# WE# Address V
PP
DQ
0–15
Reset V
IL
XXXXXXHigh Z
Standby V
IH
V
IH
XXXXXHigh Z
Output Disable V
IH
V
IL
XVIHV
IH
X X High Z
Read 1,2 V
IH
V
IL
V
IL
V
IL
V
IH
XXD
OUT
Read Identifier
Codes
V
IH
V
IL
V
IL
V
IL
V
IH
See
Table 4
X See
Table 4
Write 3,4 V
IH
V
IL
V
IL
V
IH
V
IL
XX D
IN
NOTES:
1. Refer to
DC Characteristics
. When VPP ≤ V
PPLK
, memory contents can be read, but not altered.
2. X can be V
IL
or VIH for control and address input pins and V
PPLK
or V
PPH1/2
for VPP. See
DC Characteristics
for V
PPLK
and
V
PPH1/2
voltages.
3. Command writes involving block erase or program are reliably executed when V
PP
= V
PPH1/2
and VCC = V
CC1/2
(see Section 8 for operating conditions at different temperatures).
4. Refer to Table 3 for valid D
IN
during a write operation.
FAST BOOT BLOCK DATASHEET E
14
PRODUCT PREVIEW
Table 3. Command Definitions
(1)
Bus Cycles First Bus Cycle Second Bus Cycle
Command Req’d. Notes Oper
(2)
Addr
(3)
Data
(4)
Oper
(2)
Addr
(3)
Data
(4)
Read Array/Reset 1 Write X FFH
Read Identifier Codes ≥ 2 5 Write X 90H Read IA ID
Read Status Register 2 Write X 70H Read X SRD
Clear Status Register 1 Write X 50H
Block Erase 2 6,7 Write X 20H Write BA D0H
Program 2 6,7,8 Write X 40H
or
10H
Write WA WD
Block Erase and Program
Suspend
1 6 Write X B0H
Block Erase and Program
Resume
1 6 Write X D0H
Set Read Configuration 2 Write X 60H Write RCD 03H
NOTES:
1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
2. Bus operations are defined in Table 2.
3. X = Any valid address within the device.
IA = Identifier Code Address.
BA = Address within the block being erased.
WA = Address of memory location to be written.
RCD = Data to be written to the read configuration register. This data is presented to the device on A
15-0
; set all other
address inputs to “0.”
4. SRD = Data read from status register. See Table 5 for a description of the status register bits.
WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID = Data read from identifier codes. See Table 4 for manufacturer and device codes.
RCD = Data to be written to read configuration register. See Table 6 for a description of the read configuration register bits.
5. Following the Read Identifier Codes command, read operations access manufacturer, device codes, and read
configuration register.
6. Following a block erase, program, and suspend operation, read operations access the status register.
7. To issue a block erase, program, or suspend operation to a lockable block, hold WP# at V
IH
.
8. Either 40H or 10H are recognized by the WSM as the program setup.
E FAST BOOT BLOCK DATASHEET
15
PRODUCT PREVIEW
4.1 Read Array Command
Upon initial device power-up or exit from reset, the
device defaults to read array mode. The read
configuration register defaults to asynchronous
page-mode. The Read Array command als o c auses
the device to enter read array mode. The device
remains enabled for reads until another c ommand
is written. Once the internal WSM has started a
block erase or program, the device will not
recognize the Read Array command until the WSM
completes its operation or unless the WSM is
suspended via an Erase or Program Suspend
command. The Read Array command functions
independently of the V
PP
voltage.
4.2 Read Identifier Codes
Command
The identifier code operation is initiat ed by writing
the Read Identifier Codes command. After writing
the command, read cycles retrieve the
manufacturer and device codes (see Table 4 for
identifier code values). Page-mode and burst reads
are not supported in this read mode. To t erminate
the operation, write another valid c omm and, li ke the
Read Array command. The Read Identifier Codes
command functions independently of the V
PP
voltage.
Table 4. Identifier Codes
Code
Address
(Hex)
Data
(Hex)
Manufacturer Code 00000 0089
Device Code 8 Mbit -T 00001 88F1
-B 00001 88F2
16 Mbit -T 00001 88F3
-B 00001 88F4
4.3 Read Status Register
Command
The status register can be read at any time by
writing the Read Status Register command to the
CUI. After writing this command, all subsequent
read operations output status register data until
another valid command is writ ten. Page-mode and
burst reads are not supported in this read mode.
The status register content i s updated and latched
on the rising edge of ADV# or rising (falling) CLK
edge when ADV# is low during synchronous burstmode or the falling edge of OE# or CE #, whichever
occurs first. The Read Status Register command
functions independently of the V
PP
voltage.
4.4 Clear Status Register
Command
Status register bits SR. 5, S R.4, S R.3, and SR. 1 are
set to “1”s by the WSM and can only be cleared by
issuing the Clear Status Regis ter command. These
bits indicate various error conditions. By allowing
system software to reset these bits, several
operations may be performed (such as cumul ati vely
erasing or writing several byt es in sequence). The
status register may be polled to determine if a
problem occurred during the sequence. The Clear
Status Register command functions independently
of the applied V
PP
voltage. After executing this
command, the device returns to read array mode.
4.5 Block Erase Command
Erase is executed one block at a time and init iated
by a two-cycle command. A block erase setup is
written first, followed by a block erase c onfirm. This
command sequence requires appropriate
sequencing and address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, eras e, and verify are handled
internally by the WSM. After the two-cycle block
erase sequence is written, the devic e automatically
outputs status register data when read (see
Figure 7,
Automated Block Erase Flowchart
). The
CPU can detect block erase completion by
analyzing status register bit SR.7.
When the block erase completes, check status
register bit SR.5 for an error fl ag (“1”). If an error i s
detected, check status register bits SR.4, SR.3, and
SR.1 to understand what caused t he failure. After
examining the status register, it should be c leared if
an error was detected before issuing a new
command. The device will remain in status regis ter
read mode until another command is written to the
CUI.
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