Datasheet DD28F032SA-80, DD28F032SA-70, DD28F032SA-100 Datasheet (Intel Corporation)

E

December 1996 Order Number: 290490-005

n

User-Selectable 3.3V or 5V V

CC

n

User-Configurable x8 or x16 Operation

n

70 ns Maximum Access Time

n

28.6 MB/sec Burst Write Transfer Rate

n

1 Million Typical Erase Cycles per Block

n

56-Lead, 1.2 x 14 x 20 mm Advanced
Dual Die TSOP Package Technology

n

64 Independently Lockable Blocks

n

Revolutionary Architecture



100% Backwards-Compatible with
Intel 28F016SA



Pipelined Command Execution



Program during Erase

n

2 mA Typical ICC in Static Mode

n

2 µA Typical Deep Power-Down

n

State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology

Intel’s DD28F032SA 32-Mbit Fl ashFile™ memory is a revoluti onary architec ture which enables the desi gn of
truly mobile, high performance, personal computing and communication products. With innovative
capabilities, low power operation and very high read/program performance, the DD28F032SA is also the ideal
choice for designing embedded mass storage flash memory systems.

The DD28F032SA is the result of hi ghly-advanced packagi ng innovation which encapsulates two 28F016SA
die in a single Dual Die Thin Small Outline Package (DDTSOP).

The DD28F032SA is the highest densi ty, highest performance nonvolatil e read/program solution for solid­state storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F016SA
16-Mbit FlashFile memory), very high-cycling, low-power 3.3V operation, very fast program and read
performance and selective block locking provi de a highly fl exi ble memory c omponent s uit able for hi gh-densit y
memory cards, Resident Flash Arrays and PCMCIA -ATA Fl ash Dri ves . The DD28F032S A’s dual read v oltage
enables the design of memory c ards which can be read/written in 3.3V and 5.0V systems interchangeably. Its
x8/x16 architecture al l ows the optimization of memory to processor interface. The flexible block locking option
enables bundling of executable application software in a Resident Flash Array or memory card. The
DD28F032SA will be manufactured on Intel’s 0.6 µm ETOX IV technology.

DD28F032SA

32-MBIT (2 MBIT X 16, 4 MBIT X 8)

FlashFile™ MEMORY

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provi ded in Intel ’s Terms and Condi tions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F016SA may contain design defects or errors known as errata. Current characterized errata are available upon request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

COPYRIGHT © INTEL CORPORATION, 1996 CG-041493

E DD28F032SA

3

CONTENTS

PAGE PAGE

1.0 PRODUCT OVERVIEW...................................5

2.0 DEVICE PINOUT.............................................6

2.1 Lead Descriptions........................................8

3.0 MODES OF OPERATION .............................10

4.0 MEMORY MAPS...........................................11

4.1 Extended Status Registers Memory Map... 12

5.0 BUS OPERATIONS, COMMANDS AND

STATUS REGISTER DEFINITIONS................ 13

5.1 Bus Operations for Word-Wide Mode

(BYTE# = V

IH

).............................................. 13

5.2 Bus Operations for Byte-Wide Mode

(BYTE# = V

IL

)..............................................13

5.3 28F008SA Compatible Mode Command

Bus Definitions.............................................14

5.4 28F016SA-Performance Enhancement

Command Bus Definitions............................15

5.5 Compatible Status Register .......................16

5.6 Global Status Register...............................17

5.7 Block Status Register ................................18

6.0 ELECTRICAL SPECIFICATIONS..................19

6.1 Absolute Maximum Ratings........................19

6.2 Capacitance...............................................20

6.3 Timing Nomenclature.................................21

6.4 DC Characteristics (V

CC

= 3.3V ± 0.3V).....24

6.5 DC Characteristics (V

CC

= 5.0V ± 0.5V)....26

6.6 AC Characteristics—Read Only

Operations ...................................................28

6.7 Power-Up and Reset Timings.....................32

6.8 AC Characteristics for WE#—Controlled

Command Write Operations.........................33

6.9 AC Characteristics for CE

X

#—Controlled

Write Operations..........................................37

6.10 AC Characteristics for Page Buffer Write

Operations ...................................................41

6.11 Erase and Word/Byte Program
Performance, Cycling Performance and

Suspend Latency .........................................44

7.0 DERATING CURVES....................................45

8.0 MECHANICAL SPECIFICATIONS................47

APPENDIX A: Device Nomenclature/

Ordering Information.....................................48

APPENDIX B: Additional Information...............49

DD28F032SA E

4

REVISION HISTORY

Number Description

-001 —Original Version

-002 —Never Published

-003 —Full Datasheet with Specifications
—CE

#, CE

# control 28F016SA No. 1

—CE

0

#, CE2# control 28F016SA No. 2

-004 —DC Characteristics (3.3V VCC): I

CCR

1

(TTL): BYTE# = VIL or V

IH

—Full Chip Erase Time (3.3V VCC) = 51.2 sec typ
—Full Chip Erase Time (5.0V V

CC

) = 38.4 sec typ

—Section 6.7: Added specifications t

PHEL3

, t

PHEL5

—TSOP dimension A1 = 0.05 mm (min)
—Revised Product Status to Preliminary
—t

WHGL

(3.3V) = 120 ns

—Minor cosmetic changes

-005 —Updated AC/DC parameters

E DD28F032SA

5

1.0 PRODUCT OVERVIEW

The DD28F032SA is a high-performance 32-Mbit
(33,554,432-bit) block erasable nonv ol atile random
access memory organiz ed as eit her 2 Mword x 16,
or 4 Mbyte x 8. The DD28F032SA is built using
two 28F016SA chips encapsulated in a single
56- lead TSOP Type I package. The DD28F032SA
includes sixty-f our 64-KB (65,536) blocks or sixty­four 32-KW (32,768) blocks.

The DD28F032SA architecture allows operations
to be performed on a single, 16-Mbit chip at a
time.

The implementation of a new architecture, with
many enhanced features, will improve the device
operating characteristics and results in greater
product reliability and ease of use.

Among the significant enhancements on the
DD28F032SA:

• 3.3V Low Power Capability

• Improved Program Performance

• Dedicated Block Program/Erase Protection

A 3/5# input pin reconfigures t he device internally
for optimized 3.3V or 5.0V read/program
operation.

The DD28F032SA will be available in a 56-lead,

1.2 mm thick, 14 mm x 20 mm Dual Die TSOP
Type I package. This form factor and pinout allow
for very high board layout densities. The
DD28F032SA is pinout and footprint compatible
with the 28F016SA.

Two Command User Interfaces (CUI) s erve as t he
system interface between the microprocessor or
microcontroller and the internal memory operation.

Internal algorithm automation allows word/byte
programs and block erase operations to be
executed using a two-write command s equence to
the CUI in the same way as the 28F016SA
16-Mbit FlashFile memory.

A super-set of commands has been added to the
basic 28F008SA (8-Mbit FlashFile memory)
command-set to achieve higher program
performance and provide additional capabilities.

These new commands and features include:

• Page Buffer Writes to Flash

• Command Queueing Capability

• Automatic Data Programs during Erase

• Software Locking of Memory Blocks

• Two-Byte Successive Programs in 8-bit

Systems

• Erase All Unlocked Blocks
These operations can only be performed on one

16-Mbit device at a time. If the WSM is busy
performing an operation, the system should not
attempt to select the other device.

Writing of memory data is performed in either byte

or word increments typically within 6 µs, a 33%
improvement over the 28F008SA. A block erase
operation erases one of the 64 blocks in typically

0.6 sec, independent of the ot her blocks, which is
a 65% improvement over the 28F008SA.

Each block can be written and eras ed a minimum
of 100,000 cycles. Systems can achieve typically
1 million block erase cycles by providing wear­leveling algorithms and gracef ul block retirement.
These techniques have already been employ ed in
many flash file systems. Additionally, wear leveling
of block erase cycles can be used to minimize the
program/erase performance differences across
blocks.

The DD28F032SA incorporates two Page Buff ers
of 256 bytes (128 words) on each 28F016SA to
allow page data programs. This feature can
improve a system program performance by up to

4.8 times over previous flash memory devices.
All operations are started by a sequence of

command writes to the device. Three Status
Registers (described in detai l later) and a RY/BY#
output pin provide information on the progress of
the requested operation.

The DD28F032SA allows queueing of the next
operation while the memory executes t he current
operation. This eliminates system overhead when
writing several bytes in a row to the array or
erasing several blocks at the same time. The
DD28F032SA can also perform program
operations to one block of memory while
performing erase of another block. However,
simultaneous program and/or erase operat ions are
not allowed on both 28F016SA devices. See
Modes of Operation, Section 3.0.

DD28F032SA E

6

The DD28F032SA provides user-select able block
locking to protect code or data such as device
drivers, PCMCIA card information, ROM­executable O/S or application code. Each block
has an associated nonvolatile lock-bit which
determines the lock status of the block. In
addition, the DD28F032SA has a master Write
Protect pin (WP#) which prevents any
modifications to memory blocks whose lock-bits
are set.

The DD28F032SA contains three ty pes of Status
Registers to accomplish various functions:

• A Compatible Status Register (CSR) which is
100% compatible with the 28F008S A FlashFile

memory’s Status Regist er. This register, when
used alone, provides a straightf orward upgrade
capability to the DD28F032SA from a
28F008SA-based design.

• A Global Status Register (GSR) which i nforms
the system of Command Queue status, Page
Buffer status, and overall Writ e State Machine
(WSM) status.

• 64 Block Status Registers (BSRs) which
provide block-specific status information such
as the block lock-bit status.

The GSR and BSR memory maps for byte-wide
and word-wide modes are shown in Figures 4
and 5.

The DD28F032SA incorporates an open drain
RY/BY# output pin. This feature al lows the user to
OR-tie many RY/BY# pins together in a multiple
memory configuration such as a Resident Flash
Array. Other configurations of the RY/BY # pin are
enabled via special CUI commands and are
described in detail in the

16-Mbit Flash Product

Family User’s Manual

.

The DD28F032SA also incorporates three chip­enable input pins, CE

0

#, CE1# and CE2#. The

active low combinat ion of CE

0

# and CE1# controls
the first 28F016SA. The ac tive low combinat ion of
CE

0

# and CE2# controls the second 28F016SA.

The BYTE# pin allows either x8 or x16
read/programs to the DD28F032SA. BYTE# at
logic low selects 8-bit mode with address A

0

selecting between low byte and high byte. On the
other hand, BYTE# at logic high enables 16-bit
operation with address A

1

becoming the lowest

order address and address A

0

is not used (don’t
care). A device block diagram is shown in Figure
1

.

The DD28F032SA is specified for a maximum
access time of 70 ns (t

ACC

) at 5.0V operation
(4.75V to 5.25V) over the commerc ial temperature
range (0°C to +70°C). A corres ponding maximum
access time of 150 ns at 3.3V (3.0V to 3.6V and
0°C to +70°C) is achieved for reduced power
consumption applications.

The DD28F032SA incorporates an Automatic
Power Saving (APS) feature which substantially
reduces the active current when the device is in
static mode of operation (addresses not
switching).

A deep power-down mode of operation is invoked
when the RP# (called PWD# on the 28F008SA)
pin is driven low. This mode provides additional
write protection by acting as a device reset pin
during power transitions. In t he deep power-down
state, the WSM is res et (any current operation wi ll
abort) and the CSR, GSR and BSR registers are
cleared.

A CMOS standby mode of operation is enabled
when either CE

0

#, or both CE1# and CE2#,
transition high and RP# stays high with all input
control pins at CMOS levels.

2.0 DEVICE PINOUT

The DD28F032SA Standard 56-Lead Dual Die
TSOP Type I pinout configuration is shown in
Figure 2.

E DD28F032SA

7

Output
Buffer

Output

Buffer

Input

Buffer

Input

Buffer

I/O Logic

ID

Register

CSR

Data

Comparator

Y

Decoder

X

Decoder

64-Kbyte

Block 0

64-Kbyte

Block 1

64-Kbyte

Block 30

64-Kbyte

Block 31

Program/Erase
Voltage Switc h

Address
Counter

Input

Buffer

Y Gating/Sensing

Output Multiplexer

GND

DQ

8-15

DQ

0-7

3/5#

BYTE#

CE0#
CE1#

OE#
WE#
WP#

RP#

V

CC

3/5#

RY/BY#

V

PP

A

0-20

Address

Queue

Latches

CUI

Data

Queue

Registers

Page

Buffers

WSM

ESRs

0490_01

Figure 1. Block Diagram of 16-Mbit Devices in DD28F032SA

Architectural Evolution Includes Page Buffers, Queue Registers and Extended Registers

DD28F032SA E

8

2.1 Lead Descriptions

Symbol Type Name and Function

A

0

INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when

device is in x8 mode. This address is latched in x8 data programs. Not
used in x16 mode (i.e., the A

input buffer is turned off when BYTE# is

high).

A1–A

15

INPUT WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block.

A

6-15

selects 1 of 1024 rows, and A

1-5

selects 16 of 512 columns. These

addresses are latched during data programs.

A16–A

20

INPUT BLOCK-SELECT ADDRESSES: Select 1 of 32 erase blocks in each of

the two 28F016SAs. These addresses are latched during data programs,
block erase and lock block operations.

DQ0–DQ7INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI write

cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is de-selected or the outputs are
disabled.

DQ8–DQ15INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 data program

operations. Outputs array, buffer or identifier data in the appropriate read
mode; not used for Status Register reads. Floated when the chip is de­selected or the outputs are disabled.

CE0#
CE

X

# =

CE

1

# or

CE

2

#

INPUT CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,

decoders and sense amplifiers. CE

0

#/CE1# enable/disable the first

28F016SA (16 Mbit No. 1) while CE

0

#/CE2# enable/disable the second

28F016SA (16 Mbit No. 2). CE

0

# active low enables chip operation while

CE

1

# or CE2# select between the first and second device, respectively

CE

1

# and CE2# must not be active low simultaneously. Reference Table

3.0.

RP# INPUT RESET/POWER-DOWN: RP# low places the device in a deep power-

down state. All circuits that burn static power, even those circuits enabled
in standby mode, are turned off. When returning from deep power-down,
a recovery time is required to allow these circuits to power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).

OE# INPUT OUTPUT ENABLE: Gates device data through the output buffers when

low. The outputs float to tri-state off when OE# is high.

NOTE:

CEx# overrides OE#, and OE# overrides WE#.

WE# INPUT WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue

Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.

RY/BY# OPEN DRAIN

OUTPUT

READY/BUSY: Indicates status of the internal WSM. When low, it
indicates that the WSM is busy performing an operation. RY/BY# high
indicates that the WSM is ready for new operations (or WSM has
completed all pending operations), or block erase is suspended, or the
device is in deep power-down mode. This output is always active (i.e., not
floated to tri-state off when OE# or CE

0

#/CE1#/CE2# are high), except if a
RY/BY#
Pin Disable command is issued.

E DD28F032SA

9

2.1 Lead Descriptions (Continued)

Symbol Type Name and Function

WP# INPUT WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile

lock-bit for each block. When WP# is low, those locked blocks as
reflected by the Block-Lock Status bits (BSR.6), are protected from
inadvertent data programs or block erases. When WP# is high, all blocks
can be written or erased regardless of the state of the lock-bits. The WP#
input buffer is disabled when RP# transitions low (deep power-down
mode).

BYTE# INPUT BYTE ENABLE: BYTE# low places device in x8 mode. All data is then

input or output on DQ

0-7

, and DQ

8-15

float. Address A

0

selects between
the high and low byte. BYTE# high places the device in x16 mode, and
turns off the A

0

input buffer. Address A1 then becomes the lowest order

address.

3/5# INPUT 3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V

operation. 3/5# low configures internal circuits for 5.0V operation.

NOTES:

Reading the array with 3/5# high in a 5.0V system could damage the
device.
There is a significant delay from 3/5# switching to valid data.

V

PP

SUPPLY ERASE/PROGRAM POWER SUPPLY: For erasing memory array blocks

or writing words/bytes/pages into the flash array.

V

CC

SUPPLY DEVICE POWER SUPPLY (3.3V ± 0.3V, 5.0V ± 0.5V, 5.0V ± 0.25V):

Do not leave any power pins floating.

GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY:

Do not leave any ground pins floating.

NC NO CONNECT:

Lead may be driven or left floating.

DD28F032SA E

10

28F016SV 28F016SA

1

2
3

4
5

6

7
8

9

10

11

12

13

14

15

16

17
18

19

20

21

22

23

24

25
26

27

28

29

30

31

32

33

34

56

55

53

54
52

51
50

49
48
47

46

45

44

43

42

41

40

39

38

37

36

35

DD28F032SA

56-LEAD TSOP PINOUT

14mm x 20mm

TOP VIEW

3/5#

NC

WP#
WE#
OE#
RY/BY#

GND

GND

DQ

7

DQ

14

DQ

6

DQ

13

DQ

5

DQ

12

DQ

4

DQ

11

DQ

3

DQ

10

BYTE#
NC
NC

DQ

2

DQ

9

DQ

1

DQ

8

DQ

0

A

0

DQ

15

V

CC

V

CC

NC

A

17

A

18

A

19

A

20

V

CC

A

15

A

14

A

13

A

12

CE #

0

V

PP

RP#

A

11

A

10

A

9

A

8

GND

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

16

A

17

A

18

A

19

A

20

V

CC

A

15

A

14

A

13

A

12

CE #

0

V

PP

RP#

A

11

A

10

A

9

A

8

GND

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

16

WP#

WE#

OE#

RY/BY#

GND

GND

DQ

7

DQ

14

DQ

6

DQ

13

DQ

5

DQ

12

DQ

11

DQ

3

DQ

10

BYTE#

NC

NC

DQ

2

DQ

9

DQ

1

DQ

8

DQ

0

A

0

DQ

15

V

CC

V

CC

28F016SV28F016SA

A

17

A

18

A

19

A

20

V

CC

A

15

A

14

A

13

A

12

CE #

0

V

PP

RP#

A

11

A

10

A

9

A

8

GND

A

7

A

6

A

5

A

4

A

3

A

2

A

1

CE #

1

A

16

CE #

2

CE #

1

3/5#

CE #

1

3/5#

CE #

1

WP#
WE#

OE#
RY/BY#

GND

GND

DQ

7

DQ

14

DQ

6

DQ

13

DQ

5

DQ

12

DQ

11

DQ

3

DQ

10

BYTE#

NC

NC

DQ

2

DQ

9

DQ

1

DQ

8

DQ

0

A

0

DQ

15

V

CC

V

CC

DQ

4

DQ

4

0490_02

Figure 2. Dual Die TSOP Pinout Configuration

3.0 MODES OF OPERATION

RP# CE0#CE

1

#CE

2

# 28F016SA

No. 1

28F016SA

No. 2

DD28F032S

A

Chip

0 X X X DPD DPD DPD
1 1 X X Standby Standby Standby
1 0 0 1 Standby Active Active
1 0 1 0 Active Standby Active
1 0 1 1 Standby Standby Standby
1 0 0 0 Illegal Condition

NOTES:

X = Don’t Care
DPD = Deep Power-Down
28F016SA No. 1 = First 16-Mbit Device
28F016SA No. 2 = Second 16-Mbit Device

E DD28F032SA

11

4.0 MEMORY MAPS

64-Kbyte Bloc k

1FFFFF

31

1F0000

1EFFFF

1E0000

1DFFFF

1D0000

1CFFFF

1C0000

1BFFFF

30
29
28
27

1B0000

1AFFFF

1A0000

19FFFF

190000

18FFFF

180000

17FFFF

26
25
24
23

170000

16FFFF

160000

15FFFF

150000

14FFFF

140000

13FFFF

22
21
20
19

130000

12FFFF

120000

11FFFF

110000

10FFFF

100000

0FFFFF

18
17
16
15

0F0000

0EFFFF

0E0000

0DFFFF

0D0000

0CFFFF

0C0000

0BFFFF

14
13
12
11

0B0000

0AFFFF

0A0000

09FFFF

090000

08FFFF

080000

07FFFF

10

9
8
7

070000

06FFFF

060000

05FFFF

050000

04FFFF

040000

03FFFF

6
5
4
3

030000

02FFFF

020000

01FFFF

010000

00FFFF

000000

2
1
0

64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
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64-Kbyt e Block
64-Kbyt e Block
64-Kbyte Bloc k
64-Kbyt e Block
64-Kbyte Bloc k
64-Kbyt e Block
64-Kbyte Bloc k
64-Kbyt e Block
64-Kbyte Bloc k
64-Kbyt e Block
64-Kbyte Bloc k
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64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
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64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k

64-Kbyte Bloc k

1FFFFF

63

1F0000

1EFFFF

1E0000

1DFFFF

1D0000

1CFFFF

1C0000

1BFFFF

62
61
60
59

1B0000

1AFFFF

1A0000

19FFFF

190000

18FFFF

180000

17FFFF

58
57
56
55

170000

16FFFF

160000

15FFFF

150000

14FFFF

140000

13FFFF

54
53
52
51

130000

12FFFF

120000

11FFFF

110000

10FFFF

100000

0FFFFF

50
49
48
47

0F0000

0EFFFF

0E0000

0DFFFF

0D0000

0CFFFF

0C0000

0BFFFF

46
45
44
43

0B0000

0AFFFF

0A0000

09FFFF

090000

08FFFF

080000

07FFFF

42
41
40
39

070000

06FFFF

060000

05FFFF

050000

04FFFF

040000

03FFFF

38
37
36
35

030000

02FFFF

020000

01FFFF

010000

00FFFF

000000

34
33
32

64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Block
64-Kbyte Block
64-Kbyte Bloc k
64-Kbyte Block
64-Kbyte Bloc k
64-Kbyte Block
64-Kbyte Bloc k
64-Kbyte Block
64-Kbyte Bloc k
64-Kbyte Block
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k
64-Kbyte Bloc k

28F016SA No. 1 28F016SA No. 2

0490_03

Figure 3. DD28F032SA Memory Map (Byte-Wide Mode)

DD28F032SA E

12

4.1 Extended Status Registers Memory Map for Either 28F016SA No. 1 or
28F016SA No. 2

x8 MODE A[20-0]

.
.
.

1F0004H
1F0003H

1F0002H

1F0000H

1F0001H

1F0005H

1F0006H

000004H
000003H
000002H

000000H

000001H

000006H
000005H

010002H

RESERVED

GSR

RESERVED

BSR 0
RESERVED
RESERVED

RESERVED

RESERVED

GSR

RESERVED

BSR 31

RESERVED
RESERVED

0490_04

Figure 4. Extended Status Register Memory

Map (Byte-Wide Mode)

x16 MODE A[20-1]

.
.
.

00002H

00000H

00001H

00003H

08001H

RESERVED

GSR

RESERVED

BSR 0

RESERVED

RESERVED

RESERVED

F8002H

F8000H

F8001H

F8003H

RESERVED

GSR

RESERVED

BSR 31

RESERVED

RESERVED

0490_05

Figure 5. Extended Status Register Memory

Map (Word-Wide Mode)

E DD28F032SA

13

5.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS

5.1 Bus Operations for Word-Wide Mode (BYTE# = V

IH

)

Mode Notes RP# CEX#

(8)

CE0# OE# WE# A

1

DQ

0–15

RY/BY#

Read 1,2,7 V

IH

V

IL

V

IL

V

IL

V

IH

XD

OUT

X

Output Disable 1,6,7 V

IH

V

IL

V

IL

V

IH

V

IH

X High Z X

Standby 1,6,7 V

IH

V
V
V

IH

V
V
V

IH

X X X High Z X

Deep Power-Down 1,3 V

IL

X XXXXHigh Z V

OH

Manufacturer ID 4 V

IH

V

IL

V

IL

V

IL

V

IH

V

IL

0089H V

OH

Device ID 4 V

IH

V

IL

V

IL

V

IL

V

IH

V

IH

66A0H V

OH

Write 1,5,6 V

IH

V

IL

V

IL

V

IH

V

IL

XDINX

5.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL)

Mode Notes RP# CEX#

(8)

CE0# OE# WE# A

0

DQ

0–7

RY/BY#

Read 1,2,7 V

IH

V

IL

V

IL

V

IL

V

IH

XD

OUT

X

Output Disable 1,6,7 V

IH

V

IL

V

IL

V

IH

V

IH

X High Z X

Standby 1,6,7 V

IH

V
V
V

IH

V
V
V

IH

X X X High Z X

Deep Power-Down 1,3 V

IL

X XXXXHigh Z V

OH

Manufacturer ID 4 V

IH

V

IL

V

IL

V

IL

V

IH

V

IL

89H V

OH

Device ID 4 V

IH

V

IL

V

IL

V

IL

V

IH

V

IH

A0H V

OH

Write 1,5,6 V

IH

V

IL

V

IL

V

IH

V

IL

XDINX

NOTES:

1. X can be V

IH

or V

IL

for address or control pins except for RY/BY#, which is either V

OL

or V

OH

.

2. RY/BY# output is open drain. When the WSM is ready, block erase is suspended or the device is in deep power-down
mode, RY/BY# will be at V

OH

if it is tied to V

CC

through a resistor. RY/BY# at VOH is independent of OE# while a WSM

operation is in progress.

3. RP# at GND ± 0.2V ensures the lowest deep power-down current.

4. A

0

and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively. A0 and A1 at VIH provide device ID

codes in x8 and x16 modes respectively. All other addresses are set to zero.

5. Commands for different block erase operations, data program operations or lock-block operations can only be successfully
completed when V

PP

= V

PPH.

6. While the WSM is running, RY/BY# in level-mode (default) stays at VOL until all operations are complete. RY/BY# goes to
V

OH

when the WSM is not busy or in erase suspend mode.

7. RY/BY# may be at V

OL

while the WSM is busy performing various operations; for example, a Status Register read during a

data program operation.

8. CE

X

# = CE1# or CE2#.

DD28F032SA E

14

5.3 28F008SA Compatible Mode Command Bus Definitions

First Bus Cycle Second Bus Cycle

Command Notes Oper Addr Data Oper Addr Data

Read Array Write X xxFFH Read AA AD
Intelligent Identifier 1 Write X xx90H Read IA ID
Read Compatible Status Register 2 Write X xx70H Read X CSRD
Clear Status Register 3 Write X xx50H
Word/Byte Program Write X xx40H Write PA PD
Alternate Word/Byte Program Write X xx10H Write PA PD
Block Erase/Confirm Write X xx20H Write BA xxD0H
Erase Suspend/Resume Write X xxB0H Write X xxD0H

ADDRESS DATA

A = Array Address

AD = Array Data

BA = Block Address CSRD = CSR Data
IA = Identifier Address ID = Identifier Data
PA = Program Address PD = Program Data

X = Don’t Care

NOTES:

1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes.

2. The CSR is automatically available after device enters data program, block erase, or suspend operations.

3. Clears CSR.3, CSR.4 and CSR.4. Also clears GSR.4 and all BSR.4 and BSR.2 bits.

4. The upper byte of the data bus (DQ

8–15

) during command writes is a “Don’t Care” in x16 operation of the device.

See Status Register definitions.

E DD28F032SA

15

5.4 28F016SA-Performance Enhancement Command Bus Definitions

First Bus Cycle Second Bus Cycle Third Bus Cycle

Command Mode Notes Oper Addr Data

(12)

Oper Addr Data

(12)

Oper Addr Data

Read Extended
Status Register

1 Write X xx71H Read RA GSRD

BSRD
Page Buffer Swap 7 Write X xx72H
Read Page Buffer Write X xx75H Read PBA PD
Single Load to Page

Buffer

Write X xx74H Write PBA PD

Sequential Load to
Page Buffer

x8 4,6,10 Write X xxE0H Write X BCL Write X BCH

x16 4,5,6,10 Write X xxE0H Write X WCL Write X WCH

Page Buffer Write to
Flash

x8 3,4,9,10 Write X xx0CH Write A0BC(L,H) Write PA BC(H,L)

x16 4,5,10 Write X xx0CH Write X WCL Write PA WCH
Two-Byte Write x8 3 Write X xxFBH Write A0WD(L,H) Write PA WD(H,L)
Lock Block/Confirm Write X xx77H Write BA xxD0H
Upload Status

Bits/Confirm

2 Write X xx97H Write X xxD0H

Upload Device
Information

Write X xx99H Write X xxD0H

Erase All Unlocked
Blocks/Confirm

Write X xxA7H Write X xxD0H

RY/BY# Enable to
Level-Mode

8 Write X xx96H Write X xx01H

RY/BY# Pulse-On­Write

8 Write X xx96H Write X xx02H

RY/BY# Pulse-On­Erase

8 Write X xx96H Write X xx03H

RY/BY# Disable 8 Write X xx96H Write X xx04H
Sleep 11 Write X xxF0H
Abort Write X xx80H

ADDRESS DATA

BA = Block Address AD = Array Data WC (L,H) = Word Count (Low, High)
PBA = Page Buffer Address PD = Page Buffer Data BC (L,H) = Byte Count (Low, High)
RA = Extended Register Address BSRD = BSR Data WD (L,H) = Write Data (Low, High)
PA = Program Address GSRD = GSR Data

X = Don’t Care

DD28F032SA E

16

NOTES:

1. RA can be the GSR address or any BSR address. See Figures 4 and 5 for Extended Status Register Memory Maps.

2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.

3. A

0

is automatically complemented to load the second byte of data. BYTE# must be at VIL.

The A

0

value determines which WD/BC is supplied first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.

4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size and to avoid writing the
Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future Page
Buffer expandability.

5. In x16 mode, only the lower byte DQ

0-7

is used for WCL and WCH. The upper byte DQ

8-15

is a don’t care.

6. PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.

7. This command allows the user to swap between available Page Buffers (0 or 1).

8. These commands reconfigure the RY/BY# output to one of two pulse-modes or enable and disable the RY/BY# function.

9. Program address, PA, is the destination address in the flash array which must match the source address in the Page
Buffer. Refer to the

16-Mbit Flash Product Family User’s Manual

.

10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1.

11. To ensure that the DD28F032SA’s power consumption during sleep mode reads the deep power-down current level, the

system also needs to de-select the chip by taking either or both CE

0

# or CE1#/CE2# high.

12. The upper byte of the data bus (DQ

8–15

) during command programs is a “Don’t Care” in x16 operation of the device.

5.5 Compatible Status Register

WSMS ESS ES DWS VPPS R R R

76543210

NOTES:

CSR.7 = WRITE STATE MACHINE STATUS

1 = Ready
0 = Busy

RY/BY# output or WSMS bit must be checked to
determine completion of an operation (erase
suspend, block erase or data program) before
the appropriate Status bit (ESS, ES or DWS) is
checked for success.

CSR.6 = ERASE-SUSPEND STATUS

1 = Erase Suspended
0 = Erase In Progress/Completed

CSR.5 = ERASE STATUS

1 = Error in Block Erasure
0 = Successful Block Erase

If DWS and ES are set to “1” during a block
erase attempt, an improper command sequence
was entered. Clear the CSR and attempt the
operation again.

CSR.4 = DATA WRITE STATUS

1 = Error in Data Program
0 = Data Program Successful

CSR.3 = V

STATUS

1 = V

Low Detect, Operation Abort

0 = V

OK

The VPPS bit, unlike an A/D converter, does not
provide continuous indication of V

level. The

WSM interrogates V

’s level only after the Data

Program or Block Erase command sequences
have been entered, and informs the system if
V

has not been switched on. VPPS is not
guaranteed to report accurate feedback between
V

and V

.

CSR.2–0 = RESERVED FOR FUTURE ENHANCEMENTS

These bits are reserved for future use; mask them out when polling the CSR.

E DD28F032SA

17

5.6 Global Status Register

WSMS OSS DOS DSS QS PBAS PBS PBSS

76543210

NOTES:

GSR.7 = WRITE STATE MACHINE STATUS

1 = Ready
0 = Busy

[1]

RY/BY# output or WSMS bit must be checked
to determine completion of an operation (block
lock, erase suspend, any RY/BY# reconfig­uration, Upload Status Bits, block erase or data
program) before the appropriate Status bit (OSS

or DOS) is checked for success.

GSR.6 = OPERATION SUSPEND STATUS

1 = Operation Suspended
0 = Operation in Progress/Completed

GSR.5 = DEVICE OPERATION STATUS

1 = Operation Unsuccessful
0 = Operation Successful or Currently
Running

GSR.4 = DEVICE SLEEP STATUS

1 = Device in Sleep
0 = Device Not in Sleep

MATRIX = 5/4

0 0 = Operation Successful or Currently
Running
0 1 = Device in Sleep Mode or Pending
Sleep
1 0 = Operation Unsuccessful
1 1 = Operation Unsuccessful or Aborted

If operation currently running, then GSR.7 = 0.
If device pending sleep, then GSR.7 = 0.

Operation aborted: unsuccessful due to Abort
command.

GSR.3 = QUEUE STATUS

1 = Queue Full
0 = Queue Available

GSR.2 = PAGE BUFFER AVAILABLE STATUS

1 = One or Two Page Buffers Available
0 = No Page Buffer Available

Each 28F016SA device contains two Page

Buffers.

GSR.1 = PAGE BUFFER STATUS

1 = Selected Page Buffer Ready
0 = Selected Page Buffer Busy

Selected Page Buffer is currently busy with WSM
operation

GSR.0 = PAGE BUFFER SELECT STATUS

1 = Page Buffer 1 Selected
0 = Page Buffer 0 Selected

NOTE:

1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7, or CSR.7, provides indication when all queued operations are completed.

DD28F032SA E

18

5.7 Block Status Register

BS BLS BOS BOAS QS VPPS R R

76543210

NOTES:

BSR.7 = BLOCK STATUS

1 = Ready
0 = Busy

[1]

RY/BY# output or BS bit must be checked to
determine completion of an operation (block lock,
erase suspend, any RY/BY# reconfiguration,
Upload Status Bits, block erase or data program)
before the appropriate Status bits (BOS, BLS) is
checked for success.

BSR.6 = BLOCK LOCK STATUS

1 = Block Unlocked for Program/Erase
0 = Block Locked for Program/Erase

BSR.5 = BLOCK OPERATION STATUS

1 = Operation Unsuccessful
0 = Operation Successful or
Currently Running

BSR.4 = BLOCK OPERATION ABORT STATUS

1 = Operation Aborted
0 = Operation Not Aborted

The BOAS bit will not be set until BSR.7 = 1.

MATRIX 5/4

0 0 = Operation Successful or
Currently Running
0 1 = Not a Valid Combination
1 0 = Operation Unsuccessful
1 1 = Operation Aborted Operation halted via Abort command.

BSR.3 = QUEUE STATUS

1 = Queue Full
0 = Queue Available

BSR.2 = V

STATUS

1 = V

Low Detect, Operation Abort

0 = V

OK

BSR.1-0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the BSRs.

NOTE:

1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7, or CSR.7, provides indication when all queued operations are completed.

E DD28F032SA

19

6.0 ELECTRICAL SPECIFICATIONS

6.1 Absolute Maximum Ratings*

Temperature Under Bias ....................0°C to +80°C

Storage Temperature ...................–65°C to +125°C

NOTICE: This is a production datasheet. The specifications
are subject to change without notice. Verify with your local
Intel Sales office that you have the latest datasheet before
finalizing a design.

* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may affect device
reliability.

VCC = 3.3V ± 0.3V Systems

Symbol Parameter Notes Min Max Units Test Conditions

T

A

Operating Temperature, Commercial 1 0 70 °C Ambient

Temperature

V

CC

VCC with Respect to GND 2 –0.2 7.0 V

V

PP

V

PP

Supply Voltage with Respect to GND 2,3 –0.2 14.0 V

V

Voltage on any Pin (except V

CC,VPP

) with

Respect to GND

2 –0.5

V

CC

+ 0.5

V

I Current into Any Non-Supply Pin 5 ± 30 mA
I

OUT

Output Short Circuit Current 4 100 mA

V

CC

= 5.0V ± 0.5V, VCC = 5.0V ± 0.25V Systems

(6)

Symbol Parameter Notes Min Max Units Test Conditions

T

A

Operating Temperature, Commercial 1 0 70 °C Ambient

Temperature

V

CC

VCC with Respect to GND 2 –0.2 7.0 V

V

PP

VPP Supply Voltage with Respect to GND 2,3 –0.2 14.0 V

V

Voltage on Any Pin (except V

CC,VPP

) with

Respect to GND

2 –2.0

7.0

V

I Current into Any Non-Supply Pin 5 ± 30 mA
I

OUT

Output Short Circuit Current 4 100 mA

NOTES:

1. Operating temperature is for commercial product defined by this specification.

2. Minimum DC voltage is –0.5V on input/output pins. During transitions, this level may undershoot to –2.0V for periods

<20 ns. Maximum DC voltage on input/output pins is V

CC

+ 0.5V which, during transitions, may overshoot to VCC + 2.0V for

periods <20 ns.

3. Maximum DC voltage on V

PP

may overshoot to +14.0V for periods <20 ns.

4. Output shorted for no more than one second. No more than one output shorted at a time.

5. This specification also applies to pins marked “NC.”

6. 5% V

CC

specifications refer to the DD28F032SA-070 in its High Speed Test configuration.

DD28F032SA E

20

6.2 Capacitance

For a 3.3V System:

Symbol Parameter Notes Typ Max Units Test Conditions

C

IN

Capacitance Looking into an
Address/Control Pin

11216pFT = +25°C,

f = 1.0 MHz

C

OUT

Capacitance Looking into an
Output Pin

11624pFT = +25°C,

f = 1.0 MHz

C

LOAD

Load Capacitance Driven by
Outputs for Timing Specifications

150pF

For VCC = 3.3V ± 0.3V

Equivalent Load Timing Circuit 2.5 ns 50Ω Transmission Line

Delay

For a 5.0V System:

Symbol Parameter Notes Typ Max Units Test Conditions

C

IN

Capacitance Looking into an
Address/Control Pin

11216pFT

= +25°C,

f = 1.0 MHz

C

OUT

Capacitance Looking into an
Output Pin

11624pFTA = +25°C,

f = 1.0 MHz

C

LOAD

Load Capacitance Driven by
Outputs for Timing Specifications

1 100 pF

For VCC = 5.0V ± 0.5V

30 pF

For V

= 5.0V ±

0.25V

Equivalent Testing Load Circuit for
V

CC

± 10%

2.5 ns 25Ω Transmission Line
Delay

Equivalent Testing Load Circuit for
V

CC

± 5%

2.5 ns 83Ω Transmission Line
Delay

NOTE:

1. Sampled, not 100% tested.

E DD28F032SA

21

6.3 Timing Nomenclature

All 3.3V system timings are measured from where signals cross 1.5V.
For 5.0V systems use the standard JEDEC cross point definitions.
Each timing parameter consists of 5 characters. Some common examples are defined below:

t

CEtELQV

time(t) from CEX# (E) going low (L) to the outputs (Q) becoming valid (V)

t

OEtGLQV

time(t) from OE # (G) going low (L) to the outputs (Q) becoming valid (V)

t

ACCtAVQV

time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V)

t

AS

t

AVWH

time(t) from address (A) valid (V) to WE# (W) going high (H)

t

DHtWHDX

time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X)

Pin Characters Pin States

A Address Inputs H High
D Data Inputs L Low

Q Data Outputs V Valid

ECE

X

# (Chip Enable) X Driven, but not necessarily valid

F BYTE# (Byte Enable) Z High Impedance
G OE# (Output Enable)
W WE# (Write Enable)

P RP# (Deep Power-Down Pin)

R RY/BY# (Ready Busy)

V Any Voltage Level

Y 3/5# Pin

5V VCC at 4.5V Minimum
3V VCC at 3.0V Minimum

DD28F032SA E

22

TEST POINTS

INPUT OUTPUT

2.0

0.8 0.8

2.0

2.4

0.45

0490_06

AC test inputs are driven at VOH (2.4 VTTL) for a Logic “1” and VOL (0.45 VTTL) for a Logic “0.” Input timing begins at V

IH

(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.

Figure 6. Transient Input/Output Reference Waveform (VCC = 5.0V) for Standard Test Configuration

(1)

TEST POINTSINPUT

OUTPUT

1.5

3.0

0.0

1.5

0490_07

AC test inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0.” Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.

Figure 7. Transient Input/Output Reference Waveform (VCC = 3.3V)

and High Speed Reference Waveform

(2)

(VCC = 5.0V ± 5%)

NOTES:

1. Testing characteristics for DD28F032SA-080/DD28F032SA-100.

2. Testing characteristics for DD28F032SA-070/DD28F032SA-150.

E DD28F032SA

23

From Output
under Test

Test
Point

Total Capacitance = 100 pF

2.5 ns of 25 Transmission Line

Ω

0490-08

Figure 8. Transient Equivalent Testing Load Circuit (VCC = 5.0V ± 10%)

From Output
under Test

Test
Point

Total Capacitance = 50 pF

2.5 ns of 50 Transmission Line

Ω

0490-09

Figure 9. Transient Equivalent Testing Load Circuit (VCC = 3.3V ± 0.3V)

From Output
under Test

Test
Point

Total Capacitanc e = 30 pF

2.5 ns of 83

Transmission Line

Ω

0490-10

Figure 10. High Speed Transient Equivalent Testing Load Circuit (VCC = 5.0V ± 5%)

DD28F032SA E

24

6.4 DC Characteristics

VCC = 3.3V ± 0.3V, TA = 0°C to +70°C

3/5# = Pin Set High for 3.3V Operations

Symbol Parameter Notes Min Typ Max Units Test Conditions

I

IL

Input Load Current 1 ± 2 µA

V

CC

= VCC Max

V

IN

= VCC or GND

I

LO

Output Leakage
Current

1 ± 20 µA

VCC = VCC Max
V

IN

= VCC or GND

I

CCS

VCC Standby
Current

1,5,6,8 100 200 µA

VCC = V

CC

Max

CE

0

#, CEX#, RP#, = V

CC

±

0.2V

BYTE#, WP#, 3/5# = V

CC

±

0.2V or GND ± 0.2V

28mA

V

CC

= VCC Max

CE

0

#, CEX#, RP# = V

IH

BYTE#, WP#, 3/5# = VIH or

V

IL

I

CCD

VCC Deep Power­Down Current

1 2 10 µA

RP# = GND ± 0.2V
BYTE# = V

CC

± 0.2V or GND

± 0.2V

I

CCR

1VCC Read Current 1,4,5,6 25 30 mA

V

CC

= VCC Max

CMOS: CE

0

#, CEX# = GND

± 0.2V, BYTE# = GND ±

0.2V or V

CC

± 0.2V,
Inputs = GND ± 0.2V or
V

CC

± 0.2V

f = 6.67 MHz, I

OUT

= 0 mA

26 34 mA

TTL: CE

0

#, CEX# = VIL,

BYTE# = V

IL

or V

IH’

Inputs = VIL or V

IH

f = 6.67 MHz, I

OUT

= 0 mA

I

CCW

V

CC

Program
Current for Word or
Byte

1,7 8 12 mA Program in Progress

I

CCE

V

CC

Block Erase
Current

1,7 6 12 mA Block Erase in Progress

I

CCES

VCC Erase
Suspend Current

1,2,6,7 3 6 mA

CE0#, CEX# = V

IH

Block Erase Suspended

I

PPS

V

Standby/ 1 ± 2 ± 20 µA VPP ≤ V

CC

I

PPR

Read Current

130 400 µA V

PP

> V

CC

I

PPD

V

Deep Power-

Down Current

1 0.4 10 µA RP# = GND ± 0.2V

E DD28F032SA

25

6.4 DC Characteristics (Continued)

V

CC

= 3.3V ± 0.3V, TA = 0°C to +70°C

3/5# Pin Set High for 3.3V Operations

Symbol Parameter Notes Min Typ Max Units Test Conditions

I

PPW

V

Program
Current for Word or
Byte

11015mA

V

PP

= V

PPH

Program in Progress

I

PPE

V

Block Erase
Current

1 4 10 mA

V

PP

= V

PPH

Block Erase in Progress

I

PPES

VPP Erase
Suspend Current

1 130 400 µA

VPP = V

PPH

Block Erase Suspended

V

IL

Input Low Voltage –0.3 0.8 V

V

IH

Input High Voltage 2.0

V

CC

± 0.3

V

V

OL

Output Low Voltage 0.4 V

V

CC

= VCC Min

I

OL

= 4 mA

VOH1

Output High
Voltage

2.4 V

V

CC

= VCC Min

I

OH

= –2.0 mA

VOH2

V

CC

– 0.2

V

CC

= VCC Min

I

OH

= –100 µA

V

PPL

VPP during Normal
Operations

3 0.0 6.5 V

V

PPH

VPP during
Program/Erase
Operations

11.4 12.0 12.6 V

V

LKO

VCC Program/Erase
Lock Voltage

2.0 V

NOTES:

1. All current are in RMS unless otherwise noted. Typical values at V

CC

= 3.3V, VPP = 12.0V, T = 25°C. These currents are

valid for all product versions (package and speeds).

2. I

CCES

is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum

of I

CCES

and I

CCR

.

3. Block erases, word/byte programs and lock block operations are inhibited when V

PP

= V

PPL

and not guaranteed in the

range between V

PPH

and V

PPL

.

4. Automatic Power Savings (APS) reduces I

CCR

to <1 mA in static operation.

5. CMOS Inputs are either V

CC

± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.

6. CE

X

# = CE1# or CE2#.

7. If operating with TTL levels, add 4 mA of V

CC

Standby Current to max I

CCR

1, I

CCR

2, I

CCW

, I

CCE

and I

CCES

.

8. Standby current levels are not reached when putting the chip in standby mode immediately after reading the page buffer.
Default the device into read array or read Status Register mode before entering standby to ensure standby current levels.

DD28F032SA E

26

6.5 DC Characteristics

VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C

3/5# Pin Set Low for 5.0V Operations

Symbol Parameter Notes Min Typ Max Units Test Conditions

I

IL

Input Load Current 1 ± 2 µA

V

CC

= V

CC

Max

V

IN

= V

CC

or GND

I

LO

Output Leakage
Current

1 ± 20 µA

V

CC

= V

CC

Max

V

IN

= V

CC

or GND

I

CCS

VCC Standby
Current

1,5,6,8 100 200 µA

V

CC

= V

CC

Max

CE

0

#, CEX#, RP# = V

CC

±

0.2V

BYTE#, WP#, 3/5# = V

CC

±

0.2V or GND ± 0.2V

48mA

V

CC

= V

CC

Max

CE

0

#, CEX#, RP# = V

IH

BYTE#, WP#, 3/5#

=

V

IH

or

V

IL

I

CCD

VCC Deep Power­Down Current

1 4 25 µA

RP# = GND ± 0.2V
BYTE# = VCC ± 0.2V or GND

± 0.2V

I

CCR

1VCC Read Current 1,4,5,

6,7

50 60 mA

V

CC

= VCC Max

CMOS: CE

0

#, CEX# = GND ±

0.2V, BYTE# = GND ±

0.2V or V

CC

± 0.2V,
Inputs = GND ± 0.2V or
V

CC

± 0.2V

f = 10 MHz, I

OUT

= 0 mA

52 64 mA

TTL: CE

0

#, CEX# = VIL,

BYTE# = V

IL

or VIH,

Inputs = V

IL

or V

IH

f = 10 MHz, I

OUT

= 0 mA

I

CCR

2VCC Read Current 1,4,5,

6,7

30 35 mA

V

CC

= VCC Max

CMOS: CE

0

#, CEX# = GND ±

0.2V, BYTE# = GND ±

0.2V or V

CC

± 0.2V
Inputs = GND ± 0.2V or
V

CC

± 0.2V

f = 5 MHz, I

OUT

= 0 mA

32 39 mA

TTL: CE

0

#, CEX# = VIL,

BYTE# = V

IL

or VIH,

Inputs = V

IL

or V

IH

f = 5 MHz, I

OUT

= 0 mA

I

CCW

VCC Prog. Current
for Word or Byte

1,7 25 35 mA Program in Progress

E DD28F032SA

27

6.5 DC Characteristics (Continued)

V

CC

= 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C

3/5# Pin Set Low for 5.0V Operations

Symbol Parameter Notes Min Typ Max Units Test Conditions

I

CCE

VCC Block Erase
Current

1,7 18 25 mA Block Erase in Progress

I

CCES

VCC Erase Suspend
Current

1,2,6,7 5 10 mA

CE0#, CEX# = V

IH

Block Erase Suspended

I

PPS

V

Standby/ 1 ± 2 ± 20 µA V

PP

≤ V

CC

I

PPR

Read Current

130 400 µA V

PP

> V

CC

I

PPD

VPP Deep Power­Down Current

1 0.4 10 µA RP# = GND ± 0.2V

I

PPW

V

Prog. Current

for Word or Byte

1 7 12 mA

V

PP

= V

PPH

Program in Progress

I

PPE

VPP Block Erase
Current

1 5 10 mA

V

PP

= V

PPH

Block Erase in Progress

I

PPES

VPP Erase
Suspend Current

1 130 400 µA

V

PP

= V

PPH

Block Erase Suspended

V

IL

Input Low Voltage –0.5 0.8 V

V

IH

Input High Voltage 2.0

V

CC

+ 0.5

V

V

OL

Output Low Voltage 0.45 V V

CC

= V

CC

Min, I

OL

= 5.8 mA

VOH1

Output High
Voltage

0.85
V

CC

VVCC = VCC Min, I

OH

= –2.5 mA

VOH2

V

CC

– 0.4

V

CC

= V

CC

Min, I

OH

= –100 µA

V

PPL

VPP during Normal
Operations

3 0.0 6.5 V

V

PPH

VPP during Prog.
Erase Operations

11.4 12.0 12.6 V

V

LKO

VCC Program/Erase
Lock Voltage

2.0 V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at V

CC

= 5.0V, VPP = 12.0V, T = +25°C. These currents are

valid for all product versions (package and speeds).

2. I

CCES

is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum

of I

CCES

and I

CCR.

3. Block erases, word/byte programs and lock block operations are inhibited when VPP = V

PPL

and not guaranteed in the

range between V

PPH

and V

PPL

.

4. Automatic Power Saving (APS) reduces I

CCR

to <2 mA in static operation.

5. CMOS Inputs are either V

CC

± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.

6. CE

X

#= CE1# or CE2#.

7. If operating with TTL levels, add 4 mA of V

CC

standby current. to max I

CCR

1, I

CCR

2, I

CCW

, I

CCE

and I

CCES

.

8. Standby current levels are not reached when putting the chip in standby mode immediately after reading the page buffer.
Default the device into read array or read Status Register mode before entering standby to ensure standby current levels.

DD28F032SA E

28

6.6 AC Characteristics—Read Only Operations

(1)

V

CC

= 3.3V ± 0.3V, TA = 0°C to +70°C

Versions

(5)

DD28F032SA-150

Symbol Parameter Notes Min Max Units

t

AVAV

Read Cycle Time 150 ns

t

AVQV

Address to Output Delay 150 ns

t

ELQV

CEX# to Output Delay 2 150 ns

t

PHQV

RP# High to Output Delay 750 ns

t

GLQV

OE# to Output Delay 2 50 ns

t

ELQX

CEX# to Output in Low Z 3 0 ns

t

EHQZ

CEX# to Output in High Z 3 35 ns

t

GLQX

OE# to Output in Low Z 3 0 ns

t

GHQZ

OE# to Output in High Z 3 20 ns

t

OH

Output Hold from Address, CE

# or

OE# Change, Whichever Occurs First

30 ns

t

FLQV

t

FHQV

BYTE# to Output Delay 3 150 ns

t

FLQZ

BYTE# Low to Output in High Z 3 40 ns

t

ELFL

t

ELFH

CEX# Low to BYTE# High or Low 3 5 ns

For Extended Status Register Reads

t

AVEL

Address Setup to CEX# Going Low 3,4 0 ns

t

AVGL

Address Setup to OE# Going Low 3,4 0 ns

E DD28F032SA

29

6.6 AC Characteristics—Read Only Operations

(1)

(Continued)

V

CC

= 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C

Versions

(5)

VCC ± 5% DD28F032S

A

-

070

(6)

Units

VCC ± 10%

DD28F032SA

-

080

(7)

DD28F032S

A

-

100

(7)

Sym Parameter Notes Min Max Min Max Min Max

t

AVAV

Read Cycle Time 70 80 100 ns

t

AVQV

Address to
Output Delay

70 80 100 ns

t

ELQV

CE

# to Output

Delay

2 70 80 100 ns

t

PHQV

RP# to Output
Delay

400 480 550 ns

t

GLQV

OE# to Output
Delay

2303540ns

t

ELQX

CE

# to Output

in Low Z

30 0 0 ns

t

EHQZ

CE

# to Output

in High Z

3253030ns

t

GLQX

OE# to Output in
Low Z

30 0 0 ns

t

GHQZ

OE# to Output in
High Z

3251515ns

t

OH

Output Hold from
Address, CE

#
or OE# Change,
Whichever
Occurs First

30 0 0 ns

t

FLQV

t

FHQV

BYTE# to Output
Delay

3 70 80 100 ns

t

FLQZ

BYTE# Low to
Output in High Z

3253030ns

t

ELFL

t

ELFH

CE

# Low to
BYTE# High or
Low

3555ns

For Extended Status Register Reads

t

AVEL

Address Setup to
CE

X

# Going Low

3,4 0 0 0 ns

t

AVGL

Address Setup to
OE# Going Low

3,4 0 0 0 ns

DD28F032SA E

30

NOTES:

1. See AC Input/Output Reference Waveforms for timing measurements, Figures 6 and 7.

2. OE# may be delayed up to t

ELQV-tGLQV

after the falling edge of CEX# without impact in t

ELQV

.

3. Sampled, not 100% tested.

4. This timing parameter is used to latch the correct BSR data onto the outputs.

5. Device speeds are defined as:
70/80 ns at V

CC

= 5.0V equivalent to

150 ns at V

CC

= 3.3V

100 ns at V

CC

= 5.0V equivalent to

150 ns at V

CC

= VCC = 3.3V

6. See AC Input/Output Reverence Waveforms and AC Testing Load Circuits for High Speed Test Configuration.

7. See Standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.

HIGH ZHIGH Z

ADDRESSES STABLE

VALID OUTPUT

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

CC

GND

5.0V

V

IH

V

IL

t

t

t

t

t

PHQV

AVQV

GLQV

ELQV

t

GLQX

t

ELQX

t

AVAV

t

EHQZ

t

GHQZ

OH

ADDRESSES (A)

OE# (G)

WE# (W)

DATA (D/Q)

RP# (P)

V

OL

t

AVGL

t

AVEL

CEx# (E)

(1)

V

IL

V

OH

0490-11

NOTES:

For 28F016SA No. 1: CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low, or the first of CE0# or CE2# going high.

Figure 11. Read Timing Waveforms

E DD28F032SA

31

HIGH Z

HIGH Z

ADDRESSES STABLE

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

OH

V

OL

t

t

t

AVQV

GLQV

t

ELQV

t

GLQX

ELQX

AVAV

t

EHQZ

t

GHQZ

t

OH

ADDRESSES (A)

BYTE# (F)

DATA (DQ0-DQ7)

OE# (G)

t

AVFL

t

ELFL

t

FLQV

= t

AVQV

DATA

OUTPUT

= t

ELFL

HIGH Z

DATA

OUTPUT

DATA OUTPUT

HIGH Z

DATA (DQ8-DQ15)

t

FLQZ

t

AVEL

t

AVGL

V

OH

V

OL

t

CEx #(E)

(1)

0490-12

NOTES:

For 28F016SA No. 1: CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low, or the first of CE0# or CE2# going high.

Figure 12. BYTE# Timing Waveforms

DD28F032SA E

32

6.7 Power-Up and Reset Timings

RP#

3/5#

0V

3.3V

V Power-Up

CC

5.0V

V

CC

(P)

(Y)

(3V,5V)

4.5V

PLYL

t

t

PL5V

YLPH

t

YHPH

t

Valid 5.0V Outputs

Valid

Valid

Address

Data

Valid 3.3V Outputs

AVQV

t

(A)

(Q)

AVQV

t

PHQV

t

PHQV

t

PHEL3

t

CE #

PHEL5

t

X

0490-13

Figure 13. VCC Power-Up and RP# Reset Waveforms

Symbol Parameter Notes Min Max Units

t

PLYL

t

PLYH

RP# Low to 3/5# Low (High) 0 µs

t

YLPH

t

YHPH

3/5# Low (High) to RP# High 1 2 µs

t

PL5V

t

PL3V

RP# Low to VCC at 4.5V Minimum (to V

CC

at

3.0V min or 3.6V max)

20 µs

t

PHEL3

RP# High to CE# Low (3.3V VCC) 1 500

t

PHEL5

RP# High to CE# Low (5V VCC) 1 330

t

AVQV

Address Valid to Data Valid for VCC = 5.0V ± 10% 3 80 ns

t

PHQV

RP# High to Data Valid for VCC = 5.0V ± 10% 3 480 ns

NOTES:

CE

0

#, CEX# and OE# are switched low after Power-Up.

1. The t

YLPH/tYHPH

and t

PHEL3/tPHEL5

times must be strictly followed to guarantee all other read and program specifications.

2. The power supply may start to switch concurrently with RP# going low.

3. The address access time and RP# high to data valid time are shown for the DD28F032SA-80 and 5.0V V

CC

operation.

Refer to the AC Characteristics-Read Only Operations for 3.3V V

CC

operation and all other speed options.

E DD28F032SA

33

6.8 AC Characteristics for WE#—Controlled Command Write Operations

(1)

V

CC

= 3.3V ± 0.3V, TA = 0°C to +70°C

Versions DD28F032SA-150

Symbol Parameter Notes Min Typ Max Unit

t

AVAV

Write Cycle Time 150 ns

t

VPWH

VPP Setup to WE# Going High 3 100 ns

t

PHEL

RP# Setup to CEX# Going Low 480 ns

t

ELWL

CEX# Setup to WE# Going Low 10 ns

t

AVWH

Address Setup to WE# Going High 2,6 75 ns

t

DVWH

Data Setup to WE# Going High 2,6 85 ns

t

WLWH

WE# Pulse Width 75 ns

t

WHDX

Data Hold from WE# High 2 10 ns

t

WHAX

Address Hold from WE# High 2 10 ns

t

WHEH

CEX# Hold from WE# High 10 ns

t

WHWL

WE# Pulse Width High 75 ns

t

GHWL

Read Recovery before Write 0 ns

t

WHRL

WE# High to RY/BY# Going Low 100 ns

t

RHPL

RP# Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY/BY# High

30 ns

t

PHWL

RP# High Recovery to WE# Going Low 1 µs

t

WHGL

Write Recovery before Read 120 ns

t

QVVL

V

Hold from Valid Status Register

(CSR, GSR, BSR) Data and RY/BY# High

0µs

t

WHQV

1 Duration of Word/Byte Program Operation 4,5 5 9 Note 7 µs

t

WHQV

2 Duration of Block Erase Operation 4 0.3 10 sec

DD28F032SA E

34

6.8 AC Characteristics for WE#—Controlled Command Write Operations

(1)

(Continued)

VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C

Versions VCC ± 5% DD28F032SA-070 Unit

VCC ± 10% DD28F032SA-080 DD28F032SA-100

Sym Parameter Notes Min Typ Max Min Typ Max Min Typ Max

t

AVAV

Write Cycle
Time

70 80 100 ns

t

VPWH

VPP Setup to
WE# Going
High

3 100 100 100 ns

t

PHEL

RP# Setup to
CE

X

# Going

Low

480 480 480 ns

t

ELWL

CEX# Setup
to WE# Going
Low

000ns

t

AVWH

Address
Setup to WE#
Going High

2,6 50 50 50 ns

t

DVWH

Data Setup to
WE# Going
High

2,6 60 60 60 ns

t

WLWH

WE# Pulse
Width

40 50 50 ns

t

WHDX

Data Hold
from WE#
High

20 0 0 ns

t

WHAX

Address Hold
from WE#
High

210 10 10 ns

t

WHEH

CEX# Hold
from WE#
High

10 10 10 ns

t

WHWL

WE# Pulse
Width High

30 30 50 ns

t

GHWL

Read
Recovery
before Write

000ns

t

WHRL

WE# High to
RY/BY#
Going Low

100 100 100 ns

E DD28F032SA

35

6.8 AC Characteristics for WE#—Controlled Command Write Operations

(1)

(Continued)

V

CC

= 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C

Versions VCC ± 5% DD28F032SA-070 Unit

VCC ± 10% DD28F032SA-080 DD28F032SA-100

Sym Parameter Notes Min Typ Max Min Typ Max Min Typ Max

t

RHPL

RP# Hold
from Valid
Status
Register
(CSR, GSR,
BSR) Data
and RY/BY#
High

30 0 0 ns

t

PHWL

RP# High
Recovery to
WE# Going
Low

111µs

t

WHGL

Write
Recovery
before Read

60 65 65 ns

t

QVVL

VPP Hold from
Valid Status
Register
(CSR, GSR,
BSR) Data
and RY/BY#
High

000µs

t

WHQV

1

Duration of
Word/Byte
Program
Operation

4,5 4.5 6 Note74.5 6 Note74.5 6 Note7µs

t

WHQV

2

Duration of
Block Erase
Operation

4 0.3 10 0.3 10 0.3 10 sec

NOTES:

For 28F016SA No. 1: CE

X

# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

For 28F016SA No. 2: CE

X

# is defined as the latter of CE0# or CE2# going low or the first of CE0# or CE2# going high.

1. Read timings during data program and block erase are the same as for normal read.

2. Refer to command definition tables for valid address and data values.

3. Sampled, but not 100% tested

4. Data program/block erase durations are measured to valid Status Register data.

5. Word/byte program operations are typically performed with 1 programming pulse.

6. Address and data are latched on the rising edge of WE# for all command write operations.

7. This information will be available in a technical paper. Please call Intel’s Applications Hotline or your local sales office for

more information.

DD28F032SA E

36

V

V

WE# (W)

OE# (G)

RP# (P)

V

PP

CEx # (E)

(V)

DEEP

POWER-DOWN

IH

IL

V

V

IH

IL

V
V

IH

IL

ADDRESSES (A)

t

AVAV

t

WHAX

t

WHEHELWL

t

t

WHDX

WHWL

t

V

V

IH

IL

t

WLWH

t

DVWH

V

IH

IL

V

V

IH

V

IL

PHWL

t

HIGH Z

IN

DD

IN

IN

A

t

t

QVVL

D

IN

IL

V

IH

V

PPH

V

PPL

V

t

VPWH

READ EXTENDED

STATUS REGISTER DATA

DATA (D/Q)

WHQV1,2

WRITE DATA-WRITE OR

ERASE SETUP COMMAND

WRITE VALID ADDRESS

& DATA (DATA-WRITE) OR

ERASE CONFIRM COMMAND

AUTOMATED DATA-WRITE

OR ERASE DELAY

V

V

RY/BY# (R)

t

WHRL

t

WHGL

OH

OL

V

V

IH

IL

ADDRESSES (A)

t

AVAV

AVWH

t

t

WHAX

IN

A

READ COMPATIBLE

STATUS REGISTER DATA

D

IN

WRITE READ EXTENDED

REGISTER COMMAND

A=RA

NOTE 1

NOTE 2

NOTE 3

NOTE 4

D

OUT

AVWH

t

t

RHPL

t

GHWL

NOTE 5

0490-14

NOTES:

1. This address string depicts data program/block erase cycles with corresponding verification via ESRD.

2. This address string depicts data program/block erase cycles with corresponding verification via CSRD.

3. This cycle is invalid when using CSRD for verification during data program/block erase operations.

4. For 28F016SA No. 1: CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.

For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low, or the first of CE0# or CE2# going high

5. RP# low transition is only to show t

RHPL

; not valid for above Read and Program cycles.

Figure 14. AC Waveforms for Command Write Operations

E DD28F032SA

37

6.9 AC Characteristics for CEX#—Controlled Command Write Operations

(1)

V

CC

= 3.3V ± 0.3V, TA = 0°C to +70°C

Versions DD28F032SA-150

Symbol Parameter Notes Min Typ Max Unit

t

AVAV

Write Cycle Time 150 ns

t

VPEH

VPP Setup to CEX# Going High 3 100 ns

t

PHWL

RP# Setup to WE# Going Low 480 ns

t

WLEL

WE# Setup to CEX# Going Low 0 ns

t

AVEH

Address Setup to CEX# Going High 2,6 75 ns

t

DVEH

Data Setup to CEX# Going High 2,6 85 ns

t

ELEH

CEX# Pulse Width 75 ns

t

EHDX

Data Hold from CEX# High 2 10 ns

t

EHAX

Address Hold from CEX# High 2 10 ns

t

EHWH

WE# Hold from CEX# High 10 ns

t

EHEL

CEX# Pulse Width High 75 ns

t

GHEL

Read Recovery before Write 0 ns

t

EHRL

CEX# High to RY/BY# Going Low 100 ns

t

RHPL

RP# Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY/BY# High

30 ns

t

PHEL

RP# High Recovery to CEX# Going Low 1 µs

t

EHGL

Write Recovery before Read 120 ns

t

QVVL

VPP Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY/BY# High

0µs

t

EHQV

1 Duration of Word/Byte Program Operation 4,5 5 9 Note 7 µs

t

EHQV

2 Duration of Block Erase Operation 4 0.3 10 sec

DD28F032SA E

38

6.9 AC Characteristics for CEX#—Controlled Command Write Operations

(1)

(Continued)

VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C

Versions VCC ± 5% DD28F032SA-070 Unit

VCC ± 10% DD28F032SA-080 DD28F032SA-100

Sym Parameter Notes Min Typ Max Min Typ Max Min Typ Max

t

AVAV

Write Cycle
Time

70 80 100 ns

t

VPEH

VPP Setup to
CE

X

# Going

High

3 100 100 100 ns

t

PHWL

RP# Setup to
WE# Going
Low

3 480 480 480 ns

t

WLEL

WE# Setup to
CE

X

# Going

Low

000ns

t

AVEH

Address Setup
to CE

X

# Going

High

2,6 50 50 50 ns

t

DVEH

Data Setup to
CE

X

# Going

High

2,6 60 60 60 ns

t

ELEH

CEX# Pulse
Width

40 50 50 ns

t

EHDX

Data Hold
from CEX#
High

2000ns

t

EHAX

Address Hold
from CE

X

#

High

2101010ns

t

EHWH

WE# Hold
from CE

X

#

High

10 10 10 ns

t

EHEL

CEX# Pulse
Width High

30 30 50 ns

t

GHEL

Read
Recovery
before Write

000ns

t

EHRL

CEX# High to
RY/BY# Going
Low

100 100 100 ns

t

RHPL

RP# Hold from
Valid Status
Register
(CSR, GSR,
BSR) Data
and RY/BY#
High

3000ns

E DD28F032SA

39

6.9 AC Characteristics for CEX#—Controlled Command Write Operations

(1)

(Continued)

VCC = 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C

Versions VCC ± 5% DD28F032SA-070 Unit

VCC ± 10% DD28F032SA-080 DD28F032SA-100

Sym Parameter Notes Min Typ Max Min Typ Max Min Typ Max

t

PHEL

RP# High
Recovery to
CE

X

#

Going Low

111µs

t

EHGL

Write
Recovery
before Read

60 65 80 ns

t

QVVL

VPP Hold from
Valid Status
Register
(CSR, GSR,
BSR) Data at
RY/BY# High

000µs

t

EHQV

1

Duration of
Word/Byte
Program
Operation

4,5 4.5 6 Note74.5 6 Note74.5 6 Note7µs

t

EHQV

2

Duration of
Block Erase
Operation

4 0.3 10 0.3 10 0.3 10 sec

NOTES:

For 28F016SA No. 1: CE

X

# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

For 28F016SA No. 2: CE

X

# is defined as the latter of CE0# or CE2# going low or the first of CE0# or CE2# going high.

1. Read timings during data program and block erase are the same as for normal read.

2. Refer to command definition tables for valid address and data values.

3. Sampled, but not 100% tested.

4. Data program/block erase durations are measured to valid Status Register data.

5. Word/byte program operations are typically performed with 1 programming pulse.

6. Address and data are latched on the rising edge of CE

X

# for all command write operations.

7. This information will be available in a technical paper. Please call Intel’s Applications Hotline or your local sales office for

more information.

DD28F032SA E

40

V

V

WE# (W)

OE# (G)

RP# (P)

V

PP

CEx#(E)

(V)

DEEP

POWER-DOWN

IH

IL

V

V

IH

IL

V
V

IH

IL

ADDRESSES (A)

t

AVAV

t

EHAX

t

EHWHWLEL

t

t

EHDX

EHEL

t

V

V

IH

IL

t

ELEH

t

DVEH

V

IH

IL

V

V

IH

V

IL

PHEL

t

HIGH Z

IN

DD

IN

IN

A

t

t

QVVL

D

IN

IL

V

IH

V

PPH

V

PPL

V

t

VPEH

READ EXTENDED

STATUS REGISTER DATA

DATA (D/Q)

EHQV1,2

WRITE DATA-WRITE OR

ERASE SETUP COMMAND

WRITE VALID ADDRESS

& DATA (DATA-WRITE) OR

ERASE CONFIRM COMMAND

AUTOMATED DATA-WRITE

OR ERASE DELAY

V

V

RY/BY# (R)

t

EHRL

t

EHGL

OH

OL

V

V

IH

IL

ADDRESSES (A)

t

AVAV

AVEH

t

t

EHAX

IN

A

READ COMPATIBLE

STATUS REGISTER DATA

D

IN

WRITE READ EXTENDED

REGISTER COMMAND

A=RA

NOTE 1

NOTE 2

NOTE 3

NOTE 4

D

OUT

AVEH

t

t

RHPL

t

GHEL

NOTE 5

0490_15

NOTES:

1. This address string depicts data program/block erase cycles with corresponding verification via ESRD.

2. This address string depicts data program/block erase cycles with corresponding verification via CSRD.

3. This cycle is invalid when using CSRD for verification during data program/block erase operations.

4. For 28F016SA No. 1:CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.

For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low, or the first of CE0# or CE2# going high.

5. RP# low transition is only to show t

RHPL

; not valid for above Read and Write cycles.

Figure 15. Alternate AC Waveforms for Command Write Operations

E DD28F032SA

41

6.10 AC Characteristics for Page Buffer Write Operations

(1)

V

CC

= 3.3V ± 0.3V, TA = 0°C to +70°C

Versions DD28F032SA-150

Symbol Parameter Notes Min Typ Max Unit

t

AVAV

Write Cycle Time 150 ns

t

ELWL

CEX# Setup to WE# Going Low 10 ns

t

AVWL

Address Setup to WE# Going Low 3 0 ns

t

DVWH

Data Setup to WE# Going High 2 75 ns

t

WLWH

WE# Pulse Width 75 ns

t

WHDX

Data Hold from WE# High 2 10 ns

t

WHAX

Address Hold from WE# High 2 10 ns

t

WHEH

CEX# Hold from WE# High 10 ns

t

WHWL

WE# Pulse Width High 75 ns

t

GHWL

Read Recovery before Write 0 ns

t

WHGL

Write Recovery before Read 120 ns

DD28F032SA E

42

6.10 AC Characteristics for Page Buffer Write Operations

(1)

(Continued)

V

CC

= 5.0V ± 0.5V, 5.0V ± 0.25V, TA = 0°C to +70°C

Versions DD28F032SA-070 DD28F032SA-080 DD28F032SA-100

Symbol Parameter Notes Min Typ Max Min Typ Max Min Typ Max Unit

t

AVAV

Write Cycle
Time

70 80 100 ns

t

ELWL

CEX# Setup to
WE# Going

Low

000ns

t

AVWL

Address Setup
to WE# Going
Low

3000ns

t

DVWH

Data Setup to
WE# Going
High

2505050ns

t

WLWH

WE# Pulse
Width

40 50 50 ns

t

WHDX

Data Hold from
WE# High

2000ns

t

WHAX

Address Hold
from WE# High

2101010ns

t

WHEH

CEX# Hold from
WE# High

10 10 10 ns

t

WHWL

WE# Pulse
Width High

30 30 50 ns

t

GHWL

Read Recovery
before Write

000ns

t

WHGL

Write Recovery
before Read

60 65 80 ns

NOTES:

For 28F016SA No. 1: CE

X

# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

For 28F016SA No. 2: CE

X

# is defined as the latter of CE0# or CE2# going low or the first of CE0# or CE2# going high.

1. These are WE#-controlled write timings, equivalent CE

X

#-controlled write timings apply.

2. Sampled, not 100% tested.

3. Address must be valid during the entire WE# low pulse or the entire CE

X

# low pulse (for CEX #-controlled write timings).

E DD28F032SA

43

WE#
(W)

CEx#
(E)

V

V

IH

IL

ELWL

t

t

WHDX

V

V

IH

IL

t

WLWH

t

DVWH

V

IH

IL

V

HIGH Z

IN

D

DATA
(D/Q)

V

V

IH

IL

ADDRESSES (A)

t

WHAX

VALID

t

AVWL

t

WHEH

t

WHWL

0490-16

Figure 16. Page Buffer Write Timing Waveforms

(Loading Data to the Page Buffer)

DD28F032SA E

44

6.11 Erase and Word/Byte Write Performance, Cycling Performance

and Suspend Latency

(3)

V

CC

= 3.3V ± 0.3V, VPP = 12.0V ± 0.6V, TA = 0°C to +70°C

Sym Parameter Notes Min Typ

(1)

Max Units Test Conditions

Page Buffer Byte Write Time 2,4 3.26 Note 6 µs
Page Buffer Word Write Time 2,4 6.53 Note 6 µs

t

1

Word/Byte Program Time 2 9 Note 6 µs

t

2

Block Program Time

2 0.6 2.1 sec Byte Program

t

3

Block Program Time

2 0.3 1.0 sec Word Program

Block Erase Time

2 0.8 10 sec

Full Chip Erase Time 2 51.2

sec

Erase Suspend Latency Time
to Read

7.0 µs

Auto Erase Suspend Latency
Time to Program

10.0 µs

Erase Cycles 5 100,000 1,000,000 Cycles

V

CC

= 5.0V ± 0.5V, VPP = 12.0V ± 0.6V, TA = 0°C to +70°C

Sym Parameter Notes Min Typ

(1)

Max Units Test Conditions

Page Buffer Byte Write Time 2,4 2.76 Note 6 µs
Page Buffer Word Write Time 2,4 5.51 Note 6 µs

t

1

Word/Byte Program Time 2 6 Note 6 µs

t

2

Block Program Time 2 0.4 2.1 sec Byte Program

t

3

Block Program Time 2 0.2 1.0 sec Word Program
Block Erase Time 2 0.6 10 sec
Full Chip Erase Time 2 38.4

sec

Erase Suspend Latency Time
to Read

5.0 µs

Auto Erase Suspend Latency
Time to Program

8.0 µs

Erase Cycles 5 100,000 1,000,000 Cycles

NOTES:

1. +25°C, V

CC

= 3.3V or 5.0V nominal, VPP = 12.0V nominal, 10K cycles.

2. Excludes system-level overhead.

3. These performance numbers are valid for all speed versions.

4. This assumes using the full Page Buffer to program to the flash memory (256 bytes or 128 words).

5. 1,000,000 cycle performance assumes the application uses block retirement techniques.

6. This information will be available in a technical paper. Please call Intel’s Application hotline or your local Intel sales office for

more information.

E DD28F032SA

45

7.0 DERATING CURVES

290489-16.eps

Figure 17. ICC vs. Frequency (VCC = 5.5V) for x8

or x16 Operation

290489-18.eps

Figure 18. ICC during Block Erase

290489-19.eps

Figure 19. ICC vs. Frequency (VCC = 3.6V) for x8

or x16 Operation

290489-21.eps

Figure 20. IPP during Block Erase

DD28F032SA E

46

290489-24.eps

Figure 21. Access Time (t

ACC

) vs. Output Loading

290489-25.eps

Figure 22. IPP during Word Write Operation

290490-26.eps

Figure 23. IPP during Page Buffer Write

Operation

E DD28F032SA

47

8.0 MECHANICAL SPECIFICATIONS

E

DETAIL A

D1

Z

A2

SEE DETAIL

A1

A

SEE DETAIL A

C

DETAIL B

b

O

O

O

O

SEATING

PLANE

e

Y

D

L

Ø

290490-26

Figure 24. Mechanical Specifications of the Dual Die 56-Lead TSOP Type I Package

Family: Dual Die Thin Small Out-Line Package

Symbol Millimeters Notes

Minimum Nominal Maximum

A 1.20

A

1

0.05

A

2

0.965 0.995 1.025
b 0.100 0.150 0.200
c 0.115 0.125 0.135

D

1

18.20 18.40 18.60
E 13.80 14.00 14.20
e 0.50
D 19.80 20.00 20.20
L 0.500 0.600 0.700
N56

∅0° 3° 5°

Y 0.100
Z 0.150 0.250 0.350

DD28F032SA E

48

APPENDIX A

DEVICE NOMENCLATURE/ORDERING INFORMATION

DUAL DIE

ACCESS SPEED (ns)

D2 28F0 0 03SA-7

70 ns

100 ns

D

NOTES:

Two valid combinations of speeds exist:
DD28F032SA-070, DD28F032SA-080, DD28F032SA-150

or

DD28F032SA-100, DD28F032SA-150

Option Order Code Valid Combinations

VCC = 3.3V

± 0.3V, 50 pF

VCC = 5.0V

± 5%, 30 pF

VCC = 5.0V

± 10%, 100 pF

1 DD28F032SA-070 DD28F032SA-150 DD28F032SA-070 DD28F032SA-080
2 DD28F032SA-100 DD28F032SA-150 DD28F032SA-100

E DD28F032SA

49

APPENDIX B

ADDITIONAL INFORMATION

(1,2)

Order Number Document/Tool

297372

16-Mbit Flash Product Family User’s Manual

290489

28F016SA 16-Mbit FlashFile™ Memory Datasheet

290528

28F016SV FlashFile™ Memory Datasheet

290429

28F008SA 8-Mbit FlashFile™ Memory Datasheet

292092

AP-357 Power Supply Solutions for Flash Memory

292123

AP-374 Flash Memory Write Protection Techniques

292124

AP-375 Upgrade Considerations from the 28F008SA to the 28F016SA”

292126

AP-377 16-Mbit Flash Product Family Software Drivers 28F016SA, 28F016SV,
28F016XS, 28F016XD

292127

AP-378 System Optimization Using the Enhanced Features of the 28F016SA

292144

AP-393 28F016SV Compatibility with 28F016SA

292159

AP-607 Multi-Site Layout Planning with Intel’s Flash File™ Components

294016

ER-33 ETOX™ Flash Memory Technology– Insight to Intel’s Fourth Generation
Process Innovation

297534

Small and Low-Cost Power Supply Solutions for Intel’s Flash Memory Products

(Technical Paper)

297508 FLASHBuilder Design Resource Tool

NOTES:

1. Please call the Intel Literature Center at [phone] to request Intel documentation. International customers should
contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.