Intel Corporation DD28F032SA-80, DD28F032SA-70, DD28F032SA-100 Datasheet

December 1996 Order Number: 290490-005

User-Selectable 3.3V or 5V V

User-Configurable x8 or x16 Operation

70 ns Maximum Access Time

28.6 MB/sec Burst Write Transfer Rate

1 Million Typical Erase Cycles per Block

56-Lead, 1.2 x 14 x 20 mm Advanced Dual Die TSOP Package Technology

64 Independently Lockable Blocks

Revolutionary Architecture



100% Backwards-Compatible with Intel 28F016SA



Pipelined Command Execution



Program during Erase

2 mA Typical ICC in Static Mode

2 µA Typical Deep Power-Down

State-of-the-Art 0.6 µm ETOX™ IV Flash Technology

Intel’s DD28F032SA 32-Mbit Fl ashFile™ memory is a revoluti onary architec ture which enables the desi gn of truly mobile, high performance, personal computing and communication products. With innovative capabilities, low power operation and very high read/program performance, the DD28F032SA is also the ideal choice for designing embedded mass storage flash memory systems.

The DD28F032SA is the result of hi ghly-advanced packagi ng innovation which encapsulates two 28F016SA die in a single Dual Die Thin Small Outline Package (DDTSOP).

The DD28F032SA is the highest densi ty, highest performance nonvolatil e read/program solution for solidstate storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F016SA 16-Mbit FlashFile memory), very high-cycling, low-power 3.3V operation, very fast program and read performance and selective block locking provi de a highly fl exi ble memory c omponent s uit able for hi gh-densit y memory cards, Resident Flash Arrays and PCMCIA -ATA Fl ash Dri ves . The DD28F032S A’s dual read v oltage enables the design of memory c ards which can be read/written in 3.3V and 5.0V systems interchangeably. Its x8/x16 architecture al l ows the optimization of memory to processor interface. The flexible block locking option enables bundling of executable application software in a Resident Flash Array or memory card. The DD28F032SA will be manufactured on Intel’s 0.6 µm ETOX IV technology.

DD28F032SA

32-MBIT (2 MBIT X 16, 4 MBIT X 8)

FlashFile™ MEMORY

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provi ded in Intel ’s Terms and Condi tions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. The 28F016SA may contain design defects or errors known as errata. Current characterized errata are available upon request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

E DD28F032SA

CONTENTS

PAGE PAGE

1.0 PRODUCT OVERVIEW...................................5

2.0 DEVICE PINOUT.............................................6

2.1 Lead Descriptions........................................8

3.0 MODES OF OPERATION .............................10

4.0 MEMORY MAPS...........................................11

4.1 Extended Status Registers Memory Map... 12

5.0 BUS OPERATIONS, COMMANDS AND

STATUS REGISTER DEFINITIONS................ 13

5.1 Bus Operations for Word-Wide Mode

(BYTE# = V

).............................................. 13

5.2 Bus Operations for Byte-Wide Mode

(BYTE# = V

)..............................................13

5.3 28F008SA Compatible Mode Command

Bus Definitions.............................................14

5.4 28F016SA-Performance Enhancement

Command Bus Definitions............................15

5.5 Compatible Status Register .......................16

5.6 Global Status Register...............................17

5.7 Block Status Register ................................18

6.0 ELECTRICAL SPECIFICATIONS..................19

6.1 Absolute Maximum Ratings........................19

6.2 Capacitance...............................................20

6.3 Timing Nomenclature.................................21

6.4 DC Characteristics (V

= 3.3V ± 0.3V).....24

6.5 DC Characteristics (V

= 5.0V ± 0.5V)....26

6.6 AC Characteristics—Read Only

Operations ...................................................28

6.7 Power-Up and Reset Timings.....................32

6.8 AC Characteristics for WE#—Controlled

Command Write Operations.........................33

6.9 AC Characteristics for CE

#—Controlled

Write Operations..........................................37

6.10 AC Characteristics for Page Buffer Write

Operations ...................................................41

6.11 Erase and Word/Byte Program Performance, Cycling Performance and

Suspend Latency .........................................44

7.0 DERATING CURVES....................................45

8.0 MECHANICAL SPECIFICATIONS................47

APPENDIX A: Device Nomenclature/

Ordering Information.....................................48

APPENDIX B: Additional Information...............49

DD28F032SA E

REVISION HISTORY

Number Description

-001 —Original Version

-002 —Never Published

-003 —Full Datasheet with Specifications —CE

#, CE

# control 28F016SA No. 1

—CE

#, CE2# control 28F016SA No. 2

-004 —DC Characteristics (3.3V VCC): I

CCR

(TTL): BYTE# = VIL or V

—Full Chip Erase Time (3.3V VCC) = 51.2 sec typ —Full Chip Erase Time (5.0V V

) = 38.4 sec typ

—Section 6.7: Added specifications t

PHEL3

, t

PHEL5

—TSOP dimension A1 = 0.05 mm (min) —Revised Product Status to Preliminary —t

WHGL

(3.3V) = 120 ns

—Minor cosmetic changes

-005 —Updated AC/DC parameters

E DD28F032SA

1.0 PRODUCT OVERVIEW

The DD28F032SA is a high-performance 32-Mbit (33,554,432-bit) block erasable nonv ol atile random access memory organiz ed as eit her 2 Mword x 16, or 4 Mbyte x 8. The DD28F032SA is built using two 28F016SA chips encapsulated in a single 56- lead TSOP Type I package. The DD28F032SA includes sixty-f our 64-KB (65,536) blocks or sixtyfour 32-KW (32,768) blocks.

The DD28F032SA architecture allows operations to be performed on a single, 16-Mbit chip at a time.

The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease of use.

Among the significant enhancements on the DD28F032SA:

• 3.3V Low Power Capability

• Improved Program Performance

• Dedicated Block Program/Erase Protection

A 3/5# input pin reconfigures t he device internally for optimized 3.3V or 5.0V read/program operation.

The DD28F032SA will be available in a 56-lead,

1.2 mm thick, 14 mm x 20 mm Dual Die TSOP Type I package. This form factor and pinout allow for very high board layout densities. The DD28F032SA is pinout and footprint compatible with the 28F016SA.

Two Command User Interfaces (CUI) s erve as t he system interface between the microprocessor or microcontroller and the internal memory operation.

Internal algorithm automation allows word/byte programs and block erase operations to be executed using a two-write command s equence to the CUI in the same way as the 28F016SA 16-Mbit FlashFile memory.

A super-set of commands has been added to the basic 28F008SA (8-Mbit FlashFile memory) command-set to achieve higher program performance and provide additional capabilities.

These new commands and features include:

• Page Buffer Writes to Flash

• Command Queueing Capability

• Automatic Data Programs during Erase

• Software Locking of Memory Blocks

• Two-Byte Successive Programs in 8-bit

Systems

• Erase All Unlocked Blocks These operations can only be performed on one

16-Mbit device at a time. If the WSM is busy performing an operation, the system should not attempt to select the other device.

Writing of memory data is performed in either byte

or word increments typically within 6 µs, a 33% improvement over the 28F008SA. A block erase operation erases one of the 64 blocks in typically

0.6 sec, independent of the ot her blocks, which is a 65% improvement over the 28F008SA.

Each block can be written and eras ed a minimum of 100,000 cycles. Systems can achieve typically 1 million block erase cycles by providing wearleveling algorithms and gracef ul block retirement. These techniques have already been employ ed in many flash file systems. Additionally, wear leveling of block erase cycles can be used to minimize the program/erase performance differences across blocks.

The DD28F032SA incorporates two Page Buff ers of 256 bytes (128 words) on each 28F016SA to allow page data programs. This feature can improve a system program performance by up to

4.8 times over previous flash memory devices. All operations are started by a sequence of

command writes to the device. Three Status Registers (described in detai l later) and a RY/BY# output pin provide information on the progress of the requested operation.

The DD28F032SA allows queueing of the next operation while the memory executes t he current operation. This eliminates system overhead when writing several bytes in a row to the array or erasing several blocks at the same time. The DD28F032SA can also perform program operations to one block of memory while performing erase of another block. However, simultaneous program and/or erase operat ions are not allowed on both 28F016SA devices. See Modes of Operation, Section 3.0.

DD28F032SA E

The DD28F032SA provides user-select able block locking to protect code or data such as device drivers, PCMCIA card information, ROMexecutable O/S or application code. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the DD28F032SA has a master Write Protect pin (WP#) which prevents any modifications to memory blocks whose lock-bits are set.

The DD28F032SA contains three ty pes of Status Registers to accomplish various functions:

• A Compatible Status Register (CSR) which is 100% compatible with the 28F008S A FlashFile

memory’s Status Regist er. This register, when used alone, provides a straightf orward upgrade capability to the DD28F032SA from a 28F008SA-based design.

• A Global Status Register (GSR) which i nforms the system of Command Queue status, Page Buffer status, and overall Writ e State Machine (WSM) status.

• 64 Block Status Registers (BSRs) which provide block-specific status information such as the block lock-bit status.

The GSR and BSR memory maps for byte-wide and word-wide modes are shown in Figures 4 and 5.

The DD28F032SA incorporates an open drain RY/BY# output pin. This feature al lows the user to OR-tie many RY/BY# pins together in a multiple memory configuration such as a Resident Flash Array. Other configurations of the RY/BY # pin are enabled via special CUI commands and are described in detail in the

16-Mbit Flash Product

Family User’s Manual

The DD28F032SA also incorporates three chipenable input pins, CE

#, CE1# and CE2#. The

active low combinat ion of CE

# and CE1# controls the first 28F016SA. The ac tive low combinat ion of CE

# and CE2# controls the second 28F016SA.

The BYTE# pin allows either x8 or x16 read/programs to the DD28F032SA. BYTE# at logic low selects 8-bit mode with address A

selecting between low byte and high byte. On the other hand, BYTE# at logic high enables 16-bit operation with address A

becoming the lowest

order address and address A

is not used (don’t care). A device block diagram is shown in Figure 1

The DD28F032SA is specified for a maximum access time of 70 ns (t

ACC

) at 5.0V operation (4.75V to 5.25V) over the commerc ial temperature range (0°C to +70°C). A corres ponding maximum access time of 150 ns at 3.3V (3.0V to 3.6V and 0°C to +70°C) is achieved for reduced power consumption applications.

The DD28F032SA incorporates an Automatic Power Saving (APS) feature which substantially reduces the active current when the device is in static mode of operation (addresses not switching).

A deep power-down mode of operation is invoked when the RP# (called PWD# on the 28F008SA) pin is driven low. This mode provides additional write protection by acting as a device reset pin during power transitions. In t he deep power-down state, the WSM is res et (any current operation wi ll abort) and the CSR, GSR and BSR registers are cleared.

A CMOS standby mode of operation is enabled when either CE

#, or both CE1# and CE2#, transition high and RP# stays high with all input control pins at CMOS levels.

2.0 DEVICE PINOUT

The DD28F032SA Standard 56-Lead Dual Die TSOP Type I pinout configuration is shown in Figure 2.

E DD28F032SA

Output Buffer

Output

Buffer

Input

Buffer

Input

Buffer

I/O Logic

CSR

Data

Comparator

Decoder

64-Kbyte

Block 0

64-Kbyte

Block 1

64-Kbyte

Block 30

64-Kbyte

Block 31

Program/Erase Voltage Switc h

Address Counter

Input

Buffer

Y Gating/Sensing

Output Multiplexer

GND

8-15

0-7

3/5#

BYTE#

CE0# CE1#

OE# WE# WP#

RP#

3/5#

RY/BY#

0-20

Address

Queue

Latches

CUI

Data

Queue

Registers

Page

Buffers

WSM

ESRs

0490_01

Figure 1. Block Diagram of 16-Mbit Devices in DD28F032SA

Architectural Evolution Includes Page Buffers, Queue Registers and Extended Registers

DD28F032SA E

2.1 Lead Descriptions

Symbol Type Name and Function

INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when

device is in x8 mode. This address is latched in x8 data programs. Not used in x16 mode (i.e., the A

input buffer is turned off when BYTE# is

high).

A1–A

INPUT WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block.

6-15

selects 1 of 1024 rows, and A

1-5

selects 16 of 512 columns. These

addresses are latched during data programs.

A16–A

INPUT BLOCK-SELECT ADDRESSES: Select 1 of 32 erase blocks in each of

the two 28F016SAs. These addresses are latched during data programs, block erase and lock block operations.

DQ0–DQ7INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI write

cycles. Outputs array, buffer, identifier or status data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled.

DQ8–DQ15INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 data program

operations. Outputs array, buffer or identifier data in the appropriate read mode; not used for Status Register reads. Floated when the chip is deselected or the outputs are disabled.

CE0# CE

# =

# or

INPUT CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,

decoders and sense amplifiers. CE

#/CE1# enable/disable the first

28F016SA (16 Mbit No. 1) while CE

#/CE2# enable/disable the second

28F016SA (16 Mbit No. 2). CE

# active low enables chip operation while

# or CE2# select between the first and second device, respectively

# and CE2# must not be active low simultaneously. Reference Table

3.0.

RP# INPUT RESET/POWER-DOWN: RP# low places the device in a deep power-

down state. All circuits that burn static power, even those circuits enabled in standby mode, are turned off. When returning from deep power-down, a recovery time is required to allow these circuits to power-up. When RP# goes low, any current or pending WSM operation(s) are terminated, and the device is reset. All Status Registers return to ready (with all status flags cleared).

OE# INPUT OUTPUT ENABLE: Gates device data through the output buffers when

low. The outputs float to tri-state off when OE# is high.

NOTE:

CEx# overrides OE#, and OE# overrides WE#.

WE# INPUT WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue

Registers and Address Queue Latches. WE# is active low, and latches both address and data (command or array) on its rising edge.

RY/BY# OPEN DRAIN

OUTPUT

READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the WSM is busy performing an operation. RY/BY# high indicates that the WSM is ready for new operations (or WSM has completed all pending operations), or block erase is suspended, or the device is in deep power-down mode. This output is always active (i.e., not floated to tri-state off when OE# or CE

#/CE1#/CE2# are high), except if a RY/BY# Pin Disable command is issued.

E DD28F032SA

2.1 Lead Descriptions (Continued)

Symbol Type Name and Function

WP# INPUT WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile

lock-bit for each block. When WP# is low, those locked blocks as reflected by the Block-Lock Status bits (BSR.6), are protected from inadvertent data programs or block erases. When WP# is high, all blocks can be written or erased regardless of the state of the lock-bits. The WP# input buffer is disabled when RP# transitions low (deep power-down mode).

BYTE# INPUT BYTE ENABLE: BYTE# low places device in x8 mode. All data is then

input or output on DQ

0-7

, and DQ

8-15

float. Address A

selects between the high and low byte. BYTE# high places the device in x16 mode, and turns off the A

input buffer. Address A1 then becomes the lowest order

address.

3/5# INPUT 3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V

operation. 3/5# low configures internal circuits for 5.0V operation.

NOTES:

Reading the array with 3/5# high in a 5.0V system could damage the device. There is a significant delay from 3/5# switching to valid data.

SUPPLY ERASE/PROGRAM POWER SUPPLY: For erasing memory array blocks

or writing words/bytes/pages into the flash array.

SUPPLY DEVICE POWER SUPPLY (3.3V ± 0.3V, 5.0V ± 0.5V, 5.0V ± 0.25V):

Do not leave any power pins floating.

GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY:

Do not leave any ground pins floating.

NC NO CONNECT:

Lead may be driven or left floating.

DD28F032SA E

28F016SV 28F016SA

2 3

4 5

7 8

17 18

25 26

54 52

51 50

49 48 47

DD28F032SA

56-LEAD TSOP PINOUT

14mm x 20mm

TOP VIEW

3/5#

WP# WE# OE# RY/BY#

GND

BYTE# NC NC

CE #

RP#

GND

CE #

RP#

GND

WP#

WE#

OE#

RY/BY#

GND

BYTE#

28F016SV28F016SA

CE #

RP#

GND

CE #

3/5#

CE #

3/5#

CE #

WP# WE#

OE# RY/BY#

GND

BYTE#

0490_02

Figure 2. Dual Die TSOP Pinout Configuration

3.0 MODES OF OPERATION

RP# CE0#CE

#CE

# 28F016SA

No. 1

28F016SA

No. 2

DD28F032S

Chip

0 X X X DPD DPD DPD 1 1 X X Standby Standby Standby 1 0 0 1 Standby Active Active 1 0 1 0 Active Standby Active 1 0 1 1 Standby Standby Standby 1 0 0 0 Illegal Condition

NOTES:

X = Don’t Care DPD = Deep Power-Down 28F016SA No. 1 = First 16-Mbit Device 28F016SA No. 2 = Second 16-Mbit Device

E DD28F032SA

4.0 MEMORY MAPS

64-Kbyte Bloc k

1FFFFF

1F0000

1EFFFF

1E0000

1DFFFF

1D0000

1CFFFF

1C0000

1BFFFF

30 29 28 27

1B0000

1AFFFF

1A0000

19FFFF

190000

18FFFF

180000

17FFFF

26 25 24 23

170000

16FFFF

160000

15FFFF

150000

14FFFF

140000

13FFFF

22 21 20 19

130000

12FFFF

120000

11FFFF

110000

10FFFF

100000

0FFFFF

18 17 16 15

0F0000

0EFFFF

0E0000

0DFFFF

0D0000

0CFFFF

0C0000

0BFFFF

14 13 12 11

0B0000

0AFFFF

0A0000

09FFFF

090000

08FFFF

080000

07FFFF

9 8 7

070000

06FFFF

060000

05FFFF

050000

04FFFF

040000

03FFFF

6 5 4 3

030000

02FFFF

020000

01FFFF

010000

00FFFF

000000

2 1 0

64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyt e Block 64-Kbyt e Block 64-Kbyte Bloc k 64-Kbyt e Block 64-Kbyte Bloc k 64-Kbyt e Block 64-Kbyte Bloc k 64-Kbyt e Block 64-Kbyte Bloc k 64-Kbyt e Block 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k

64-Kbyte Bloc k

1FFFFF

1F0000

1EFFFF

1E0000

1DFFFF

1D0000

1CFFFF

1C0000

1BFFFF

62 61 60 59

1B0000

1AFFFF

1A0000

19FFFF

190000

18FFFF

180000

17FFFF

58 57 56 55

170000

16FFFF

160000

15FFFF

150000

14FFFF

140000

13FFFF

54 53 52 51

130000

12FFFF

120000

11FFFF

110000

10FFFF

100000

0FFFFF

50 49 48 47

0F0000

0EFFFF

0E0000

0DFFFF

0D0000

0CFFFF

0C0000

0BFFFF

46 45 44 43

0B0000

0AFFFF

0A0000

09FFFF

090000

08FFFF

080000

07FFFF

42 41 40 39

070000

06FFFF

060000

05FFFF

050000

04FFFF

040000

03FFFF

38 37 36 35

030000

02FFFF

020000

01FFFF

010000

00FFFF

000000

34 33 32

64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Block 64-Kbyte Block 64-Kbyte Bloc k 64-Kbyte Block 64-Kbyte Bloc k 64-Kbyte Block 64-Kbyte Bloc k 64-Kbyte Block 64-Kbyte Bloc k 64-Kbyte Block 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k 64-Kbyte Bloc k

28F016SA No. 1 28F016SA No. 2

0490_03

Figure 3. DD28F032SA Memory Map (Byte-Wide Mode)

DD28F032SA E

4.1 Extended Status Registers Memory Map for Either 28F016SA No. 1 or 28F016SA No. 2

x8 MODE A[20-0]

. . .

1F0004H 1F0003H

1F0002H

1F0000H

1F0001H

1F0005H

1F0006H

000004H 000003H 000002H

000000H

000001H

000006H 000005H

010002H

RESERVED

GSR

RESERVED

BSR 0 RESERVED RESERVED

RESERVED

GSR

RESERVED

BSR 31

RESERVED RESERVED

0490_04

Figure 4. Extended Status Register Memory

Map (Byte-Wide Mode)

x16 MODE A[20-1]

. . .

00002H

00000H

00001H

00003H

08001H

RESERVED

GSR

RESERVED

BSR 0

RESERVED

F8002H

F8000H

F8001H

F8003H

RESERVED

GSR

RESERVED

BSR 31

RESERVED

0490_05

Figure 5. Extended Status Register Memory

Map (Word-Wide Mode)

E DD28F032SA

5.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS

5.1 Bus Operations for Word-Wide Mode (BYTE# = V

)

Mode Notes RP# CEX#

(8)

CE0# OE# WE# A

0–15

RY/BY#

Read 1,2,7 V

OUT

Output Disable 1,6,7 V

X High Z X

Standby 1,6,7 V

V V V

X X X High Z X

Deep Power-Down 1,3 V

X XXXXHigh Z V

Manufacturer ID 4 V

0089H V

Device ID 4 V

66A0H V

Write 1,5,6 V

XDINX

5.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL)

Mode Notes RP# CEX#

(8)

CE0# OE# WE# A

0–7

RY/BY#

Read 1,2,7 V

OUT

Output Disable 1,6,7 V

X High Z X

Standby 1,6,7 V

V V V

X X X High Z X

Deep Power-Down 1,3 V

X XXXXHigh Z V

Manufacturer ID 4 V

89H V

Device ID 4 V

A0H V

Write 1,5,6 V

XDINX

NOTES:

1. X can be V

or V

for address or control pins except for RY/BY#, which is either V

or V

2. RY/BY# output is open drain. When the WSM is ready, block erase is suspended or the device is in deep power-down mode, RY/BY# will be at V

if it is tied to V

through a resistor. RY/BY# at VOH is independent of OE# while a WSM

operation is in progress.

3. RP# at GND ± 0.2V ensures the lowest deep power-down current.

4. A

and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively. A0 and A1 at VIH provide device ID

codes in x8 and x16 modes respectively. All other addresses are set to zero.

5. Commands for different block erase operations, data program operations or lock-block operations can only be successfully completed when V

= V

PPH.

6. While the WSM is running, RY/BY# in level-mode (default) stays at VOL until all operations are complete. RY/BY# goes to V

when the WSM is not busy or in erase suspend mode.

7. RY/BY# may be at V

while the WSM is busy performing various operations; for example, a Status Register read during a

data program operation.

8. CE

# = CE1# or CE2#.

DD28F032SA E

5.3 28F008SA Compatible Mode Command Bus Definitions

First Bus Cycle Second Bus Cycle

Command Notes Oper Addr Data Oper Addr Data

Read Array Write X xxFFH Read AA AD Intelligent Identifier 1 Write X xx90H Read IA ID Read Compatible Status Register 2 Write X xx70H Read X CSRD Clear Status Register 3 Write X xx50H Word/Byte Program Write X xx40H Write PA PD Alternate Word/Byte Program Write X xx10H Write PA PD Block Erase/Confirm Write X xx20H Write BA xxD0H Erase Suspend/Resume Write X xxB0H Write X xxD0H

ADDRESS DATA

A = Array Address

AD = Array Data

BA = Block Address CSRD = CSR Data IA = Identifier Address ID = Identifier Data PA = Program Address PD = Program Data

X = Don’t Care

NOTES:

1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes.

2. The CSR is automatically available after device enters data program, block erase, or suspend operations.

3. Clears CSR.3, CSR.4 and CSR.4. Also clears GSR.4 and all BSR.4 and BSR.2 bits.

4. The upper byte of the data bus (DQ

8–15

) during command writes is a “Don’t Care” in x16 operation of the device.

See Status Register definitions.

E DD28F032SA

5.4 28F016SA-Performance Enhancement Command Bus Definitions

First Bus Cycle Second Bus Cycle Third Bus Cycle

Command Mode Notes Oper Addr Data

(12)

Oper Addr Data

(12)

Oper Addr Data

Read Extended Status Register

1 Write X xx71H Read RA GSRD

BSRD Page Buffer Swap 7 Write X xx72H Read Page Buffer Write X xx75H Read PBA PD Single Load to Page

Buffer

Write X xx74H Write PBA PD

Sequential Load to Page Buffer

x8 4,6,10 Write X xxE0H Write X BCL Write X BCH

x16 4,5,6,10 Write X xxE0H Write X WCL Write X WCH

Page Buffer Write to Flash

x8 3,4,9,10 Write X xx0CH Write A0BC(L,H) Write PA BC(H,L)

x16 4,5,10 Write X xx0CH Write X WCL Write PA WCH Two-Byte Write x8 3 Write X xxFBH Write A0WD(L,H) Write PA WD(H,L) Lock Block/Confirm Write X xx77H Write BA xxD0H Upload Status

Bits/Confirm

2 Write X xx97H Write X xxD0H

Upload Device Information

Write X xx99H Write X xxD0H

Erase All Unlocked Blocks/Confirm

Write X xxA7H Write X xxD0H

RY/BY# Enable to Level-Mode

8 Write X xx96H Write X xx01H

RY/BY# Pulse-OnWrite

8 Write X xx96H Write X xx02H

RY/BY# Pulse-OnErase

8 Write X xx96H Write X xx03H

RY/BY# Disable 8 Write X xx96H Write X xx04H Sleep 11 Write X xxF0H Abort Write X xx80H

ADDRESS DATA

BA = Block Address AD = Array Data WC (L,H) = Word Count (Low, High) PBA = Page Buffer Address PD = Page Buffer Data BC (L,H) = Byte Count (Low, High) RA = Extended Register Address BSRD = BSR Data WD (L,H) = Write Data (Low, High) PA = Program Address GSRD = GSR Data

X = Don’t Care

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Intel Corporation DD28F032SA-80, DD28F032SA-70, DD28F032SA-100 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual