Intel Corporation E28F320J5-100, DA28F320J5-100 Datasheet
E
PRELIMINARY
July 1998 Order Number: 290606-006
n
High-Density Symmetrically-Blocked
Architecture
64 128-Kbyte Erase Blocks (64 M)
32 128-Kbyte Erase Blocks (32 M)
n
4.5 V–5.5 V VCC Operation
2.7 V–3.6 V and 4.5 V–5.5 V I/O
Capable
n
Configurable x8 or x16 I/O
n
100 ns Read Access Time (32 M)
150 ns Read Access Time (64 M)
n
Enhanced Data Protection Features
Absolute Protection with
V
PEN
= GND
Flexible Block Locking
Block Erase/Program Lockout
during Power Transitions
n
Industry-Standard Packaging
µBGA* Package (64 M), SSOP and
TSOP Packages (32 M)
n
Cross-Compatible Command Support
Intel Basic Command Set
Common Flash Interface
Scaleable Command Set
n
32-Byte Write Buffer
6.3 µs per Byte Effective
Programming Time
n
6,400,000 Total Erase Cycles (64 M)
3,200,000 Total Erase Cycles (32 M)
100,000 Erase Cycles per Block
n
Automation Suspend Options
Block Erase Suspend to Read
Block Erase Suspend to Program
n
System Performance Enhancements
STS Status Output
n
Expanded Temperature Operation
–20 °C to +70 °C
n
Intel® StrataFlash™ Memory Flash
Technology
Capitalizing on two-bit-per-cell technol ogy, Intel® StrataFlash™ mem ory products provide 2X the bits in 1X
the space. Offered in 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel Strat aFlash memory devices
are the first to bring reliable, two-bit-per-cell storage technology to the flash market.
Intel StrataFlash memory benefits include: more density in less space, lowest cost-per-bit NOR devices,
support for code and data storage, and easy migration to future devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash
memory
devices take advantage of 400 million units of manufacturing experience since 1988. As a result,
Intel StrataFlash com ponents are ideal for code or data applications where high density and low cos t are
required. Examples include networking, telecommunications, audio recording, and digital imaging.
By applying FlashFile™ mem ory family pinouts, Intel StrataFlash mem ory components allow easy design
migrations from existing 28F016S A/SV, 28F032SA, and Word-W ide FlashFile memory devices (28F160S5
and 28F320S5).
Intel StrataFlash memory com ponents deliver a new generation of forward-compatible software support. By
using the Common Flash Interface (CFI) and the Scaleable Command Set (SCS), customers can take
advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices.
Manufactured on Intel’s 0.4 m icron ETOX™ V process technology, Int el StrataFlash memory provi des the
highest levels of quality and reliability.
INTEL® StrataFlash™ MEMORY TECHNOLOGY
32 AND 64 MBIT
28F320J5 and 28F640J5
2
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided i n Intel’s Terms and Conditi ons of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F320J5 and 28F640J4 may contain design defects or errors known as errata. Current characterized errata are available
on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 8021-9808
or call 1-800-548-4725
or visit Intel’s website at http://www.intel.com
COPYRIGHT © INTEL CORPORATION 1997, 1998 CG-041493
*Third-party brands and names are the property of their respective owners.
E INTEL
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
3
PRELIMINARY
CONTENTS
PAGE PAGE
1.0 PRODUCT OVERVIEW...................................5
2.0 PRINCIPLES OF OPERATION .....................11
2.1 Data Protection ..........................................12
3.0 BUS OPERATION.........................................12
3.1 Read..........................................................13
3.2 Output Disable...........................................13
3.3 Standby......................................................13
3.4 Reset/Power-Down....................................13
3.5 Read Query................................................14
3.6 Read Identifier Codes.................................14
3.7 Write ..........................................................14
4.0 COMMAND DEFINITIONS............................14
4.1 Read Array Command................................18
4.2 Read Query Mode Command.....................18
4.2.1 Query Structure Output .......................18
4.2.2 Query Structure Overview ...................20
4.2.3 Block Status Register..........................21
4.2.4 CFI Query Identification String.............22
4.2.5 System Interface Information...............23
4.2.6 Device Geometry Definition.................24
4.2.7 Primary-Vendor Specific Extended
Query Table .......................................25
4.3 Read Identifier Codes Command...............26
4.4 Read Status Register Command................27
4.5 Clear Status Register Command................27
4.6 Block Erase Command ..............................27
4.7 Block Erase Suspend Command................27
4.8 Write to Buffer Command...........................28
4.9 Byte/Word Program Commands.................28
4.10 Configuration Command...........................29
4.11 Set Block and Master Lock-Bit
Commands................................................29
4.12 Clear Block Lock-Bits Command..............30
5.0 DESIGN CONSIDERATIONS........................40
5.1 Three-Line Output Control..........................40
5.2 STS and Block Erase, Program, and Lock-
Bit Configuration Polling............................40
5.3 Power Supply Decoupling ..........................40
5.4 V
CC
, V
PEN
, RP# Transitions........................40
5.5 Power-Up/Down Protection........................41
5.6 Power Dissipation.......................................41
6.0 ELECTRICAL SPECIFICATIONS..................42
6.1 Absolute Maximum Ratings........................42
6.2 Operating Conditions..................................42
6.3 Capacitance...............................................42
6.4 DC Characteristics .....................................43
6.5 AC Characteristics—Read-Only
Operations.................................................46
6.6 AC Characteristics— Write Operations.......48
6.7 Block Erase, Program, and Lock-Bit
Configuration Performance........................51
7.0 ORDERING INFORMATION..........................52
8.0 ADDITIONAL INFORMATION.......................53
INTEL
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT E
4
PRELIMINARY
REVISION HISTORY
Date of
Revision
Version Description
09/01/97 -001 Original Version
09/17/97 -002 Modifications made to cover sheet
12/01/97 -003 VCC/GND Pins Converted to No Connects specification change added
I
CCS
, I
CCD
, I
CCW
, and I
CCE
specification change added
Order Codes specification change added
1/31/98 -004 The µBGA* chip-scale package in Figure 2 was changed to a 52-ball
package and appropriate documentation added. The 64-Mb µBGA
package dimensions were changed in Figure 2. Changed Figure 4 to read
SSOP instead of TSOP.
3/23/98 -005 32-Mbit Intel StrataFlash memory read access time added. The number
of block erase cycles was changed. The write buffer program time was
changed. The operating temperature was changed. A read parameter
was added. Several program, erase, and lock-bit specifications were
changed. Minor documentation changes were made as well. Datasheet
designation changed from Advance Information to Preliminary.
7/13/98 -006 Intel StrataFlash memory 32-Mb µBGA package removed. t
EHEL
read
specification reduced. Table 4 was modified. The
Ordering Information
was updated.
E INTEL
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
5
PRELIMINARY
1.0 PRODUCT OVERVIEW
The Intel® StrataFlash™ memory famil y contains
high-density memories organiz ed as 8 Mbytes or
4 Mwords (64-Mbit) and 4 Mbytes or 2 Mwords
(32-Mbit). These devices can be accessed as 8- or
16-bit words. The 64-Mbit devic e is organized as
sixty-four 128-Kbyt e (131,072 bytes) erase block s
while the 32-Mbits device c ontains thirty-two 128Kbyte erase blocks. Blocks are selectively and
individually lockable and unlockable in-system.
See the memory map in Figure 5.
A Common Flash Interface (CFI) permits software
algorithms to be used for entire families of
devices. This allows device-independent, JEDEC
ID-independent, and forward- and backwardcompatible software support for the s pecified fl ash
device families. Flash vendors can standardize
their existing interfaces for long-term compatibility.
Scaleable Command Set (SCS) allows a single,
simple software driver in all host systems to work
with all SCS-compliant flash memory devices,
independent of system-level packaging (e.g.,
memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest
system/device data transfer rates and minimizes
device and system-level implementation costs.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid c ommand
sequence written to the CUI initiates device
automation. An internal Write State Machine
(WSM) automatically ex ecutes the algorithms and
timings necessary for block erase, program, and
lock-bit configuration operations.
A block erase operation erases one of the devic e’s
128-Kbyte blocks typically within one second—
independent of other blocks. Each block can be
independently erased 100,000 times . Block erase
suspend mode allows system software to suspend
block erase to read or program data from any
other block.
Each device incorporates a Write Buffer of
32 bytes (16 words) to allow optimum
programming performance. By using the Write
Buffer, data is programmed in buffer increments.
This feature can improve system program
performance by up to 20 times over non Write
Buffer writes.
Individual block locking us es a combi nation of bit s,
block lock-bits and a m aster lock-bit, to lock and
unlock blocks. Block lock-bits gate block erase
and program operations while the master l ock-bit
gates block lock-bit modification. Three lock-bit
configuration operations set and clear lock-bits
(Set Block Lock-Bit, Set Master Lock-Bit, and
Clear Block Lock-Bits commands).
The status register indicates when the WSM’s
block erase, program, or lock-bit configuration
operation is finished.
The STS (STATUS) output gives an additional
indicator of WSM activity by providing both a
hardware signal of status (vers us software polling)
and status masking (interrupt masking for
background block erase, for example). Status
indication using STS minimizes both CPU
overhead and system power consumption. When
configured in level mode (default mode), it acts as
a RY/BY# pin. When low, STS indicat es that the
WSM is performing a block erase, program, or
lock-bit configuration. S TS-high indicates that the
WSM is ready for a new command, block erase is
suspended (and programming is inactive), or the
device is in reset/power-down m ode. Additionally,
the configuration command all ows the STS pin to
be configured to pulse on completion of
programming and/or block erases.
Three CE pins are used to enable and disable the
device. A unique CE logic design (see Table 2,
Chip Enable Truth Table
) reduces decoder logic
typically required for multi-chip designs. External
logic is not required when designing a s ingle chip,
a dual chip, or a 4-chip miniature card or SIMM
module.
The BYTE# pin allows either x8 or x16 read/writes
to the device. BYTE# at logic low selects 8-bit
mode; address A
0
selects between the low byte
and high byte. BYTE# at logic hi gh enables 16-bit
operation; address A
1
becomes the lowest order
address and address A
0
is not used (don’t care). A
device block diagram is shown in Figure 1.
When the device is disabled (see Table 2,
Chip
Enable Truth Table
) and the RP# pin is at VCC, the
standby mode is enabled. When the RP # pin is at
GND, a further power-down mode is enabled
which minimizes power consumpti on and provides
write protection during reset. A res et time (t
PHQV
)
is required from RP# switchi ng high until outputs
INTEL
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT E
6
PRELIMINARY
are valid. Likewise, the device has a wake time
(t
PHWL
) from RP#-high until writes to t he CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.
The Intel StrataFlash memory devices are
available in several package t ypes. The 64-Mbit is
available in 56-lead SSOP (Shrink Small Outline
Package) and µBGA* package (micro Ball Grid
Array). The 32-Mbit is availabl e in 56-lead TSOP
(Thin Small Outline Package) and 56-lead SSOP.
Figures 2, 3, and 4 show the pinouts.
32-Mbit: Thirty-two
64-Mbit: Sixty-four
128-Kbyte Blocks
Input Buffer
Output
Multiplexer
Y-Gating
Program/Erase
Voltage Switch
Data
Comparator
Status
Register
Identifier
Register
Data
Register
I/O Logic
Address
Latch
Address
Counter
X-Decoder
Y-Decoder
Input Buffer
Output Buffer
GND
V
CC
V
PEN
CE
0
CE
1
CE
2
WE#
OE#
RP#
BYTE#
Command
User
Interface
32-Mbit: A0- A
21
64-Mbit: A
0 - A22
DQ0 - DQ
15
V
CC
Write Buffer
Write State
Machine
Multiplexer
Query
STS
V
CCQ
CE
Logic
0606_01
Figure 1. Intel® StrataFlash™ Memory Block Diagram
E INTEL
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
7
PRELIMINARY
Table 1. Lead Descriptions
Symbol Type Name and Function
A
0
INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when the device
is in x8 mode. This address is latched during a x8 program cycle. Not used in
x16 mode (i.e., the A
0
input buffer is turned off when BYTE# is high).
A1–A
22
INPUT ADDRESS INPUTS: Inputs for addresses during read and program operations.
Addresses are internally latched during a program cycle.
32-Mbit: A
0–A21
64-Mbit: A0–A
22
DQ0–DQ
7
INPUT/
OUTPUT
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and
inputs commands during Command User Interface (CUI) writes. Outputs array,
query, identifier, or status data in the appropriate read mode. Floated when the
chip is de-selected or the outputs are disabled. Outputs DQ
6
–DQ0 are also
floated when the Write State Machine (WSM) is busy. Check SR.7 (Status
Register bit 7) to determine WSM status.
DQ8–DQ
15
INPUT/
OUTPUT
HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming
operations. Outputs array, query, or identifier data in the appropriate read mode;
not used for Status Register reads. Floated when the chip is de-selected, the
outputs are disabled, or the WSM is busy.
CE0,
CE
1
,
CE
2
INPUT CHIP ENABLES: Activates the device’s control logic, input buffers, decoders,
and sense amplifiers. When the device is de-selected (see Table 2,
Chip Enable
Truth Table
), power reduces to standby levels.
All timing specifications are the same for these three signals. Device selection
occurs with the first edge of CE
0
, CE1, or CE2 that enables the device. Device
deselection occurs with the first edge of CE
0
, CE1, or CE2 that disables the
device (see Table 2,
Chip Enable Truth Table
).
RP# INPUT RESET/ POWER-DOWN: Resets internal automation and puts the device in
power-down mode. RP#-high enables normal operation. Exit from reset sets the
device to read array mode. When driven low, RP# inhibits write operations which
provides data protection during power transitions.
RP# at V
HH
enables master lock-bit setting and block lock-bits configuration
when the master lock-bit is set. RP# = V
HH
overrides block lock-bits thereby
enabling block erase and programming operations to locked memory blocks. Do
not permanently connect RP# to V
HH
.
OE# INPUT OUTPUT ENABLE: Activates the device’s outputs through the data buffers
during a read cycle. OE# is active low.
WE# INPUT WRITE ENABLE: Controls writes to the Command User Interface, the Write
Buffer, and array blocks. WE# is active low. Addresses and data are latched on
the rising edge of the WE# pulse.
STS OPEN
DRAIN
OUTPUT
STATUS: Indicates the status of the internal state machine. When configured in
level mode (default mode), it acts as a RY/BY# pin. When configured in one of
its pulse modes, it can pulse to indicate program and/or erase completion. For
alternate configurations of the STATUS pin, see the Configurations command.
Tie STS to V
CCQ
with a pull-up resistor.
INTEL
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT E
8
PRELIMINARY
Table 1. Lead Descriptions (Continued)
Symbol Type Name and Function
BYTE# INPUT BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input
or output on DQ
0
–DQ7, while DQ8–DQ15 float. Address A0 selects between the
high and low byte. BYTE# high places the device in x16 mode, and turns off the
A
0
input buffer. Address A1 then becomes the lowest order address.
V
PEN
INPUT ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks,
programming data, or configuring lock-bits.
With V
PEN
≤ V
PENLK
, memory contents cannot be altered.
V
CC
SUPPLY DEVICE POWER SUPPLY: With VCC ≤ V
LKO
, all write attempts to the flash
memory are inhibited.
V
CCQ
OUTPUT
BUFFER
SUPPLY
OUTPUT BUFFER POWER SUPPLY: This voltage controls the device’s output
voltages. To obtain output voltages compatible with system data bus voltages,
connect V
CCQ
to the system supply voltage.
GND SUPPLY GROUND: Do not float any ground pins.
NC NO CONNECT: Lead is not internally connected; it may be driven or floated.
E INTEL
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
9
PRELIMINARY
GND A10V
PENCE0A14VCC
A7A9A11A12A15A
17
A
4
A
19
A6A8RP# A13A16A
21
A
5
A
20
A1A
3
A18CE
1
A
2
A
22
BYTE# DQ
7
CE
2
WE#
DQ8DQ
1
DQ6DQ
15
A
0
OE#DQ3DQ
12
DQ9DQ
2
DQ13DQ
14
DQ
0
STSDQ11DQ
4
V
CC
(1)
DQ
10
DQ5GND
(1)
GND V
CCQ
GNDA
10
V
PEN
CE
0
A
14
V
CC
A
7
A
9
A
11
A
12
A
15
A
17
A
4
A
19
A
6
A
8
RP#A
13
A
16
A
21
A
5
A
20
A
1
A
3
A
18
CE
1
A
2
A
22
BYTE#DQ
7
CE
2
WE#
DQ
8
DQ
1
DQ
6
DQ
15
A
0
OE# DQ
3
DQ
12
DQ
9
DQ
2
DQ
13
DQ
14
DQ
0
STS DQ
11
DQ
4
V
CC
(1)
DQ
10
DQ
5
GND
(1)
GNDV
CCQ
A
B
C
D
E
F
G
H
I
A
B
C
D
E
F
G
H
I
78 6543
21
21 3456
78
Top ViewBottom View - Ball Side Up
NC
(1)
NC
(1)
NC
(1)
NC
(1)
64-Mbit Intel® StrataFlash™ Memory: 7.67 mm x 16.37 mm
NOTE:
1. VCC (Ball I7), GND (Ball I2), and NC (Balls F2 and F7) have been removed. Future generations of Intel StrataFlash
memory may make use of these missing ball locations.
Figures are not drawn to scale.
Figure 2. µBGA* Package (64 Mbit)
INTEL
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT E
10
PRELIMINARY
28F320J5
Intel® StrataFlash™ Memory
56-Lead TSOP
Standard Pinout
14 mm x 20 mm
Top View
1
3
4
2
5
7
8
6
9
11
12
10
13
15
16
14
17
19
20
18
21
23
24
22
25
27
28
26
56
54
53
55
52
50
49
51
48
46
45
47
44
42
41
43
40
38
37
39
36
34
33
35
32
30
29
31
NC
A
21
A
20
CE
1
A
19
A
17
A
16
A
18
V
CC
A
14
A
13
A
15
A
12
V
PEN
RP#
CE
0
A
11
A
9
A
8
A
10
GND
A
6
A
5
A
7
A
4
A
2
A
1
A
3
28F016SV
28F016SA
28F032SA
3/5#
NC
A
20
CE
1
A
19
A
17
A
16
A
18
V
CC
A
14
A
13
A
15
A
12
V
PP
RP#
CE
0
A
11
A
9
A
8
A
10
GND
A
6
A
5
A
7
A
4
A
2
A
1
A
3
3/5#
CE
2
A
20
CE
1
A
19
A
17
A
16
A
18
V
CC
A
14
A
13
A
15
A
12
V
PP
RP#
CE
0
A
11
A
9
A
8
A
10
Highlights pinout changes
A
6
A
5
A
7
A
4
A
2
A
1
A
3
GND
28F160S5
NC
NC
A
20
CE
1
A
19
A
17
A
16
A
18
V
CC
A
14
A
13
A
15
A
12
V
PP
RP#
CE
0
A
11
A
9
A
8
A
10
A
6
A
5
A
7
A
4
A
2
A
1
A
3
GND
NC
OE#
STS
WE#
DQ
15
DQ
14
DQ
6
DQ
7
GND
DQ
5
DQ
12
DQ
13
DQ
4
GND
DQ
11
V
CCQ
DQ
3
DQ
2
V
CC
DQ
10
DQ
9
DQ
8
DQ
0
DQ
1
A
0
NC
CE
2
BYTE#
28F016SV
28F016SA
28F032SA
WP#
OE#
RY/BY#
WE#
DQ
15
DQ
14
DQ
6
DQ
7
GND
DQ
5
DQ
12
DQ
13
GND
DQ
11
DQ
3
DQ
2
V
CC
DQ
10
DQ
9
DQ
8
DQ
0
DQ
1
A
0
NC
NC
BYTE#
WP#
OE#
RY/BY#
WE#
DQ
15
DQ
14
DQ
6
DQ
7
GND
DQ
5
DQ
12
DQ
13
DQ
11
DQ
3
DQ
2
V
CC
DQ
10
DQ
9
DQ
8
DQ
0
DQ
1
A
0
NC
NC
BYTE#
28F320J5 28F160S5
WP#
OE#
STS
WE#
DQ
15
DQ
14
DQ
6
DQ
7
GND
DQ
5
DQ
12
DQ
13
GND
DQ
11
DQ
3
DQ
2
V
CC
DQ
10
DQ
9
DQ
8
DQ
0
DQ
1
A
0
NC
NC
BYTE#
V
CC
DQ
4
GND
V
CCVCC
DQ4DQ
4
0606_03
NOTE:
1. VCC (Pin 37) and GND (Pin 48) are not internally connected. For future device revisions, it is recommended that these
pins be connected to their respected power supplies (i.e., Pin 37 = VCC and Pin 48 = GND).
2. For compatibility with future generations of Intel® StrataFlash™ memory, this NC (pin 56) should be connected to GND.
Figure 3. TSOP Lead Configuration (32 Mbit)
E INTEL
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
11
PRELIMINARY
Intel
®
StrataFlash™ Memory
56-Lead SSOP
Standard Pinout
16 mm x 23.7 mm
Top View
1
3
4
2
5
7
8
6
9
11
12
10
13
15
16
14
17
19
20
18
21
23
24
22
25
27
28
26
56
54
53
55
52
50
49
51
48
46
45
47
44
42
41
43
40
38
37
39
36
34
33
35
32
30
29
31
V
PEN
A
11
A
10
RP#
A
9
A
2
A
3
A
1
A
4
A
6
A
7
A
5
GND
V
CC
DQ
9
A
8
DQ
1
DQ
0
A
0
DQ
8
BYTE#
CE
2
DQ
2
NC
DQ
10
DQ
11
GND
DQ
3
V
PEN
A
11
A
10
RP#
A
9
A
2
A
3
A
1
A
4
A
6
A
7
A
5
GND
V
CC
DQ
9
A
8
DQ
1
DQ
0
A
0
DQ
8
BYTE#
CE
2
DQ
2
NC
DQ
10
DQ
11
GND
DQ
3
V
PP
A
11
A
10
RP#
A
9
A
2
A
3
A
1
A
4
A
6
A
7
A
5
GND
V
CC
DQ
9
A
8
DQ
1
DQ
0
A
0
DQ
8
BYTE#
NC
DQ
2
NC
DQ
10
DQ
11
GND
DQ
3
28F640J5 28F320J5 28F320S528F640J528F320J5
Highlights pinout changes.
28F320S5
RY/BY#
28F160S5
28F016SV
28F016SA
CE
0
A
13
A
14
A
12
A
15
CE
1
A
21
NC
A
20
A
18
A
17
A
19
A
16
DQ
6
V
CC
DQ
14
DQ
15
STS
DQ
7
OE#
NC
DQ
13
WE#
DQ
5
DQ
4
V
CCQ
DQ
12
GND
CE
0
A
13
A
14
A
12
A
15
CE
1
A
21
A
20
A
18
A
17
A
19
A
16
DQ
6
V
CC
DQ
14
DQ
15
STS
DQ
7
OE#
NC
DQ
13
WE#
DQ
5
DQ
4
V
CCQ
DQ
12
A
22
GND
CE0#
A
13
A
14
A
12
A
15
CE1#
NC
A
20
A
18
A
17
A
19
A
16
GND
DQ
6
V
CC
DQ
14
DQ
15
RY/BY#
DQ
7
OE#
WP#
DQ
13
WE#
DQ
5
DQ
4
V
CC
DQ
12
A
21
CE0#
A
13
A
14
A
12
A
15
CE1#
NC
A
20
A
18
A
17
A
19
A
16
GND
DQ
6
V
CC
DQ
14
DQ
15
DQ
7
OE#
WP#
DQ
13
WE#
DQ
5
DQ
4
V
CC
DQ
12
NC
CE0#
A
13
A
14
A
12
A
15
CE1#
3/5#
A
20
A
18
A
17
A
19
A
16
GND
DQ
6
V
CC
DQ
14
DQ
15
RY/BY#
DQ
7
OE#
WP#
DQ
13
WE#
DQ
5
DQ
4
V
CC
DQ
12
NC
V
PP
A
11
A
10
RP#
A
9
A
2
A
3
A
1
A
4
A
6
A
7
A
5
GND
V
CC
DQ
9
A
8
DQ
1
DQ
0
A
0
DQ
8
BYTE#
NC
DQ
2
NC
DQ
10
DQ
11
GND
DQ
3
28F160S5
V
PP
A
11
A
10
RP#
A
9
A
2
A
3
A
1
A
4
A
6
A
7
A
5
GND
V
CC
DQ
9
A
8
DQ
1
DQ
0
A
0
DQ
8
BYTE#
NC
DQ
2
NC
DQ
10
DQ
11
GND
DQ
3
28F016SV
28F016SA
0606_04
NOTE:
1. VCC (Pin 42) and GND (Pin 15) are not internally connected. For future device revisions, it is recommended that these
pins be connected to their respected power supplies (i.e., Pin 42 = VCC and Pin 15 = GND).
2. For compatibility with future generations of Intel StrataFlash memory, this NC (pin 23) should be connected to GND
Figure 4. SSOP Lead Configuration (64 Mbit and 32 Mbit)
2.0 PRINCIPLES OF OPERATION
The Intel StrataFlash memory devices include an
on-chip WSM to manage block eras e, program, and
lock-bit configuration functions. It allows for 100%
TTL-level control inputs, fixed power supplies
during block erasure, program, lock-bit
configuration, and minimal process or overhead with
RAM-like interface timings.
After initial device power-up or return from
reset/power-down mode (see Bus Operations), the
device defaults to read array mode. Manipul ation of
external memory control pins allows array read,
standby, and output disable operations.
Read array, status register, query, and identifier
codes can be accessed through the CUI (Command
User Interface) independent of the V
PEN
voltage.
INTEL
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT E
12
PRELIMINARY
V
PENH
on V
PEN
enables successful block erasure,
programming, and lock-bit configuration. All
functions associated with altering memory
contents—block erase, program, lock-bit
configuration—are accessed via the CUI and
verified through the status register.
Commands are written using standard microprocessor write timings . The CUI cont ents s erve as
input to the WSM, which c ontrols the block erase,
program, and lock-bit configuration. The internal
algorithms are regulated by the WSM, including
pulse repetition, internal v erification, and margini ng
of data. Addresses and data are internally lat ched
during program cycles.
Interface software that initiates and polls progress
of block erase, program, and lock-bit configuration
can be stored in any block. This code is c opied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system
software to suspend a block erase to read or
program data from/to any other block.
2.1 Data Protection
Depending on the application, the system designer
may choose to make the V
PEN
switchable (availabl e
only when memory block erases , program s, or loc kbit configurations are required) or hardwired to
V
PENH
. The device accommodates either design
practice and encourages optimization of the
processor-memory interface.
When V
PEN
≤ V
PENLK
, memory contents c annot be
altered. The CUI’s two-step block erase, byte/word
program, and lock-bit configuration command
sequences provide protection from unwanted
operations even when V
PENH
is applied to V
PEN
. All
program functions are disabled when V
CC
is below
the write lockout v oltage V
LKO
or when RP# is VIL.
The device’s block locking capability provides
additional protection from inadv ertent code or data
alteration by gating erase and program operations.
3.0 BUS OPERATION
The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
64-Kword Block
64-Kword Block
64-Kword Block
64-Kword Block
31
1
0
63
Word Wide (x16) Mode
1FFFFF
1F0000
3FFFFF
3F0000
01FFFF
010000
00FFFF
000000
A [22-1]: 64-Mbit
A [21-1]: 32-Mbit
128-Kbyte Block
128-Kbyte Block
128-Kbyte Block
128-Kbyte Block
31
1
0
63
Byte-Wide (x8) Mode
3FFFFF
3E0000
7FFFFF
7E0000
03FFFF
020000
01FFFF
000000
A [22-0]: 64-Mbit
A [21-0]: 32-Mbit
32-Mbit
64-Mbit
0606_05
Figure 5. Memory Map
E INTEL
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
13
PRELIMINARY
Table 2. Chip Enable Truth Table
(1,2)
CE
2
CE
1
CE
0
DEVICE
V
IL
V
IL
V
IL
Enabled
V
IL
V
IL
V
IH
Disabled
V
IL
V
IH
V
IL
Disabled
V
IL
V
IH
V
IH
Disabled
V
IH
V
IL
V
IL
Enabled
V
IH
V
IL
V
IH
Enabled
V
IH
V
IH
V
IL
Enabled
V
IH
V
IH
V
IH
Disabled
NOTE:
1. See Application Note
AP-647 Intel StrataFlash™
Memory Design Guide
for typical CE configurations.
2. For single-chip applications CE
2
and CE1 can be
strapped to GND.
3.1 Read
Information can be read from any block, query,
identifier codes, or status register independent of
the V
PEN
voltage. RP# can be at either VIH or VHH.
Upon initial device power-up or after exit from
reset/power-down mode, the device automatically
resets to read array mode. Otherwise, write the
appropriate read mode command (Read Array,
Read Query, Read Identifier Codes, or Read St atus
Register) to the CUI. Six control pins dictate the
data flow in and out of the component: CE
0
, CE1,
CE
2
, OE#, WE#, and RP#. The device must be
enabled (see Table 2,
Chip Enable Truth Table
),
and OE# must be driven activ e to obt ain data at the
outputs. CE
0
, CE1, and CE2 are the device
selection controls and, when enabled (see Table 2,
Chip Enable Truth Table
), select the memory
device. OE# is the data output (DQ
0
–DQ15) control
and, when active, drives the select ed memory data
onto the I/O bus. WE# must be at V
IH
.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ
0
–DQ15 are
placed in a high-impedance state.
3.3 Standby
CE0, CE1, and CE2 can disable the device (see
Table 2,
Chip Enable Truth Table
) and place it in
standby mode which substantially reduces device
power consumption. DQ
0
–DQ15 outputs are placed
in a high-impedance state independent of OE#. If
deselected during block erase, program, or lock-bit
configuration, the WSM continues f unctioning, and
consuming active power until the operation
completes.
3.4 Reset/Power-Down
RP# at VIL initiates the reset/power-down mode.
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state,
and turns off numerous internal circui ts. RP# must
be held low for a minimum of t
PLPH
. Time t
PHQV
is
required after return from reset mode until initial
memory access outputs are valid. After this wakeup interval, normal operation is rest ored. The CUI is
reset to read array mode and status regis ter is set
to 80H.
During block erase, program, or lock-bit
configuration modes, RP#-low will abort the
operation. In default mode, ST S transiti ons low and
remains low for a maximum time of t
PLPH
+ t
PHRH
until the reset operation is complete. Memory
contents being altered are no longer v alid; the data
may be partially corrupted after a program or
partially altered after an erase or lock-bit
configuration. Time t
PHWL
is required after RP#
goes to logic-high (V
IH
) before another command
can be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it ex pect s t o read from t he flas h
memory. Automated flash memori es provide status
information when accessed during block erase,
program, or lock-bit confi guration modes. If a CP U
reset occurs with no flash memory reset, proper
initialization may not occur because the flash
memory may be providing status information
instead of array data. Int el’s flash memories allow
proper initialization foll owi ng a system reset through
the use of the RP# input. In t his applicat ion, RP# is
controlled by the same RESET# signal that resets
the system CPU.
INTEL
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT E
14
PRELIMINARY
3.5 Read Query
The read query operation outputs block status
information, CFI (Common Flash Interface) ID
string, system interface information, device
geometry information, and Intel-specific extended
query information.
3.6 Read Identifier Codes
The read identifier codes operation outputs the
manufacturer code, device code, block lock
configuration codes for each block, and the master
lock configuration code (see Figure 6). Using the
manufacturer and device codes, the system CPU
can automatically match t he device with its proper
algorithms. The block lock and master lock
configuration codes identify locked and unlocked
blocks and master lock-bit setting.
3.7 Write
Writing commands to the CUI enables reading of
device data, query, identi fier codes, inspecti on and
clearing of the status register, and, when V
PEN
=
V
PENH
, block erasure, program, and lock-bit
configuration.
The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Byte/Word Program command
requires the command and address of the location
to be written. Set Master and Block Lock-Bit
commands require the command and address
within the device (Master Lock) or bl ock within the
device (Block Lock ) to be locked. The Clear Block
Lock-Bits command requires the command and
address within the device.
The CUI does not occupy an address able memory
location. It is written when the device is enabled
and WE# is active. The address and data needed to
execute a command are latched on the risi ng edge
of WE# or the first edge of CE
0
, CE1, or CE2 that
disables the device (see Table 2,
Chip Enable Truth
Table
). Standard microprocessor write timings are
used.
4.0 COMMAND DEFINITIONS
When the V
PEN
voltage ≤ V
PENLK
, only read
operations from the status regis ter, query, identif ier
codes, or blocks are enabled. Placing V
PENH
on
V
PEN
additionally enables block erase, program,
and lock-bit configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these
commands.
Reserved for Future
Implementation
Reserved for Future
Implementation
(Blocks 32 through 62)
Reserved for Future
Implementation
Reserved for Future
Implementation
(Blocks 2 through 30)
Reserved for Future
Implementation
Reserved for Future
Implementation
Block 63
Block 31
Block 1
Block 0 Lock Configuration
Reserved for Future
Implementation
Block 0
Master Lock Configuration
Manufacturer Code
Device Code
3FFFFF
3F0003
3F0002
3F0000
3EFFFF
1EFFFF
1F0003
1F0002
1F0000
01FFFF
010003
010002
010000
00FFFF
000004
000003
000002
000001
000000
32 Mbit
64 Mbit
Word
Address
A[22-1]: 64 Mbit
A[21-1]: 32 Mbit
Block 31 Lock Configuration
Block 63 Lock Configuration
Block 1 Lock Configuration
0606_06
NOTE:
A0 is not used in either x8 or x16 modes when obtaining
these identifier codes. Data is always given on the low byte
in x16 mode (upper byte contains 00h).
Figure 6. Device Identifier Code Memory Map
E INTEL
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
15
PRELIMINARY
Table 3. Bus Operations
Mode Notes RP# CE
0,1,2
(10)
OE#
(11)
WE#
(11)
Address V
PEN
DQ
(8)
STS
(default
mode)
Read Array 1,2,3 VIH or
V
HH
Enabled V
IL
V
IH
XX D
OUT
High Z
(9)
Output
Disable
VIH or
V
HH
Enabled V
IH
V
IH
X X High Z X
Standby VIH or
V
HH
Disabled X X X X High Z X
Reset/PowerDown Mode
V
IL
X X X X X High Z High Z
(9)
Read
Identifier
Codes
VIH or
V
HH
Enabled V
IL
V
IH
See
Figure 6
X Note 4 High Z
(9)
Read Query VIH or
V
HH
Enabled V
IL
V
IH
See
Table 7
X Note 5 High Z
(9)
Read Status
(WSM off)
VIH or
V
HH
Enabled V
IL
V
IH
XX D
OUT
Read Status
(WSM on)
VIH or
V
HH
Enabled V
IL
V
IH
XV
PENH
DQ7 = D
OUT
DQ
15–8
= High Z
DQ
6–0
= High Z
Write 3,6,7 VIH or
V
HH
Enabled V
IH
V
IL
XX D
IN
X
NOTES:
1. Refer to
DC Characteristics
. When V
PEN
≤ V
PENLK
, memory contents can be read, but not altered.
2. X can be V
IL
or VIH for control and address pins, and V
PENLK
or V
PENH
for V
PEN
. See
DC Characteristics
for V
PENLK
and
V
PENH
voltages.
3. In default mode, STS is V
OL
when the WSM is executing internal block erase, program, or lock-bit configuration algorithms.
It is V
OH
when the WSM is not busy, in block erase suspend mode (with programming inactive), or reset/power-down
mode.
4. See
Read Identifier Codes Command
section for read identifier code data.
5. See
Read Query Mode Command
section for read query data.
6. Command writes involving block erase, program, or lock-bit configuration are reliably executed when V
PEN
= V
PENH
and
V
CC
is within specification. Block erase, program, or lock-bit configuration with VIH < RP# < VHH produce spurious results
and should not be attempted.
7. Refer to Table 4 for valid D
IN
during a write operation.
8. DQ refers to DQ
0
–DQ7 if BYTE# is low and DQ0–DQ15 if BYTE# is high.
9. High Z will be V
OH
with an external pull-up resistor.
10. See Table 2 for valid CE configurations.
11. OE# and WE# should never be enabled simultaneously.
INTEL
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT E
16
PRELIMINARY
Table 4. Intel® StrataFlash™ Memory Command Set Definitions
(14)
Command Scaleable
or Basic
Command
Set
(15)
Bus
Cycles
Req'd.
Notes First Bus Cycle Second Bus Cycle
Oper
(1)
Addr
(2)
Data
(3,4)
Oper
(1)
Addr
(2)
Data
(3,4)
Read Array SCS/BCS 1 Write X FFH
Read Identifier
Codes
SCS/BCS ≥2 5 Write X 90H Read IA ID
Read Query SCS ≥ 2 Write X 98H Read QA QD
Read Status
Register
SCS/BCS 2 6 Write X 70H Read X SRD
Clear Status
Register
SCS/BCS 1 Write X 50H
Write to Buffer SCS/BCS > 2 7,8,9 Write BA E8H Write BA N
Word/Byte
Program
SCS/BCS 2 10,11 Write PA 40H
or
10H
Write PA PD
Block Erase SCS/BCS 2 9,10 Write BA 20H Write BA D0H
Block Erase
Suspend
SCS/BCS 1 9,10 Write X B0H
Block Erase
Resume
SCS/BCS 1 10 Write X D0H
Configuration SCS 2 Write X B8H Write X CC
Set Block Lock-Bit SCS 2 12 Write BA 60H Write BA 01H
Clear Block Lock-
Bits
SCS 2 13 Write X 60H Write X D0H
Set Master LockBit
2 12,13 Write X 60H Write X F1H
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