Intel Corporation E28F016SV-120, E28F016SV-080, E28F016SV-075, E28F016SV-070, E28F016SV-065 Datasheet

E













28F016SV

16-MBIT (1 MBIT x 16, 2 MBIT x 8)

FlashFile™ MEMORY

Includes Commercial and Extended Temperature Specifications

n

SmartVoltage Technology

User-Selectable 3.3V or 5V V
User-Selectable 5V or 12V V

n

65 ns Access Time

n

1 Million Erase Cycles per Block

n

30.8 MB/sec Burst Write Transfer Rate

n

0.48 MB/sec Sustainable Write Transfer
Rate

n

Configurable x8 or x16 Operation

n

56-Lead TSOP and SSOP Type I
Packages

Intel’s 28F016SV 16-Mbit Flas hFile™ memory is a revolutionary architect ure which is the ideal choice for
designing embedded direct-execute c ode and mass s torage data/fi le flash m emory sys tems. Wi th innovati ve
capabilities, low-power operation, user-selectable V
28F016SV enables the design of trul y mobile, high-performance personal computing and communic ations
products.

The 28F016SV is the highest dens ity, highest performanc e nonvolatile read/program s olution for solid-s tate
storage applications. I ts s ymm etric ally-block ed architec ture (100% c ompat ible with the 28F008SA 8-Mbit and
28F016SA 16-Mbit FlashFile memories), extended cycling, flexible V
technology), fast program and read performance and select i ve block locking, provi de a highly-flexible memory
component suitable f or Resident Flash Arrays, high-density mem ory cards and PCMCIA-ATA flas h drives.
The 28F016SV’s dual read voltage enables t he design of memory cards which can be read/written in 3.3V
and 5V systems interchangeably. Its x8/x16 architecture allows optimization of the memory-to-processor
interface. The flexible block locking option enables bundling of executable application sof tware in a Resident
Flash Array or memory card. The 28F016SV is manufactured on Intel’s 0.6 µm ETOX IV process technology.

CC

PP

n

Backwards-Compatible with 28F016SA,
28F008SA Command Set

n

Revolutionary Architecture

Multiple Command Execution
Program during Erase
Command Super-Set of the Intel
28F008SA
Page Buffer Program

n

2 µA Typical Deep Power-Down

n

32 Independently Lockable Blocks

n

State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology

voltage and high read/program performance, the

PP

and VPP voltage (SmartVoltage

CC

July 1997 Order Number: 290528-007

7/11/97 11:03 AM 29052807.DOC

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditi ons of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F016SV may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

or visit Intel’s Website at http:\\www.intel.com

COPYRIGHT © INTEL CORPORATION, 1997 CG-041493
*Third-party brands and names are the property of their respective owners.

E 28F016SV FlashFile™ MEMORY

CONTENTS

PAGE PAGE

1.0 INTRODUCTION .............................................7

1.1 Enhanced Features......................................7

1.2 Product Overview.........................................7

2.0 DEVICE PINOUT.............................................9

2.1 Lead Descriptions ......................................11

3.0 MEMORY MAPS...........................................15

3.1 Extended Status Registers Memory Map...16

4.0 BUS OPERATIONS, COMMANDS AND

STATUS REGISTER DEFINITIONS................17

4.1 Bus Operations for Word-Wide Mode

(BYTE# = V

4.2 Bus Operations for Byte-Wide Mode

(BYTE# = V

4.3 28F008SA—Compatible Mode Command

Bus Definitions.............................................18

4.4 28F016SV—Performance Enhancement

Command Bus Definitions............................19

4.5 Compatible Status Register........................21

4.6 Global Status Register...............................22

4.7 Block Status Register.................................23

4.8 Device Configuration Code.........................24

)..............................................17

IH

)...............................................17

IL

5.0 ELECTRICAL SPECIFICATIONS..................25

5.1 Absolute Maximum Ratings........................25

5.2 Capacitance...............................................26

5.3 DC Characteristics (V

5.4 DC Characteristics (V

5V ± 0.25V)..................................................33

5.5 Timing Nomenclature .................................37

5.6 AC Characteristics—Read Only Operations38

5.7 Power-Up and Reset Timings.....................43

5.8 AC Characteristics for WE#—Controlled

Command Write Operations.........................44

5.9 AC Characteristics for CE#—Controlled

Command Write Operations)........................49

5.10 AC Characteristics for WE#—Controlled

Page Buffer Program Operations..................54

5.11 AC Characteristics for CE#—Controlled

Page Buffer Program Operations..................56

5.12 Erase and Word/Byte Program

Performance.................................................58

6.0 MECHANICAL SPECIFICATIONS.................60

APPENDIX A: Device Nomenclature and

Ordering Information .....................................61

APPENDIX B: Ordering Information .................63

= 3.3V ± 0.3V) .....29

CC

= 5V ± 0.5V)

CC

3

28F016SV FlashFile™ MEMORY E

WHRH1A

WHRH1B

WHRH2

REVISION HISTORY

Number Description

-001

-002

-003

Original Version
Added 28F016SV-065/-070 at 5V V

and 28F016SV-075 at 3.3V VCC.

CC

Improved burst write transfer rate to 30.8 MB/sec.
Added 56-lead SSOP Type I packaging information.
Changed V
Increased I

I

CCR1

I

CCR2

I

CCR1

I

CCR2

from 2V to 1.5V.

PPLK

at 5V V

CCR

from 30 mA (typ)/35 mA (max) to 40 mA (typ)/50 mA (max) @ V
from 15 mA (typ)/20 mA (max) to 20 mA (typ)/30 mA (max) @ V
from 50 mA (typ)/60 mA (max) to 75 mA (typ)/95 mA (max) @ V

and 3.3V VCC:

= 3.3V
= 3.3V
= 5V

from 30 mA (typ)/35 mA (max) to 45 mA (typ)/55 mA (max) @ VCC = 5V
Moved AC Characteristics for Extended Register Reads into separate table.
Increased V

MAX from 13V to 14V.

PP

Added Erase Suspend Command Latency times to Section 5.12
Modified Device Nomenclature Section to include SSOP package option and Ordering

Information

Changed definition of “NC.” Removed “No internal connection to die” from description.

xx” to Upper Byte of Command (Data) Definition in Sections 4.3 and 4.4.

Added “
Added Note to Sleep Command (Section 4.4) denoting that the chip must be de-selected

in order for the power consumption in sleep mode to reach deep power-down

levels.
Modified parameters “V” and “I” of Section 5.1 to apply to “NC” pins.
Increased I
Changed V

(VPP Read Current) for VPP> VCC to 200 µA at VCC = 3.3V and VCC = 5V

PPR

= 5V DC Characteristics (Section 5.5) marked with Note 1 to indicate
that these currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns
and a TTL rise/fall time of <10 ns.

Corrected the graphical representation of t

WHGL

and t

in Figures 15 and 16.

EHGL

Increased Typical “Page Buffer Byte/Word Program Times” from 6.0 µs to 8.0 µs (Byte)

and 12.1 µs to 16.0 µs (Word) @ V

Increased Typ. “Byte/Word Program Times” (t

= 3.3V/5V and VPP = 5V:

CC

/t

WHRH1B

) for V

= 5V (Section

5.12)
t

from 16.5 µs to 29.0 µs and t

WHRH1A

t

from 11.0 µs to 20.0 µs and t

WHRH1A

Increased Typical “Block Program Times” (t

t

from 1.1 sec to 1.9 sec and t

WHRH2

t

from 0.8 sec to 1.4 sec and t

WHRH2

from 24.0 µs to 35.0 µs at V
from 16.0 µs to 25.0 µs at VCC = 5V

WHRH1B

WHRH3
WHRH3

/t

)for V

WHRH3

=5V (Section 5.12):
from 0.8 sec to 1.2 sec at V
from 0.6 sec to 0.85 sec at VCC = 5V

=3.3V

= 3.3V

Changed “Time from Erase Suspend Command to WSM Ready” spec name to “Erase

Suspend Latency Time to Read;” modified typical values and added Min/Max
values at V

=3.3/5V and VPP =5V/12V (Section 5.12)

CC

Added “Erase Suspend Latency Time to Program” Specifications to Section 5.12
Minor cosmetic changes throughout document

4

E 28F016SV FlashFile™ MEMORY

)

REVISION HISTORY (Continued)

Number Description

-004 Added 3/5# pin to Block Diagram (Figure 1), Pinout Configurations (Figures 2 and 3),
Product Overview (Section 1.1) and Lead Descriptions (Section 2.1)

PLYL

PPES

CCS

, t

Specifications

, t

PLYH

, and t

YLPH

from 0.50 mm to 0.050 mm (Section 6.0)

1

, t

AVAV

ELWL

, t

AVAV

, t

AVAV

AVQV

)

ELEH

AVQV

YHPH

, t

specifications

, t

, and t

ELQV

)

EHEL

, t

, and t

ELQV

FLQV/tFHQV

FLQV/tFHQV)

5VPH

Added 3/5# pin to Test Conditions of I
Added 3/5# pin (Y) to Timing Nomenclature (Section 5.5)
Increased t

and 480 ns for E28F106SV 070 devices.

Modified Power-Up and Reset Timings (Section 5.9) to include 3/5# pin: Removed t

and t

Added t
Corrected TSOP Mechanical Specification A
Corrected SSOP Mechanical Spec. B (max) from 0.20 mm to 0.40 mm (Section 6.0)

Minor cosmetic changes throughout document.

-005 Updated DC Specifications: I

Updated AC Specifications: Page Buffer Reads: (t

Page Buffer WE#-Controlled Command Writes (t
CE#-Controlled Command Write Parameters (t

Combined Commercial and Extended Temperature information into single datasheet.

-006 Updated AC Specifications: Page Buffer Reads: (t

-007 Updated Disclaimer

Specifications at 5V VCC to 400 ns for E28F016SV 065 devices

PHQV

specifications; Added t

3VPH

PHEL3

and t

specifications to Power-Up and Reset Timings (Section 5.9)

PHEL5

, I

CCD

5

28F016SV FlashFile™ MEMORY E

Page intentionally left blank

6

E 28F016SV FlashFile™ MEMORY

1.0 INTRODUCTION

The documentation of t he Intel 28F016SV m em ory

device includes this datasheet, a detailed user’s
manual, and a number of application notes and
design tools, all of which are referenced in
Appendix B.

The datasheet is intended to give an overview of
the chip feature-set and of the operating AC/DC
specifications. The

User’s Manual

the user modes, system interface examples and
detailed descriptions of all principles of operation.
It also contains the full list of software algorithm
flowcharts, and a brief section on compatibility
with the Intel 28F008SA.

A significant 28F016SV change occurred between
datasheet revisions 290528-003 and 290528-004.
This change centers around the addit ion of a 3/5#

pin to the device’s pinout configuration. Figures 2
and 3 show the 3/5# pin assignment for TSOP and
SSOP Type 1 packages. I ntel recommends that all
customers obtain the latest revisi ons of 28F016SV
documentation.

16-Mbit Flash Product Family

provides complete descriptions of

1.1 Enhanced Features

The 28F016SV is backwards compatible with t he
28F016SA and offers the following enhancements:

• SmartVoltage Technology
 Selectable 5V or 12V V

• VPP Level Bit in Block Status Register

• Additional RY/BY# Configuration
 Pulse-On-Program/Erase

• Additional Upload Device Information

Command Feedback

 Device Proliferation Code
 Device Configuration Code

PP

1.2 Product Overview

The 28F016SV is a high-performance, 16-Mbit
(16,777,216-bit) block erasable, nonvolatile
random access memory, organized as either
1 Mword x 16 or 2 Mbyte x 8. The 28F016SV
includes thirty-two 64-KB (65,536 by te) blocks or
thirty-two 32-KW (32,768 word) blocks. A chip
memory map is shown in Figure 4.

The implementation of a new architecture, with
many enhanced features, will improve the device
operating characteristics and result in greater
product reliability and ease-of-use.

The 28F016SV incorporates SmartVoltage
technology, providing V
and 5V and program and erase capability at V
12V or 5V. Operating at V
28F016SV consumes approximately one half the
power consumption at 5V V
provides the highest read performance capability.
V

= 5V operation eliminates the need for a

PP

separate 12V converter, while V
maximizes program/erase performance. In
addition to the flexible program and erase
voltages, the dedicat ed V
protection with V

A 3/5# input pin configures the device’s internal
circuitry for optimal 3.3V or 5V read/program
operation.

A Command User Interface (CUI) serves as the
system interface between the microprocessor or
microcontroller and the internal memory operation.

Internal Algorithm Automation allows byte/word
programs and block erase operations to be
executed using a Two-Program command
sequence to the CUI in the same way as the
28F008SA 8-Mbit FlashFile™ memory.

A super-set of commands has been added to the
basic 28F008SA command-set to achieve higher
program performance and provide additional
capabilities. These new commands and features
include:

• Page Buffer Programs to Flash

• Command Queuing Capability

• Automatic Data Programs during Erase

• Software Locking of Memory Blocks

• Two-Byte Successive Programs in 8-bit

Systems

• Erase All Unlocked Blocks
Writing of memory data is performed in either byt e

or word increments typically within 6 µs
(12V V
28F008SA. A block erase operat ion erases one of
the 32 blocks in typically 0.6 sec (12V V
independent of the other blocks, which is about a
65% improvement over the 28F008SA.

PP

≤ V

PP

)—a 33% improvement over the

operation at both 3.3V

CC

= 3.3V, the

CC

, while 5V V

CC

PP

gives complete code

PP

.

PPLK

PP

CC

= 12V

PP

=

),

7

28F016SV FlashFile™ MEMORY E

Each block can be writt en and erased a minimum
of 100,000 cycles. Systems can achieve one
million Block Erase Cycles by providing wear­leveling algorithms and gracef ul block retirement.
These techniques have already been employ ed in
many flash file systems and hard disk drive
designs.

The 28F016SV incorporates two Page Buffers of
256 bytes (128 words) each to allow page data
programs. This feature can improve a system
program performance by up to 4.8 times over
previous flash memory devices, which have no
Page Buffers.

All operations are started by a sequence of
Program commands to the device. Three Status
Registers (described in detail later in this
datasheet) and a RY/BY# output pin provide
information on the progress of the requested
operation.

While the 28F008SA requires an operation to
complete before the next operation can be
requested, the 28F016SV allows queuing of the
next operation while the memory executes the
current operation. This eliminates system
overhead when writing several bytes in a row to
the array or erasing several blocks at the same
time. The 28F016SV can also perform program
operations to one block of memory while
performing erase of another block.

The 28F016SV provides selectable block locking
to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable O/S
or Application Code. Each block has an
associated nonvolatile lock-bit which determines
the lock status of the block. In addition, the
28F016SV has a master Write Protect pi n (WP#)
which prevents any modifications to memory
blocks whose lock-bits are set.

The 28F016SV contains three types of Status
Registers to accomplish various functions:

• A Compatible Status Register (CSR) which is
100% compatible with the 28F008S A FlashFile
memory Status Regist er. The CSR, when used
alone, provides a straightforward upgrade
capability to the 28F016SV from a 28F008SA­based design.

• A Global Status Register (GSR) which i nforms
the system of command Queue status, Page
Buffer status, and overall Writ e State Machine
(WSM) status.

• 32 Block Status Registers (BSRs) which
provide block-specific status information such
as the block lock-bit status.

The GSR and BSR memory maps for byte-wide
and word-wide modes are shown in Figures 5
and 6.

The 28F016SV incorporates an open drain
RY/BY# output pin. This feature al lows the user t o
OR-tie many RY/BY# pins together in a multiple
memory configuration such as a Resident Flash
Array.

Other configurations of the RY/BY# pin are
enabled via special CUI commands and are
described in detail in the

16-Mbit Flash Product

Family User’s Manual.

The 28F016SV’s enhanced Upload Device
Information command provides access to
additional information that the 28F016SA
previously did not offer. This command uploads
the Device Revision Number, Dev ice Proliferation
Code and Device Configuration Code to the page
buffer. The Device Proliferation Code for the
28F016SV is 01H, and the Device Configuration
Code identifies the current RY /BY# configuration.
Section 4.4 documents the exact page buffer
address locations for all uploaded information. A
subsequent Page Buffer Swap and Page Buffer
Read command sequence is necessary to read
the correct device information.

The 28F016SV also incorporates a dual chip­enable function with two input pins, CE
CE

#. These pins have exactly the same

1

functionality as the regular c hip-enable pin, CE#,

# and

0

on the 28F008SA. For minimum chip designs,
CE

# may be tied to ground and system logic may

1

use CE
uses the logical combinati on of these two signals
to enable or disable the entire chip. Both CE
CE
either one becomes inactive, the chip will be

# as the chip enable input. The 28F016SV

0

# and

# must be active low to enabl e the device. If

1

0

disabled. This feature, along with the open drain
RY/BY# pin, allows the system designer to reduce
the number of control pins used in a large array of
16-Mbit devices.

The BYTE# pin allows either x8 or x16
read/programs to the 28F016SV. BYTE# at logic
low selects 8-bit m ode with address A
between the low byte and high byte. On the other

selecting

0

hand, BYTE# at logic high enables 16-bit
operation with address A

becoming the lowest

1

8

E 28F016SV FlashFile™ MEMORY

order address and address A0 is not used (don’t

care). A device block diagram is shown in Figure

1.
The 28F016SV is specified for a max imum ac cess

time of 65 ns (t

5.25V) over the commercial temperature range
(0°C to +70°C). A corres ponding max im um acc es s
time of 75 ns at 3.3V (3.0V to 3.6V and 0°C to
+70°C) is achieved for reduced power
consumption applications.

The 28F016SV incorporates an Automat ic Power
Saving (APS) feature, which substantially reduces
the active current when the device is in static
mode of operation (addresses not switching). In
APS mode, the typical I
(3.0 mA at 3.3V).

A deep power-down mode of operation is invoked
when the RP# (called PWD# on the 28F008SA)
pin transitions low. This mode brings the device
power consumption to less than 2.0 µA, typically,
and provides additional program protection by
acting as a device reset pin during power
transitions. A reset time of 400 ns (5V V

) at 5V operation (4.75V to

ACC

current is 1 mA at 5V

CC

CC

operation) is required from RP# switching high
until outputs are again valid. In the Deep Power­Down state, the WSM is reset (any current
operation will abort) and the CSR, GS R and BSR
registers are cleared.

A CMOS standby mode of operation is enabled
when either CE
RP# stays high with all input c ontrol pins at CMOS
levels. In this mode, the dev ice typically draws an
I

standby current of 70 µA at 5V VCC.

CC

The 28F016SV will be available in 56-lead,

1.2 mm thick, 14 mm x 20 mm TSOP and 56-lead,

1.8 mm thick, 16 mm x 23.7 SSOP Type I
packages. The form factor and pi nout of thes e two
packages allow for very high board layout
densities.

# or CE1# transitions high and

0

2.0 DEVICE PINOUT

The 28F016SV 56-lead TSOP and 56-lead SSOP
Type I pinout configurations are shown in Figures
2 and 3.

9

28F016SV FlashFile™ MEMORY E

Output

Buffer

DQ

8-15

Output

Buffer

DQ

ID

Register

CSR

0-7

Input

Buffer

Data

Queue

Registers

Page

Buffers

Input

Buffer

I/O Logic

3/5#

BYTE#

Output Multiplexer

CE #

OE#
WE#
WP#
RP#

CE #

0

1

ESRs

0-20

A

Input
Buffer

Y

Decoder

Data

Comparator

Y Gating/Sensing

CUI

10

Address

Queue

Registers

Address
Counter

X

Decoder

Block 1

Block 0

64-Kbyte

64-Kbyte

Block 30

Block 31

64-Kbyte

64-Kbyte

Figure 1. 28F016SV Block Diagram

Architectural Evolution Includes SmartVoltage Technology,

Page Buffers, Queue Registers and Extended Registers

WSM

Program/Erase
Voltage Sw it ch

RY/BY#

V

V

GND

PP

3/5#

CC

0528_01

E 28F016SV FlashFile™ MEMORY

2.1 Lead Descriptions

Symbol Type Name and Function

A

0

A1–A

15

A16–A

20

DQ0–DQ7INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI program

DQ8–DQ15INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 data program

CE0#, CE1# INPUT CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,

RP# INPUT RESET/POWER-DOWN: RP# low places the device in a deep power-

OE# INPUT OUTPUT ENABLE: Gates device data through the output buffers when

WE# INPUT WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue

INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when

device is in x8 mode. This address is latched in x8 data programs. Not
used in x16 mode (i.e., the A
high).

INPUT WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block.

A

selects 1 of 1024 rows, and A

6–15

addresses are latched during data programs.

INPUT BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These

addresses are latched during data programs, erase and lock block
operations.

cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is de-selected or the outputs are
disabled.

operations. Outputs array, buffer or identifier data in the appropriate read
mode; not used for Status Register reads. Floated when the chip is de­selected or the outputs are disabled.

decoders and sense amplifiers. With either CE
is de-selected and power consumption reduces to standby levels upon
completion of any current data program or erase operations. Both CE

# must be low to select the device.

and CE
All timing specifications are the same for both signals. Device Selection
occurs with the latter falling edge of CE

# or CE1# disables the device.

CE

0

down state. All circuits that consume static power, even those circuits
enabled in standby mode, are turned off. When returning from deep
power-down, a recovery time of t
power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).
Exit from deep power-down places the device in read array mode.

low. The outputs float to tri-state off when OE# is high.

CEx# overrides OE#, and OE# overrides WE#.

Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.
Page Buffer addresses are latched on the falling edge of WE#.

input buffer is turned off when BYTE# is

selects 16 of 512 columns. These

1–5

# or CE

# or CE

is required to allow these circuits to

PHQV

NOTE:

# high, the device

#. The first rising edge of

#

11

28F016SV FlashFile™ MEMORY E

2.1 Lead Descriptions (Continued)

Symbol Type Name and Function

RY/BY# OPEN DRAIN

OUTPUT

WP# INPUT WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile

BYTE# INPUT BYTE ENABLE: BYTE# low places device in x8 mode. All data is then

3/5# INPUT 3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V

V

PP

V

CC

SUPPLY PROGRAM/ERASE POWER SUPPLY (12V ± 0.6V, 5V ± 0.5V) : For

SUPPLY DEVICE POWER SUPPLY (3.3V ± 0.3V, 5V ± 0.5V, 5.0 ± 0.25V):

GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY:

NC NO CONNECT:

READY/BUSY: Indicates status of the internal WSM. When low, it
indicates that the WSM is busy performing an operation. RY/BY# floating
indicates that the WSM is ready for new operations (or WSM has
completed all pending operations), or erase is suspended, or the device is
in deep power-down mode. This output is always active (i.e., not floated

#, CE

to tri-state off when OE# or CE

# are high), except if a RY/BY# Pin

Disable command is issued.

lock-bit for each block. When WP# is low, those locked blocks as
reflected by the Block-Lock Status bits (BSR.6), are protected from
inadvertent data programs or erases. When WP# is high, all blocks can
be written or erased regardless of the state of the lock-bits. The WP#
input buffer is disabled when RP# transitions low (deep power-down
mode).

input or output on DQ

, and DQ– float. Address A

–

selects between
the high and low byte. BYTE# high places the device in x16 mode, and
turns off the A

input buffer. Address A, then becomes the lowest order

address.

operation. 3/5# low configures internal circuits for 5V operation.

NOTE:

Reading the array with 3/5# high in a 5V system could damage the
device. Reference the power-up and reset timings (Section 5.7) for 3/5#
switching delay to valid data.

erasing memory array blocks or writing words/bytes/pages into the flash
array. V

= 5V ± 0.5V eliminates the need for a 12V converter, while

connection to 12V ± 0.6V maximizes Program/Erase Performance.

NOTE:

Successful completion of program and erase attempts is inhibited with

at or below 1.5V. Program and erase attempts with V

V

between 1.5V
and 4.5V, between 5.5V and 11.4V, and above 12.6V produce spurious
results and should not be attempted.

To switch 3.3V to 5V (or vice versa), first ramp V
then power to the new V

voltage.

CC

down to GND, and

CC

Do not leave any power pins floating.

Do not leave any ground pins floating.

Lead may be driven or left floating.

12

E 28F016SV FlashFile™ MEMORY

3/5#

CE #

CE #

A

A

A

A

A

V

A

A

A

A

CE #

V

RP#

A

A

GND

28F016SA28F032SA

3/5#

3/5#

CE #

CE #

1

1

NC

2

20
19

18

17
16

CC

15
14

13

12

0

PP

11
10

A

9

A

8

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

A

A

A

A

V

A

A

A

A

CE #

V

RP#

A

A

GND

A

20

A

19

A

18

A

17

A

16

V

CC

A

15

A

14

A

13

A

12

CE #

0

V

PP

RP#

A

11

A

10

A

9

A

8

GND

A

7

A

6

A

5

A

4

A

3

A

2

A

1

NC

1
2

1

3

4

20

5

19

6

18

7

17

8

16

9

CC

10

15

11

14

12

13

13

12

14

0

15

PP

16
17

11

18

10

19

A

9

20

A

8

21

22

A

7

23

A

6

24

A

5

25

A

4

26

A

3

27

A

2

28

A

1

E28F016SV

56-LEAD TSOP PINOUT

14 mm x 20 mm

TOP VIEW

NOTE:

56-lead TSOP Mechanical Diagrams and dimensions are shown at the end of this datasheet.

Figure 2. 28F016SV 56-Lead TSOP Pinout Configuration

Shows Compatibility with 28F016SA/28F032SA

56

WP#

55

WE#

54

OE#

53

RY/BY#

52

DQ

51

50

49

48

47
46

45

44
43

42

41
40

39

38
37

36
35
34

33

32
31

30

29

15

DQ

7

DQ

14

DQ

6

GND
DQ

13

DQ

5

DQ

12

DQ

4

V

CC

GND
DQ

11

DQ

3

DQ

10

DQ

2

V

CC

DQ

9

DQ

1

DQ

8

DQ

0

A

0

BYTE#
NC
NC

WP#
WE#
OE#
RY/BY#
DQ

15

DQ

7

DQ

14

DQ

6

GND
DQ

13

DQ

5

DQ

12

DQ

4

V

CC

GND
DQ

11

DQ

3

DQ

10

DQ

2

V

CC

DQ

9

DQ

1

DQ

8

DQ

0

A

0

BYTE#
NC
NC

28F032SA28F016SA

WP#
WE#
OE#
RY/BY#
DQ

15

DQ

7

DQ

14

DQ

6

GND
DQ

13

DQ

5

DQ

12

DQ

4

V

CC

GND
DQ

11

DQ

3

DQ

10

DQ
V

CC

DQ
DQ
DQ
DQ
A

0

BYTE#
NC
NC

0528_02

2

9
1
8
0

13

28F016SV FlashFile™ MEMORY E

28F016SA

A
A
A
A

3/5#

NC
A
A
A

A
A

V

DQ

DQ

OE#

DQ

DQ

V

0

1

CC

CC

12
13
14

15

20
19
18
17

16

14

15

13

12

6

7

5

4

CE #

A

A
A
A

3/5#

CE #

NC
A
A
A

A
A
V

GND

DQ

DQ

DQ

DQ

RY/BY#

OE#
WE#
WP#
DQ

DQ

DQ

DQ
V

0

1

CC

1
2

12

3

13

4

14

5

15

6
7

8
9

20

10

19

11

18
17

12
13

16

14

15

6

16

14

17

7

18

15

19

DA28F016SV
56-LEAD SSOP

STANDARD PINOUT

16 mm x 23.7 mm

TOP VIEW

20
21
22
23

24

13

25

5

26

12

27

4

CC

28

CE #

CE #

GND

DQ

DQ

RY/BY#

WE#
WP#
DQ

DQ

NOTE:

56-lead SSOP Mechanical Diagrams and dimensions are shown at the end of this datasheet.

Figure 3. 56-Lead SSOP Pinout Configuration

56
55

54
53
52
51
50

49
48
47
46

45
44

43
42
41
40
39

38
37
36
35
34
33
32
31
30
29

V

PP

R/P#
A

11

A

10

A

9

A

1

A

2

A

3

A

4

A

5

A

6

A

7

GND
A

8

V

CC

DQ

9

DQ

1

DQ

8

DQ

0

A

0

BYTE#
NC

NC
DQ

2

DQ

10

DQ

3

DQ

11

GND

V

PP

R/P#
A

11

A

10

A

9

A

1

A

2

A

3

A

4

A

5

A

6

A

7

GND
A

8

V

CC

DQ

9

DQ

1

DQ

8

DQ

0

A

0

BYTE#
NC

NC
DQ

2

DQ

10

DQ

3

DQ

11

GND

0528_03

28F016SA

14

E 28F016SV FlashFile™ MEMORY

e

3.0 MEMORY MAPS

A

[20-0]

1FFFFF

1F0000

1EFFFF

1E0000

1DFFFF

1D0000

1CFFFF

1C0000

1BFFFF

1B0000

1AFFFF

1A0000

19FFFF

190000

18FFFF

180000

17FFFF

170000

16FFFF

160000

15FFFF

150000

14FFFF

140000

13FFFF

130000

12FFFF

120000

11FFFF

110000

10FFFF

100000

0FFFFF

0F0000

0EFFFF

0E0000

0DFFFF

0D0000

0CFFFF

0C0000

0BFFFF

0B0000

0AFFFF

0A0000

09FFFF

090000

08FFFF

080000

07FFFF

070000

06FFFF

060000

05FFFF

050000

04FFFF

040000

03FFFF

030000

02FFFF

020000

01FFFF

010000

00FFFF

000000

64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block

Byte-Wide (x8) Mode

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1
0

A

[20-1]

FFFFF

32-Kword Block

F8000

F7FFF

32-Kword Block

F0000

EFFFF

32-Kword Block

E8000

E7FFF

32-Kword Block

E0000

DFFFF

32-Kword Block

D8000

D7FFF

32-Kword Block

D0000

CFFFF

32-Kword Block

C8000

C7FFF

32-Kword Block

C0000

BFFFF

32-Kword Block

B8000

B7FFF

32-Kword Block

B0000

A8FFF

32-Kword Block

A8000

A7FFF

32-Kword Block

A0000

9FFFF

32-Kword Block

98000

97FFF

32-Kword Block

90000

8FFFF

32-Kword Block

88000

87FFF

32-Kword Block

80000

7FFFF

32-Kword Block

78000

77FFF

32-Kword Block

70000

6FFFF

32-Kword Block

68000

67FFF

32-Kword Block

60000

5FFFF

32-Kword Block

58000

57FFF

32-Kword Block

50000

4FFFF

32-Kword Block

48000

47FFF

32-Kword Block

40000

3FFFF

32-Kword Block

38000

37FFF

32-Kword Block

30000

2FFFF

32-Kword Block

28000

27FFF

32-Kword Block

20000

1FFFF

32-Kword Block

18000

17FFF

32-Kword Block

10000

0FFFF

32-Kword Block

08000

07FFF

32-Kword Block

00000

Word-Wide (x16) Mod

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1
0

Figure 4. 28F016SV Memory Maps (Byte-Wide and Word-Wide Modes)

0528_04

15

28F016SV FlashFile™ MEMORY E

3.1 Extended Status Registers Memory Map

x8 MODE

RESERVED

GSR

RESERVED

BSR 31
RESERVED
RESERVED

.
.
.

RESERVED

RESERVED

GSR

RESERVED

BSR 0
RESERVED
RESERVED

A[20-0]
1F0006H

1F0005H
1F0004H
1F0003H

1F0002H
1F0001H
1F0000H

010002H

000006H

000005H
000004H

000003H

000002H

000001H
000000H

0528_05

x16 MODE

RESERVED

GSR

RESERVED

BSR 31

RESERVED

RESERVED

.
.
.

RESERVED

RESERVED

GSR

RESERVED

BSR 0

RESERVED

RESERVED

A[20-1]
F8003H

F8002H

F8001H

F8000H

08001H

00003H

00002H

00001H

00000H

0528_06

Figure 5. Extended Status Register Memory

Map (Byte-Wide Mode)

16

Figure 6. Extended Status Register Memory

Map (Word-Wide Mode)

E 28F016SV FlashFile™ MEMORY

4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS

4.1 Bus Operations for Word-Wide Mode (BYTE# = V

Mode Notes RP# CE1#CE0# OE# WE# A

Read 1,2,7 V
Output Disable 1,6,7 V
Standby 1,6,7 V

Deep Power-Down 1,3 V
Manufacturer ID 4 V
Device ID 4,8 V
Write 1,5,6 V

V

IH

V

IH

V

IH

V
V

IL

V

IH

V

IH

V

IH

V

IL

V

IL

V

IL

V

IL

V
V
V

IH

IH

XXXXXHigh Z V

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

)

IH

DQ

1

V

IL

V

IH

XD

IH

X High Z X

IH

0–15

OUT

RY/BY#

X X X High Z X

V

IL

V

IL

V

IH

V

IH

IH

IL

IL

V

IH

XDINX

0089H V

66A0H V

X

OH

OH

OH

4.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL)

Mode Notes RP# CE1#CE0# OE# WE# A

Read 1,2,7 V
Output Disable 1,6,7 V
Standby 1,6,7 V

Deep Power-Down 1,3 V
Manufacturer ID 4 V
Device ID 4,8 V
Write 1,5,6 V

NOTES:

1. X can be V

2. RY/BY# output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode.
RY/BY# will be at V
is in progress.

3. RP# at GND ± 0.2V ensures the lowest deep power-down current.

4. A

and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively. A0 and A1 at VIH provide device ID

0

codes in x8 and x16 modes respectively. All other addresses are set to zero.

5. Commands for erase, data program, or lock-block operations can only be completed successfully when V
V

= V

PP

6. While the WSM is running, RY/BY# in level-mode (default) stays at V

7. RY/BY# may be at V

8. The 28F016SV shares an identical device identifier (66A0H in word-wide mode, A0H in byte-wide mode) with the

PPH2

V

when the WSM is not busy or in erase suspend mode.

OH

program operation).

28F016SA. See application note
differentiate between the 28F016SV and 28F016SA.

for address or control pins except for RY/BY#, which is either V

or V

IH

IL

if it is tied to V

OH

.

while the WSM is busy performing various operations (for example, a Status Register read during a

OL

CC

AP-393 28F016SV Compatibility with 28F016SA

V

IH

V

IH

V

IH

V
V

IL

V

IH

V

IH

V

IH

through a resistor. RY/BY# at V

V

IL

IL

IL

V

IL

V
V
V

IH

IH

XXXXXHigh Z V

V

IL

IL

IL

IL

V

IL

V

IL

OL

V
V

V

IL

IH

IH

V

IH

X X X High Z X

V
V
V

V

IL

IL

IH

OH

until all operations are complete. RY/BY# goes to

IH

V

IH

V

IL

or V

OL

is independent of OE# while a WSM operation

for software and hardware techniques to

DQ

0

XD

0–7

OUT

RY/BY#

X High Z X

V
V

IL

IH

89H V

A0H V

XDINX

.

OH

= V

PP

PPH1

X

OH

OH

OH

or

17

28F016SV FlashFile™ MEMORY E

4.3 28F008SA—Compatible Mode Command Bus Definitions

First Bus Cycle Second Bus Cycle

Command Notes Oper Addr Data

(4)

Oper Addr Data

Read Array Write X xxFFH Read AA AD
Intelligent Identifier 1 Write X xx90H Read IA ID
Read Compatible Status Register 2 Write X xx70H Read X CSRD
Clear Status Register 3 Write X xx50H
Word/Byte Program Write X xx40H Write PA PD
Alternate Word/Byte Program Write X xx10H Write PA PD
Block Erase/Confirm Write X xx20H Write BA xxD0H
Erase Suspend/Resume Write X xxB0H Write X xxD0H

ADDRESS DATA

AA = Array Address AD = Array Data
BA = Block Address CSRD = CSR Data
IA = Identifier Address ID = Identifier Data
PA = Program Address PD = Program Data

X = Don’t Care

NOTES:

1. Following the Intelligent Identifier command, two Read operations access the manufacturer and device signature codes.

2. The CSR is automatically available after device enters data program, erase, or suspend operations.

3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSR.4 and BSR.2 bits. See Status Register
definitions.

4. The upper byte of the data bus (DQ

) during command writes is a “Don’t Care” in x16 operation of the device.

8–15

(4)

18

E 28F016SV FlashFile™ MEMORY

4.4 28F016SV—Performance Enhancement Command Bus Definitions

Command Mode Notes First Bus Cycle Second Bus Cycle Third Bus Cycle

Oper Addr Data

Read Extended
Status Register

Page Buffer Swap 7 Write X xx72H
Read Page Buffer Write X xx75H Read PBA PD
Single Load to Page

Buffer
Sequential Load to

Page Buffer

Page Buffer Write to
Flash

Two-Byte Program x8 3 Write X xxFBH Write A0WD(L,H) Write PA WD(H,L)
Lock Block/Confirm Write X xx77H Write BA xxD0H
Upload Status

Bits/Confirm
Upload Device

Information/Confirm
Erase All Unlocked

Blocks/Confirm
RY/BY# Enable to

Level-Mode
RY/BY#

Pulse-On-Write
RY/BY#

Pulse-On-Erase
RY/BY# Disable 8 Write X xx96H Write X xx04H
RY/BY# Pulse-On-

Write/Erase
Sleep 12 Write X xxF0H
Abort Write X xx80H

ADDRESS DATA

BA = Block Address AD = Array Data WC (L,H) = Word Count (Low, High)
PBA = Page Buffer Address PD = Page Buffer Data BC (L,H) = Byte Count (Low, High)
RA = Extended Register Address BSRD = BSR Data WD (L,H) = Write Data (Low, High)
PA = Program Address GSRD = GSR Data

X = Don’t Care

x8 4,6,10 Write X xxE0H Write X BCL Write X BCH

x16 4,5,6,10 Write X xxE0H Write X WCL Write X WCH

x8 3,4,9,10 Write X xx0CH Write A0BC(L,H) Write PA BC(H,L)

x16 4,5,10 Write X xx0CH Write X WCL Write PA WCH

1 Write X xx71H Read RA GSRD

Write X xx74H Write PBA PD

2 Write X xx97H Write X xxD0H

11 Write X xx99H Write X xxD0H

Write X xxA7H Write X xxD0H

8 Write X xx96H Write X xx01H

8 Write X xx96H Write X xx02H

8 Write X xx96H Write X xx03H

8 Write X xx96H Write X xx05H

(13)

Oper Addr Data

BSRD

(13)

Oper Addr Data

19