Intel Corporation D80C52-24 Datasheet
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March 1996COPYRIGHT©INTEL CORPORATION, 1996 Order Number: 272336-004
8XC52/54/58
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Commercial/Express
87C52/80C52/80C32/87C54/80C54/87C58/80C58
*See Table 1 for Proliferation Options
Y
High Performance CHMOS EPROM/
ROM/CPU
Y
12/24/33 MHz Operations
Y
Three 16-Bit Timer/Counters
Y
Programmable Clock Out
Y
Up/Down Timer/Counter
Y
Three Level Program Lock System
Y
8K/16K/32K On-Chip Program Memory
Y
256 Bytes of On-Chip Data RAM
Y
Improved Quick Pulse Programming
Algorithm
Y
Boolean Processor
Y
32 Programmable I/O Lines
Y
6 Interrupt Sources
Y
Programmable Serial Channel with:
Ð Framing Error Detection
Ð Automatic Address Recognition
Y
TTL and CMOS Compatible Logic
Levels
Y
64K External Program Memory Space
Y
64K External Data Memory Space
Y
MCSÉ51 Microcontroller Compatible
Instruction Set
Y
Power Saving Idle and Power Down
Modes
Y
ONCE (On-Circuit Emulation) Mode
Y
Four-Level Interrupt Priority
Y
Extended Temperature Range Except
for 33 MHz Offering (
b
40§Ctoa85§C)
MEMORY ORGANIZATION
ROM EPROM ROMless ROM/EPROM RAM
Device Version Version Bytes Bytes
80C52 87C52 80C32 8K 256
80C54 87C54 80C32 16K 256
80C58 87C58 80C32 32K 256
These devices can address up to 64 Kbytes of external program/data memory.
The Intel 8XC52/8XC54/8XC58 is a single-chip control-oriented microcontroller which is fabricated on Intel’s
reliable CHMOS III-E technology. Being a member of the MCS 51 family of controllers, the 8XC52/8XC54/
8XC58 uses the same powerful instruction set, has the same architecture, and is pin-for-pin compatible with
the existing MCS 51 family of products. The 8XC52/8XC54/8XC58 is an enhanced version of the
87C51/80C51BH/80C31BH. The added features make it an even more powerful microcontroller for applications that require clock output, and up/down counting capabilities such as motor control. It also has a more
versatile serial channel that facilitates multi-processor communications.
Throughout this document 8XC5X will refer to the 8XC52, 80C32, 8XC54 and 8XC58 unless information
applies to a specific device.
8XC52/54/58
Table 1. Proliferations Options
Standard
*1
-1 -2 -24 -33
80C32 X X X X X
80C52 X X X X X
87C52 X X X X X
80C54 X X X X X
87C54 X X X X X
80C58 X X X X X
87C58 X X X X X
NOTES:
*1 3.5 MHz to 12 MHz; 5V
g
20%
-1 3.5 MHz to 16 MHz; 5V
g
20%
-2 0.5 MHz to 12 MHz; 5V
g
20%
-24 3.5 MHz to 24 MHz; 5V
g
20%
-33 3.5 MHz to 33 MHz; 5V
g
10%
272336–1
Figure 1. 8XC5X Block Diagram
2
8XC52/54/58
PROCESS INFORMATION
This device is manufactured on P629.0, a CHMOS
III-E process. Additional process and reliability information is available in Intel’s
Components Quality
and Reliability Handbook,
Order No. 210997.
PACKAGES
Part Prefix Package Type
8XC5X P 40-Pin Plastic DIP (OTP)
87C5X D 40-Pin CERDIP (EPROM)
8XC5X N 44-Pin PLCC (OTP)
8XC5X S 44-Pin QFP (OTP)
272336–2
DIP
272336–3
PLCC
272336–4
*Do not connect reserved pins. QFP
Figure 2. Pin Connections
3
8XC52/54/58
PIN DESCRIPTIONS
VCC: Supply voltage.
V
SS
: Circuit ground.
V
SS1
: Secondary ground (not on DIP). Provided to
reduce ground bounce and improve power supply
by-passing.
NOTE:
This pin is not a substitute for the V
SS
pin (pin 22).
(Connection not necessary for proper operation.)
Port 0: Port 0 is an 8-bit, open drain, bidirectional
I/O port. As an output port each pin can sink several
LS TTL inputs. Port 0 pins that have 1’s written to
them float, and in that state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting 1’s, and can source and
sink several LS TTL inputs.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are required during program verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally pulled low will source current
(I
IL
, on the data sheet) because of the internal pull-
ups.
In addition, Port 1 serves the functions of the following special features of the 8XC5X:
Port Pin Alternate Function
P1.0 T2 (External Count Input to Timer/
Counter 2), Clock-Out
P1.1 T2EX (Timer/Counter 2 Capture/
Reload Trigger and Direction Control)
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally pulled low will source current
(I
IL
, on the data sheet) because of the internal pull-
ups.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX
@
DPTR). In this application it
uses strong internal pullups when emitting 1’s. During accesses to external Data Memory that use 8-bit
addresses (MOVX
@
Ri), Port 2 emits the contents of
the P2 Special Function Register.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally pulled low will source current
(I
IL
, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special
features of the 8051 Family, as listed below:
Port Pin Alternate Function
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1
(external interrupt 1)
P3.4 T0 (Timer 0 external input)
P3.5 T1 (Timer 1 external input)
P3.6 WR
(external data memory write strobe)
P3.7 RD
(external data memory read strobe)
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. The port pins will be driven to their reset condition when a minimum V
IHI
voltage is applied whether
the oscillator is running or not. An internal pulldown
resistor permits a power-on reset with only a capacitor connected to V
CC
.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the 87C5X.
In normal operation ALE is emitted at a constant
rate of (/6 the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
4
8XC52/54/58
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With this bit set, the pin is
weakly pulled high. However, the ALE disable feature will be suspended during a MOVX or MOVC instruction, idle mode, power down mode and ICE
mode. The ALE disable feature will be terminated by
reset. When the ALE disable feature is suspended or
terminated, the ALE pin will no longer be pulled up
weakly. Setting the ALE-disable bit has no affect if
the microcontroller is in external execution mode.
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.
PSEN
: Program Store Enable is the read strobe to
external Program Memory.
When the 8XC5X is executing code from external
Program Memory, PSEN
is activated twice each
machine cycle, except that two PSEN
activations
are skipped during each access to external Data
Memory.
EA
/VPP: External Access enable. EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
0000H to 0FFFFH. Note, however, that if any of the
Lock bits are programmed, EA will be internally
latched on reset.
EA
should be strapped to VCCfor internal program
executions.
This pin also receives the programming supply voltage (V
PP
) during EPROM programming.
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifi-
er.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, ‘‘Oscillators for Microcontrollers’’, Order No. 230659.
272336–5
C1, C2e30 pFg10 pF for Crystals
For Ceramic Resonators, contact resonator manufacturer.
Figure 3. Oscillator Connections
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the V
IL
and VIHspecifications the capacitance will not exceed 20 pF.
272336–6
Figure 4. External Clock Drive Configuration
IDLE MODE
The user’s software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an enabled interrupt occurs.
5
8XC52/54/58
Table 2. Status of the External Pins during Idle and Power Down
Mode
Program
ALE PSEN PORT0 PORT1 PORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down mode is terminated.
On the 8XC5X either a hardware reset or an external
interrupt can cause an exit from Power Down. Reset
redefines all the SFRs but does not change the onchip RAM. An external interrupt allows both the
SFRs and on-chip RAM to retain their values.
To properly terminate Power Down, the reset or external interrupt should not be executed before V
CC
is
restored to its normal operating level, and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
With an external interrupt, INT0 and INT1 must be
enabled and configured as level-sensitive. Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
DESIGN CONSIDERATION
#
The window on the D87C5X must be covered by
an opaque label. Otherwise, the DC and AC characteristics may not be met, and the device may
be functionally impaired.
#
When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
ONCE MODE
The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates
testing and debugging of systems using the 8XC5X
without the 8XC5X having to be removed from the
circuit. The ONCE Mode is invoked by:
1) Pull ALE low while the device is in reset and
PSEN
is high;
2) Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins
float and the other port pins and ALE and PSEN
are
weakly pulled high. The oscillator circuit remains active. While the 8XC5X is in this mode, an emulator or
test CPU can be used to drive the circuit. Normal
operation is restored when a normal reset is applied.
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I, (Order No. 270645) and Application Note AP-252 (Embedded Applications Handbook, Order No.
270648), ‘‘Designing with the 80C51BH.’’
6
8XC52/54/58
8XC5X EXPRESS
The Intel EXPRESS system offers enhancements to
the operational specifications of the MCS 51 family
of microcontrollers. These EXPRESS products are
designed to meet the needs of those applications
whose operating requirements exceed commercial
standards.
The EXPRESS program includes the commercial
standard temperature range with burn-in and an extended temperature range with or without burn-in.
With the commercial standard temperature range,
operational characteristics are guaranteed over the
temperature range of 0
§
Ctoa70§C. With the extended temperature range option, operational characteristics are guaranteed over the range of
b
40§C
to
a
85§C.
The optional burn-in is dynamic for a minimum time
of 168 hours at 125
§
C with V
CC
e
6.9Vg0.25V,
following guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified
by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 3.
For the extended temperature range option, this
data sheet specifies the parameters which deviate
from their commercial temperature range limits.
NOTE:
Intel offers Express Temperature specifications for all 8XC5X speed options except for
33 MHz.
Table 3. Prefix Identification
Prefix
Package Temperature
Burn-In
Type Range
P Plastic Commercial No
D Cerdip Commercial No
N PLCC Commercial No
S QFP Commercial No
TP Plastic Extended No
TD Cerdip Extended No
TN PLCC Extended No
TS QFP Extended No
LP Plastic Extended Yes
LD Cerdip Extended Yes
LN PLCC Extended Yes
LS QFP Extended Yes
NOTE:
Contact distributor or local sales office to match EXPRESS prefix with proper device.
EXAMPLES:
P80C52 indicates 80C52 in a plastic package and specified for commercial temperature range, without burn-in. TD80C52
indicates 80C52 in a Cerdip package and specified for extended temperature range, without burn-in.
7
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