Intel Corporation AS82527, AN82527 Datasheet

82527

SERIAL COMMUNICATIONS CONTROLLER

CONTROLLER AREA NETWORK PROTOCOL

Automotive

Y

Supports CAN Specification 2.0
Ð Standard Data and Remote Frames
Ð Extended Data and Remote Frames

Y

Programmable Global Mask
Ð Standard Message ldentifier
Ð Extended Message ldentifier

Y

15 Message Objects of 8-Byte Data
Length
Ð 14 Tx/Rx Buffers
Ð 1 Rx Buffer with Programmable Mask

Y

Flexible CPU Interface
Ð 8-Bit Multiplexed
Ð 16-Bit Multiplexed
Ð 8-Bit Non-Multiplexed

(Synchronous/Asynchronous)

Ð Serial Interface

The 82527 serial communications controller is a highly integrated device that performs serial communication
according to the CAN protocol. It performs all serial communication functions such as transmission and
reception of messages, message filtering, transmit search, and interrupt search with minimal interaction from
the host microcontroller, or CPU.

The 82527 is Intel’s first device to support the standard and extended message frames in CAN Specification

2.0 Part B. It has the capability to transmit, receive, and perform message filtering on extended message
frames. Due to the backwardly compatible nature of CAN Specification 2.0, the 82527 also fully supports the
standard message frames in CAN Specification 2.0 Part A.

The 82527 features a powerful CPU interface that offers flexibility to directly interface to many different CPUs.
It can be configured to interface with CPUs using an 8-bit multiplexed, 16-bit multiplexed, or 8-bit non-multi­plexed address/data bus for Intel and non-Intel architectures. A flexible serial interface (SPI) is also available
when a parallel CPU interface is not required.

The 82527 provides storage for 15 message objects of 8-byte data length. Each message object can be
configured as either transmit or receive except for the last message object. The last message object is a
receive-only buffer with a special mask design to allow select groups of different message identifiers to be
received.

The 82527 also implements a global masking feature for message filtering. This feature allows the user to
globally mask any identifier bits of the incoming message. The programmable global mask can be used for
both standard and extended messages.

The 82527 PLCC offers hardware, or pinout, compatibility with the 82526. It is pin-to-pin compatible with the
82526 except for pins 9, 30, and 44. These pins are used as chip selects on the 82526 and are used as CPU
interface mode selection pins on the 82527.

The 82527 is fabricated using Intel’s reliable CHMOS III 5V technology and is available in either 44-lead PLCC
or 44-lead QFP for the automotive temperature range (

Y

Programmable Bit Rate

Y

Programmable Clock Output

Y

Flexible Interrupt Structure

Y

Flexible Status Interface

Y

Configurable Output Driver

Y

Configurable Input Comparator

Y

Two 8-Bit Bidirectional I/O Ports

Y

44-Lead PLCC Package

Y

44-Lead QFP Package

Y

Pinout Compatibility with the 82526

b

40§Ctoa125§C).

*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

December 1995COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 272250-006

82527

272250– 1

Figure 1. 82527 Block Diagram

272250– 2

Figure 2. 44-Pin PLCC Package

2

Figure 3. 44-Pin QFP Package

82527

272250– 15

3

82527

PIN DESCRIPTION

The 82527 pins are described in this section. Table 1 presents the legend for interpreting the pin types.

Table 1. Pin Type Legend

Symbol Description

I Input only pin

O Output only pin

I/O Pin can be either input or output

PIN DESCRIPTIONS

Pin Name Pin Type Pin Description

V

SS1

V

SS2

V

CC

XTAL1 I Input for an external clock. XTAL1 (along with XTAL2) are the crystal

XTAL2 O Push-pull output from the internal oscillator. XTAL2 (along with XTAL1) are the

CLKOUT O Programmable clock output. This output may be used to drive the oscillator of

RESET

Ý

CS

Ý

INT
(V

/2) O

CC

RX0 I Inputs from the CAN bus line(s) to the input comparator. A recessive level is
RX1 I

TX0 O Serial data push-pull output to the CAN bus line. During a recessive bit TX0 is
TX1 O

Ground GROUND connection must be connected externally to a VSSboard plane.

Provides digital ground.

Ground GROUND connection must be connected externally to a VSSboard plane.

Provides ground for analog comparator.

Power POWER connection must be connected externally toa5V DC. Provides power

for entire device.

connections to an internal oscillator.

crystal connections to an internal oscillator. If an external oscillator is used
XTAL2 must be floated, or not be connected. XTAL2 must not be used as a
clock output to drive other CPUs.

the host microcontroller.

Ý

I Warm Reset: (VCCremains valid while RESETÝis asserted), RESETÝmust be

driven to a valid low level for 1 ms minimum.
Cold Reset: (V
must be driven low for 1 ms minimum measured from a valid VCClevel. No

is driven to a valid level while RESETÝis asserted), RESET

CC

falling edge on the reset pin is required during a cold reset event.

I A low level on this pin enables CPU access to the 82527 device.

O The interrupt pin is an open-drain output to the host microcontroller. VCC/2 is

the power supply for the ISO low speed physical layer. The function of this pin is
determined by the MUX bit in the CPU Interface Register (Address 02H) as
follows:

e

MUX

1: pin 24 (PLCC)eVCC/2, pin 11eINT

MUXe0: pin 24 (PLCC)eINT

read when RX0

l

RX1. A dominant level is read when RX1lRX0. When the

Ý

Ý

CoBy bit (Bus Configuration register) is programmed as a ‘‘1’’, the input
comparator is bypassed and RX0 is the CAN bus line input.

high and TX1 is low. During a dominant bit TX0 is low and TX1 is high.

Ý

4

82527

Pin Name Pin Type Pin Description

AD0/A0/ICP I/O-I-I Address/Data bus in 8-bit multiplexed mode.
AD1/A1/CP I/O-I-I Address bus in 8-bit non-multiplexed mode.
AD2/A2/CSAS I/O-I-I Low byte of A/D bus in 16-bit multiplexed mode.
AD3/A3/STE I/O-I In Serial Interface mode, the following pins have the following meaning:
AD4/A4/MOSI I/O-I-I AD0: ICP Idle Clock Polarity
AD5/A5 I/O-I AD1: CP Clock Phase
AD6/A6/SCLK I/O-I-I AD2: CSAS Chip Select Active State
AD7/A7 I/O-I AD3: STE Sync Transmit Enable

AD8/D0/P1.0 I/O-O-I/O High byte of A/D bus in 16-bit multiplexed mode.
AD9/D1/P1.1 I/O-O-I/O Data bus in 8-bit non-multiplexed mode.
AD10/D2/P1.2 I/O-O-I/O Low speed I/O port. P1 pins in 8-bit multiplexed mode and serial mode.
AD11/D3/P1.3 I/O-O-I/O
AD12/D4/P1.4 I/O-O-I/O

Port pins have weak pullups until the port is configured by writing to 9FH
and AFH.

AD13/D5/P1.5 I/O-O-I/O
AD14/D6/P1.6 I/O-O-I/O
AD15/D7/P1.7 I/O-O-I/O

P2.0 I/O P2 in all modes.
P2.1 I/O P2.6 is INTÝwhen MUXe1 and is open-drain.
P2.2 I/O P2.7 is WRH

Ý

P2.3 I/O
P2.4 I/O
P2.5 I/O
P2.6/INT
P2.7/WRH

Ý

Ý

I/O-O

I/O-I

Mode0 I These pins select one of the four parallel interfaces. These pins are
Mode1 I

weakly held low during reset.

Mode1 Mode0

0 0 8-bit multiplexed Ð Intel
0 0 Serial Interface mode entered when RD

0 1 16-bit multiplexed Ð Intel
1 0 8-bit multiplexed Ð non-Intel
1 1 8-bit non-multiplexed

ALE/AS I-I ALE used for Intel modes.

AS used for non-Intel modes, except Mode 3 this pin must be tied high.

RD

Ý

IRD

Ý

used for Intel modes.

E I E used for non-Intel modes, except Mode 3 Asynchronous this pin must

be tied high.

WRÝ/WRL

Ý

R/W

Ý

IWR
I R/WÝused for non-Intel modes.

Ý

in 8-bit Intel mode and WRLÝin 16-bit Intel mode.

READY O READY is an output to synchronize accesses from the host
MISO O

microcontroller to the 82527. READY is an open-drain output to the host
microcontroller. MISO is the serial data output for the serial interface
mode.

DSACK0

Ý

O DSACK0Ýis an open-drain output to synchronize accesses from the host

microcontroller to the 82527.

AD6: SCLK Serial Clock Input
AD4: MOSI Serial Data Input

in 16-bit multiplexed mode.

e

Ý

WR

0 upon reset.

e

Ý

0,

5

82527

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS*

Storage Temperature ААААААААААb60§Ctoa150§C

Voltage from Any Pin

to V

АААААААААААААААААААААААb0.5V toa7.0V

SS

NOTICE: This is a production data sheet. The specifi­cations are subject to change without notice.

*

WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex­tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.

Laboratory testing shows the 82527 will withstand
up to 10 mA of injected current into both RX0 and
RX1 pins for a total of 20 days without sustaining
permanent damage. This high current condition may
be the result of shorted signal lines. The 82527 will
not function properly if the RX0/RX1 input voltage
exceeds V

D.C. Characteristics V

CC

a

0.5V.

CC

e

5Vg10%; T

eb

40§Ctoa125§C

A

Symbol Parameter Min Max Conditions

V

IL

V

IL1

V

IL2

V

IL3

V

IH

V

IH1

V

IH2

V

IH3

V

OL

V

OH

V

OHR1

I

LK

C

IN

Input Low Voltage (All except RX0, RX1,
AD0–AD7 in Mode 3)

Input Low Voltage for AD0–AD7 in
Mode 3

Input Low Voltage (RX0) for Comparator 0.5V
Bypass Mode

Input Low Voltage for Port 1 and Port 2 0.3 V
Pins Not Used for Interface to Host CPU

Input High Voltage (All except RX0, RX1, 3.0V V

Ý

RESET

)

Input High Voltage (RESETÝ) 3.0V V
Hysteresis on RESET

Ý

Input High Voltage (RX0) for Comparator 4.0V
Bypass Mode

Input High Voltage for Port 1 and Port 2 0.7 V
Pins Not Used for Interface to Host CPU

Output Low Voltage (All Outputs except 0.45V I
TX0, TX1)

Output High Voltage (All Outputs except V
TX0, TX1, CLOCKOUT)

Output High Voltage (CLOCKOUT) 0.8 V

Input Leakage Current

PIN Capacitance** 10 pF f

b

0.5V 0.8V

b

0.5V 0.5V

CC

CC

200 mV

CC

b

0.8V I

CC

CC

CC

a

0.5V

a

0.5V

OL

OH

I

OH

g

10 mAV

XTAL

SS

e

1.6 mA

eb

eb

k

e

V

IN

1 KHz

200 mA

80 mA

k

V

CC

6

82527

D.C. Characteristics V

CC

e

5Vg10%; T

eb

40§Ctoa125§C

A

Symbol Parameter Min Max Conditions

I

CC

I

SLEEP

Supply Current

Sleep Current

(1)

(1)

50 mA f

XTAL

e

with VCC/2 Output Enabled, No Load 700 mA
with V

I

PD

NOTES:

**Typical value based on characterization data.

Port pins are weakly held after reset until the port configuration registers are written (9FH, AFH).

1. All pins are driven to V

Powerdown Current

/2 Output Disabled 100 mA

CC

(1)

or VCCincluding RX0 and RX1.

SS

25 mA XTAL1 Clocked

PHYSICAL LAYER SPECIFICATIONS Load Condition: 100 pF

D.C. Characteristics V

CC

e

5Vg10%; T

RX0/RX1 and TX0/TX1 Min Max Conditions

Input Voltage

Common Mode Range V

Differential Input Threshold

Internal Delay 1: Sum of the Comparator Input 60 ns Load on TX0, TX1
Delay and the TX0/TX1 Output Driver Delay 100 pF,a100 mV to

Internal Delay 2: Sum of the RX0 Pin Delay (if 50 ns Load on TX0, TX1
the Comparator is Bypassed) and the TX0/TX1 100 pF
Output Driver Delay

Source Current on Each TX0, TX1

Sink Current on Each TX0, TX1 10 mA V

Input Hysteresis for RX0/RX1 0V

VCC/2

VCC/2 2.38V 2.62V I

eb

40§Ctoa125§C

A

b

SS

g

0.5V V

a

1V V

100 mV

a

0.5V

CC

b

1V

CC

b

10 mA V

b

100 mV RX0/RX1

differential

e

b

V

OUT

OUT

OUT

e

1.0V

s

75 mA, V

CC

1.0V

CC

16 MHz

e

e

e

5V

CLOCKOUT SPECIFICATIONS

Load Condition: 50 pF

Parameter Min Max

CLOCKOUT Frequency XTAL/15 XTAL

7