Intel Corporation AN87C196KR, AN87C196KQ, AN87C196JV, AN87C196JT, AN87C196JR Datasheet
...
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changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
November 1995COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 270827-006
87C196KR/KQ 87C196JV/JT 87C196JR/JQ
ADVANCED 16-BIT CHMOS MICROCONTROLLER
Automotive
Y
b
40§Ctoa125§C Ambient
Y
High Performance CHMOS 16-Bit CPU
Y
Up to 48 Kbytes of On-Chip EPROM
Y
Up to 1.5 Kbytes of On-Chip Register
RAM
Y
Up to 512 Bytes of Additional RAM
(Code RAM)
Y
Register-Register Architecture
Y
Up to 8 Channel/10-Bit A/D with
Sample/Hold
Y
Up to 37 Prioritized Interrupt Sources
Y
Up to Seven 8-Bit (56) I/O Ports
Y
Full Duplex Serial I/O Port
Y
Dedicated Baud Rate Generator
Y
Interprocessor Communication Slave
Port
Y
High Speed Peripheral Transaction
Server (PTS)
Y
Two 16-Bit Software Timers
Y
10 High Speed Capture/Compare (EPA)
Y
Full Duplex Synchronous Serial I/O
Port (SSIO)
Y
Two Flexible 16-Bit Timer/Counters
Y
Quadrature Counting Inputs
Y
Flexible 8-/16-Bit External Bus
Y
Programmable Bus (HLD/HLDA)
Y
1.75 ms 16 x 16 Multiply
Y
3 ms 32/16 Divide
Y
68-Pin and 52-Pin PLCC Packages
Device Pins/Package EPROM Reg RAM Code RAM I/O EPA SIO SSIO A/D
87C196KR 68-pin PLCC 16K 488 256 56 10 Y Y 8
87C196KQ 68-pin PLCC 12K 360 128 56 10 Y Y 8
87C196JV 52-pin PLCC 48K 1.5K 512 41 6 Y Y 6
87C196JT 52-pin PLCC 32K 1.0K 512 41 6 Y Y 6
87C196JR 52-pin PLCC 16K 488 256 41 6 Y Y 6
87C196JQ 52-pin PLCC 12K 360 128 41 6 Y Y 6
The 87C196KR/KQ JV/JT JR/JQ devices represent the fourth generation of MCSÉ96 Microcontroller products implemented on Intel’s advanced 1 micron process technology. These products are based on the
80C196KB device with improvements for automotive applications. The instruction set is a true super set of
80C196KB. The 87C196JR is a 52-pin version of the 87C196KR device, while the 87C196KQ/JQ are memory
scalars of the 87C196KR/JR.
The 87C196JV/JT A-step devices (JV-A, JT-A) are the newest members of the MCS 96 microcontroller family.
These devices are memory scalars of the 87C196JR D-step (JR-D) and are designed for strict functional and
electrical compatibility. The JT-A has 32 Kbytes of on-chip EPROM, 1.0 Kbytes of Register RAM and 512
bytes of Code RAM. The JV-A has 48 Kbytes of on-chip EPROM, 1.5 Kbytes of Register RAM and 512 bytes
of Code RAM.
87C196KR/KQ 87C196JV/JT 87C196JR/JQ
The MCS 96 microcontroller family members are all
high performance microcontrollers with a 16-bit
CPU. The 87C196Kx/Jx family members listed
above are composed of the high-speed (16 MHz)
core as well as the following peripherals: up to 48
Kbytes of Programmable EPROM, up to 1.5 Kbytes
of Register RAM, 512 bytes of code RAM (16-bit
addressing modes) with the ability to execute from
this RAM space, an eight channel-10-Bit/
g
3 LSB
analog to digital converter with programmable S/H
times with conversion times
k
5 ms at 16 MHz, an
asynchronous/synchronous serial I/O port (8096
compatible) with a dedicated 16-bit baud rate generator, an additional synchronous serial I/O port (8096
compatible) with a dedicated 16-bit baud rate generator, an additional synchronous serial I/O port with
full duplex master/slave transceivers, a flexible timer/counter structure with prescaler, cascading, and
quadrature capabilities, 10 modularized multiplexed
high speed I/O for capture and compare (called
Event Processor Array) with 250 ns resolution and
double buffered inputs, a sophisticated prioritized interrupt structure with programmable Peripheral
Transaction Server (PTS). The PTS has several
channel modes, including single/burst block transfers from any memory location to any memory location, a PWM and PWM toggle mode to be used in
conjunction with the EPA, and an A/D scan mode.
Additional SFR space is allocated for the EPA and
can be ‘‘windowed’’ into the lower Register RAM
area.
Please refer to the following datasheets for higher
frequency versions of devices contained within this
datasheet: 20 MHz 87C196JT: Order
Ý
272529;
20 MHz 87C196JV: Order Number 272580.
ARCHITECTURE
The 87C196KR/KQ/JV/JT/JR/JQ are members of
the MCS 96 microcontroller family, has the same architecture and uses the same instruction set as the
80C196KB/KC. Many new features have been added including:
CPU FEATURES
#
Powerdown and Idle Modes
#
16 MHz Operating Frequency
#
A High Performance Peripheral Transaction Server (PTS)
#
Up to 37 Interrupt Vectors
#
Up to 512 Bytes of Code RAM
#
Up to 1.5 Kbytes of Register RAM
#
‘‘Windowing’’ Allows 8-Bit Addressing to Some
16-Bit Addresses
#
1.75 ms 16 x 16 Multiply
#
3 ms 32/16 Divide
#
Oscillator Fail Detect
PERIPHERAL FEATURES
#
Programmable A/D Conversion and S/H Times
#
10 Capture/Compare I/O with 2 Flexible Timers
#
Synchronous Serial I/O Port for Full Duplex Serial I/O
#
Total Utilization of ALL Available Pins (I/O Mux’d
with Control)
#
2 16-Bit Timers with Prescale, Cascading and
Quadrature Counting Capabilities
#
Up to 12 Externally Triggered Interrupts
NEW INSTRUCTIONS
XCH/XCHB
Exchange the contents of two locations, either Word
or Byte is supported.
BMOVi
Interruptable Block Move Instruction, allows the user
to be interrupted during long executing Block Moves.
TIJMP
Table Indirect JUMP. This instruction incorporates a
way to do complex CASE level branches through
one instruction. An example of such code savings:
several interrupt sources and only one interrupt vector. The TIJMP instruction will sort through the
sources and branch to the appropriate sub-code level in one instruction. This instruction was added especially for the EPA structure, but has other code
saving advantages.
EPTS/DPTS
Enable and Disable PTS Interrupts (Works like EI
and DI).
2
87C196KR/KQ 87C196JV/JT 87C196JR/JQ
SFR OPERATION
An additional 256 bytes of SFR registers were added to the 8XC196KR devices. These locations were
added to support the wide range of on-chip peripherals that the 8XC196KR has. This memory space
(1F00–1FFFH) has the ability to be addressed as
direct 8-bit addresses through the ‘‘windowing’’
technique. Any 32-, 64- or 128-byte section can be
relocated in the upper 32, 64 or 128 bytes of the
internal register RAM (080– FFH) address space.
270827– 1
Figure 1. Block Diagram
270827– 15
Figure 2. The 8XC196KR Family Nomenclature
3
87C196KR/KQ 87C196JV/JT 87C196JR/JQ
270827– 2
270827– 3
Figure 3. Package Diagrams
4
87C196KR/KQ 87C196JV/JT 87C196JR/JQ
PIN DESCRIPTIONS
Symbol Name and Function
V
CC
Main supply voltage (a5V).
VSS,VSS,V
SS
Digital circuit ground (0V). There are three VSSpins, all of which MUST be
connected to a single ground plane.
V
REF
Reference for the A/D converter (a5V). V
REF
is also the supply voltage to the
analog portion of the A/D converter and the logic used to read Port 0. Must be
connected for A/D and Port 0 to function.
V
PP
Programming voltage for the EPROM parts. It should bea12.5V for
programming. It is also the timing pin for the return from powerdown circuit.
Connect this pin with a 1 mF capacitor to V
SS
anda1MXresistor to VCC. If this
function is not used, V
PP
may be tied to VCC.
ANGND Reference ground for the A/D converter. Must be held at nominally the same
potential as VSS.
XTAL1 Input of the oscillator inverter and the internal clock generator.
XTAL2 Output of the oscillator inverter.
P2.7/CLKOUT Output of the internal clock generator. The frequency is (/2 the oscillator
frequency. It has a 50% duty cycle. Also LSIO pin.
RESET Reset input to the chip. Input low for at least 16 state times will reset the chip. The
subsequent low to high transition resynchronizes CLKOUT and commences a 10state time sequence in which the PSW is cleared, bytes are read from 2018H and
201AH loading the CCBs, and a jump to location 2080H is executed. Input high for
normal operation. RESET
has an internal pullup.
P5.7/BUSWIDTH Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin
dynamically controls the Bus width of the bus cycle in progress. If BUSWIDTH is
low, an 8-bit cycle occurs. If BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1
is ‘‘0’’ and CCR1 bit 2 is ‘‘1’’, all bus cycles are 8-bit, if CCR bit 1 is ‘‘1’’ and CCR1
bit 2 is ‘‘0’’, all bus cycles are 16-bit. CCR bit 1e‘‘0’’ and CCR1 bit 2e‘‘0’’ is
illegal. Also an LSIO pin when not used as BUSWIDTH.
NMI A positive transition causes a non-maskable interrupt vector through memory
location 203EH. Used by Intel (GND this pin).
P5.1/INST Output high during an external memory read indicates the read is an instruction
fetch. INST is valid throughout the bus cycle. INST is active only during external
memory fetches, during internal[EP]ROM fetches INST is held low. Also LSIO
when not INST.
EA Input for memory select (External Access). EA equal to a high causes memory
accesses to locations 2000H through 5FFFH to be directed to on-chip EPROM/
ROM. EA
equal to a low causes accesses to these locations to be directed to off-
chip memory. EA
ea
12.5V causes execution to begin in the Programming
Mode. EA
latched at reset.
P5.0/ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin
options provide a latch to demultiplex the address from the address/data bus.
When the pin is ADV
, it goes inactive (high) at the end of the bus cycle. ADV can
be used as a chip select for external memory. ALE/ADV
is active only during
external memory accesses. Also LSIO when not used as ALE.
5
87C196KR/KQ 87C196JV/JT 87C196JR/JQ
PIN DESCRIPTIONS (Continued)
Symbol Name and Function
P5.3/RD Read signal output to external memory. RD is active only during external memory
reads or LSIO when not used as RD
.
P5.2/WR/WRL Write and Write Low output to external memory, as selected by the CCR, WR will
go low for every external write, while WRL
will go low only for external writes
where an even byte is being written. WR
/WRL is active during external memory
writes. Also an LSIO pin when not used as WR/WRL.
P5.5/BHE/WRH Byte High Enable or Write High output, as selected by the CCR. BHEe0 selects
the bank of memory that is connected to the high byte of the data bus. A0
e
0
selects that bank of memory that is connectd to the low byte. Thus accesses to a
16-bit wide memory can be to the low byte only (A0
e
0, BHE
e
1), to the high
byte only (A0
e
1, BHEe0) or both bytes (A0e0, BHEe0). If the WRH
function is selected, the pin will go low if the bus cycle is writing to an odd memory
location. BHE
/WRH is only valid during 16-bit external memory write cycles. Also
an LSIO pin when not BHE/WRH.
P5.6/READY Ready input to lengthen external memory cycles, for interfacing with slow or
dynamic memory, or for bus sharing. If the pin is high, CPU operation continues in
a normal manner. If the pin is low prior to the falling edge of CLKOUT, the memory
controller goes into a wait state mode until the next positive transition in CLKOUT
occurs with READY high. When external memory is not used, READY has no
effect. The max number of wait states inserted into the bus cycle is controlled by
the CCR/CCR1. Also an LSIO pin when READY is not selected.
P5.4/SLPINT Dual functional I/O pin. As a bidirectional port pin or as a system function. The
system function is a Slave Port Interrupt Output Pin.
P6.2/T1CLK Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however it
may also be used as a TIMER1 Clock input. The TIMER1 will increment or
decrement on both positive and negative edges of this pin.
P6.3/T1DIR Dual function I/Opin. Primary function is that of a bidirectional I/O pin, however it
may also be used as a TIMER1 Direction input. The TIMER1 will increment when
this pin is high and decrements when this pin is low.
PORT1/EPA0–7 Dual function I/O port pins. Primary function is that of bidirectional I/O. System
function is that of High Speed capture and compare. EPA0 and EPA2 have yet
P6.0–6.1/EPA8– 9
another function of T2CLK and T2DIR of the TIMER2 timer/counter.
PORT 0/ACH0 – 7 8-bit high impedance input-only port. These pins can be used as digital inputs
and/or as analog inputs to the on-chip A/D converter. These pins are also used
as inputs to EPROM parts to select the Programming Mode.
P6.4–6.7/SSIO Dual function I/O ports that have a system function as Synchronous Serial I/O.
Two pins are clocks and two pins are data, providing full duplex capability.
PORT 2 8-bit multi-functional port. All of its pins are shared with other functions.
PORT 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with
the multiplexed address/data bus which has strong internal pullups.
6
87C196KR/KQ 87C196JV/JT 87C196JR/JQ
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS**
Storage Temperature ААААААААААb60§Ctoa150§C
Voltage from VPPor EA to
V
SS
or ANGND ААААААААААААААb0.5V toa13.0V
Voltage from Any Other Pin
to V
SS
or ANGND АААААААААААААb0.5V toa7.0V
This includes V
PP
on ROM and CPU devices.
Power DissipationАААААААААААААААААААААААААА0.5W
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
*
WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
OPERATING CONDITIONS
Symbol Parameter Min Max Units
T
A
Ambient Temperature under Bias
b
40
a
125
§
C
V
CC
Digital Supply Voltage 4.50 5.50 V
V
REF
Analog Supply Voltage 4.50 5.50 V
F
OSC
Oscillator Frequency 4 16 MHz
(4)
NOTE:
ANGND and V
SS
should be nominally at the same potential.
DC CHARACTERISTICS (Under Listed Operating Conditions)
Symbol Parameter Min Typ Max Units Test Conditions
I
CC
VCCSupply Current 75 mA XTAL1e16 MHz,
(
b
40§Ctoa125§C (JVe80) V
CC
e
V
PP
e
V
REF
e
5.5V
Ambient) 50 (While Device in Reset)
I
CC1
Active Mode Supply 50 mA
Current (Typical) (JV
e
55)
I
REF
A/D Reference
25mA
Supply Current
I
IDLE
Idle Mode Current 15 30 mA XTAL1e16 MHz,
(JV
e
32) V
CC
e
V
PP
e
V
REF
e
5.5V
I
PD
Powerdown Mode
50 TBD mA
V
CC
e
V
PP
e
V
REF
e
5.5V
Current (Note 6)
V
IL
Input Low Voltage
b
0.5V 0.3 V
CC
V
(All Pins)
V
IH
Input High Voltage 0.7 V
CC
V
CC
a
0.5 V (Note 7)
(All Pins)
V
OL
Output Low Voltage 0.3 V I
OL
e
200 mA (Notes 3, 5)
(Outputs Configured 0.45 V I
OL
e
3.2 mA
as Push/Pull) 1.5 V I
OL
e
7.0 mA
7
87C196KR/KQ 87C196JV/JT 87C196JR/JQ
DC CHARACTERISTICS (Under Listed Operating Conditions) (Continued)
Symbol Parameter Min Typ Max Units Test Conditions
V
OH
Output High Voltage V
CC
b
0.3 V I
OH
eb
200 mA (Notes 3, 5)
(Outputs Configured V
CC
b
0.7 V I
OH
eb
3.2 mA
as Push/Pull) V
CC
b
1.5 V I
OH
eb
7.0 mA
I
LI
Input Leakage Current
g
8 mAV
SS
s
V
IN
s
V
CC
(Std. Inputs) JT/JV:g10 (Note 2)
I
LI1
Input Leakage Current
g
1 mAV
SS
s
V
IN
s
V
REF
(Port 0ÐA/D Inputs) JT/JV:g2
I
IH
Input High Current
a
175 mAV
SS
s
V
IN
s
V
CC
(NMI Pin)
V
OH2
Output High Voltage V
CC
b
1V V I
OH
eb
15 mA (Notes 1, 8)
in RESET
I
OH2
Output High Current
b
6
b
35 mAV
OH2
e
V
CC
b
1.0V
(KR, KQ) in RESET
b
15
b
60 mAV
OH2
e
V
CC
b
2.5V
b
20
b
70 mAV
OH2
e
V
CC
b
4.0V
I
OH2
Output High
b
30
b
120 mAV
OH2
e
V
CC
b
1.0V
(JV, JT, Current in
b
75
b
240 mAV
OH2
e
V
CC
b
2.5V
JR-D, JQ-D) RESET
b
90
b
280 mAV
OH2
e
V
CC
b
4.0V
R
RST
Reset Pullup Resistor 6K 65K X
V
OL3
Output Low Voltage 0.3 V I
OL3
e
4 mA (Note 9)
in RESET 0.5 V I
OL3
e
6mA
(RESET Pin only) 0.8 V I
OL3
e
10 mA
C
S
Pin Capacitance 10 pF F
TEST
e
1.0 MHz
(Any Pin to V
SS
)
R
WPU
Weak Pullup Resistance 150K X (Note 6)
(Approx)
NOTES:
1. All BD (bidirectional) pins except P5.1/INST and P2.7/CLKOUT which are excluded due to their not being weakly pulled
high in reset. BD pins include Port1, Port2, Port3, Port4, Port5 and Port6.
2. Standard Input pins include XTAL1, EA
, RESET and Ports 1, 2, 3, 4, 5, 6 when configured as inputs.
3. All Bidirectional I/O pins when configured as Outputs (Push/Pull).
4. Device is Static and should operate below 1 Hz, but only tested down to 4 MHz.
5. Maximum I
OL/IOH
currents per pin will be characterized and published at a later date. Target values areg10 mA.
6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
V
REF
e
V
CC
e
5.0V.
7. V
IH
max for Port0 is V
REF
a
0.5V.
8. Refer to ‘‘V
OH2/IOH2
Specification’’ errataÝ1 in errata section of this datasheet.
9. This specification is not tested in production and is based upon theoretical estimates and/or product characterization.
8
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