Intel Corporation AN87C196KD Datasheet

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changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

January 1995COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 272168-002

87C196KD

16-BIT HIGH PERFORMANCE CHMOS

MICROCONTROLLER

Automotive

Y

b

40§Ctoa125§C

Y

32 Kbytes of On-Chip EPROM

Y

232 Byte Register File

Y

768 Bytes of Additional RAM

Y

Register-to-Register Architecture

Y

28 Interrupt Sources/16 Vectors

Y

Peripheral Transaction Server

Y

1.75 ms 16 x 16 Multiply (16 MHz)

Y

3.0 ms 32/16 Divide (16 MHz)

Y

Powerdown and Idle Modes

Y

Five 8-Bit I/O Ports

Y

16-Bit Watchdog Timer

Y

Dynamically Configurable 8-Bit or
16-Bit Buswidth

Y

Full Duplex Serial Port

Y

High Speed I/O Subsystem

Y

16-Bit Timer

Y

16-Bit Up/Down Counter with Capture

Y

3 Pulse-Width-Modulated Outputs

Y

Four 16-Bit Software Timers

Y

8- or 10-Bit 8-Channel A/D Converter
with Sample/Hold

Y

HOLD/HLDA Bus Protocol

Y

OTP One-Time Programmable and
QROM Versions

Y

Available in 12 MHz and 16 MHz
Versions

Y

16 MHz Operation

The 87C196KD 16-bit microcontroller is a high-performance member of the MCSÉ96 microcontroller family.
The 87C196KD is an enhanced 8XC196KC device with 1000 bytes RAM, 16 MHz operation and 32 Kbytes of
on-chip EPROM. Intel’s CHMOS process provides a high-performance processor along with low power con­sumption.

Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter.

NOTICE:

This datasheet contains information on products in full production. Specifications within this datasheet
are subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design.

MCSÉ96 is a registered trademark of Intel Corporation.

AUTOMOTIVE 87C196KD

272168– 1

Figure 1. 87C196KD Block Diagram

272168– 2

Figure 2. The 87C196KD Family Nomenclature

87C196KD Enhanced Feature Set over the 87C196KC

1. The 87C196KD has twice the RAM and twice the EPROM of the 87C196KC.

2. The vertical windowing scheme has been extended to allow all 1000 bytes of register RAM to be windowed
into the lower register file.

3. A CLKOUT disable bit has been added to the IOC3 SFR. This can be used to reduce noise in systems not
requiring the CLKOUT signal.

2

AUTOMOTIVE 87C196KD

PACKAGING

PLCC Description PLCC Description PLCC Description

9 ACH7/P0.7 54 AD6/P3.6 31 P1.6/HLDA
8 ACH6/P0.6 53 AD7/P3.7 30 P1.5/BREQ
7 ACH2/P0.2 52 AD8/P4.0 29 HSO.1
6 ACH0/P0.0 51 AD9/P4.1 28 HSO.0
5 ACH1/P0.1 50 AD10/P4.2 27 HSO.5/HSI.3
4 ACH3/P0.3 49 AD11/P4.3 26 HSO.4/HSI.2
3 NMI 48 AD12/P4.4 25 HSI.1
2EA 47 AD13/P4.5 24 HSI.0
1V

CC

46 AD14/P4.6 23 P1.4/PWM2

68 V

SS

45 AD15/P4.7 22 P1.3/PWM1
67 XTAL1 44 T2CLK/P2.3 21 P1.2
66 XTAL2 43 READY 20 P1.1
65 CLKOUT 42 T2RST/P2.4 19 P1.0
64 BUSWIDTH 41 BHE

/WRH 18 TXD/P2.0

63 INST 40 WR

/WRL

17 RXD/P2.1

62 ALE/ADV

39 PWM0/P2.5 16 RESET
61 RD 38 P2.7/T2CAPTURE 15 EXTINT/P2.2
60 AD0/P3.0 37 V

PP

14 V

SS

59 AD1/P3.1 36 V

SS

13 V

REF

58 AD2/P3.2 35 HSO.3 12 ANGND
57 AD3/P3.3 34 HSO.2 11 ACH4/P.04
56 AD4/P3.4 33 P2.6/T2UP-DN 10 ACH5/P.05
55 AD5/P3.5 32 P1.7/HOLD

Figure 3. 68-Pin PLCC Functional Pin-out

3

AUTOMOTIVE 87C196KD

272168– 3

Figure 4. 68-Pin PLCC Package

Table 1. Prefix Identification

PLCC

87C196KD AN87C196KD*

*OTP Version

4

AUTOMOTIVE 87C196KD

PIN DESCRIPTIONS

Symbol Name and Function

V

CC

Main supply voltage (5V).

V

SS

Digital circuit ground (0V). There are three VSSpins, all of which must be connected.

V

REF

Reference voltage for the A/D converter (5V). V

REF

is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D
and Port 0 to function.

ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as

V

SS

.

V

PP

Timing pin for the return from powerdown circuit. Connect this pin with a 1 mF capacitor to
V

SS

anda1MXresistor to VCC. If this function is not used VPPmay be tied to VCC. This pin

is the programming voltage on the EPROM device.

XTAL1 Input of the oscillator inverter and of the internal clock generator.

XTAL2 Output of the oscillator inverter.

CLKOUT Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator

frequency.

RESET Reset input to the chip.

BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus

cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH isa0an
8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.

NMI A positive transition causes a vector through 203EH.

INST Output high during an external memory read indicates the read is an instruction fetch. INST

is valid throughout the bus cycle. INST is activated only during external memory accesses
and output low for a data fetch.

EA Input for memory select (External Access). EA equal to a TTL-high causes memory

accesses to locations 2000H through 5FFFH to be directed to on-chip ROM/EPROM. EA
equal to a TTL-low causes accesses to those locations to be directed to off-chip memory.

ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options

provide a signal to demultiplex the address from the address/data bus. When the pin is
ADV

, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during

external memory accesses.

RD Read signal output to external memory. RD is activated only during external memory reads.

WR/WRL Write and Write Low output to external memory, as selected by the CCR. WR will go low for

every external write, while WRL

will go low only for external writes where an even byte is

being written. WR

/WRL is activated only during external memory writes.

BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCR. BHE

e

0 selects the bank of memory that is connected to the high byte of the data bus. A0e0
selects the bank of memory that is connected to the low byte of the data bus. Thus
accesses to a 16-bit wide memory can be to the low byte only (A0

e

0, BHEe1), to the
high byte only (A0e1, BHEe0), or both bytes (A0e0, BHEe0). If the WRH function is
selected, the pin will go low if the bus cycle is writing to an odd memory location. BHE

/WRH

is valid only during 16-bit external memory write cycles.

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AUTOMOTIVE 87C196KD

PIN DESCRIPTIONS (Continued)

Symbol Name and Function

READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,

or for bus sharing. When the external memory is not being used, READY has no effect.

HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3.

Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.

HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,

HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.

Port 0 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as

analog inputs to the on-chip A/D converter.

Port 1 8-bit quasi-bidirectional I/O port.

Port 2 8-bit multi-functional port. All of its pins are shared with other functions in the 87C196KD.

Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the

multiplexed address/data bus.

HOLD Bus Hold input requesting control of the bus.

HLDA Bus Hold acknowledge output indicating release of the bus.

BREQ Bus Request output activated when the bus controller has a pending external memory

cycle.

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AUTOMOTIVE 87C196KD

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings*

Ambient Temperature

Under Bias ААААААААААААААААА

b

40§Ctoa125§C

Storage Temperature ААААААААААb65§Ctoa150§C

Voltage On Any Pin to V

SS

Except EA and VPPААААААААААААb0.5V toa7.0V

Voltage from EA or

V

PP

to VSSААААААААААААААААААb0.5V toa13.0V

Power Dissipation АААААААААААААААААААААААА0.43W

NOTICE: This is a production data sheet. The specifi­cations are subject to change without notice.

*

WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex­tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.

OPERATING CONDITIONS

Symbol Description Min Max Units

T

A

Ambient Temperature Under Bias

b

40

a

125

§

C

V

CC

Digital Supply Voltage 4.50 5.50 V

V

REF

Analog Supply Voltage 4.50 5.50 V

F

OSC

Oscillator Frequency 4 16 MHz

NOTE:

ANGND and V

SS

should be nominally at the same potential.

DC CHARACTERISTICS (Over Specified Operating Conditions)

Symbol Description Min Max Units Test Conditions

V

IL

Input Low Voltage

b

0.5 0.8 V

V

IH

Input High Voltage (Note 1) 0.2 V

CC

a

1.0 V

CC

a

0.5 V

V

IH1

Input High Voltage on XTAL 1, EA 0.7 V

CC

V

CC

a

0.5 V

V

IH2

Input High Voltage on RESET 2.2 V

CC

a

0.5 V

V

OL

Output Low Voltage 0.3 V I

OL

e

200 mA

0.45 V I

OL

e

2.8 mA

1.5 V I

OL

e

7mA

V

OL1

Output Low Voltage 0.8 V I

OL

ea

0.2 mA

in RESET on P2.5 (Note 2)

V

OH

Output High Voltage V

CC

b

0.3 V I

OH

eb

200 mA

(Standard Outputs) V

CC

b

0.7 V I

OH

eb

3.2 mA

V

CC

b

1.5 V I

OH

eb

7mA

V

OH1

Output High Voltage V

CC

b

0.3 V I

OH

eb

10 mA

(Quasi-bidirectional Outputs) V

CC

b

0.7 V I

OH

eb

30 mA

V

CC

b

1.5 V I

OH

eb

60 mA

I

OH2

Output High Current

b

0.8 mA V

IH

e

V

CC

b

1.5 V

In RESET on P2.0 (Note 2)

NOTES:

1. All pins except RESET, XTAL1 and EA.

2. Violating these specifications in Reset may cause the part to enter test modes.

7