Intel Corporation AN83C196LD-22, AN83C196LD-18, AN83C196LD, AN83C196LC-22, AN83C196LC-18 Datasheet

ADVANCE INFORMATION

COPYRIGHT © INTEL CORPORATION, 1996 December 1996 Order Number: 272805-001

83C196LC, 83C196LD

CHMOS 16-BIT MICROCONT R O LLER

Automotive

NOTE

This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify
with your local Intel sales office that you have the latest datasheet before finalizing a
design.

The 83C196LC, 83C196LD are low-cost, pin-compatible replacements for the existing 87C196JT and
87C196JR, respectively. These products feature an enhanced synchronous serial I/O (SSIO) port for more

flexible communication to other devices. The enhanced SSIO is compatible with Motorola’s Serial Peripheral
Interface (SPI) protocol and National’s Microwire protocol. To optimize die size, the A/D converter was
removed for use in those applications that use an off-chip A/D converter.

The MCS

®

96 microcontroller family members are all high-performanc e microcontrollers with 16-bit CPUs.
The 83C196LC, 83C196LD are composed of a high-speed core with the following peripherals: an
asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud-rate generator; an
additional synchronous serial I/O port with full duplex master/slave transceivers; a flexible timer/counter
structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O
for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs;
and a sophisticated, prioritized interrupt structure with programmable peripheral transaction server (PTS).
The 83C196LC has the highest memory density of the 52-pin MCS 96 microcontroller family, with 32 Kbytes
of on-chip ROM, 1 Kbyte of on-chip register RAM, and 512 bytes of code RAM. The high memory integration
of the 83C196LC supports high functionality in a low pin-count package and the use of the C programming
language.

■ 22 MHz operation

†

■ 32 Kbytes of on-chip ROM (LC)

16 Kbytes of on-chip ROM (LD)

■ 1 Kbyte of on-chip register RAM (LC)

384 bytes of on-chip register RAM (LD)

■ 512 bytes of on-chip code RAM

(LC only)

■ Register-to-register architecture

■ Peripheral transaction server (PTS)

with high-speed, microcoded interrupt
service routines

■ Full-duplex serial I/O port with

dedicated baud-rate generator

■ Enhanced full-duplex, synchronous

serial I/O port (SSIO)

†

12 MHz standard; 18 MHz and 22 MHz are speed
premium

■ High-speed event processor array

—Six capture/compare channels
—Two compare-only channels
— Two 16-bit software timers

■ Programmable 8- or 16-bit external bus

■ Design enhancements for EMI

reduction

■ Oscillator failure detection circuitry

■ SFR register that indicates the source

of the last reset

■ Watchdog timer (WDT)

■ Cost reduced replacements for the

87C196JT and 87C196JR.

■ –40° C to +125° C ambient temperature

■ 52-pin PLCC package

2 ADVANCE INFORMATION

83C196LC, 83C196L D — AUTOMOTIVE

Figure 1. 83C196LC, 83C196LD Block Diagram

Code/Data RAM

512 Bytes

(LC only)

Queue

Source (16)

Destination (16)

AD15:0

EPA

2 Timers

6 Capture/

Compare

Channels †

Bus

Controller

Watchdog

Timer

Enhanced

SSIO

ROM
32 Kbytes (LC)
16 Kbytes (LD)

A3383-01

SIO

Baud-rate

Generator

Port 6

Memory Data Bus (16)

Bus-Control

Interface Unit

Microcode

Engine

Peripheral

Transaction

Server

Memory

Interface

Unit

Register RAM

1 Kbyte (LC)

384 Bytes (LD)

ALU

Interrupt

Controller

Bus Control

Peripheral Addr Bus (10)

Peripheral Data Bus (16)

Memory Addr Bus (16)

2

Compare-only

Channels

Port 2

Port 1,6

† A seventh capture/compare channel (EPA7) is available as a software timer. It is not connected to a package pin.

Port 0

ADVANCE INFORMATION 3

AUTOMOTIVE — 83C196LC, 83C196LD

1.0 NOMENCLATURE OVERVIEW

Figure 2. Product Nomenclature

Table 1. Description of Product Nomenclature

Parameter Options Description

Temperature and Burn-in Options A Automotive operating temperature range (–40° C to

125° C ambient) with Intel standard burn-in.
Packaging Options N PLCC
Program-memory Options 3 Internal ROM
Process Information C CHMOS
Product Family 196L

x

8XC196Lx family of products
Device Speed no mark

18
22

12 MHz

18 MHz

22 MHz

Program Memory Options

XXXXX XXXX8XXX

Packaging Options

Temperature and Burn-in Options

A2815-01

Process Information

Product Family

Device Speed

4 ADVANCE INFORMATION

83C196LC, 83C196L D — AUTOMOTIVE

2.0 PINOUT

Figure 3. 83C196LC, 83C196LD 52-pin PLCC Package

Table 2. 83C196LC, 83C196LD 52-pin PLCC Package Pin Assignments

Pin Name Pin Name Pin Name Pin Name

1V

SS

14 AD8/P4.0 27 P2.0/TXD 40 V

CC

2 P5.0/ADV#/ALE 15 AD7/P3.7 28 P2.1/RXD 41 P1.3/EPA3
3V

SS

16 AD6/P3.6 29 P2.2/EXTINT 42 P1.2/EPA2/T2DIR

4V

PP

17 AD5/P3.5 30 P2.4 43 P1.1/EPA1
5 P5.3/RD# 18 AD4/P3.4 31 P2.6/ONCE# 44 P1.0/EPA0/T2CLK
6 P5.2/WR#/WRL# 19 AD3/P3.3 32 P2.7/CLKOUT 45 P6.0/EPA8
7 AD15/P4.7 20 AD2/P3.2 33 P0.2 46 P6.1/EPA9
8 AD14/P4.6 21 AD1/P3.1 34 P0.3 47 P6.4/SC0
9 AD13/P4.5 22 AD0/P3.0 35 P0.4 48 P6.5/SD0

10 AD12/P4.4 23 RESET# 36 P0.5 49 P6.6/SC1
11 AD11/P4.3 24 EA# 37 P0.6 50 P6.7/SD1
12 AD10/P4.2 25 V

SS

38 P0.7 51 XTAL2

13 AD9/P4.1 26 V

CC

39 V

SS

52 XTAL1

P6.1 / EPA9
P6.0 / EPA8
P1.0 / EPA0 / T2CLK
P1.1 / EPA1
P1.2 / EPA2 / T2DIR
P1.3 / EPA3

V

CC



V

SS


P0.7
P0.6
P0.5
P0.4
P0.3

AD15 / P4.7

P5.2 / WR# / WRL#

P5.3 / RD#

V

PP



V

SS



P5.0 / ADV# / ALE

V

SS



XTAL1

XTAL2

P6.7 / SD1

P6.6 / SC1

P6.5 / SD0

P6.4 / SC0

A3403-01

AD14 / P4.6
AD13 / P4.5
AD12 / P4.4
AD11 / P4.3
AD10 / P4.2

AD9 / P4.1
AD8 / P4.0
AD7 / P3.7
AD6 / P3.6
AD5 / P3.5
AD4 / P3.4
AD3 / P3.3
AD2 / P3.2

46
45
44
43
42
41
40
39
38
37
36
35
34

N83C196LC
N83C196LD

View of component as
mounted on PC board

8
9
10
11
12
13
14
15
16
17
18
19
20

AD1 / P3.1

AD0 / P3.0

RESET#

EA#

V

SS



V

CC



P2.0 / TXD

P2.1 / RXD

P2.2 / EXTINT

P2.4

P2.6 / ONCE#

P2.7 / CLKOUT

P0.2

21

22

23

24

25

26

27

28

29

30

31

32

33

7654321

52

51

50

49

48

47

ADVANCE INFORMATION 5

AUTOMOTIVE — 83C196LC, 83C196LD

Table 3. Pin Assignment Arranged by Functional Categories

Addr & Data Input/Output Input/Output (Cont’d) Processor Control

Name Pin Name Pin Name Pin Name Pin

AD0 22 P1.0/EPA0/T2CLK 44 P4.7 7 CLKOUT 32
AD1 21 P1.1/EPA1 43

P5.0 2 EA# 24

AD2 20 P1.2/EPA2/T2DIR 42

P5.2 6EXTINT 29

AD3 19 P1.3/EPA3 41

P5.3 5 ONCE# 31

AD4 18 P2.0/TXD 27

P6.0/EPA8 45 RESET# 23

AD5 17 P2.1/RXD 28

P6.1/EPA9 46 XTAL1 52

AD6 16

P2.2 29 P6.4/SC0 47 XTAL2 51

AD7 15

P2.4 30 P6.5/SD0 48

AD8 14

P2.6 31 P6.6/SC1 49 Bus Control & Status

AD9 13

P2.7 32 P6.7/SD1 50 Name Pin

AD10 12 P3.0 22

ADV#/ALE 2

AD11 11 P3.1 21 Power & Ground

RD# 5

AD12 10 P3.2 20 Name Pin

WR#/WRL# 6

AD13 9 P3.3 19

V

CC

26

AD14 8 P3.4 18

V

CC

40

AD15 7 P3.5 17

V

PP

4

P3.6 16

V

SS

1

Input P3.7 15

V

SS

3

Name Pin P4.0 14 V

SS

25

P0.2 33 P4.1 13 V

SS

39
P0.3 34 P4.2 12
P0.4 35 P4.3 11
P0.5 36 P4.4 10
P0.6 37 P4.5 9
P0.7 38 P4.6 8

6 ADVANCE INFORMATION

83C196LC, 83C196L D — AUTOMOTIVE

3.0 SIGNALS

Table 4. Signal Descriptions

Name Type Description

AD15:0 I/O Address/Data Lines

These pins provide a multiplexed address and data bus. During the address

phase of the bus cycle, address bits 0–15 are presented on the bus and can be
latched using ALE or ADV#. During the data phase, 8- or 16-bit data is
transferred.

AD7:0 share package pins with P3.7:0. AD15:8 share package pins with P4.7:0.

ADV# O Address Valid

This active-low output signal is asserted only during external memory
accesses. ADV# indicates that valid address information is available on the
system address/data bus. The signal remains low while a valid bus cycle is in
progress and is returned high as soon as the bus cycle completes.

An external latch can use this signal to demultiplex the address from the
address/data bus. A decoder can also use this signal to generate chip selects
for external memory.

ADV# shares a package pin with P5.0 and ALE.

ALE O Address Latch Enable

This active-high output signal is asserted only during external memory cycles.
ALE signals the start of an external bus cycle and indicates that valid address
information is available on the system address/data bus.

An external latch can use this signal to demultiplex the address from the
address/data bus.

CLKOUT O Output

Output of the internal clock generator. The CLKOUT frequency is ½ the
oscillator input frequency (F

XTAL1

). CLKOUT has a 50% duty cycle.

CLKOUT shares a package pin with P2.7

EA# I External Access

This input determines whether memory accesses to special-purpose and
program memory partitions are directed to internal or external memory. These
accesses are directed to internal memory if EA# is held high and to
externalmemory if EA# is held low. For an access to any other memory location,
the value of EA# is irrelevant.

EA# is sampled and latched only on the rising edge of RESET#. Changing the
level of EA# after reset has no effect.

EPA9:8
EPA3:0

I/O Event Processor Array (EPA) Capture/Compare Channels

High-speed input/output signals for the EPA capture/compare channels.
The EPA signals share package pins with the following signals:

EPA0/P1.0/T2CLK, EPA1/P1.1, EPA2/P1.2/T2DIR, EPA3/P1.3,
EPA8/P6.0/COMP0, and EPA9/P6.1/COMP1. EPA7 does not connect to a
package pin. It cannot be used to capture an event, but it can function as a
software timer. EPA6:4 are not implemented.

ADVANCE INFORMATION 7

AUTOMOTIVE — 83C196LC, 83C196LD

EXTINT I External Interrupt

In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt
pending bit. EXTINT is sampled during phase 2 (CLKOUT high). The minimum
high time is one state time.

In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the
device to resume normal operation. The interrupt does not need to be enabled.

In idle mode, asserting any enabled interrupt causes the device to resume
normal operation.

EXTINT shares a package pin with P2.2.

ONCE# I On-circuit Emulation

Holding ONCE# low during the rising edge of RESET# places the
microcontroller into on-circuit emulation (ONCE) mode. This mode puts all pins
into a high-impedance state, thereby isolating the microcontroller from other
components in the system. The value of ONCE# is latched when the RESET#
pin goes inactive. While the microcontroller is in ONCE mode, you can debug
the system using a clip-on emulator.

To exit ONCE mode, reset the microcontroller by pulling the RESET# signal
low. To prevent inadvertent entry into ONCE mode, either configure this pin as
an output or hold it high during reset and ensure that your system meets the V

IH

specification.
ONCE# shares a package pin with P2.6.

P0.7:2 I Port 0

This is a high-impedance, input-only port. Port 0 pins should not be left floating.

P1.3:0 I/O Port 1

This is a standard bidirectional port that shares package pins with individually
selectable special-function signals.

Port 1 shares package pins with the following signals: P1.0/EPA0/T2CLK,
P1.1/EPA1 , P1.2/EPA2/T2DIR, P1.3/EPA3.

P2.7:6
P2.4
P2.2:0

I/O P ort 2

This is a standard bidirectional port that shares package pins with individually
selectable special-function signals.

P2.6 is multiplexed with the ONCE function. If this pin is held low during reset,
the device will enter ONCE mode, so exercise caution if you use this pin for
input. If you choose to configure this pin as an input, always hold it lowhigh
during reset and ensure that your system meets the V

IH

specification to prevent

inadvertent entry into ONCE mode.
Port 2 shares package pins with the following signals: P2.0/TXD, P2.1/RXD,

P2.2/EXTINT, P2.6/ONCE#, P2.7/CLKOUT.

P3.7:0 I/O Port 3

This is a memory-mapped, 8-bit, bidirectional port with programmable open­drain or complementary output modes. The pins are shared with the
multiplexed address/data bus, which has complementary drivers.

P3.7:0 share package pins with AD7:0.

Table 4. Signal Descriptions (Continued)

Name Type Description