© INTEL C ORPORATION, 1997 September, 1997 Order Number: 273123-001
PRELIMINARY
80960MC
EMBEDDED 32-BIT MICROPROCESSOR
WITH INTEGRATED FLOATING-POINT UNIT
AND MEMORY MANAGEMENT UNIT
Figure 1. The 80960MC Processor’s Highly Parallel Architecture
Commercial
■ High-Performance Embedded Architecture
— 25 MIPS Burst Execution at 25 MHz
— 9.4 MIPS* Sustained Execution at
25 MHz
■ On-Chip Floating Point Unit
— Supports IEEE 754 Floati ng Point
Standard
— Full Transcendental Support
— Four 80-Bit Regist ers
— 13.6 Million W hetstones/s
(Single Precision) at 25 MHz
■ 512-Byte On-Chi p Inst ruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncache d
Instructions
■ Multiple Register Sets
— Sixteen Global 32-Bi t Registers
— Sixteen Local 32-Bit Registers
— Four Local Regist er Sets Stored
On-Chip (Sixteen 32-Bit Registers per
Set)
— Register Scoreboarding
■ On-Chip Memory Management Unit
— 4 Gbyte Virtual Address Space per
Task
— 4 Kbyte Pages with Supervisor/User
Protection
■ Built-in Interrupt Controller
— 32 Priority Levels
— 248 Vectors
— Supports M8259A
—3.4µs Latency @ 25 MHz
■ Easy to Use, High Bandwidth 32-Bit Bus
— 66.7 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
■ Multitasking and Multiprocessor Support
— Automatic Task dispatching
— Priori tized Task Queues
■ Advanced Package Technol ogy
— 132-Lead Ceramic Pin Grid Array
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BUS CONTROL
LOGIC
32-BIT
BURST
BUS
FOUR
80-BIT FP
REGISTERS
80-BIT
FPU
MMU
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Copyright © Intel Corporation 1997
80960MC
iii
1.0 THE i960® MC PROCESSOR ................................................................................................................... 1
1.1 Key Performance Features ................................................................................................................. 2
1.1.1 Memory Space And Addressing Modes ...................................................................................4
1.1.2 Data Types ...............................................................................................................................4
1.1.3 Large Register Set ...................................................................................................................4
1.1.4 Multiple Register Sets .............................................................................................................. 5
1.1.5 Instruction Cache .....................................................................................................................5
1.1.6 Register Scoreboarding ........................................................................................................... 5
1.1.7 Memory Management and Protection ......................................................................................6
1.1.8 Floating-Point Arithmetic .......................................................................................................... 6
1.1.9 Multitasking Support ................................................................................................................ 7
1.1.10 Synchronization and Communication .................................................................................... 7
1.1.11 High Bandwidth Local Bus .....................................................................................................7
1.1.12 Multiple Processor Support .................................................................................................... 7
1.1.13 Interrupt Handling .................................................................................................................. 8
1.1.14 Debug Features ..................................................................................................................... 8
1.1.15 Fault Detection .......................................................................................................................8
1.1.16 Inter-Agent Communications (IAC) ........................................................................................ 9
1.1.17 Built-in Testability ...................................................................................................................9
1.1.18 Compatibility with 80960K-Series ..........................................................................................9
1.1.19 CHMOS ..................................................................................................................................9
2.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 13
2.1 Power and Grounding .......................................................................................................................13
2.2 Power Decoupling Recommendations .............................................................................................13
2.3 Connection Recommendations ........................................................................................................ 13
2.4 Characte ris ti c Curv es .... .... ....................... ... .... .... .................................. .... .... .... ........................... ... . 13
2.5 Test Load Ci rcuit ....... .... .... .... .................................. .... .... ... ................................... .... ... .................... 16
2.7 DC Characteristics ............................................................................................................................17
2.6 Absolu te Max im um Ra tin gs ......................... .... .... .... .................................. .... .... .... ............... ............ 17
2.8 AC Specifications .............................................................................................................................18
2.9 Design Con side rations .......... ... .... .... .................................. .... .... .... ..................................................22
3.0 MECHANICAL DATA .............................................................................................................................. 22
3.1 Packaging ......................................................................................................................................... 22
3.1.1 Pin Assignment ......................................................................................................................22
3.2 Pinout ............................................................................................................................................... 26
3.3 Package The rm al Specification ................................... .... ... .... .... ....................... .... .... ... .... ........ .... ... . 28
4.0 WAVEFOR M S .......... ....................... .... .... .... .... .................................. .... .... ... .... ................ ... .... .... .... ........ 30
5.0 REVISION HISTORY ............................................................................................................................... 35
80960MC
iv
FIGURES
Figure 1. 80960MC Programming Environment ........................................................................................1
Figure 2. Instruction Formats ....................................................................................................................4
Figure 3. Multiple Register Sets Are Stored On-Chip ...............................................................................6
Figure 4. Connection Recommendations for Low Current Drive Network ..............................................13
Figure 5. Connection Recommendations for High Current Drive Network ..............................................13
Figure 6. Typical Supply Current vs. Case Temperature ........................................................................14
Figure 7. Typical Current vs. Frequency (Room Temp) ..........................................................................14
Figure 8. Typical Current vs. Frequency (Hot Temp) ..............................................................................15
Figure 9. Worst-Case Voltage vs. Output Current on Open-Drain Pins ..................................................15
Figure 10. Capacit iv e Dera tin g Curv e .. .................................. .... .... .... ... ....................... .... .... .... .... .............15
Figure 11. Test Load Circuit for Three-State Output Pins .........................................................................16
Figure 12. Test Load Circuit for Open-Drain Output Pins .........................................................................16
Figure 13. Drive Levels and Timing Relationships for 80960MC Signals .................................................18
Figure 14. Timing Relationship of L-Bus Signals ......................................................................................19
Figure 15. System and Processor Clock Relationship ..............................................................................19
Figure 16. Processor Clock Pulse (CLK2) ................................................................................................21
Figure 17. RESET Signal Timing ..............................................................................................................21
Figure 18. HOLD Timing ...........................................................................................................................22
Figure 19. 132-Lead Pin-Grid Array (PGA) Package ................................................................................23
Figure 20. 80960MC PGA Pinout—View from Bottom (Pins Facing Up) ..................................................24
Figure 21. 80960MC PGA Pinout—View from Top (Pins Facing Down) ..................................................25
Figure 22. 25 MHz Maximum Allowable Ambient Temperature ................................................................29
Figure 23. Non-Burst Read and Write Transactions Without Wait States .................................................30
Figure 24. Burst Read and Write Transaction Without Wait States ..........................................................31
Figure 25. Burst Write Transaction with 2, 1, 1, 1 Wait States ..................................................................32
Figure 26. Accesses Gene rated by Quad Word Rea d Bus Request, Misaligned Two Bytes from
Quad Word Boundary (1, 0, 0, 0 Wait States) .........................................................................33
Figure 27. Interrupt Acknowledge Transaction .........................................................................................34
Figure 28. Bus Ex change Transaction (PBM = Primary Bus Master, SBM = Secondary Bus Master) .....35
TABLES
Table 1. 80960MC Instruction Set ...........................................................................................................3
Table 2. Memory Addressing Modes .......................................................................................................4
Table 3. Sample Floating-Point Execution Times (µs) at 25 MHz ...........................................................7
Table 4. 80960MC Pin Description: L-Bus Signals ..................................................................................9
Table 5. 80960MC Pin Description: Support Signals .............................................................................11
Table 6. DC Characteristics ...................................................................................................................17
Table 7. 80960MC AC Characteristics (25 MHz) ...................................................................................20
Table 8. 80960MC PGA Pinout — In Pin Order .....................................................................................26
Table 9. 80960MC PGA Pinout — In Signal Order ................................................................................27
Table 10. 80960MC PGA Package Thermal Characteristics ...................................................................28
PRELIMINARY 1
80960MC
1.0 THE i960® MC PROCESSOR
The 80960MC, a member of Intel’s i960® 32-bit
processor family, is ideally suited for embedded
applications. It includes a 512-byte instruction cache
and a built-in interrupt controller. The 80960MC has
a larg e registe r set, mul tiple parallel execut ion units
and a high-bandwidth burst bus. Using advanced
RISC technology, this processor is capable of
execution rates in excess of 9.4 million instructions
per s eco nd
*
. The 8 0960 MC is we ll- suite d for a w ide
range of applications including non-impact printers,
I/O control and specialty instrumentation. The
embedded market includes applications as diverse
as industrial automation, avionics, image
processing, graphics and networking. These types of
applications require high integration, low power
consumption, quick interrupt response times and
* Relative to Digital Equipment Corporation’s VAX-11/780*
at 1 MIPS
high performance. Since time to market is critical,
embedded processors must be easy to use in both
hardware and software designs.
All members of the i960 processor family share a
comm on c ore ar ch itect ure w hic h util izes RI SC te chnology so that, except for special functions, the
family members are object-code compatible. Each
new p ro ce ss o r in th e family a dds its o w n sp ec ial set
of functions to the core to satisfy the needs of a
specific application or range of applications in the
embedded market.
The 80960MC includes an integrated Floating Point
Unit (FPU), a Memory Management Unit (MMU),
multitasking support, and multiprocessor support.
Two commercial members of the i960
®
family
provide similar features: the 80960KB processor with
integrated FPU and the 80960KA without floatingpoint.
Figure 1. 80960MC Programming Environment
INSTRUCTION CACHE
INSTRUCTION
STREAM
FETCH LOAD STORE
SIXTEEN 32-BIT GLOBAL REGISTERS
g0
g15
SIXTEEN 32-BIT LOCAL REGISTERS
REGISTER CACHE
FOUR 80-BIT FLOATING POINT REGISTERS
r0
r15
CONTROL REGISTERS
INSTRUCTION
EXECUTION
INSTRUCTION
POINTER
ARITHMETIC
CONTROLS
PROCESS
CONTROLS
TRACE
CONTROLS
ARCHITECTURALLY
DEFINED
DATA STRUCTURES
FFFF FFFFH0000 0000H
ADDRESS SPACE
PROCESSOR STATE
REGISTERS
80960MC
2
PRELIMINARY
1.1 Key Performan ce Featu res
The 80 96 0 arc hitec tur e is b ased on the mos t rece nt
advances in microprocessor technology and is
grounded in Intel’s long experience in the design and
manufacture of embedded microprocessors. Many
features contribute to the 80960MC’s exceptional
performance:
1. Large Register Set. H a vi ng a large nu m be r of
registers reduces the number of times that a
processor needs to access memory. Modern
compilers can take advantage of this feature to
optimize execution speed. For maximum flexibility, the 80960MC provides thirty-two 32-bit
registers. (See Figure 2.)
2. Fast I nst ruction E xecut ion. Sim ple functi ons
make up the bulk of instructions in most
programs so that execution speed can be
improved by ensuring that these core instructions are ex ecut ed as quic kly as po ssib le. Th e
most frequently executed instructions such as
register-register moves, add/subtract, logical
operations and shifts execute in one to two
cycles. (Table 1 contains a list of instructions.)
3. Load/Store Architecture. One way to improve
execution speed is to reduce the number of
times that the processor must access memory
to perform an operation. As with other processors based on RISC technology, the 80960MC
has a Load/Store architecture. As such, only
the LOAD and STORE instructions reference
memory; all other instructions operate on registers. This type of architecture simplifies instruction d ecodin g and i s used in co mbinat ion wi th
other techniques to increase parallelism.
4. Simple Instruction Formats. All instructions
in the 80960MC are 32 bits long and must be
aligned on word boundaries. This alignment
makes it possible to eliminate the instruction
align me nt stage in the pipeline. To si m pli fy th e
instruction decoder, there are only five instruction formats; each instruction uses only one
format. (See Figure3.)
5. Overlapped Instruction Execution. Load
operations allow execution of subsequent
instructions to continue before the data has
been returned from memory, so that these
instructions can overlap the load. The
80960MC manages this process transparently
to software through the use of a register scoreboar d. Condi tional ins tructio ns also m ake use
of a scoreboard so that subsequent unrelated
instructions may be executed while the conditional instruction is pending.
6. Integer Execution Optimization. When the
resu lt of an a rith meti c ex ecu tion i s us ed a s an
operand in a subsequent calculation, the value
is sen t immediate ly to its destinatio n register.
Yet at the same time, the value is put on a
bypass path to the ALU, thereby saving the
time that otherwise would be required to
retrieve the value f or the next operatio n.
7. Bandwidth Optimizations. The 80960MC
gets op timal us e of its mem ory bus ba ndwid th
because the bus is tuned for use with the onchip instruction cache: instruction cache line
size matches the maximum burst size for
instruction fetches. The 80960MC automatically fetches four word s in a bu rst and stores
them directly in the cache. Due to the size of
the cache and the fact that it is continually filled
in anticipation of needed instructions in the
program flow, the 80960MC is relatively insensitive to memory wait states. The benefit is that
the 80960MC delivers outstanding performance even with a low cost memor y system.
8. Cache Bypass. When a cache miss occurs,
the processor fetches the needed instruction
then se nds it on to the in struction decode r at
the sam e time it update s the cache. Thu s, no
extra time is spent to load and read the cache.
80960MC
PRELIMINARY 3
Table 1. 80960MC Instruction Set
Data Movement Process Management Floating Point Logical
Load
Store
Move
Load Address
Load Physical Address
Schedule Process
Saves Process
Resume Process
Load Process Time
Modify Process Controls
Wait
Conditional Wait
Signal
Receive
Conditional Receive
Send
Send Service
Atomic Add
Atom i c Mo di fy
Add
Subtract
Multiply
Divide
Remainder
Scale
Round
Square Root
Sine
Cosine
Tangent
Arctangent
Log
Log Binary
Log Natural
Exponent
Classify
Copy Real Exten ded
Compare
And
Not And
And Not
Or
Exclusive Or
Not Or
Or Not
Nor
Exclusive Nor
Not
Nand
Rotate
Comparison Branch Bit and Bit Field String
Compare
Conditional Compare
Com pa re an d Inc r e me nt
Com pa re and Decrem e nt
Unc on di tional Bran c h
Conditional Branch
Com pa re an d B ran c h
Set Bit
Clear Bit
Not Bit
Check Bit
Alter Bit
Scan For Bit
Scan Over Bit
Extract
Modif y
Move String
Move Quick String
Fill String
Comp are String
Scan Byte for Equal
Conversion Decimal Call/Return Arithmetic
Convert Real to Integer
Convert Integer to Real
Move
Add with Carry
Subtract with Carry
Call
Call Extended
Call System
Return
Bra nch and Link
Add
Subtract
Multiply
Divide
Rema inder
Modulo
Shift
Fault Debug Miscellaneous
Conditional Fault
Synchr onize Faults
Modify Trace Controls
Mark
Force Mark
Flush Loca l Registers
Inspect Access
Modify Arithmetic
Controls
Test Condition Code
80960MC
4 PRELIMINARY
Figure 2. Instruction Formats
Opcode Displacement
Opcode Reg/Lit Reg M Displacement
Displacement
Control
Compare and
Branch
Register to
Register
Memory Access-
Short
Memory Access-
Long
Opcode Reg Reg/Lit Modes Ext’d Op Reg/Lit
Opcode Reg Base M X Offset
Opcode Reg Base Mode Scale xx Offset
1.1.1 Memory Space And Addressing Modes
The 80960MC allows each task (process) to address
a logical memory space of up to 4 Gbytes. Each
task’s address space is divided into four 1 Gbyte
regions and each region can be mapped to physical
addresses by zero, one, or two levels of page tables.
The r egio n wi th the high est ad dr esse s (R egio n 3) is
common to all tasks.
In keeping with RISC design principles, the number
of addressing modes is minimal yet includes all
those necessary to ensure efficient execution of
high-level languages such as Ada, C, and Fortran.
Table 2 lists the memory acc essing modes.
1.1.2 Data Types
The 80960MC recognizes the following data types:
Numeric:
• 8-, 16-, 32- and 64-bit ordinals
• 8-, 16-, 32- and 64-bit integers
• 32-, 64- and 80-bit real numbers
Non-Numeric:
•Bit
• Bit Field
• Triple Word (96 bits)
• Quad-Word (128 bits)
1.1.3 Large R eg ister Set
The 80960MC programming envi ronment includes a
large number of registers. 36 registe rs are available
at any time; this greatly reduces the number of
memory accesses required to perform algorithms,
which leads to greater instruction processing speed.
Two types of general-purpose registers are available: local and global. The 20 global registers
consist of sixteen 32-bit reg isters (G0 thou gh G15)
and four 80-bit registers (FP0 through FP3). These
Table 2. Memory Addressing Modes
• 12-Bit Offset
• 32-Bit Offset
• Register-Indirect
• Registe r + 12-Bit Off s et
• Registe r + 32-Bit Off s et
• Register + (Index-Register x Scale-Factor)
• Reg ister x Scale F actor + 32-Bit Displacement
• Register + (Index-Register x Scale-Factor) + 32Bit Displacement
• Scale-Factor is 1, 2, 4, 8 or 16
80960MC
PRELIMINARY 5
registers perform the same function as the generalpurpose registers provided in other popular microprocessors. The term
global
refers to the fact that
these registers retain their contents across procedure ca ll s.
The loc al r eg ister s are p roce du re-sp ecifi c. Fo r each
procedure call, the 80960MC allocates 16 local
regist e rs ( R0 throug h R 15 ). Each l oc a l re gister i s 32
bits wide. A ny re gi ster ca n a ls o be u se d for floa ti ng point operations; the 80-bit floating-point registers
are provid ed for extended precision.
1.1.4 Multiple Register Sets
To furt her in crea se th e eff icie ncy of the regis ter s et,
multiple sets of local registers are stored on-chip
(See Figure 4). This cache holds up to four local
register fr ames, which means that up to three procedure calls can be made without having to access the
procedure stack resident in memory.
Although programs m ay have procedure cal ls nested
many ca lls d ee p, a prog ram typi call y osc illat es bac k
and forth between only two to three levels. As a
result, with four stack frames in the cache, the probability of having a free frame available on the cache
when a call is made is very high. Runs of representative C- la ng uage pro gra ms sh ow th at 80% of t he ca lls
are handled without needing to access memory.
When four or mor e procedures are active and a new
proced ure is ca lled, the 80 960MC mo ves the ol dest
local register set in the stack-frame cache to a
proced ure stac k in me mory to mak e ro om fo r a new
set of registers. Global register G15 is the frame
pointer (FP) to the procedure stack.
Global registers are not exchanged on a procedure
call, but retain their contents, making them available
to all procedures for fast parameter passi ng.
1.1.5 Instruction Cache
To further reduce memory accesses, the 80960MC
includes a 512-byte on-chip instruction cache. The
instr uctio n ca che is ba sed on th e con cep t o f
locali ty
of reference
; most programs are typically not
executed in a steady stream but consist of many
branches, loops and procedure calls that lead to
jumpin g ba ck an d for th i n the sam e sm all s ecti on of
code. Th us, by main tain ing a bloc k of in struc tio ns in
cache, the number of memory r eferences required to
read instructions into the processor is greatly
reduced.
To load the instruction cache, instructions are
fetched in 16-byte bl oc k s; up to f our instr uc tio ns c an
be fetched at one time. An efficient prefetch algorithm increases the probability that an instruction is
already in the cache when it is needed.
Code for small loops often fits entirely within the
cache, leading to an increase in processing speed
since further memory references might not be
necessary until the program exits the loop. Similarly,
when calling short procedures, the code for the
calling procedure is likely to remain in the cache so it
is there on the procedure’s return.
1.1.6 Register Scoreboarding
The instruction decoder is optimized in several ways.
One optimization method is the ability to overlap
instructions by u s ing
register scoreboarding
.
Regi ster scoreboarding occurs when a LOAD moves
a variable from memory into a register. When the
instruction initiates, a scoreboard bit on the target
register is set. Once the register is loaded, the bit is
reset. In between, any reference to the register
conten ts is a cc o mp anied by a te s t of the score board
bit to ensure that the load has completed before
proc essi ng c ontin ues . Si nce t he pr oc esso r do es n ot
need to wait for the LOAD to complete, it can
execute additional instructions placed between the
LOAD and the instruction that uses the register
con tents, as sho wn in the following example:
ld data_2, r4
ld data_2, r5
Unrelated instruction
Unrelated instruction
add R4, R5, R6
In essence, the two unrelated instructions between
LOAD an d AD D are ex e cu te d “for free ” (i. e., take no
apparent time to execute) because they are
executed while the register is being loaded. Up to
three load instructions can be pending at one time
with three corresponding scoreboard bits set. By
exploiting this feature, system programmers and
compiler writers have a useful tool for optimizing
execu tion spee d.
80960MC
6 PRELIMINARY
Figure 3. Multiple Register Sets Are Stored On-Chip
REGISTER
CACHE
ONE OF FOUR
LOCAL
REGISTER SETS
LOCAL REGISTER SET
R
15
R
0
31
0
1.1.7 Memory Management and Protection
The 80960MC is ideal for multitasking applications
that require software protection and a large address
space. To en sure the high est level of p erformance
possible, the memory management unit (MMU) and
tran s lat io n look-a si de bu ffe r (TLB) ar e c on ta ine d onchip.
The 80960MC supports a conventional form of
demand-paged virtual memory in which the address
space is divided into 4-Kbyte pages. Studies indicate
that a 4-K byte page is th e op timum siz e for a b road
range of applications.
Each page table entry includes a 2-bit page rights
field that specifies whether the page is a no-access,
read-only, or read-write page. This field is interpreted differently depending on whether the current
task (process) is executing in user or supervisor
mode, as shown below:
Rights User Supervisor
00 No Access Read-Only
01 No Access Read-Write
10 Read -Only Read-Write
11 Read-Write Read-Write
1.1.8 Floating-Point Arithmetic
In the 80960MC, floating-point arithmetic is an
integr al part of th e archite cture. Hav ing the fl oatingpoint unit integrated on-chip provides two advantages. First, it improves the performance of the chip
for floating-point applications, since no additional
bus ove r he ad is as s oc ia ted with fl oa ting-po in t calculations, thereby leaving more time for other bus operations such as I/O. Second, the cost of using
floating-point operations is reduced because a
separate coprocessor chip is not required.
The 80960MC floating-point (real-number) data
types include single-precision (32-bit), double-precisio n (64-bit) and extended precision (80-bit) floati ngpoint numbers. Any registers may be used to
execute floating-point operations.
The processor provides hardware support for both
mandatory and recommended portions of IEEE
Standard 754 for floating-point arithmetic, including
all arithmetic, exponential, logarithmic and other
transcendental functions. Table 3 shows execution
times for some representative instructions.
80960MC
PRELIMINARY 7
1.1.9 Multitasking Support
Multita sking programs common ly involv e the moni toring and control of an external operation, such as
the activities of a process controller or the movements of a machine tool. These programs generally
consis t of a numb er of processe s that run indep endently of one another, but share a common
database or pass data among themselves.
The 80960MC offers several hardware functions
designed to support multitasking systems. One
unique feature, called self-dispatching, allows a
processor to switch itself automatically among
scheduled tasks. When self-dispatching is used, all
the operating system is required to do is place the
task in the scheduling queue.
When the processor becomes available, it
dispatches the task from the beginning of the queue
and the n ex ecu tes i t u ntil it be com es b lo cke d, in terrupted, or until its time-slice expires. It then returns
the task to the end of the queue (i.e., automatically
resche dules it ) and dispat ches the next read y task.
During these operations, no communication between
the pr oc es sor an d th e oper a tin g sys te m is nece ss ary
until the runnin g task is comple te or an interrup t is
issued .
1.1.10 Synchronization and Communication
The 80960MC also offers instructions to set up and
test semaphores to ensure that concurrent tasks
remain synchronized and no data inconsistency
results. Special data structures, known as communication ports, provide the means for exchanging
parameters and data structures. Transmission of
information by means of communication ports is
asynchronous and automatically buffered by the
processor.
Communication between tasks by means of ports
can be carried out independently of the operating
system. Once the ports have been set up by the
programmer, the processor handles the message
passing automatically.
1.1.11 High Bandwidth Local Bus
The 80960MC CPU resides on a high-bandwidth
address/data bus known as the local bus (L-Bus).
The L-Bus provides a direct communication path
between the processor and the memory and I/O
subsystem interfaces . The processor uses the L-Bus
to fetch instructions, manipulate memory and
respond to interrupts. L-Bus features include:
• 32-bit multiplexed address/data path
• Four-word burst capability which allows transfers
from 1 to 16 bytes at a time
• Hi gh bandwidth reads an d writes with 66.7
MBytes/s burst (at 25 MHz)
• Special signal to indicate w hether a memory transaction can be cached
Table 4 d efines L -bus signal names and fu nctions;
Table 5 defines other component-support signals
such as interr upt lines.
1.1.12 Multiple Processor Support
One me ans of inc rea sing the p roces sin g pow er of a
system is to run tw o or mor e proc essors in parall el.
Since microprocessors are not generally designed to
run in tandem with other processors, designing such
a system is us ually dif fic u lt an d co stly.
The 80960MC solves this problem by offering a
number of functions to coordinate the actions of
multiple pr oc es s ors . First, m e ss ag es can be p as s ed
between processors to initiate actions such as
flushing a cache, stopping or starting another
processor, or preempting a task. The messages are
passe d on t he b us and allo w m ultip le p ro cesso rs to
run together smoothly, with rare need to lock the bus
or memory.
Table 3. Sample Floating-Point Execution Times
(µs) at 25 MHz
Function 32-Bit 64-Bit
Add 0.4 0.5
Subtract 0.4 0.5
Multiply 0.7 1.3
Divide 1.3 2.9
Square Root 3.7 3.9
Arctangent 10.1 13.1
Exponent 11.3 12.5
Sine 15.2 16.6
Cosine 15.2 16.6
80960MC
8
PRELIMINARY
Second, a set of synchronization instructions help
maintain memory coherency. These instructions
permit several processors to modify memory at the
same time without inserting inaccuracies or ambiguities into shar ed data structures.
The self-dispatching mechanism — in addition to
being used in single-processor systems — provides
the m eans to in cr ease the p erf orma nce o f a syst em
merely by adding processors. Each processor can
either work on the same pool of tasks (sharing the
same queue with other processors) or can be
restricted to its own queue.
When processors perform system operation, they
synchronize themselves by using atomic operations
and se nd ing sp ecia l mes sage s betw ee n each oth er.
In theory, changing the number of processors in a
system does not require a software change.
Software executes correctly regardless of the
number of processors in the system; systems with
more processors simply execute faster.
1.1.13 Interrupt Handling
The 80960MC can be interrupted in two ways: by the
activ atio n of o ne of fo ur inte rru pt pi ns or by se ndin g
a message on the processor’s data bus.
The 80960MC is unusual in that it automatically
hand les inter rupts on a p riority b asis and ca n keep
trac k of pe nding interru pts thro ugh its on-c hip in terrupt controller. Two of the interrupt pins can be
configured to provide 8259A-style handshaking for
expansion beyond four interrupt lines.
An interrup t mess age is made up of a vector number
and an interrupt priority. When the interrupt priority is
greater than that of the currently running task, the
pro cessor accept s the inter rupt an d uses the ve ctor
as an index into the interrupt table. When the priority
of the i nt erru pt me ssa ge is below tha t of the cur rent
task, the processor saves the information in a
section of the interrupt table reserved for pending
interrupts.
1.1.14 Debug Features
The 80960MC has built-in debug capabilities,
including two types of breakpoints and six trace
modes. Debug features are controlled by two
internal 3 2-bit regist ers: the Pro cess-Controls Word
and the Trace-Controls Word. By setting bits in these
contr ol w ord s , a s of t war e d eb ug mo nit or can cl os el y
control how the processor responds during program
execut io n.
The 80960MC has both hardware and software
breakpoints. It provides two hardware breakpoint
registers on-chip which, by using a special
command, can be set to any value. When the
instruction po inter matche s either breakpoint register
value, the breakpoint handling routine is automatically called.
The 80960MC also provides software breakpoints
through the use of two instructions: MARK and
FMARK. These can be placed at any point in a
progra m and cause th e process or to halt exe cution
at that point and call the breakpoint handling routine .
The breakpoint mechanism is easy to use and
provides a powerful debugging too l.
Tracing is available for instructions (single step
execution), calls and returns and branching. Each
trace type may be enabled separately by a special
debug instruction. In each case, the 80960MC
executes the instruction first and then calls a trace
handling routine (usually part of a software debug
monitor). Further program execution is halted until
the routine completes, at which time execution
resumes at the next instruction. The 80960MC’S
tracing mechanisms, implemented completely in
hardware, greatly simplify the task of software test
and debug.
1.1.15 Fault Detection
The 80960MC has an automatic mechanism to
handle faults. There are ten fault types include
floating point, trace and arithmetic faults. When the
processor detects a fault, it automatically calls the
appropriate fault handling routine and saves the
current instruction pointer and necessary state information to make efficient recovery possible. The
processor posts diagnostic information on the type of
fault to a Fault Record. Like interrupt handling
routines, fault handling routines are usually written to
meet the needs of specific applications and are often
included as part of the operating system or kernel.
For ea ch of t he ten f ault ty pes, nu merous subty pes
provide specific information about a fault. For
example, a floating point fault may have the subtype
set to an Overflow or Zero-Divide fault. The fault
handle r can use this sp ecifi c in forma tion to resp ond
correctly to the fault.
80960MC
PRELIMINARY 9
1.1.16 Inter-Ag ent Com mu nic ations (IAC)
To coor dinate their actions, processors in a multiple
proc esso r sys tem need a me an s for com muni cati ng
with e ach ot her. Th e 8096 0MC does t his thr ough a
mechanism known as “IACs” — Inter-Agent Communication messages.
IAC messages cause a variety of actions including
starting and stopping processors, flushing instruction
caches and TLBs, and sending interrupts to other
proces sors in the system . The upper 16 Mb ytes of
the processor’s physical memory space is reserved
for sending and receiving IAC messages.
1.1.17 Built-in Testability
Upon reset, the 80960MC automaticall y conducts an
exhaus tive int ernal te st of its major bl ocks of logic.
Then, be fore ex ecuting its f irst ins truction , it doe s a
zero check sum on the first eight words in memory to
ensure that the memory image was programmed
correctly. When a problem is discovered at any point
during the self-test, the 80960MC asserts its
FAILURE
pin and does not begin program execution. Self test takes approximately 47,000 cycles to
comp lete .
Syst em ma nufa ctur ers can us e t he 80 960M C’s se lf test feature during incoming parts inspection. No
specia l dia gnos ti c prog rams need to be w ritte n. The
test is both thorough and fast. The self-test capability
helps ensure that defective parts are discovered
before s ystems are shipped and, once in the f ield,
the self-t est makes it eas ier to distingu ish between
probl ems ca used by pr oc esso r failu re and pro blem s
resulting from other caus es.
1.1.18 Compatibility with 80960K-Series
Application programs written for the 80960K-Series
microprocessors can be run on the 80960MC
withou t modificat ion. The 80960K-S eries ins truction
set forms the core of the 80960MC’s instructions, so
binar y co m pa tibility is as sured.
1.1.19 CHM OS
The 80 960M C i s fa brica ted u sin g Int el’ s CH MOS I V
(Complementary High Speed Metal Oxide Semiconductor) process. The 80960MC is currently available
at 25 MHz.
Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 1 of 3)
NAME TYPE DESCRIPTION
CLK2 I SYSTEM CLOCK provides t he fundamental timing for 80960MC system s. It is
divided by two inside the 80960MC to gen erate the internal processor clock. Refer
to Figure 16, Processor Clock Pulse (CLK2) (pg. 21)
LAD31:0 I/O
T.S.
LOCAL ADDRESS / DATA BUS carries 32-bit physical addresses and data to and
from memory. During an address (T
a
) cycle, bits 2-31 contain a physical word
address (bits 0-1 indicate SIZE; see below). During a data (T
d
) cycle, bits 0-31
contain read or write data. These pins float to a high impedance state when not
active.
Bits 0-1 comprise SIZE during a T
a
cycle. S IZE specifies burst transfe r size in
words.
LAD1 LAD0
00 1 Word
0 1 2 Words
1 0 3 Words
1 1 4 Words
ALE
O
T.S.
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
asserted during a T
a
cycle and deasserted before the beginning of the Td state. It is
active LOW and floats to a high impedanc e state during a hold cycle (T
h
).
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
80960MC
10
PRELIMINARY
ADS O
O.D.
ADDRESS/DATA STATUS indicates an address state. ADS is asserted every Ta
state and deasserted during the following T
d
state. For a burst transaction, ADS is
asserted again every T
d
state where READY was asserted in the previous cycle.
W/R
O
O.D.
WRITE/READ specifies, dur ing a Ta cycle, whether the operation is a write or read.
It is latched on-chip and remains valid during T
d
cycles.
DT/R
O
O.D.
DATA TRANSMIT / RECEIVE indica tes the direction of dat a tr an sf er to an d fr om
the L-Bus. It is low during T
a
and Td cycles for a read or interrupt acknowledgment;
it is high during T
a
and Td cycles for a write. DT/R never changes state when DEN
is asser ted.
DEN
O
O.D.
DATA ENABLE (active low) enables data transceivers. The processor asserts
DEN# during all T
d
and Tw states. The DEN# line is an open drain-output of the
80960MC .
READY
I READY indicates that data on LAD lines can be sampled or removed. When
READY
is not asserted during a Td cycle, the Td cycle is extended to the next cycle
by inserting a w ait state (T
w
) and ADS is not asserted in the next cycle.
LOCK
I/O
O.D.
BUS LOCK prevents bus masters fr om gaining control of the L-Bus during
Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert
LOCK
.
At the start of a RMW op eration, the processor examines the LOCK
pin. When th e
pin is already asserted, the processor waits until it is not asserted. When the pin is
not asserted, the processor asserts LOCK
during the Ta cycle of the read tra ns-
action. The processor deasserts LOCK
in the Ta cycle of the write transaction.
During the time LOCK
is asserted, a bus agent can per form a normal read or w rite
but not a RMW oper ation.
The proc es s or al so ass erts LOCK
durin g int err u pt - ac k no w le dg e tr an s ac tio ns .
Do not leave LOCK
unconnected. It must be pulled high for the processor to
function properly.
BE3:0
O
O.D.
BYTE ENABLE LINES specify the data bytes (up to four) on the bus which are
used in the current bus cycle. BE3
corresponds to LAD31:24; BE0 corresponds to
LAD7:0.
The byte enables are provided in a dvance of data:
Byte enable s asserted duri ng T
a
specify the bytes of the first data word.
Byte enables asserted during T
d
specify the bytes of the next data word, if any (the
word to be transmitted following the next assertion of READ Y
).
Byte enables that occur during T
d
cycles that precede the last assertion of READY
are undefined. Byte enables are latched on-chip and remain constant from one T
d
cycle to the next when READY
is not asserted.
For reads, byte enables specify the byte(s) that the processor actually uses. L-Bus
agents are required to assert only adjacent byte enables (e.g., as serting just BE0
and BE2
is not permit ted) and are required to assert at least one byt e enable.
Address bits A
0
and A1 can be decoded externally from the byte enables.
Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 2 of 3)
NAME TYPE DESCRIPTION
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
80960MC
PRELIMINARY 11
HOLD/
HLDAR
I HOLD: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it float s its
three-state bus lines and open-drain control lines, asserts HLDA and enters the T
h
state. When HOLD deasserts, the processor deasserts HLDA and enters the T
i
or
T
a
state.
HOLD ACKNOWLEDGE RECEIVED: Indicates that the processor has acquired
the bus. When the processor is initialized as the secondary bus master this input is
interpreted as HLDAR.
Refer to Figure 18, HOLD Timing (pg. 22).
HLDA/
HOLDR
O
T.S.
HOLD ACKNOWLEDGE: Relinquishes control of the bus to another bus master.
When the processor is initiali zed as the primary bus master this output is
interpreted as HLDA. When HOLD is deasserted, the processor deasserts HLDA
and goes to either the T
i
or Ta state.
HOLD REQUEST: Indicates a request to acquire th e bus. When the processo r is
initialized as the secondary bus master this output is interpreted as HOLDR.
Refer to Figure 18, HOLD Timing (pg. 22).
CACHE/
TAG
O
T.S.
CACHE indicates when an access is cacheable during a T
a
cycle. It is not asserted
durin g any synchronous access, such as a synchronous load or move instruction
used for sending an IAC message. The CACHE signal floats to a high impedance
state when the processor is idle.
TAG is an input/output signal that, during T
d
and Tw cycles, identifies the contents
of a 32-bit w ord as either data (TAG = 0) or an access des c riptor (TAG = 1).
Table 5. 80960MC Pin Description: Support Signals (Sheet 1 of 2)
NAME T YPE DESCRIPTION
BADAC
I BAD ACCESS, when asserted in the cycle following the one in which the last
READY
of a transaction is asserted, indicates that an unrecoverable error has
occurred on the curren t bus transaction or that a syn chronous load/store instruction
has not been acknowledged.
During system reset the BADAC
signal is interpreted differently. When the signal is
high, it indicates that this processor will perform system initialization. When low,
another processor in the system will perform system initialization instead.
RESET I RESET clears the processor’s internal logic and causes it to reinitialize.
Duri ng RESET assertion, the input pins ar e ignored (except for BADAC
and
IAC
/INT0), the three-state output pins are placed in a high impedance state and
other output pins are placed in their non-asserted states.
RESET must be asserted for at least 41 CLK2 cycles for a predictable RESET. The
HIGH to LOW transition of RESET should occur after the rising edge of both CLK2
and the exte rnal bus clock and befor e the next rising edge of CLK2.
Refer to Figure 17, RESET Signal Timing (pg. 21).
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 3 of 3)
NAME TYPE DESCRIPTION
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
80960MC
12
PRELIMINARY
FAILURE O
O.D.
INITI ALIZ A TION FAIL U RE indicates that the processor did not initialize correctly.
After R ESET de asserts and before the first bus transaction begins, FAILURE
assert s while the processor perfor ms a self-test. W hen the self-test completes
successfully, then FAILURE
deasserts. The processor then performs a zero
checksum on the first eight words of memory. When it fails, FAILURE
asserts for a
second time and remains asserted. When it passes, system initialization continues
and FAILURE
remains deasserted.
IAC
/INT
0
LOCAL
PROCESSOR
NUMBER
I INTERAGENT COMMUNICATION REQUEST/INTERRUPT 0 indicates an IAC
message or an interrupt is pending. The bus interrupt control register determines
how the signal is interpreted. To signal an interrupt or IAC request in a synchronous
system, this pin — as well as the other interrupt pins — must be enabled by being
deasserted for at least one bus cycle and then asserted for at least one a dditional
bus cycle. In an asynchronous system the pin must remain deasserted for at least
two bus cycles and then asserted for at least two more bus cycles.
LOCAL PROCESSOR NUMBER - this signal is interpreted differently during
system reset. When the signal is a high voltage level it indicates that this processor
is a primary bus master (local processor number = 0). When at a low voltage level it
indicates that this proce ssor is a secondary bus master (local processor number
=1).
INT
1
I INTERRUPT 1, like INT0, provides direct interrupt signaling.
INT
2
/INTR I I NTERRUPT2 /INTERRUPT REQUEST: The inter rupt control register determines
how this pin is interpreted. When INT
2
, it has the same interpretation as the INT0
and INT
1
pins. When INTR, it is used to receive an interrupt request from an
external interrupt con troller.
INT
3
/INTA I/O
O.D.
INTERRUPT3/INTERRUPT ACKNOWLEDGE: The bus interrupt control register
determines how this pin is interpreted. When INT
3
, it has the same interpretation as
the INT
0
, INT1 and INT2 pins. When INTA, it is used as an output to control
interrupt-acknowledge transactions. The INTA
output is latched on-chip and
remain s valid during T
d
cycles; as an output, it is open-drain.
N.C. N/A NOT CONNECTED indicates pins should not be connected. Never connect any pin
marked N.C. as these p ins may be reserv ed for factory use.
Table 5. 80960MC Pin Description: Support Signals (Sheet 2 of 2)
NAME TYPE DESCRIPTION
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
80960MC
PRELIMINARY 13
2.0 ELECTRICAL SPECIFICATIONS
2.1 Power and Grounding
The 80960MC is implemented in CHMOS IV technology and therefore has modest power requirements. Its high clock frequency and numerous
output b uffer s (ad dres s/da ta, cont rol, er ror an d a rbitratio n signa ls) can cause p ower s urges as multip le
output buffers simultaneously drive new signal
levels. For clean on-chip power distribution, V
CC
and
V
SS
pins separately feed the device’s functional
units. Power and ground connections must be made
to all 80960MC power and ground pins. On the
circuit board, all V
cc
pins must be strapped closely
togethe r, prefera bly on a power plane; al l V
ss
pins
should be stra pp ed tog ether, p r ef erably on a ground
plane.
2.2 Power Decoupling
Recommendations
Place a liberal amount of decoupling capacitance
near the 80960MC. When driving the L-bus the
proces sor can c aus e trans ien t po wer sur ges , part icularly when connected to a large capacitive load.
Low inductance capacitors and interconnects are
recommended for best high frequency electrical
performance. Inductance is reduced by shortening
board traces betw een the proc esso r an d deco upli ng
capacitors as much as possible.
2.3 Connection Recommendat i ons
For reliable operation, always connect unused inputs
to an appropriate signal level. In particular, when
one or mor e inte r ru pt li nes are not use d, they shou ld
be pulled up. No inputs should ever be left floating.
All open-drain outputs require a pull-up device.
While in most cases a simple pull-up resistor is
adequa te, a net work of pull-up a nd pull -down r esistors biased to a valid V
IH
(>3. 0 V) and t erm inat ed in
the characteristic impedance of the circuit board is
recommended to limit noise and AC power
consumption. Figure 5 and Figure 6 show recom-
mended values for the resistor network for low and
high cu rre nt dr ive , ass umi ng a ch arac teri stic imp edance of 100
Ω. Terminating output signals in this
fashion limits signal swing and reduces AC power
consumption.
NOTE:
Do not connect external logic to pins marked N.C.
Figure 4. Connection Recommendations
for Low Current Drive Network
Figure 5. Connection Recommendations
for High Current Drive Network
2.4 Characteristic Curves
Figure 7 shows typi cal supply current requirem ents
over the operating temperature range of the
processor at supply voltage (V
CC
) of 5 V. Fig ure 8
and Figure 9 show the typical power supply current
(I
CC
) that the 80960MC requires at various operating
frequencies when measured at three input voltage
(V
CC
) levels an d two temperatures.
For a given output current (I
OL
) the curve in
Figure 10 shows the worst case output low voltage
(V
OL
). Fi gure 11 shows the typical capacitive
derating curve for the 80960MC measured from 1.5V
on the system clock (CLK) to 1.5V on the falling
edge and 1.5V on the rising edge of the L-Bus
address/data (LAD) signals.
220 Ω
330 Ω
Low Drive Network:
V
OH
= 3.0 V
I
OL
= 20.7 mA
V
CC
OPEN-DRAIN OUTPUT
OPEN-DRAIN OUTPUT
180 Ω
390 Ω
High Drive Network:
V
OH
= 3.4 V
I
OL
= 25.3 mA
V
CC
80960MC
14
PRELIMINARY
Figure 6. Typical Supply Current vs. Case Temperature
Figure 7. Typical Current vs. Frequency (Room Temp)
-60 -40 -20 0 20 40 60 80 100 120 140
VCC = 5.0 V
POWER SUPPLY CURRENT (mA)
CASE TEMPERATURE (°C)
25 MHz
20 MHz
16 MHz
380
360
340
320
300
280
260
240
220
200
OPERATING FREQUENCY (MHz)
@4.5V
@5.0V
@5.5V
TYPICAL SUPPLY CURRENT (mA)
TEMP = +22°C
400
380
360
340
320
300
280
260
240
220
200
180
16 20 25
80960MC
PRELIMINARY 15
Figure 8. Typical Current vs. Frequency (Hot Temp)
OPERATING FREQUENCY (MHz)
@4.5V
@5.0V
@5.5V
TYPICAL SUPPLY CURRENT (mA)
TEMP = +22°C
380
360
340
320
300
280
260
240
220
200
180
16 20 25
160
Figure 9. Worst-Case Voltage vs. Output Current
on Open-Drain Pins
Figure 10. Capacitive Derating Curve
01020304050
0.8
0.6
0.4
0.2
0.0
OUTPUT LOW CURRENT(mA)
(TEMP = +85°C, V
CC
= 4.5V)
OUTPUT LOW VOLT AGE (V)
020406080100
30
25
20
15
10
CAPACITIVE LOAD(pF)
(TEMP = +85°C, V
CC
= 4.5V)
5
0
RISING
FALLING
VALID DELAY(ns)
THREE-STATE OUTPUT
80960MC
16
PRELIMINARY
2.5 Test Load Circuit
Figure 12 illustrates the load circuit used to test the
80960MC’s three-state pins; Figure 13 shows the
load circuit used to test the open drain outputs. The
open drain test uses an active load circuit in the form
of a matched diode bridge. Since the open-drain
outputs sink current, only the I
OL
legs of the bridg e
are necessary and the I
OH
legs are not used. When
the 80960MC driver under test is turned off, the
outpu t pin is pu lled up to V
REF
(i.e., VOH). Diode D
1
is turned off and the IOL current source flows through
diode D
2
.
When the 80960MC open-drain driver under test is
on, diode D
1
is a lso on a nd the v oltage on the pin
being tested drops to V
OL
. Di ode D2 turns off and I
OL
flows through diode D1.
Figure 11. Test Load Circuit for Three-State
Output Pins
Figure 12. Test Load Circuit for Open-Drain
Output Pins
THREE-STATE OUTPUT
C
L
= 50 pF for all signals
C
L
C
L
OPEN-DRAIN OUTPUT
I
OL
D
2
IOL Tested at 25 mA
V
REF
= V
CC
D1 and D2 are matched
D
1
CL = 50 pF for all signals
80960MC
PRELIMINARY 17
2.7 DC Characteristics
2.6 Absolut e Maximum Ratings
NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
Operating Temperature (PGA) ...... 0° C to +85° C Case
Storage Temperature..................... –65° C to +150° C
Voltage on Any Pin........................ –0.5 V to VCC +0.5 V
Power Dissipation .......................... 2.5 W (25 MHz)
*WARNING: Stressing the devic e beyond the
“Absolute Maximum Ratings” may cause
permanent damage. These ar e stress ratings
only . Operation beyond the “Op e rating Conditions” is not recommended and exten d ed
exposure beyond the “Operating Conditions”
may affect device reliability.
PGA: 80960MC (25 MHz) T
CASE
= 0° C to +85° C, VCC = 5V ± 5%
Table 6. DC Characteristics
Symbol Parameter Min Max Units Notes
V
IL
Input Low Voltage –0.3 +0.8 V
V
IH
Input High Voltage 2.0 VCC + 0.3 V
V
CL
CLK2 Input Low Voltage –0.3 +0.8 V
V
CH
CLK2 Input High Voltage 0.55 V
CC
VCC + 0.3 V
V
OL
Output Low Voltage 0.45 V (1,2)
V
OH
Out put High Voltage 2.4 V (3,4)
I
CC
Power Supply Current:
16 MHz
20 MHz
25 MHz
315
360
420
mA
mA
mA
(5)
(5)
(5)
I
LI
Input Leakage Cur rent ±15 µA 0 ≤ VIN ≤ V
CC
I
LO
Output Leakage Current ±15 µA 0.45 ≤ VO ≤ V
CC
C
IN
Input Capacitance 10 pF fC = 1 MHz (6)
C
O
Output Capacitance 12 pF fC = 1 MHz (6)
C
CLK
Clock Capacitance 10 pF fC = 1 MHz (6)
NOTES:
1. For three-state outputs, this parameter is measured at:
Address/Data 4.0 mA
Controls 5.0 mA
2. For open-drain outputs 25 mA
3. This parameter is measured at:
Address/Data –1.0 mA
Controls –0.9 mA
ALE
–5.0 mA
4. Not measured on open-drain outputs.
5. Measured at worst case frequency, V
CC
and temperature, with device operating and outputs loaded to the test conditions
in Figure 12 and Figure 13. Figure7, Figure 8 and Figure 9 indicate typical values.
6. Input, output and clock capacitance are not tested.
18 PRELIMINARY
80960MC
2.8 AC Specifications
This sect ion des cribes the AC specif icatio ns for th e
80960MC pins. All input and output timings are specified relative to the 1.5 V level of th e rising edge of
CLK2. Fo r output tim ings the spec ifications refe r to
the time it takes the signal to reach 1.5 V.
For input timings the specifications refer to the time
at which the signal reaches (for input setup) or
leaves (for hold time) the TTL levels of LOW (0.8 V)
or HIGH (2.0 V). All AC testing should be done with
input voltages of 0.4 V and 2.4 V, except for the
clock (CLK2), which should be tested with input
voltages of 0.45 V and 0.55V
CC
.
Figure 13. Drive Levels and Timing Relationships for 80960MC Signals
ABC
D
A
BC
1.5V
1.5V 1.5V 1.5V
0.8V
T
6
1.5V
1.5V
T
7
1.5V
1.5V
VALID OUTPUT
T
6
T
8
T
8
T
13
T
14
1.5V 1.5V
VALID OUTPUT
T
9
2.0V 2.0V
2.0V 2.0V
0.8V 0.8V
0.8V 0.8V
EDGE
CLK2
OUTPUTS:
LAD 31:0
ADS
W/R, DEN
BE3:0
HLDA/HOLDR
CACHE
LOCK, INTA
ALE
DT/R
INPUTS:
LAD31:0
BADAC
IAC/INT0, INT1
INT2/INTR, INT3
HOLD, HLDAR
LOCK
READY
T
9
VALID INPUT
T
10
T
11
T
12
T
11
80960MC
PRELIMINARY 19
Figure 14. Timing Relationship of L-Bus Signals
Figure 15. System and Processor Clock Relationship
A4484-01
READY#
DEN#
DT/R
W/R#
BE(0:3)#
ADS#
ALE#
LAD
(31-0)
CLK
CLK2
T
11
T
12
T
11
T
12
T
11
T
12
T
6
T
6
T
6
T
6
T
9
T
13
T
14
T
9
T
13
14
T
T
7
T
6
Address Data
T
13
T
8
T
14
T
9
T
10
T
11
T
6
T
13
Address
Data
T
9
T
6
T
9
T
8
T
7
T
T
T
ad r
T
T
T
ad r
T
2
T
3
T
d
T
1
T
9
CLK
CLK2
T
T
a
T
dr
Bus
State
Bus
State
Bus
State
80960MC
20
PRELIMINARY
1. Clock rise and fall times are not tested.
2. A float condition occurs when the maximum output current becomes less than I
LO
. Float delay is not tested; however, it
should not be longer than the valid delay.
3. LAD31:0, BADAC
, HOLD, LOCK and READY are synchronous inputs. IAC/INT0, INT1, INT2/INTR and INT3 may be syn-
chronous or asynchronous.
Table 7. 80960MC AC Characteristics (25 MHz)
Symbol Parameter Min Max Units Notes
Input Clock
T
1
Processor Clock Period (CLK2) 20 125 ns VIN = 1.5V
T
2
Processor Clock Low Time (CLK2) 5 ns VIL = 10% Point = 1.2V
T
3
Processor Clock High Ti me (CLK2) 5 ns VIH = 90% Point = 0 .1V + 0. 5 V
CC
T
4
Processor Clock Fall Time (CLK2) 10 ns VIN = 90% Point to 10% Point (1)
T
5
Processor Clock Rise Time (CLK2) 10 ns VIN = 10% Point to 90% Point (1)
Synchr onous Outputs
T
6
Output Valid Delay 2 18 ns
T
6H
HLDA Output Valid Delay 4 23 ns
T
7
ALE Width 12 ns
T
8
ALE Output Valid Delay 2 18 ns
T
9
Outp ut Float Dela y 2 18 ns (2)
T
9H
HLDA Output Float Delay 4 20 ns (2)
Synchronous Inputs
T
10
Input Setup 1 3 ns (3)
T
11
Input Hold 5 ns (3)
T
11H
HOLD Input Hold 4 ns
T
12
Input Setup 2 7 ns
T
13
Setup to ALE Inac tive 8 ns
T
14
Hold after ALE Inactive 8 ns
T
15
Reset Hold 3 ns
T
16
Reset Setup 5 ns
T
17
Reset Width 820 ns 41 CLK2 Periods Minimum
NOTES:
80960MC
PRELIMINARY 21
Figure 16. Processor Clock Pulse (CLK2)
Figure 17. RESET Signal Timing
HIGH LEVEL (MIN) 0.55V
CC
LOW LEVEL (MAX) 0.8V
T
1
T
3
T
5
T
4
T
2
90%
10%
1.5 V
...
...
...
...
CLK2
CLK
RESET
OUTPUTS
FIRST
ABCDA
INIT PARAMETERS (BADAC
,
INT
0
/IAC) MUST BE SET UP 8 CLOCKS
PRIOR TO THIS CLK2 EDGE
INIT PARAMETERS MUST BE HELD
BEYOND THIS CLK2 EDGE
T15 = RESET HOLD
T
16
= RESET SETUP
T
17
= RESET WIDTH
T
15T16
T
17
80960MC
22 PRELIMINARY
Figure 18. HOLD Timing
A4490-01
HOLDR
HOLDAR
D
Secondary
D
HOLD
HLDA
Primary
Delay of 5 ns Minimum
is Required
Th
ThThTh
CLK2
CLK
HOLDR
HOLD
HLDA
HLDAR
T
9h
T
11h
T
9h
T
11h
T
12
T
6h
T
12
T
6h
2.9 D es i gn Considera t io ns
Inp ut ho ld times ca n be disreg arded by the de si gn er
whenever the input is removed because a subsequent output from the processor is deasserted (e.g.,
DEN
becomes deasserted).
In other words, whenever the processor generates
an output that indicates a transition into a subsequent state, the processor must have sampled any
inputs for the previous state.
Similarly, whenever the processor generates an
outpu t that indicates a transiti on into a subsequent
state, any outputs that are specified to be three
stated in this new state are guaranteed to be three
stated.
3.0 MECHANICAL DATA
3.1 Packaging
The 80960MC is available in one package type: a
132-lead ceramic pin-grid array (PGA). Pins are
arranged 0.100 inch (2.54 mm) center-to-center, in a
14 by 14 mat rix, th re e row s aro und (see Figure 20).
Dimensions for the PGA package type is given in the
Intel
Packaging
handbo ok (Or d er #240800) .
3.1.1 Pin Assignment
Figure 21 shows the view from the PGA bottom (pins
facing up). Table 8 and Ta ble 9 list the function of
each PGA pin.
80960MC
PRELIMINARY 23
Figure 19. 132-Lead Pin-Grid Array (PGA) Package
1
2
3
ABCDEFGHJK LMNP
4
5
6
7
8
9
10
11
12
13
14
80960MC
24
PRELIMINARY
Figure 20. 80960MC PGA Pinout—View from Bottom (Pins Facing Up)
V
CC
V
SS
N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.V
CC
N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.N.C.V
SS
N.C.N.C.N.C.
V
CC
V
SS
N.C.N.C.N.C.N.C.
V
CC
V
SS
V
CC
N.C.
V
SS
V
CC
N.C.DEN
V
SS
FAILBE
3
V
SS
BE
2
DT/R
LOCKBE
0
W/R
BE
1
READYLAD
30
CACHE
LAD
31
LAD
29
LAD
27
LAD
26
LAD
28
HLDAADSALE
N.C.N.C.
N.C.N.C.
N.C.N.C.N.C.
N.C.N.C.N.C.
N.C.N.C.N.C.
N.C.N.C.N.C.
N.C.N.C.
N.C.N.C.
V
SS
V
CC
V
SS
V
CC
V
SS
V
SS
V
SS
V
SS
V
CC
V
CC
V
CC
V
CC
INT
2
INT
0
INT
1
INT
3
LAD
3
LAD
8
LAD
20
LAD
13
BADACHOLD LAD
25
RESETLAD
0
LAD
1
LAD
4
LAD
5
LAD
7
LAD
9
LAD
11
LAD
14
LAD
16
LAD
17
LAD
19
LAD
2
LAD
6
LAD
10
LAD
12
LAD
15
LAD
18
LAD
21
LAD
22
LAD
24
LAD
23
CLK2
P
N
M
L
K
J
H
G
F
E
D
C
B
A
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1413121110987654321
1413121110987654321
80960MC
PRELIMINARY 25
Figure 21. 80960MC PGA Pinout—View from Top (Pins Facing Down)
V
CCVSS
N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. V
CC
N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
N.C.
N.C. N.C.
V
SS
N.C. N.C. N.C.
VCCV
SS
N.C. N.C. N.C. N.C.
VCCV
SS
VCCN.C.
V
SS
V
CC
N.C. DEN
V
SS
FAIL BE
3
V
SS
BE2DT/R
LOCK BE0W/R
BE1READY LAD
30
CACHE LAD31LAD
29
LAD27LAD26LAD
28
HLDA ADS ALE
N.C. N.C.
N.C. N.C.
N.C. N.C. N.C.
N.C. N.C. N.C.
N.C. N.C. N.C.
N.C. N.C. N.C.
N.C. N.C.
N.C. N.C.
V
SS
V
CC
V
SS
V
CC
V
SS
V
SS
V
SS
VSSV
CC
V
CC
V
CC
VCCINT
2
INT0INT1INT
3
LAD3LAD
8
LAD
20
LAD
13
BADAC HOLDLAD
25
RESET LAD
0
LAD1LAD4LAD5LAD7LAD9LAD11LAD14LAD16LAD17LAD
19
LAD2LAD6LAD10LAD12LAD15LAD18LAD21LAD22LAD24LAD
23
CLK2
P
N
M
L
K
J
H
G
F
E
D
C
B
A
P
N
M
L
K
J
H
G
F
E
D
C
B
A
14 13 12 11 10 9 8 7 6 5 4 3 2 1
14 13 12 11 10 9 8 7 6 5 4 3 2 1
A80960MC-25
XXXXXXXX
XXXXXX
XXXXXX
80960MC
26
PRELIMINARY
3.2 Pinout
NOTES: Do not connect any external logic to any pins marked N.C.
Table 8. 80960MC PGA Pinout — In Pin Order
Pin Signal Pin Signal Pin Signal Pin Signal
A1 V
CC
C6 LAD
20
H1 W/R M10 V
SS
A2 V
SS
C7 LAD
13
H2 BE
0
M11 V
CC
A3 LAD
19
C8 LAD
8
H3 LOCK M12 N.C.
A4 LAD
17
C9 LAD
3
H12 N.C. M13 N.C.
A5 LAD
16
C10 V
CC
H13 N.C. M14 N.C.
A6 LAD
14
C11 V
SS
H14 N.C. N1 V
SS
A7 LAD
11
C12 INT3/INTA J1 DT/R N2 N.C.
A8 LAD
9
C13 INT
1
J2 BE
2
N3 N.C.
A9 LAD
7
C14 IAC/INT
0
J3 V
SS
N4 N.C.
A10 LAD
5
D1 ALE J12 N.C. N 5 N.C.
A11 LAD
4
D2 ADS J13 N.C. N6 N.C.
A12 LAD
1
D3 HLDA/HOLDR J14 N.C. N7 N.C.
A13 INT
2
/INTR D12 V
CC
K1 BE
3
N8 N.C.
A14 V
CC
D13 N.C. K2 FAILURE N9 N.C.
B1 LAD
23
D14 N.C. K3 V
SS
N10 N.C.
B2 LAD
24
E1 LAD
28
K12 V
CC
N11 N.C.
B3 LAD
22
E2 LAD
26
K13 N.C. N12 N.C.
B4 LAD
21
E3 LAD
27
K14 N.C. N13 N.C.
B5 LAD
18
E12 N.C. L1 DEN N14 N.C.
B6 LAD
15
E13 V
SS
L2 N.C. P1 V
CC
B7 LAD
12
E14 N.C. L3 V
CC
P2 N.C.
B8 LAD
10
F1 LAD
29
L12 V
SS
P3 N.C.
B9 LAD
6
F2 LAD
31
L13 N.C. P4 N.C.
B10 LAD
2
F3 CACHE/TAG L14 N.C. P5 N.C.
B11 CLK2 F12 N.C. M1 N.C. P6 N.C.
B12 LAD
0
F13 N.C. M2 V
CC
P7 N.C.
B13 RESET F14 N.C. M3 V
SS
P8 N.C.
B14 V
SS
G1 LAD
30
M4 V
SS
P9 N.C.
C1 HOLD/HLDAR G2 READY
M5 V
CC
P10 N.C.
C2 LAD
25
G3 BE
1
M6 N.C. P11 N.C.
C3 BADAC
G12 N.C. M7 N.C. P12 N.C.
C4 V
CC
G13 N.C. M8 N.C. P13 V
SS
C5 V
SS
G14 N.C. M9 N.C. P14 V
CC
80960MC
PRELIMINARY 27
NOTE: Do not connect external logic to any pins marked N.C.
Table 9. 80960MC PGA Pinout — In Signal Order
Signal Pin Signal Pin Signal Pin Signal Pin
ADS
D2 LAD
15
B6 N.C. J14 N.C. P9
ALE
D1 LAD
16
A5 N.C. K13 N.C. P10
BADAC
C3 LAD
17
A4 N.C. K14 N.C. P11
BE
0
H2 LAD
18
B5 N.C. L13 N.C. P12
BE
1
G3 LAD
19
A3 N.C. L14 N.C. L2
BE
2
J2 LAD
20
C6 N.C. M1 REA DY G2
BE
3
K1 LAD
21
B4 N.C. M6 RESET B13
CACHE F3 LAD
22
B3 N.C. M7 V
CC
A1
CLK2 B11 LAD
23
B1 N.C. M8 V
CC
A14
DEN
L1 LAD
24
B2 N.C. M9 V
CC
C4
DT/R
J1 LAD
25
C2 N.C. M12 V
CC
C10
FAILURE
K2 LAD
26
E2 N.C. M 13 V
CC
D12
HLDA/HOLDR D3 LAD
27
E3 N.C. M 14 V
CC
K12
HOLD/HLDAR C1 LAD
28
E1 N.C. N2 V
CC
L3
IAC
/INT
0
C14 LAD
29
F1 N.C. N3 V
CC
M2
INT
1
C13 LAD
30
G1 N.C. N4 V
CC
M5
INT
2
/INTR A13 LAD
31
F2 N.C. N5 V
CC
M11
INT
3
/INTA C12 LOCK H3 N.C. N6 V
CC
P1
LAD
0
B12 N.C. D13 N.C. N7 V
CC
P14
LAD
1
A12 N.C. D14 N.C. N8 V
SS
A2
LAD
2
B10 N.C. E12 N.C. N9 V
SS
B14
LAD
3
C9 N.C. E14 N.C. N10 V
SS
C5
LAD
4
A11 N.C. F12 N.C. N11 V
SS
C11
LAD
5
A10 N.C. F13 N.C. N12 V
SS
E11
LAD
6
B9 N.C. F14 N.C. N13 V
SS
J3
LAD
7
A9 N.C. G12 N.C. N14 V
SS
K3
LAD
8
C8 N.C. G13 N.C. P2 V
SS
L12
LAD
9
A8 N.C. G14 N.C. P3 V
SS
M3
LAD
10
B8 N.C. H12 N.C. P4 V
SS
M4
LAD
11
A7 N.C. H13 N.C. P5 V
SS
M10
LAD
12
B7 N.C. H14 N.C. P6 V
SS
N1
LAD
13
C7 N.C. J12 N.C. P7 V
SS
P13
LAD
14
A6 N.C. J13 N.C. P8 W/R H1
28 PRELIMINARY
80960MC
3.3 Package Thermal Specification
The 80 960MC is spec ified for operat ion when c ase
temp eratur e is within the range 0°C to 85°C (PGA).
Measure case temperature at the top center of the
package. Ambient temperature can be calculated
from:
•T
J
= TC + P*θ
jc
•T
A
= TJ + P*θ
ja
•T
C
= TA + P*[θja−θjc]
Values for θ
ja
and θjc for various airflows are given in
Table 10 f or the PGA package . The PGA’s θ
ja
can
be reduced by adding a heatsink.
Maximum allowable ambient temperature (T
A
)
permitted without exceeding T
C
is shown by the
graphs in Figure 23, Figure 24 and Figure 25. The
curves assume the maximum permitted supply
current (I
CC
) at each speed, VCC of +5.0 V and a
T
CASE
of +85° C (PGA).
Table 10. 80960MC PGA Package Thermal Character istics
Thermal Resistance — °C/Watt
Parameter
Airflow — ft./min (m/sec)
0
(0)50(0.25)
100
(0.50)
200
(1.01)
400
(2.03)
600
(3.04)
800
(4.06)
θ Junction-to-Case2222222
θ Case-to-Ambient
(No Heatsink)
19 18 17 15 12 10 9
θ Case-to-Ambient
(Omnidirectional
Heatsink)
16 15 14 12 9 7 6
θ Case-to-Ambient
(Unid ire ct iona l
Heatsink)
15 14 13 11 8 6 5
NOTES:
1. This table applies to 80960MC PGA plugged into socket or soldered directly to board.
2. θ
JA
= θJC + θ
CA
3. θ
J-CAP
= 4°C/W (approx.)
θ
J-PIN
= 4°C/W (inner pins) (approx.)
θ
J-PIN
= 8°C/W (outer pins) (approx.)
θ
JC
θ
JA
θ
J-PIN
θ
J-CAP
80960MC
PRELIMINARY 29
Figure 22. 25 MHz Maximum Allowable Ambient Temperature
AIRFLOW (ft/min)
TEMPERATURE (
o
C)
80
75
70
65
60
55
50
45
40
0 100 200 300 400 500 600 700 800
PGA with no
heatsink
PGA with omnidirectional heatsink
PGA with unidirectional heatsink
85
80960MC
30
PRELIMINARY
4.0 WAVEFORMS
The following figures present waveforms for various transactions on the 80960MC’S local bus:
• Figure 23, Non-Burst Read and Write Transactions Without W ait States (pg. 30)
• Figure 24, Burst Read and Write Tran saction Without Wait Stat es (pg. 31)
• Figure 25, Burs t Write Transaction with 2 , 1, 1, 1 Wait States (pg. 3 2)
• Figure 26, Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad Word
Boundary (1, 0, 0, 0 Wait States) (pg. 33)
• Figure 27, Interrupt Acknowledge Transaction (pg. 34)
• Figure 28, Bus Exchange Transaction (PBM = Primary Bus Master, SBM = Secondary Bus Master) (pg. 35)
Figure 23. Non-Burst Read and Write Transactions Without Wait States
T
a
T
d
T
r
T
a
T
d
T
r
CLK2
CLK
LAD31:0
ALE
ADS
BE3:0
W/R
DT/R
DEN
READY
80960MC
PRELIMINARY 31
Figure 24. Burst Read and Write Transaction Without Wait States
T
a
T
d
T
d
T
r
T
a
T
d
T
d
T
d
T
d
T
r
CLK2
CLK
LAD31:0
ALE
ADS
BE3:0
W/R
DT/R
DEN
READY
80960MC
32
PRELIMINARY
Figure 25. Burst Write Transaction with 2, 1, 1, 1 Wait States
T
a
T
w
T
w
T
d
T
w
T
d
T
w
T
d
T
w
T
d
T
r
CLK2
CLK
LAD31:0
ALE
ADS
BE3:0
W/R
DT/R
DEN
READY
80960MC
PRELIMINARY 33
Figure 26. Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad
Word Boundary (1, 0, 0, 0 Wait States)
T
a
T
w
T
d
T
d
T
d
T
d
T
r
T
a
T
w
T
d
T
r
CLK2
CLK
LAD31:0
ALE
ADS
BE3:2
W/R
DT/R
DEN
READY
BE1:0
80960MC
34
PRELIMINARY
Figure 27. Inter rupt A cknow l ed ge Tr an sa ction
CLK2
T
X
T
X
T
a
T
d
T
r
T
r
T
I
T
I
T
I
T
I
T
I
T
a
T
w
T
d
INTR
LAD31:0
ALE
ADS
INTA
DT/R
DEN
LOCK
READY
NOTE:
INTR can go low no sooner than the input hold time following the beginning of interrupt acknowledgment cycle 1.
For a second interrupt to be acknowledged, INTR must be low for at least three cycles before it can be reasserted.
INTERRUPT
ACKNOWLEDGEMENT
CYCLE 1
IDLE
(5 BUS STATES)
INTERRUPT
ACKNOWLEDGEMENT
CYCLE 2
PREVIOUS
CYCLE
ADDR
VECTOR
ADDR
CLK
80960MC
PRELIMINARY 35
Figure 28. Bus Exchange Transaction (PBM = Primary Bus Master, SBM = Secondary Bus Master)
5.0 REVISION HISTORY
No revision history was maintained in earlier revisions of this data sheet. All errata that has been identified to
date is incorporated into this revision. The sections significantly changed since the previous revision are:
Section
Last
Rev.
Description
This is the initial commercial data sheet for the A80960MC.
A4492-01
LAD
31
CLK
T
T
T
adh
T
T
T
ad
r
Addr
Data
Addr
Data
Addr
Data
DataData
Data
Addr
ThThThThT
h
T
h
T
h
T
d
T
h
ThrThrT
hr
T
a
T
d
T
r
ThrThrThrT
hr
T
a
TdT
d
T
i
T
i
T
h
T
h
T
h
T
h
W/R#
LAD
0
_
PBM ALE#
SBM ALE#
READY#
SBM
HOLDR
PBM
HOLD
PBM
HLDA
SBM
HLDAR
PBM BUS
STATE
SBM BUS
STATE
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