Intel Corporation A80960CF-40, A80960CF-33, A80960CF-25 Datasheet
© INTEL CORPORATION, 1996 June 1996 Order Number: 272886-001
A PRELIMINARY
80960CF-40, -33, -25, -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
EMBEDDED MICROPROCESSOR
• Socket and Object Code Compatible with 80960CA
• Two Instructions/Clock Sustained Execution
• Four 71 Mbytes/s DMA Channels with Data Chaining
• Demultiplexed 32-Bit Burst Bus with Pipelining
■ 32-Bit Parallel Architecture
— Two Instructions/clock Execution
— Load/Store Architecture
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers
— Manipulates 64-Bit Bit Fields
— 11 Addressing Modes
— Full Parallel Fault Model
— Supervisor Protection Mo del
■ Fast Procedure Call/Return Model
— Full Procedure Call in 4 Clocks
■ On-Chip Register Cache
— Caches Registers on Call/Ret
— Minimum of 6 Frames Provided
— Up to 15 Programmable Frames
■ On-Chip Instruction Cache
— 4 Kbyte Two-W ay Set Associati ve
— 128-Bit Path to Instruction Sequencer
— Cache-Lock Modes
— Cache-Off Mode
■ High Bandwidth On-Chip Data RAM
— 1 Kbyte On-Chip Data RAM
— Sustains 128 bits per Clock Access
■ Selectable Big or Little Endian Byte
Ordering
■ Four On-Chip DMA Channels
— 71 Mbytes/s Fly-by Transfers
— 40 Mbytes/s Two-Cycle Transfers
— Data Chaining
— Data Packing/Unpacking
— Programmable Priority Method
■ 32-Bit Demultiplexed Burst Bus
— 128-Bit Internal Data Paths to
and
from
Registers
— Burst Bus for DRAM Interfacing
— Address Pipelining Option
— Fully Programmable Wait States
— Supports 8-, 16- or 32-Bit Bus Widths
— Supports Unaligned Accesses
— Supervisor Protection Pin
■ High-Speed Interrupt Controller
— Up to 248 External Interrupts
— 32 Fully Programmable Priorities
— Multi-mode 8-Bit Interrupt Port
— Four Internal DMA Interrupts
— Separate, Non-maskable Interrupt Pin
— Context Switch in 625 ns Typical
■ On-Chip Data Cache
— 1 Kbyte Direct-Mapped, Write Through
— 128 bits per Clock Access on Cache Hit
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sustaining applications.
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Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained from:
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P.O. Box 7641
Mt. Prospect IL 60056-764
or call 1-800-548-4725
PRELIMINARY
iii
A CONTENTS
80960CF-40, -33, -25, -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
EMBEDDED MICROPROCESS OR
1.0 PUR P OSE ... ...... . ...... ............ ........... .. ...... ........... .. ...... ........... .. ...... .. ...... . ...... ............ ........... .. ...... ........... .. .. 1
2.0 80960CF OVERVIEW ................................................................................................................................1
2.1 The 80960C-Series Core . .......................................... .......................................... ...............................3
2.2 Pipelined, Burst Bus ...........................................................................................................................3
2.3 Instruction Set Summary ....... ........ ....... .... ........ ...... ..... ...... ........ ..... ...... ........ ....... .... ........ ...... ..... ...... ..3
2.4 Flexible DMA Controller ... .......................................... .......................................... ...............................3
2.5 Priority Interrupt Controller ...................... .............. ....... ................ ....... .............. ....... ................ ....... ....4
3.0 PACKAGE INFORMATION ......................................................................................... ............................... 5
3.1 Package Introduction ............................ .......................................... .......................................... ..........5
3.2 Pin Descriptions ............ ....... ................ ....... .............. ....... ............... ........ ............. ........ ............. ..........5
3.3 80960CF Mechanical Data ................. ........... .... .... ............. .... .... ........... .... .... .... ............. .... .... ..........12
3.3.1 80960CF PGA PINOUT .........................................................................................................12
3.3.2 80960CF PQFP Pinout (80960CF-33, -25, -16 Only) ............................................................1 6
3.4 Package Thermal Specifications ................ .............. ....... ............... ........ ............. ........ ............. ........19
3.5 Stepping Register Information .................................................................. ........... ............ ......... ........22
3.6 Sources for Accessories ............................................ ........ ............. .......... ........... .......... ........... ........22
4.0 ELECTRICAL SPECIFICATIONS ............................................................................................................ 23
4.1 Absolute Maximum Ratings . ...................................... .......................................... .............................23
4.2 Operating Conditions ........................................................................................................................23
4.3 Recommended Connections ................................................................................................ ........... .24
4.4 DC Specifications .............................................................................................................................24
4.5 AC Specifications .................................. ........ ............. .......... ........... .......... ........... ............ ......... ........26
4.5.1 AC TEST CONDITIONS ............ .... ........ ........ ... ........ ...... ..... ...... ........ ....... .... ........ ........ ... ......3 6
4.5.2 AC TIMING WAVEFORMS ....... . ...... .... ...... .... ... ...... .... ...... ... .... .... ...... .... ... .... ...... .... ...... ... .... ..37
4.5.3 DERATING CURVES ........ ........ ... ........ ...... ..... ...... ........ ....... .... ........ ........ ... ........ ...... ..... ...... ..41
5.0 RESET, BACKOFF AND HOLD ACKNOWL EDGE ................................................................................42
6.0 BUS WAVEFORMS ..................................................................................................................................44
7.0 REVISION HISTORY ............................................................................................................................... 71
iv
PRELIMINARY
CONTENTS A
FIGURES
Figure 1. 80960CF Block Diagram ............................................................................................................2
Figure 2. 80960CF PGA Pinout—View from Top (Pins Facing Down) ....................... .............................12
Figure 3. 80960CF PGA Pinout — View from Bottom (Pins Facing Up) ...................................... ....... ....13
Figure 4. 80960CF PQFP Pinout—Top View (80960CF-33, -25, -16 Only) ............................................19
Figure 5. Measuring 80960CF PGA and PQFP Case Tem perat ure .......................................................20
Figure 6. Register g0 ...............................................................................................................................22
Figure 7. AC Test Load ...........................................................................................................................37
Figure 8. Input and Output Clocks Waveform .........................................................................................37
Figure 9. CLKIN Waveform .....................................................................................................................37
Figure 10. Output Delay and Float Waveform ...........................................................................................38
Figure 11. Input Setup and Hold Waveform ..............................................................................................3 8
Figure 12. NMI
, XINT7:0 Input Setup and Hold Waveform .......................................................................39
Figure 13. Hold Acknowledge Timings ......................................................................................................39
Figure 14. Bus Backoff (BOFF) Timings ...................................................................................................40
Figure 15. Relative Timings Waveforms ...................................................................................................40
Figure 16. Output Delay or Hold vs. Load Capacitance ............................................................................41
Figure 17. Rise and Fall Time Derating at Highest Operating Temperature and M inimum V
CC
............... 41
Figure 18. I
CC
vs. Frequency and Tempera ture— 80960CF -33, -25, -16 ..................................................42
Figure 19. I
CC
vs. Frequency and Tempera ture— 80960CF -40 ................................................................ 4 2
Figure 20. Cold Reset Waveform ..............................................................................................................44
Figure 21. Warm Reset Waveform ............................................................................................................45
Figure 22. Entering the ONCE State .................................. .............. ....... .............. ....... ................ ....... ......46
Figure 23. Clock Synchronization in the 2-x Clock Mode ..........................................................................47
Figure 24. Clock Synchronization in the 1-x Clock Mode ..........................................................................47
Figure 25. Non-Burst, Non-Pipelined Requests Without Wait States ........................................................48
Figure 26. Non-Burst, Non-Pipelined Read Request With Wait States ............................................. ........49
Figure 27. Non-Burst, Non-Pipelined Write Request With Wait States .....................................................50
Figure 28. Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus .....................................51
Figure 29. Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus ..........................................52
Figure 30. Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus ............................. .... ....53
Figure 31. Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus .......................................... 54
Figure 32. Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus ..........................................55
Figure 33. Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus ............................................56
Figure 34. Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus .....................................5 7
Figure 35. Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus ..........................................58
Figure 36. Burst, Pipelined Read Request Without Wait States, 32-Bit Bus .............................................59
Figure 37. Burst, Pipelined Read Request With Wait States, 32-Bit Bus ..................................................60
Figure 38. Burst, Pipelined Read Request With Wait States, 16-Bit Bus ..................................................61
Figure 39. Burst, Pipelined Read Request With Wait States, 8-Bit Bus .. ..................... .............................62
PRELIMINARY
v
A CONTENTS
Figure 40. Using External READY ............................................................................................................ 63
Figure 41. Terminating a Burst with BTERM
............................................................................................. 64
Figure 42. BOFF
Functional Timing ..........................................................................................................65
Figure 43. HOLD Functional Timing ..........................................................................................................66
Figure 44. DREQ
and DACK Functional Timing .......................................................................................67
Figure 45. EOP
Functional Timing ............................................................................................................67
Figure 46. Terminal Count Functional Timing ...........................................................................................68
Figure 47. FAIL
Functional Timing ............................................................................................................68
Figure 48. A Summary of Aligned and Unaligned Transfers for Little Endian Regions .............................69
Figure 49. A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) .........70
Figure 50. Idle Bus Operation ...................................................................................................................71
TABLES
Table 1. 80960CF Instruction Set ............................................................................................................4
Table 2. 80960CF Pin Description — External Bus Signals ....................................................................6
Table 3. 80960CF Pin Description — Processor Control Signals ............................................................9
Table 4. 80960CF Pin Description — DMA and Interrupt Unit Control Signals ..................................... 11
Table 5. 80960CF PGA Pinout — In Signal Order ................................................................................14
Table 6. 80960CF PGA Pinout — In Pin Order .....................................................................................1 5
Table 7. 80960CF PQFP Pinout — In Signal Order (80960CF-33, -25, -16 Only ) ................................ 17
Table 8. 80960CF PQFP Pinout — In Pin Order (80960CF-33, -25, -16 Only) ......... ............................18
Table 9. Maximum T
A
at Various Airflows in oC (PGA Package Only) ..................................... ....... .......20
Table 10. 80960CF PGA Package Thermal Characteristics ...................................................................21
Table 11. 80960CF PQFP Package Therm al Characteristics .................................................................21
Table 12. Die Stepping Cross Reference ................................................................................................22
Table 13. Operating Conditions ...............................................................................................................23
Table 14. DC Characteristics ............................................................................................................ .......24
Table 15. 80960CF AC Characteristics (40 MHz) ...................................................................................26
Table 16. 80960CF AC Characteristics (33 MHz) ...................................................................................29
Table 17. 80960CF AC Characteristics (25 MHz) ...................................................................................32
Table 18. 80960CF AC Characteristics (16 MHz) ...................................................................................34
Table 19. Reset Conditions .....................................................................................................................43
Table 20. Hold Acknowledge and Ba ckoff Conditions .............................................................................43
A 80960CF-40, -33, -25, -16
PRELIMINARY
1
1.0 PURPOSE
This document provides electrical characteristics of
Intel’s i960
®
CF embedded microprocessor. For
functional descriptions consult the
i960® Cx Micro-
processor User’s Manual
(270710). To obtain data
sheet updates and errata, contact Intel at any of the
following numbers.
2.0 80960CF OVERVIEW
Intel’s 80960CF is the second processor in the series
of superscalar i960 microprocessors that also
includes the 80960CA and the 80960HA/HD/HT.
Upgrading from the 80960CA to the 80960CF is
straightforward because the two processors are
socket- and object code-compatible.
As shown in Figure 1, the 80960CF’s instruction
cache is 4 K bytes; data cache is 1 K byte (80960CA
instruction cache is 1 Kbyte; it does not have a data
cache.) This extra cache on the CF adds a significant performance boost over the CA.
Intel’s World-Wide Web (WWW) Location: http://www.intel.com/
Customer Support (US and Canad a): 800-628-8686
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800-628-2283
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dedicated 2400-baud line, worldwide
916-356-7209
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+44(0)793-496340
2
PRELIMINARY
80960CF-40, -33, -25, -16 A
Figure 1. 80960CF Block Diagram
Execution
Unit
Programmable
Bus Controller
Bus Request
Queues
Six-Port
Register File
64-Bit
SRC1 Bus
64-Bit
SRC2 Bus
64-Bit
DST Bus
32-Bit
Base Bus
128-Bit
Load Bus
128-Bit
Store Bus
Instruction
Instruction Cache
(4 Kbyte, Two-Way
Set Associative)
128-BIT CACHE BUS
Prefetch Queue
Interrupt Controller
Control
Address
Data
Memory-side
Machine Bus
Register-side
Machine Bus
Parallel
Instruction
Scheduler
Memory Region
Configuration
Multiply/Divide
Unit
Four-Channel
DMA Controller
Interrupt
Port
1 Kbyte
5 to 15 Sets
Register Cache
Data RAM
Address
Generation Unit
F_CF001A
DMA Port
1 Kbyte
Direct Mapped
Data Cache
The 80960CF, object code compatible with the 32-bit
80960 core Architecture, employs Special Function
Register extensions to control on-chip peripherals
and instruction set extensions to shift 64-bit
operands and configure on-chip hardware. Multiple
128-bit internal buses, on-chip instruction caching
and a sophisticated instruction scheduler allow the
processor to sustain execution of two instructions
per clock with peak execution of three instructions
per clock.
A 32-bit demultiplexed and pipelined burst bus
provides a 132 Mbyte/s bandwidth to a system’s
high-speed external memory subsystem. Also, the
80960CF’s on-chip caching of instructions, procedure context and critical pr ogram data substantially
decouples system perf ormance from the wait states
associated with accesses to the system’s slower,
cost sensitive, main memory subsystem.
The 80960CF bus controller integrates full wait st ate
and bus width control for highest system performance with minimal system design complexity.
Unaligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CF.
A 80960CF-40, -33, -25, -16
PRELIMINARY
3
The processor also integrates four complete datachaining DMA channels and a high-speed interrupt
controller on-chip. DMA channels perform singlecycle or two-cycle transfers, data packing and
unpacking and data chaining. Block transfers — in
addition to source or destination synchronized transfers — are supported.
The interrupt controller provides full programmability
of 248 interrupt sources into 32 prior ity levels with a
typical interrupt task switch (latency) time of 625 ns.
2.1 The 80960C-Series Core
The C-Series core is a very high performance
microarchitectural implement ation of th e 80960 Cor e
Architecture. This core can sustain execu tion of two
instructions per clock (80 MIPS at 40 MHz). To
achieve this level of performance, Intel has incorporated state-of-the-art s ilicon technology and innovative microarchitectural constructs into the C-Series
core implementation. Factors that contribute to the
core’s performance include:
• Parallel instruction decoding allows issuance of up
to three instructions per clock
• Single-clock execution of most instructions
• Parallel instruction decode allows sustained,
simultaneous execution of two single-clock instructions every clock cycle
• Efficient instruction pipeline minimizes pipeline
break losses
• Register and resource scoreboarding allow simultaneous multi-clock instruction execution
• Branch look-ahead and prediction allows many
branches to execute with no pipeline break
• Local Register Cache integrated on-chip caches
Call/Return context
• Two-way set associative, 4 Kbyte integrated
instruction cache
• 1 Kbyte integrated Data RAM sustains a four-word
(128-bit) access every clock cycle
• Direct mapped, 1 Kbyte data cache, write through,
write allocate
2.2 Pipelined, Burst Bus
A 32-bit high performance bus controller interfaces
the 80960CF to external memory and peripherals.
The Bus Control Unit features a maximum transfer
rate of 160 Mbytes per second (at 40 MHz). Internally programmable wait states and 16 separately
configurable memory regions allow the processor to
interface with a variety of memory subsystems with a
minimum of system complexity and a maximum of
performance. The Bus C ontrol Unit’s main features
include:
• Demultiplexed, burst bus to exploit most efficient
DRAM access modes
• Address pipelining to reduce memory cost while
maintaining performance
• 32-, 16- and 8-bit modes for I/O interfacing ease
• Full internal wait state generation to reduce system
cost
• Little and Big Endian support to ease application
development
• Unaligned access support for code portability
• Three-deep request queue to decouple the bus
from the core
2.3 Instruction Set Summary
Table 1 summarizes the 80960CF instruction set by
logical groupings. See the
i960® Cx Microprocessor
User’s Manual
(270710) for a complete description
of the instruction set.
2.4 Flexible DMA Controller
A four-channel DMA controller provides high speed
DMA control for data transfers involving peripherals
and memory. The DMA provides advanced features
such as data chaining, byte assembly and disassembly and a high performance fly-by mode capable
of transfer speeds of up to 71 Mbytes per second at
40 MH z. The DMA c ontr oller feat ures a p erfor mance
and flexibility which is only possible by integrating
the DMA controller and the 80960CF core.
80960CF-40, -33, -25, -16 A
4
PRELIMINARY
2.5 Priority Interrupt Controller
A programmable-priority interrupt controller
manages up to 248 external sources through the 8bit external interrupt port. The Interrupt Unit also
handles the four internal sources from the DMA
controller and a single non-maskable interrupt input.
The 8-bit interrupt port can also be configured to
provide individual interrupt s ources that are level or
edge triggered.
80960CF interrupts are prioritized and signaled
within 225 ns of the request. If the interrupt is of
higher priority than the processor priority, the context
switch to the interrupt routine typically completes in
another 400 ns. The interrupt unit provides the
mechanism for the low latency and high throughput
interrupt service which is essential for embedded
applications.
Table 1. 80960CF Instruction Set
Data Movement Arithmetic Logical Bit / Bit Field / Byte
Load
Store
Move
Load Address
Add
Subtract
Multiply
Divide
Remainder
Modulo
Shift
*Extended Shift
Extended Multiply
Extended Divide
Add with Carry
Subtract with Carry
Rotate
And
Not And
And Not
Or
Exclusive Or
Not Or
Or Not
Nor
Exclusive Nor
Not
Nand
Set Bit
Clear Bit
Not Bit
Alter Bit
Scan For Bit
Span Over Bit
Extract
Modify
Scan Byte for Equal
Comparison Branch Call/Return Fault
Compare
Conditional Compare
Compare and Increment
Compare and Decrement
Test Condition Code
Check Bit
Unconditional Branch
Conditional Branch
Compare and Branch
Call
Call Extended
Call System
Return
Branch and Link
Conditional Fault
Synchronize Faults
Debug Processor Mgmt Atomic
Modify Trace Controls
Mark
Force Mark
Flush Local Registers
Modify Arithmetic Controls
Modify Process Controls
*System Control
*DMA Control
Atomic Add
Atomic Modify
NOTES: Instructions marked by (*) are 80960Cx extensions to th e 80960 instruct ion set.
A 80960CF-40, -33, -25, -16
PRELIMINARY
5
3.0 PACKAGE INFORMATION
3.1 Package Introduction
This section describes the pins, pinouts and therma l
characteristics for the 80960CF in the 168-pin
Ceramic Pin Grid Array (PGA) package; the
80960CF-33, -25, -16 devices are also available in
the 196-pin Plastic Quad Flat Package (PQFP). For
complete package specifications and information,
see the
Packaging
Handbook (# 240800).
3.2 Pin Descriptions
This section defines the 80960CF pins. Table 2
presents the legend for interpreting the pin descriptions in the following tables. Pins associated w ith the
32-bit demultiplexed processor bus are described in
Table 2. Pins associated with the 80960CF DMA
Controller and Interrupt Unit are described in T able 3.
Pins associated with basic processor configuration
and control are described in Table 2.
All pins float while the processor is in the ONCE
mode.
Symbol Description
I Input only pin
O Output only pin
I/O Pin can be either an input or output
– Pins “must be” connected as descr ibe d
S(...) Synchronous. Inputs must meet setup
and hold times relative to PCLK2:1 for
proper operation. Outputs are synchronous to PCLK2:1.
S(E) Edge sensitive input
S(L) Level sensitive input
A(...) Asynchronous. Inputs may be asynchro-
nous to PCLK2:1.
A(E) Edge sensitive input
A(L) Level sensitive input
H(...) While the bus is in the Hold Acknowledge
or Bus Backoff state, the pin:
H(1) is driven to V
CC
H(0) is driven to V
SS
H(Z) floats
H(Q) continues to be a valid input
R(...) While the processor’s RESET
pin is low,
the pin:
R(1) is driven to V
CC
R(0) is driven to V
SS
R(Z) floats
R(Q) continues to be a valid output
6
PRELIMINARY
80960CF-40, -33, -25, -16 A
Table 2. 80960CF Pin Description — External Bus Signals (Sheet 1 of 3)
Name Type Description
A31:2 O
S
H(Z)
R(Z)
ADDRESS BUS carries the physical address’ upper 30 bits. A31 is the most significant
bit; A2 is least significant. During a bus access, A31:2 identify all external addresses to
word (4-byte) boundaries. Byte enable signals indicate the selected byte in each word.
During burst accesses, A3:2 increment to indicate successive data cycles.
D31:0 I/O
S(L)
H(Z)
R(Z)
DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configuration. The least significant bit is carried on D0 and the most significant on D31. When the
bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used. For 16-bit data
bus widths, D15:0 are used. For 32-bit bus widths the full data bus is used.
BE3:0
O
S
H(Z)
R(1)
BYTE ENABLES select which of the four bytes addressed by A31:2 are active during
an access to a memory region configured for a 32-bit data-bus width. BE3
applies to
D31:24; BE2
applies to D23:16; BE1 applies to D15:8 BE0 applies to D7:0.
32-bit bus:
BE3
Byte Enable 3 enable D31:24
BE2
Byte Enable 2 enable D23:16
BE1
Byte Enable 1 enable D15:8
BE0
Byte Enable 0 enable D7:0
For accesses to a memory region configured for a 16-bit data-bus width, the processor
uses the BE3
, BE1 and BE0 pins as BHE, A1 and BLE respectively.
16-bit bus:
BE3
Byte High Enable (BHE) enable D15:8
BE2
Not used (driven high or low)
BE1
Address Bit 1 (A1)
BE0
Byte Low Enable (BLE) enable D7:0
For accesses to a memory region configured for an 8-bit data-bus width, the processor
uses the BE1
and BE0 pins as A1 and A0 respectively.
8-bit bus:
BE3
Not used (driven high or low)
BE2
Not used (driven high or low)
BE1
Address Bit 1 (A1)
BE0
Address Bit 0 (A0)
W/R O
S
H(Z)
R(0)
WRITE/READ is asserted for read requests and deasserted for write requests . The
W/R
signal changes in the same clock cycle as ADS. It remains valid for the entire
access in non-pipelined regions. In pipelined regions, W/R
is not guaranteed to be valid
in the last cycle of a read access.
ADS
O
S
H(Z)
R(1)
ADDRESS STROBE indicates a valid address and the start of a new bus access. ADS
is asserted for the first clock of a bus access.
READY
I
S(L)
H(Z)
R(Z)
READY is an input which signals the termination of a data transfer. READY
is used to
indicate that read data on the bus is valid or that a write-data transfer has completed.
The READY
signal works in conjunction with the internally programmed wait-state
generator. If READY
is enabled in a region, the pin is sampled after the programmed
number of wait-states has expired. If the READY
pin is deasserted, wait states continue
to be inserted until READY
becomes asserted. This is true for the N
RAD
, N
RDD
, N
WAD
and N
WDD
wait states. The N
XDA
wait states cannot be extended.
PRELIMINARY
7
A 80960CF-40, -33, -25, -16
BTERM I
S(L)
H(Z)
R(Z)
BURST TERMINATE is an input which breaks up a burst access and causes another
address cycle to occur. The BTERM
signal works in conjunction with the internally
programmed wait-state generator. If READY
and BTERM are enabled in a region, the
BTERM
pin is sampled after the programmed number of wait states has expired. When
BTERM
is asserted, a new ADS signal is generated and the access is completed. The
READY
input is ignored when BTERM is asserted. BTERM must be externally synchro-
nized to satisfy BTERM
setup and hold times.
WAIT
O
S
H(Z)
R(1)
WAIT indicates internal wait state generator status. WAIT
is asserted when wait states
are being caused by the internal wait state generator and not by the READY
or BTERM
inputs. WAIT
can be used to derive a write-data strobe. WAIT can also be thought of as
a READY
output that the processor provides when it is inserting wait states.
BLAST
O
S
H(Z)
R(0)
BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the last
data transfer of burst and non-burst accesses after the wait state counter reaches zero.
BLAST
remains asserted until the clock following the last cycle of the last data transfer
of a bus access. If the READY
or BTERM input is used to extend wait states, the
BLAST
signal remains asserted until READY or BTERM terminates the access.
DT/R
O
S
H(Z)
R(0)
DATA TR ANSM IT/R ECE IVE indicates direct ion for data tra nsceiver s. DT/R
is used in
conjunction with DEN
to provide control for data transceivers attached to the external
bus. When DT/R
is asserted, the signal indicates that the processor receives data.
Conversely, when deasserted, the processor sends data. DT/R
changes only while
DEN
is high.
DEN
O
S
H(Z)
R(1)
DATA ENABLE indicates data cyc les in a bus request. DEN
is asserted at the start of
the bus request first data cycle and is deasserted at the end of the last data cycle. DEN
is used in conjunction with DT/R
to provide control for data transceivers attached to the
external bus. DEN
remains asserted for sequential reads from pipelined memory
regions. DEN
is deasserted when DT/R changes.
LOCK
O
S
H(Z)
R(1)
BUS LOCK indicates that an atomic read-modify-write operat ion is in progress. LOCK
may be used to prevent external agents from accessing memory whic h is currently
involved in an atomic operation. LOCK
is asserted in the first clock of an atomic operation and deasserted in the clock cycle following the last bus access for the atomic
operation. To allow the most flexibility for memory syst em enfor ceme nt of locked
accesses, the processor acknowledges a bus hold request when LOCK
is asserted.
The processor performs DMA transfers while LOCK
is active.
HOLD I
S(L)
H(Z)
R(Z)
HOLD REQUEST signals that an external agent request s access to the external bus.
The processor asserts HOLDA after completing the current bus reques t. HOLD,
HOLDA and BREQ are used together to arbitrate acces s to the processor’s external
bus by external bus agents.
BOFF
I
S(L)
H(Z)
R(Z)
BUS BACKOFF, when asserted, suspends the current access and causes the bus pins
to float. When BOFF
is deasserted, the ADS signal is asserted on the next clock cycle
and the access is resumed.
Table 2. 80960CF Pin Description — External Bus Signals (Sheet 2 of 3)
Name Type Description
8
PRELIMINARY
80960CF-40, -33, -25, -16 A
HOLDA O
S
H(1)
R(Q)
HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has relinquished control of the external bus. When HOLDA is asserted, the external address
bus, data bus and bus control signals are floated. HOLD, BOFF
, HOLDA and BREQ are
used together to arbitrate access to the processor’s external bus by external bus
agents. Since the processor grants HOLD requests and enters the Hold Acknowledge
state even while RESET
is asserted, the state of the HOLDA pin is independent of the
RESET
pin.
BREQ O
S
H(Q)
R(0)
BUS REQUEST is asserted when the bus controller has a request pending. BREQ can
be used by external bus arbitration logic in conjunction with HOLD and HOLDA to determine when to return mastership of the external bus to the processor.
D/C
O
S
H(Z)
R(Z)
DA TA OR CODE is asserted for a data request and deasserted for instruction requests.
D/C
has the same timing as W/R.
DMA
O
S
H(Z)
R(Z)
DMA ACCESS indicates whether the bus request was initiated by the DMA controller.
DMA
is asserted for any DMA request. DMA is deasserted for all other requests.
SUP
O
S
H(Z)
R(Z)
SUPERVISOR ACCESS indicates whether the bus request is issued while in supervisor mode. SUP
is asserted when the request has supervisor privileges and is
deasserted otherwise. SUP
can be used to isolate supervisor code and data structures
from non-supervisor requests.
Table 2. 80960CF Pin Description — External Bus Signals (Sheet 3 of 3)
Name Type Description
PRELIMINARY
9
A 80960CF-40, -33, -25, -16
Table 3. 80960CF Pin Description — Processor Contro l Signal s (Sheet 1 of 2)
Name Type Description
RESET
I
A(L)
H(Z)
R(Z)
RESET causes the chip to reset. When RESET
is asserted, all external signals return
to the reset state. When RESET
is deasserted, initialization begins. When the 2-x
clock mode is selected, RESET
must remain asserted for 32 CLKIN cycles before
being deasserted to guarantee correct processor initialization. When the 1-x clock
mode is selected, RESET
must remain asserted for 10,000 CLKIN cycles before
being deasserted to guarantee correct processor initialization. The CLKMO DE pin
selects 1-x or 2-x input clock division of the CLKIN pin.
The Hold Acknowledge bus state functions while the chip is reset. If the bus is in the
Hold Acknowledge state when RESET
is asserted, the processor internally resets,
but maintains the Hold Acknowledge state on external pins until the Hold request is
removed. If a Hold request is made while the processor is in the reset state, the
processor bus grants HOLDA and enters the Hold Acknowledge stat e.
FAIL
O
S
H(Q)
R(0)
FAIL indicat es failure of the self- test perfor med at initialization. When RES ET
is
deasserted and initialization begins, the FAIL
pin is asserted. An internal self-test is
performed as part of the initialization process. If this self-test passes, the FAIL
pin is
deasserted; otherwise it remains asserted. The FAIL
pin is reasserted while the
processor performs an external bus self-confidence test. If this self-test passes, the
processor deasserts the FAIL
pin and branches to the user’s initialization routine;
otherwise the FAIL
pin remains asserted. Internal self-test and the use of the FAIL pin
can be disabled with the STEST pin.
STEST I
S(L)
H(Z)
R(Z)
SELF TEST enables or disables the internal self-test feature at initialization. STEST
is read on the rising edge of RESET
. When asserted, internal self-test and external
bus confidence tests are performed during processor initialization. When deasserted,
only the bus confidence tests are performed during initialization.
ONCE
I
A(L)
H(Z)
R(Z)
ON CIRCUIT EMULATION, when asserted, causes all outputs to be floated. ONCE
is
continuously sampled while RESET
is low and is latched on the rising edge of
RESET
. To place the processor in the ONCE state:
(1) assert RESET
and ONCE (order does not matter)
(2) wait for at least 16 CLKIN periods in 2-x mode—or 10,000 CLKIN
periods in 1-x mode—after V
CC
and CLKIN are within operating
specifications
(3) deassert RESET
(4) wait at least 32 CLKIN periods
(The processor will now be latched in the ONCE state while RESET
is high.)
To exit the ONCE state, bring V
CC
and CLKIN to operating conditions, then assert
RESET
and bring ONCE high prior to deasserting RESET.
CLKIN must operate within the specified operating conditions until Step 4 completes.
CLKIN may then be changed to DC to achieve the lowest possible ONCE mode
leakage current.
ONCE
can be used by emulator products or board testers to effectively make an
installed processor transparent in the board.
10
PRELIMINARY
80960CF-40, -33, -25, -16 A
CLKIN I
A(E)
H(Z)
R(Z)
CLOCK INPUT is an input for the external clock needed to run the processor. The
external clock is internally divided as prescribed by the CLKMODE pin to produce
PCLK2:1.
CLKMODE I
A(L)
H(Z)
R(Z)
CLOCK MODE selects the division factor applied to the external clock input (CLKIN).
When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and the
processor’s internal clock. When CLKMODE is low, CLKIN is divided by two to create
PCLK2:1 and the processor ’s internal clock. CLKMODE should be tied high or low in
a system as the clock mode is not latched by the processor. If left unconnected, the
processor internally pulls the CLKMODE pin low, enabling the 2-x clock mode.
PCLK2:1 O
S
H(Q)
R(Q)
PROCESSOR OUTP UT CLOCKS prov ide a timing reference for all inputs and
outputs. All input and output timings are specified in relation to PCLK2 and PCLK1.
PCLK2 and PCLK1 are identical signals. Two output pins are provided to allow flexibility in the system’s allocation of capacitive loading on the clock. PCLK2:1 may also
be connected at the processor to form a single clock signal.
V
SS
– GROUND connections must be connect ed exte rnally to a VSS board plane.
V
CC
– POWER connections mus t be connected externally to a VCC board plane.
V
CCPLL
– V
CCPLL
is a separate VCC supply pin for the phase lock loop used in 1-x clock mode.
Connecting a simple lowpass filter to V
CCPLL
may help reduce clock jitter (TCP) in
noisy environments. Otherwise, V
CCPLL
should be connected to VCC.
NC – NO CONNEC T pins must not be connected in a system.
Table 3. 80960CF Pin Description — Processor Co ntrol Signals (Sheet 2 of 2)
Name Type Description
PRELIMINARY
11
A 80960CF-40, -33, -25, -16
Table 4. 80960CF Pin Description — DMA and Interrupt Unit Con tro l Signal s
Name Type Description
DREQ3:0
I
A(L)
H(Z)
R(Z)
DMA REQUEST is used to request a DMA transfer. Each of the four signals
requests a transfer on a single channel. DREQ0
requests channel 0, DREQ1
requests channel 1, etc. When two or more channels are requested simultaneously,
the channel with the highest priority is serviced first. Channel priority mode is
programmable.
DACK3:0
O
S
H(1)
R(1)
DMA ACKNOWLEDGE indicates that a DMA transfer is being execut ed. Each of
the four signals acknowledges a transfer for a single channel. DACK0
acknowl-
edges channel 0, DACK1
acknowledges channel 1, etc. DACK3:0 are asserted
when the requesting device of a DMA is accessed.
EOP
/TC3:0 I/O
A(L)
H(Z/Q)
R(Z)
END OF PROCESS/TERMINA L COUNT can be programmed as either an input
(EOP3:0
) or output (TC3:0), but not both. Each pin is individually programmable.
When programmed as an input, EOPx
causes termination of a current DMA transfer
for the channel that corresponds to the EOPx
pin. EOP0 corresponds to channel 0,
EOP1
corresponds to channel 1, etc. When a channel is configured for source
and
destination chaining, the EOP pin for that channel causes termination of only the
current buffer transferred and causes the next buffer to be transferred. EO P 3:0
are
asynchronous inputs.
When programmed as an output, the channel’s TCx
pin indicates that the channel
byte count has reached 0 and a DMA has terminated. TCx
is driven with the same
timing as DACKx
during the last DMA transfer for a buffer. If the last bus request is
executed as multiple bus accesses, TCx
stays asserted for the entire bus request.
XINT7:0
I
A(E/L)
H(Z)
R(Z)
EXTERNAL INTERRUP T PINS caus e interrupts to be requested. These pins can
be configured in three modes:
Dedicated Mode: each pin is a dedicated external interrupt source. Dedicated
inputs can be individually programmed to be level (low) or edge (falling) activated.
Expanded M ode: the eight pins act together as an 8-bit vectored interrupt source.
The interrupt pins in this mode are level activated. Since the interrupt pins are active
low, the vector number requested is the 1’s complement of the positive logic value
place on the port. This eliminates glue logic to interface to combinational priority
encoders which output negative logic.
Mixed Mode: XINT7:5
are dedicated sources and XINT4:0 act as the five most
significant bits of an expanded mode vector. The least significant bits are set to 010
internally.
NMI
I
A(E)
H(Z)
R(Z)
NON-MASKABLE INTER RUPT causes a non-maskable interrupt event to occur.
NMI
is the highest priority interrupt recognized. NMI is an edge (falling) activated
source.
80960CF-40, -33, -25, -16 A
12
PRELIMINARY
3.3 80960CF Mechanical Data
3.3.1 80960CF PGA PINOUT
Figure 2 depicts the complete 80960CF PGA pinout
as viewed from the top side of the component (i.e.,
pins facing down). Figure 3 shows the complete
80960CF PGA pinout as viewed from the pin-s ide of
the package (i.e., pins facing up).
Table 5 lists the 80960CF pin names and package
location in signal order; Table 6 lists the pin names
and package location in pin order. See Section 4. 0,
ELECTRICAL SPECIFICATIONS for specifications
and recommended connections.
Figure 2. 80960CF PGA Pinout—View from Top (Pins Facing Down)
D5D7D8D9D11D12D13D15D16D17D19D21D24D25
D2D4D6V
CC
D10V
CC
V
CC
D14V
CC
D18D20D23D27D29
NCD0V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
CC
D22D31READY D26
D28
BTERM
HOLDA
D30HOLDBE3
V
CC
ADSBE2
V
SS
V
CC
BE1
V
SS
V
CC
BLAST
V
SS
BE0DEN
V
SS
V
CC
W/R
V
SS
V
CC
DT/R
A29LOCK
SUPWAIT DMA
A28
A30BREQD/C
D3
D1
ONCE
NC
NC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
CLKIN
CLKMODE
V
SS
BOFF
STEST
NC
NC
DREQ0
DREQ2
V
CC
DACK0
VCC
V
CCPLL
V
CC
PCLK2
PCLK1
V
CC
NC
FAIL
NC
NC
NC
DREQ1
DREQ3
DACK1
DACK2
DACK3
EOP/TC0
EOP/TC2
EOP/TC3
EOP/TC1
V
SS
A2
V
CC
A22A25
A20 V
SS
A3A5
NMI
V
CC
V
SS
V
SS
V
SS
VSSV
SS
A24A31 A26
A4V
CC
A6A8A9A10A11A12A14A15A17A18
V
CC
V
CC
V
CC
A13V
CC
A16A19A21A23A27 A7 XINT6
XINT7
XINT4
XINT3
XINT5
XINT0
RESET
XINT2
XINT1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
ABCDEFGHJKLMNPQRS
F_CA002A
ABCDEFGHJKLMNPQRS
PRELIMINARY
13
A 80960CF-40, -33, -25, -16
Figure 3. 80960CF PGA Pinout — View from Bottom (Pins Faci ng Up)
D5 D7 D8 D9 D11 D12 D13 D15 D16 D17 D19 D21 D24 D25
D2 D4 D6 V
CC
D10 VCCVCCD14 VCCD18 D20 D23 D27 D29
NC D0 V
CCVSSVSSVSSVSSVSSVSSVCC
D22 D31 READYD26
D28 BTERM
HOLDA
D30 HOLD BE 3
VCCADS BE2
VSSVCCBE1
VSSVCCBLAST
V
SS
BE0 DEN
VSSVCCW/R
VSSVCCDT/R
A29 LOCK
SUP WAITDMA
A28
A30 BREQ D/C
D3
D1
ONCE
NC
NC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
CLKIN
CLK MODE
V
SS
BOFF
STEST
NC
NC
DREQ0
DREQ2
V
CC
DACK0
VCC
V
CCPLL
V
CC
PCLK2
PCLK1
V
CC
NC
FAIL
NC
NC
NC
DREQ1
DREQ3
DACK1
DACK2
DACK3
EOP/TC0
EOP/TC2
EOP/TC3
EOP/TC1
V
SS
A2
V
CC
A22 A25
A20V
SS
A3 A5
NMI
VCCV
SS
VSSV
SS
V
SS
V
SS
A24 A31A26
A4 V
CC
A6 A8 A9 A10 A11 A12 A14 A15 A17 A18
V
CCVCCVCC
A13 VCCA16 A19 A21 A23 A27A7XINT6
XINT7
XINT4
XINT3
XINT5
XINT0
RESET
XINT2
XINT1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
F_CA003A
ABCDEFGHJKLMNPQRS
ABCDEFGHJKLMNPQRS
Metal Lid
14
PRELIMINARY
80960CF-40, -33, -25, -16 A
Table 5. 80960CF PGA Pinout — In Signal Order
Address Bus Data Bus Bus Control Processor Control I/O
Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin
A31 S15 D31 R3 BE3
S5 RESET A16 DREQ3 A7
A30 Q13 D30 Q5 BE2
S6 DREQ2 B6
A29 R14 D29 S2 BE1
S7 FAIL A2 DREQ1 A6
A28 Q14 D28 Q4 BE0
R9 DREQ0 B5
A27 S16 D27 R2 STEST B2
A26 R15 D26 Q3 W/R
S10 DACK3 A10
A25 S17 D25 S1 ONCE
C3 DACK2 A9
A24 Q15 D24 R1 ADS
R6 DACK1 A8
A23 R16 D2 3 Q2 CLKIN C13 DACK0
B8
A22 R17 D22 P3 READY
S3 CLKMODE C14
A21 Q16 D21 Q1 BTERM
R4 PLCK 1 B14 EOP/TC3 A14
A20 P15 D20 P2 PLCK2 B13 EOP
/TC2 A13
A19 P16 D19 P1 WAIT
S12 EOP/TC1 A12
A18 Q17 D18 N2 B LAS T
S8 V
SS
EOP/TC0 A11
A17 P17 D17 N1
Location
A16 N16 D16 M1 DT/R S11 C7, C8, C9, C10, C11,
C12, F15, G3, G15,
H3, H15, J3, J15, K3,
K15, L3, L15, M3, M15,
Q7, Q8, Q9, Q10, Q11
XINT7
C17
A15 N17 D15 L1 DEN
S9 XINT6 C16
A14 M17 D14 L2 XINT5
B17
A13 L16 D13 K1 LOCK S14 XINT4
C15
A12 L17 D12 J1 XINT3
B16
A11 K17 D11 H1 V
CC
XINT2 A17
A10 J17 D10 H2 HOLD R5
Location
XINT1 A15
A9 H 17 D9 G1 HOLDA S4 B7, B9, B11, B12, C6,
E15, F3, F16, G2, H16,
J2, J16, K2, K16, M2,
M16, N3, N15, Q6, R7,
R8, R10, R11
XINT0
B15
A8 G 17 D8 F1 BREQ R13
A7 G 16 D7 E1 NMI
D15
A6 F1 7 D6 F2 D/C
S13
A5 E17 D5 D1 DMA
R12
A4 E16 D4 E2 SUP
Q12 V
CCPLL
B10
A3 D17 D3 C1 No Connect
A2 D16 D2 D2 BOFF
B1
Location
D1 C2 A1, A3, A4, A5, B3, B4,
C4, C5, D3
D0 E3
PRELIMINARY
15
A 80960CF-40, -33, -25, -16
Table 6. 80960CF PGA Pinout — In Pin Order
Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal
A1 NC C1 D3 F17 A6 M15 V
SS
R3 D31
A2 FAIL
C2 D1 G1 D9 M16 V
CC
R4 BTERM
A3 NC C3 ONCE G2 V
CC
M17 A14 R5 HOLD
A4 NC C4 NC G3 V
SS
N1 D17 R6 ADS
A5 NC C5 NC G15 V
SS
N2 D18 R7 V
CC
A6 DREQ1 C6 V
CC
G16 A7 N3 V
CC
R8 V
CC
A7 DREQ3 C7 V
SS
G17 A8 N15 V
CC
R9 BE0
A8 DACK1 C8 V
SS
H1 D11 N16 A16 R10 V
CC
A9 DACK2 C9 V
SS
H2 D10 N17 A15 R11 V
CC
A10 DACK3 C10 V
SS
H3 V
SS
P1 D19 R12 DMA
A11 EOP/TC0 C11 V
SS
H15 V
SS
P2 D20 R13 BREQ
A12 EOP/TC1
C12 V
SS
H16 V
CC
P3 D22 R14 A29
A13 EOP/TC2
C13 CLKIN H17 A9 P15 A20 R15 A26
A14 EOP/TC3
C14 CLKMODE J1 D12 P16 A19 R16 A23
A15 XINT1
C15 XINT4 J2 V
CC
P17 A17 R17 A22
A16 RESET
C16 XINT6 J3 V
SS
Q1 D21 S1 D25
A17 XINT2
C17 XINT7 J15 V
SS
Q2 D23 S2 D29
B1 BOFF
D1 D5 J16 V
CC
Q3 D26 S3 READY
B2 STEST D2 D2 J17 A10 Q4 D28 S4 HOLDA
B3 NC D3 NC K1 D13 Q5 D30 S5 BE3
B4 NC D15 NMI K2 V
CC
Q6 V
CC
S6 BE2
B5 DREQ0 D16 A 2 K3 V
SS
Q7 V
SS
S7 BE1
B6 DREQ2 D17 A 3 K15 V
SS
Q8 V
SS
S8 BLAST
B7 V
CC
E1 D7 K16 V
CC
Q9 V
SS
S9 DEN
B8 DACK0 E2 D 4 K17 A11 Q10 V
SS
S10 W/R
B9 V
CC
E3 D0 L1 D15 Q11 V
SS
S11 DT/R
B10 V
CCPLL
E15 V
CC
L2 D14 Q12 SUP S12 WAIT
B11 V
CC
E16 A4 L3 V
SS
Q13 A30 S13 D/C
B12 V
CC
E17 A5 L15 V
SS
Q14 A28 S14 LOCK
B13 PCLK2 F1 D8 L16 A13 Q15 A24 S15 A31
B14 PCLK1 F2 D6 L17 A12 Q16 A21 S16 A27
B15 XINT0
F3 V
CC
M1 D16 Q17 A18 S17 A25
B16 XINT3
F15 V
SS
M2 V
CC
R1 D24
B17 XINT5
F16 V
CC
M3 V
SS
R2 D27
16
PRELIMINARY
80960CF-40, -33, -25, -16 A
3.3.2 80960CF PQFP Pinout (80960CF-33, -25, -16 Only)
Tables 7 and 8 list the 80960CF pin names with package location. Figure 4 shows the 80960CF PQFP pinout
as viewed from the top side. See Section 4.0, ELEC TRI CAL SPECIFICATIONS for specifications and recommended connections.
PRELIMINARY
17
A 80960CF-40, -33, -25, -16
Table 7. 80960CF PQFP Pinout — In Signal Order (80960CF-33, -25, -16 Only)
Address Bus Data Bus Bus Co ntrol Processor Control I/O
Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin
A31 153 D31 186 BE3 176 RESET 91 DREQ3 60
A30 152 D30 187 BE2
175 FAIL 45 DREQ2 59
A29 151 D29 188 BE1
172 STEST 46 DREQ1 58
A28 145 D28 189 BE0
170 ONCE 43 DREQ0 57
A27 144 D27 191 CLKIN 87
A26 143 D26 192 W/R
164 CLKMODE 85 DACK3 65
A25 142 D25 194 PCLK2 74 DACK2
64
A24 141 D24 195 ADS
178 PCLK1 78 DACK 1 63
A23 139 D23 3 V
SS
DACK0 62
A22 138 D22 4 READY
182
Location
A21 137 D21 5 BTERM 184 2, 7, 16, 24, 30, 38,
39, 49, 56, 70, 75,
77, 81, 83, 88, 89,
92, 98, 105, 109,
110, 121, 125, 131,
135, 147, 150, 161,
165, 173, 174, 185,
196
EOP/TC3
69
A20 136 D20 6 EOP/TC2
68
A19 134 D19 8 WAIT
162 EOP/TC1 67
A18 133 D18 9 BLAST
169 EOP/TC0 66
A17 132 D17 10
A16 130 D16 11 DT/R
163 XINT7 107
A15 129 D15 13 DEN
167 V
CC
XINT6 106
A14 128 D14 14
Location
XINT5 102
A13 124 D13 15 LOCK
156 1, 12, 20, 28, 32, 37,
44, 50, 61, 71, 79,
82, 96, 99, 103, 115,
127, 140, 148, 154,
168, 171, 180, 190
XINT4
101
A12 123 D12 17 XINT3
100
A11 122 D11 18 HOLD 181 XINT2
95
A10 120 D10 19 HOLDA 179 XINT1
94
A9 119 D9 21 BREQ 155 XINT0
93
A8 118 D8 22 V
CCPLL
72
A7 117 D7 23 D/C
159 No Connect NMI 108
A6 116 D6 25 DMA
160
Location
A5 114 D5 26 SUP 158 29, 31, 41, 42, 47,
48, 51, 52, 53, 54,
55, 73, 76, 80, 84,
86, 90, 97, 104, 126,
146, 149, 157, 166,
177, 183, 193
A4 113 D4 27
A3 112 D3 33 BOFF
40
A2 111 D2 34
D1 35
D0 36
18
PRELIMINARY
80960CF-40, -33, -25, -16 A
Table 8. 80960CF PQFP Pinout — In Pin Order (80960CF-33, -25, -16 Only)
Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal
1V
CC
34 D2 67 EOP/TC1 100 XINT3 133 A18 166 NC
2V
SS
35 D1 68 EOP/TC2 101 XINT4 134 A19 167 DEN
3 D23 36 D0 69 EOP/TC3 102 XINT5 135 V
SS
168 V
CC
4 D22 37 V
CC
70 V
SS
103 V
CC
136 A20 169 BLA ST
5 D21 38 V
SS
71 V
CC
104 NC 137 A21 170 BE0
6 D20 39 V
SS
72 V
CCPLL
105 V
SS
138 A22 171 V
CC
7VSS40 BOFF 73 NC 106 XINT6 139 A23 172 BE1
8 D19 41 NC 74 PCLK2 107 XINT7 140 V
CC
173 V
SS
9 D18 42 NC 75 V
SS
108 NMI 141 A 24 174 V
SS
10 D17 43 ONCE 76 NC 109 V
SS
142 A25 175 BE2
11 D16 44 V
CC
77 V
SS
110 V
SS
143 A26 176 BE3
12 V
CC
45 FAIL 78 PCLK1 111 A2 144 A27 177 NC
13 D15 46 STEST 79 V
CC
112 A3 145 A28 178 ADS
14 D14 47 NC 80 NC 113 A4 146 NC 179 HOLDA
15 D13 48 NC 81 V
SS
114 A5 147 V
SS
180 V
CC
16 V
SS
49 V
SS
82 V
CC
115 V
CC
148 V
CC
181 HOLD
17 D12 50 V
CC
83 V
SS
116 A6 149 NC 182 READY
18 D11 51 NC 8 4 NC 117 A7 150 V
SS
183 NC
19 D10 52 NC 85 CLKMODE 118 A8 151 A29 184 BTERM
20 V
CC
53 NC 86 NC 119 A9 152 A30 185 V
SS
21 D9 54 NC 87 CLKIN 120 A10 153 A31 186 D31
22 D8 55 NC 88 V
SS
121 V
SS
154 V
CC
187 D30
23 D7 56 V
SS
89 V
SS
122 A11 155 BREQ 188 D29
24 V
SS
57 DREQ0 90 NC 123 A12 156 L OCK 189 D28
25 D6 58 DREQ1
91 RES ET 124 A13 157 NC 190 V
CC
26 D5 59 DREQ2 92 V
SS
125 V
SS
158 SUP 191 D27
27 D4 60 DREQ3
93 XI NT 0 126 NC 159 D/C 192 D26
28 V
CC
61 V
CC
94 XI NT 1 127 V
CC
160 DMA 193 NC
29 NC 62 DACK0
95 XI NT 2 128 A14 161 V
SS
194 D25
30 V
SS
63 DACK1 96 V
CC
129 A15 162 WAIT 195 D24
31 NC 64 DACK2
97 NC 130 A16 163 DT/R 196 V
SS
32 V
CC
65 DACK3 98 V
SS
131 V
SS
164 W/R
33 D3 66 EOP/TC0 99 V
CC
132 A17 165 V
SS
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