Intel Corporation 82371AB Datasheet
E
DATASHEET
ADDENDUM
82371AB (PIIX4) PCI
Timing Specifications
Order Number: 290548-001
ISA IDE Xcelerator
September 1997
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
COPYRIGHT © INTEL CORPORATION, 1997 CG-041493
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions
of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating
to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability,
or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical,
life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 82371AB (PIIX4) may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-4725
or call 1-800-548-4725
E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS
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82371AB (PIIX4) PCI ISA IDE
XCELERATOR FEATURES
Supported Kits for both Pentium and
Pentium
82430TX ISA Kit
82440LX ISA/DP Kit
Multifunction PCI to ISA Bridge
Supports PCI at 30 MHz and 33
Supports PCI Rev 2.1 Specification
Supports Full ISA or Extended I/O
Supports full Positive Decode or
Supports ISA/EIO at 1/4 of PCI
Supports Both Mobile and Desktop
Deep Green Environments
3.3V Operation With 5V Tolerant
Ultra-Low Power for Mobile
Power-On Suspend and Soft-OFF
All Registers Readable/Restorable
Power Management Logic
Global and Local Device
Suspend/Resume Logic
Supports Thermal Alarm
Support for External
Full Support for Advanced
Integrated IDE Controller
Independent Timing of Up to
PIO Mode 4 Transfers Up to
Pro Microprocessors
MHz
(EIO) Bus
Subtractive Decode of PCI
Frequency
Buffers
Environments
for Desktop Environment
for Proper Resume From 0V
Suspend
Management
Microcontroller
Configuration and Power Interface
(ACPI) Specification and OS
Directed Power Management
4 Drives
14 Mbytes/sec
Supports “Ultra DMA/33”
Synchronous DMA Mode Transfers
Up to 33 Mbytes/sec
Integrated 8 x 32-Bit Buffer for IDE
PCI Burst Transfers
Supports Glue-Less “Swap-Bay”
Option With Full Electrical Isolation
Enhanced DMA Controller
Two 82C37 DMA Controllers
Supports PCI DMA With 3 PC/PCI
Channels and Distributed DMA
Protocols (Simultaneously)
Fast Type-F DMA for Reduced PCI
Bus Usage
Interrupt Controller Based on Two
82C59
15 interrupt support
Independently Programmable for
Edge/Level Sensitivity
Supports Optional I/O APIC
Serial Interrupt Input
Timers based on 82C54
System Timer, Refresh Request,
Speaker Tone Output
USB
Two USB 1.0 Ports for Serial
Transfers at 12 or 1.5 Mbit/sec
Supports Legacy Keyboard and
Mouse Software With USB-Based
Keyboard and Mouse
Supports UHCI Design Guide
Revision 1.1 Interface
SMBus
Host interface Allows CPU to
Communicate via SMBus
Slave Interface Allows External
SMBus Master to Control Resume
Events
Real-Time Clock
256-Byte Battery-Back CMOS
SRAM
Includes Date Alarm
Two 8-Byte Lockout Ranges
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Microsoft Windows* 95 Compliant 324 mBGA Package
REFERENCE INFORMATION: The information in this document is provided as a supplement to the standard
package datasheets published for the Intel 82371AB (PIIX4) PCI ISA IDE Xcelerator. Please refer to the
standard package datasheet (order number 290562 for the PIIX4) for product information and specifications
not found in this document.
NOTICE: This document contains information on products in the sampling and initial production phases of
development. The specifications are subject to change without notice. Verify with your local Intel Sales office
that you have the latest datasheet before finalizing a design.
The 82371AB (PIIX4) may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
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1.0. INTRODUCTION............................................................................................................................... 5
2.0. ELECTRICAL CHARACTERISTICS...................................................................................................5
2.1. Absolute Maximum Ratings............................................................................................................5
2.2. D.C. Characteristics ......................................................................................................................6
2.3. A.C. Characteristics .................................................................................................................... 10
2.4. Clock, Reset, ISA Bus, X-Bus and Host Timing Diagrams ............................................................. 29
2.5. PCI Timing Diagrams................................................................................................................... 48
2.6. IDE Timing Diagrams................................................................................................................... 51
2.7. USB Timing Diagrams.................................................................................................................. 53
2.8. IOAPIC Timing Diagrams............................................................................................................. 54
2.9. SMBus Timing Diagrams.............................................................................................................. 55
2.10. Ultra DMA/33 Timing Diagrams .................................................................................................. 56
FIGURES
Figure 1. Test Load ............................................................................................................................ 29
Figure 2. Clock Timing........................................................................................................................ 29
Figure 3. Reset Inactive Timing........................................................................................................... 30
Figure 4. Reset Active Pulse Width..................................................................................................... 30
Figure 5. SMI#, EXTSMI# and STPCLK# Timing.................................................................................. 31
Figure 6. Input to PCICLK Setup/Hold Times ....................................................................................... 31
Figure 7. HCLKIN to Output Valid Delay .............................................................................................. 32
Figure 8. 8-Bit ISA Memory Slave Timing (PIIX4 as Master)................................................................. 32
Figure 9. 16-Bit ISA Memory Slave Timing (PIIX4 as Master)............................................................... 33
Figure 10. 8-Bit ISA I/O Slave Timing (PIIX4 as Master) ...................................................................... 34
Figure 11. 16-Bit I/O Slave Timing (PIIX4 as Master)........................................................................... 35
Figure 12. ISA Master Accessing PCI Memory Timing......................................................................... 36
Figure 13. ISA Master Accessing PIIX4 Register Timing...................................................................... 37
Figure 14. NMI Timing........................................................................................................................ 37
Figure 15. Interrupt Timing.................................................................................................................. 38
Figure 16. ISA Master Miscellaneous Timing....................................................................................... 38
Figure 17. ISA Master Data Swap Timing ............................................................................................ 39
Figure 18. DMA Compatible Timing (Memory Read)............................................................................. 40
Figure 19. DMA Compatible Timing (Memory Write)............................................................................. 41
Figure 20. DMA Compatible Timing (Data Swap).................................................................................. 42
Figure 21. DMA Type F Timing............................................................................................................ 43
Figure 22. PIIX4-Initiated Refresh Timing ............................................................................................ 44
Figure 23. ISA Master-Initiated Refresh Timing.................................................................................... 45
Figure 24. PIIX4 and ISA Master Access to X-Bus Timing.................................................................... 46
CONTENTS
PAGE
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Figure 25. Coprocessor Error and Mouse Support Timing.....................................................................47
Figure 26. Real Time Clock Timing (RTCALE Generation)....................................................................47
Figure 27. Speaker Timing ..................................................................................................................48
Figure 28. Propagation Delay ..............................................................................................................48
Figure 29. Valid Delay From Rising Clock Edge ...................................................................................49
Figure 30. Setup and Hold Times.........................................................................................................49
Figure 31. Float Delay.........................................................................................................................50
Figure 32. Pulse Width........................................................................................................................50
Figure 33. Output Enable Delay...........................................................................................................50
Figure 34. IDE PIO Mode....................................................................................................................51
Figure 35. IDE Multiword DMA Mode...................................................................................................52
Figure 36. Data Signal Rise and Fall Time............................................................................................53
Figure 37. Data Jitter..........................................................................................................................53
Figure 38. EOP Width Timing..............................................................................................................54
Figure 39. PIIX4 to IOAPIC Timing ......................................................................................................54
Figure 40. SMBus Timing....................................................................................................................55
Figure 41. SMBus Timeout Timing.......................................................................................................55
Figure 42. Ultra DMA/33 Drive Initiating a DMA Burst for a Read Command..........................................56
Figure 43. Ultra DMA/33 Sustained Synchronous DMA Burst................................................................57
Figure 44. Ultra DMA/33 Sustained Synchronous DMA Burst................................................................58
Figure 45. Ultra DMA/33 Host Terminating a DMA Burst During a Write Command................................58
TABLES
Table 1. Package Thermal Resistance...................................................................................................5
Table 2. DC Characteristics ..................................................................................................................6
Table 3. DC Characteristic Signal Association .......................................................................................8
Table 4. DC Current Characteristics......................................................................................................9
Table 5. Clock/Reset Timings..............................................................................................................10
Table 6. ISA Bus and X-Bus Timings ...................................................................................................12
Table 7. PCI Interface Timing..............................................................................................................23
Table 8. PCI Bus IDE Timing...............................................................................................................24
Table 9. Universal Serial Bus Timing...................................................................................................26
Table 10. IOAPIC Bus Timing..............................................................................................................27
Table 11. SMBUS Timing....................................................................................................................27
Table 12. Serial IRQ Timing ................................................................................................................28
Table 13. Ultra DMA/33 Timing............................................................................................................28
Table 14. A.C. Test Loads...................................................................................................................29
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1.0. INTRODUCTION
This document contains the Electrical and the Thermal Specification (ETS) for the 82371AB (PIIX4). PIIX4 is
a multi-function PCI device implementing a PCI-to-ISA bridge function, a PCI IDE function, a Universal Serial
Bus Host/Hub function, and a Power Management function.
The contents of this document are based on simulation and parametric data. This information may be
modified as more data is available.
REFERENCES
The ETS assumes that the reader is familiar with the following documents:
• 82371AB PIIX4 External Design Specification
• Universal Serial Bus Specification
• Universal Host Controller Interface (UHCI) Design Guide
• System Management Bus Specification
• Serialized IRQ Support for PCI Systems Specification
• Distributed DMA Support for PCI Systems Specification
2.0. ELECTRICAL CHARACTERISTICS
2.1. Absolute Maximum Ratings
Case Temperature under Bias ............................................0oC to +85oC
Storage Temperature .........................................................-55oC to +150oC
Voltage on Any Pin with Respect to Ground ........................-0.3 to V
3.3V Supply Voltage with Respect to Vss............................-0.3 to +4.6V
5.0V Supply Voltage with Respect to Vss (V
Maximum Power Dissipation ..............................................1.0W
WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent
The 82371AB PIIX4 (BGA) is designed for operation at case temperatures between 0oC and 85oC. The
thermal resistances of the package are given in Table 1.
Thetaja (oC/Watt) 29 24.5
Thetajc (oC/Watt) 9.0
CC + 0.3V
REF).................-0.3 to +5.5V
damage. These are stress ratings only. Operating beyond the “Operating Conditions” is not
recommended and extended exposure beyond “Operating Conditions” may affect reliability.
Table 1. Package Thermal Resistance
Parameter Air Flow
Meters/Second (Linear Feet per Minute)
0 (0) 1.0 (196.9)
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2.2. D.C. Characteristics
Table 2. DC Characteristics
Functional Operating Range (V
Symbol Parameter Min Max Unit Notes
VCC(RTC) Battery Voltage 2.0 3.6 V
VCC(SUS) Standby Voltage 3.0 3.6 V
VIL1 Input Low Voltage -0.5 0.3 VCC V 1
VIH1 Input High Voltage 0.5 VCC VCC + 0.5 V 1
VIL2 Input Low Voltage -0.3 0.6 V 1
VIH2 Input High Voltage 1.4 VCC + 0.3 V 1
VIL3 Input Low Voltage -0.5 0.8 V 1
VIH3 Input High Voltage 2.0 VCC5 + 0.5 V 1
VOL1 Output Low Voltage 0.4 V 1
VOH1 Output High Voltage VCC - 0.5 V 1
VOL2 Output Low Voltage 0.3 V 1, 2
VOH2 Output High Voltage 2.8 3.6 V 1, 2
VOL3 Output Low Voltage 0.5 V 1
VOH3 Output High Voltage VCC - 0.5 V 1
VOL4 Output Low Voltage 0.45 V 1
VOH4 Output High Voltage VCC - 0.5 V 1
VDI Differential Input Sensitivity 0.2 V |(USBPx+, USBPx-)|
VCM Differential Common Mode Range 0.8 2.5 V Includes VDI
VSE Single Ended Rcvr Threshold 0.8 2.0 V
IOL1 Output Low Current 4 mA 1, @ VOL1
IOH1 Output High Current -1 mA 1, @ VOH1
IOL2 Output Low Current 10 mA 1, @ VOL4
IOH2 Output High Current -3 mA 1, @ VOH4
IOL3 Output Low Current 3 mA 1, @ VOL1
IOH3 Output High Current -2 mA 1, @ VOH1
IOL4 Output Low Current 6 mA 1, @ VOL1
IOH4 Output High Current -2 mA 1, @ VOH1
IOL5 Output Low Current 2 mA 1, @ VOL2
IOH5 Output High Current -0.25 mA 1, @ VOH2
REF=5V ±±5%, VCC=3.3V ±±0.3V, TCASE=0°C to +85°C)
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Table 2. DC Characteristics
Functional Operating Range (V
Symbol Parameter Min Max Unit Notes
IOL6 Output Low Current 6 mA 1, @ VOL1
IOH6 Output High Current -2 mA 1, @ VOH1
IOL7 Output Low Current 7 mA 1, @ VOL1
IOH7 Output High Current -2 mA 1, @ VOH1
IOL8 Output Low Current 11 mA 1, @ VOL3
IOH8 Output High Current -2 mA 1, @ VOH3
ILI1 Input Leakage Current ±1 µA
ILI2 Hi-Z State Data Line Leakage -10 +10 µA (0V< VIN< 3.3V)
CIN Input Capacitance 12 pF FC=1 MHz
COUT Output Capacitance 12 pF FC=1 MHz
CI/O I/O Capacitance 12 pF FC=1 MHz
CL Crystal Load Capacitance 7.5 15 pF
NOTES:
1. Refer to Table 3. for the signals associated with this specification.
OL2 assumes RL of 1.5 kohms to 3.6V and VOH2 assumes RL of 15 kohms to GND.
2. V
REF=5V ±±5%, VCC=3.3V ±±0.3V, TCASE=0°C to +85°C)
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Table 3. DC Characteristic Signal Association
Symbol Associated Signals
VIL1/VIH1 VREF=5.0V: (all 3.3V only inputs except SMBCLK & SMBDATA)
PWROK, RSMRST#, RTCX1, TEST, BATLOW#, CONFIG[1:2], EXTSMI#, GPI[1], IRQ8#,
LID, RI#, SMBALERT#, PWRBTN#, USBP[1:0]+, USBP[1:0]-, FERR#
REF=3.3V: (all inputs except SMBCLK & SMBDATA)
V
PWROK, RSMRST#, RTCX1, TEST, BATLOW#, CONFIG[1:2], EXTSMI#, GPI[1], IRQ8#,
LID, RI#, SMBALERT#, PWRBTN#, USBP[1:0]+, USBP[1:0]-, FERR#, AD[31:0],
C/BE[3:0]#, CLKRUN#, DEVSEL#, FRAME#, IDSEL, IRDY#, PHLDA#, SERR#, STOP#,
TRDY#, IOCHK#, IOCHRDY, IOCS16#, IOR#, IOW#, LA[23:17], MEMCS16#, MEMR#,
MEMW#, REFRESH#, SA[19:0], SBHE#, SD[15:0], ZEROWS#, A20GATE, RCIN#,
DREQ[0:3, 5:7], REQ[A:C]#, APICREQ#, IRQ[1, 3:7, 9:12, 14:15], PIRQ[A:D], SERIRQ,
CLK48, PCICLK, OSC, PDD[15:0], PDDREQ, PIORDY, SDD[15:0], SDDREQ, SIORDY,
OC[1:0]#, PCIREQ[A:D],THRM#
VIL2/VIH2 SMBCLK, SMBDATA
VIL3/VIH3 VREF=5.0V: (all 5V tolerant inputs)
AD[31:0], C/BE[3:0]#, CLKRUN#, DEVSEL#, FRAME#, IDSEL, IRDY#, PHLDA#, SERR#,
STOP#, TRDY#, IOCHK#, IOCHRDY, IOCS16#, IOR#, IOW#, LA[23:17], MEMCS16#,
MEMR#, MEMW#, REFRESH#, SA[19:0], SBHE#, SD[15:0], ZEROWS#, A20GATE,
RCIN#, DREQ[0:3, 5:7], REQ[A:C]#, APICREQ#, IRQ[1, 3:7, 9:12, 14:15], PIRQ[A:D],
SERIRQ, CLK48, PCICLK, OSC, PDD[15:0], PDDREQ, PIORDY, SDD[15:0], SDDREQ,
SIORDY, OC[1:0]#, PCIREQ[A:D],THRM#
VOL1/VOH1 PDA[2:0], PDCS1#, PDCS3#, PDD[15:0], PDDACK#, PDIOR#, PDIOW#, SDA[2:0],
VOL2/VOH2 USBP[1:0]+, USBP[1:0]-
VOL3/VOH3 SLP#
VOL4/VOH4 ISA/EIO Output Signals: AEN, BALE, IOCHRDY, IOR#, IOW#, LA[23:17], MEMCS16#,
IOL1/IOH1 IDE Output Signals: PDA[2:0], PDCS1#, PDCS3#, PDD[15:0], PDDACK#, PDIOR#,
IOL2/IOH2 ISA/EIO Output Signals: AEN, BALE, IOCHRDY, IOR#, IOW#, LA[23:17], MEMCS16#,
SDCS1#, SDCS3#, SDD[15:0], SDDACK#, SDIOR#, SDIOW#, CPU_STP#, EXTSMI#, ZZ,
GPO8, PCI_STP#, SMBCLK, SMBDATA, SUS[A:C]#, SUS_STAT[1:2]#, A20M#, CPURST,
IGNNE#, INIT, INTR, NMI, SMI#, STPCLK#, BIOSCS#, KBCCS#, MCCS#, PCS0#, PCS1#,
RTCALE, RTCCS#, XDIR#, XOE#, SUSCLK, RTCX2, SMBCLK, SMBDATA, APICACK#,
APICCS#, IRQ[0, 8], SPKR, GNT[A:C], GPO[0, 8, 27, 28, 30], IRQ9OUT#, AD[31:0],
C/BE[3:0]#, CLKRUN#, DEVSEL#, FRAME#, IRDY#, PAR, PCIRST#, PHOLD#, SERR#,
STOP#, TRDY#, SERIRQ
MEMR#, MEMW#, REFRESH#, RSTDRV, SA[19:0], SBHE#, SD[15:0], SMEMR#,
SMEMW#, SYSCLK, DACK[0:3, 5:7]#, TC
PDIOW#, SDA[2:0], SDCS1#, SDCS3#, SDD[15:0], SDDACK#, SDIOR#, SDIOW#
MEMR#, MEMW#, REFRESH#, RSTDRV, SA[19:0], SBHE#, SD[15:0], SMEMR#,
SMEMW#, SYSCLK, DACK[0:3, 5:7]#, TC
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Table 3. DC Characteristic Signal Association
Symbol Associated Signals
IOL3/IOH3 Power Management Signals: CPU_STP#, EXTSMI#, ZZ, GPO8, PCI_STP#, SMBCLK,
IOL4/IOH4 PCI Bus Signals: AD[31:0], C/BE[3:0]#, CLKRUN#, DEVSEL#, FRAME#, IRDY#, PAR,
IOL5/IOH5 USB Signals: USBP[1:0]+, USBP[1:0]-
IOL6/IOH6 SMI#, STPCLK#
IOL7/IOH7 INIT#
IOL8/IOH8 SLP#
Symbol Parameter Typ Max Unit Notes
ICC(3V) VCC Supply Current 110 155 mA
ICC(SUS)ONSuspend Well Supply Current—Full On 3 5 mA
SMBDATA, SUS[A:C]#, SUS_STAT[1:2]#
CPU Interface Signals: A20M#, CPURST, IGNNE#, INTR, NMI
X-Bus Interface Signals: BIOSCS#, KBCCS#, MCCS#, PCS0#, PCS1#, RTCALE,
RTCCS#, XDIR#, XOE#, SUSCLK, RTCX2
Other Signals: SMBCLK, SMBDATA, APICACK#, APICCS#, IRQ[0, 8], SPKR, GNT[A:C],
GPO[0, 8, 27, 28, 30], IRQ9OUT#
PCIRST#, PHOLD#, SERR#, STOP#, TRDY#, SERIRQ
Table 4. DC Current Characteristics
Functional Operating Range (V
REF=5V ±±5%, VCC=3.3V ±±0.3V, TCASE=0°C to +85°C)
ICC(SUS)
POS/STR
ICC(SUS)
STD/Soff
Icc(RTC) Battery Standby Current 6 8 µA VCC(RTC)=3.0V
Suspend Well Supply Current—Power On
Suspend or Suspend to RAM
Suspend Well Supply Current—Suspend to
Disk or Soft Off
30 150 µA
9 150 µA
Mech Off State
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2.3. A.C. Characteristics
Table 5. Clock/Reset Timings
Functional Operating Range (V
Sym Parameter Min Max Units Notes Figure
PCI Clock Timings
PCICLK
t1a Period 30 33.3 ns 2
t1b High Time 12.0 ns 2
t1c Low Time 12.0 ns 2
t1c Rise Time 3.0 ns 2
t1d Fall Time 3.0 ns 2
ISA Clock Timings
SYSCLK
t1f Period 120 133.3 ns 2
t1g High Time 49 ns 2
t1h Low Time 49 ns 2
t1i Rise Time 4 ns 2
t1j Fall Time 4 ns 2
Oscillator Clock Timings
OSC
t1l OSC Period 67 70 ns 2
t1m High Time 20 2
t1n Low Time 20 ns 2
USB Clock Timings
f
clk48
t1p Frequency Tolerance ±2500 ppm 1 2
t1q High Time 7 ns 2
t1r Low Time 7 ns 2
t1s Rise Time 1.2 ns 2
t1t Fall Time 1.2 ns 2
f
susclk
t1v High Time 10 µs
t1w Low Time 10 µs
Operating Frequency 48 MHz
Suspend Clock Timings
SUSCLK Operating Frequency 32 KHz
REF=5V ±±5%, VCC=3.3V ±±0.3V, TCASE=0°C to +85°C)
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Table 5. Clock/Reset Timings
Functional Operating Range (V
Sym Parameter Min Max Units Notes Figure
SMBus Clock
f
smb
t2b High Time 4.0 50 µs 40
t2c Low Time 4.7 µs 40
t2d Clock/Data Rise Time 1000 ns 40
t2e Clock/Data Fall Time 300 ns 40
t2f PCIRST#, RSTDRV Driven Inactive After
t2g CPURST, PCIRST#, RSTDRV Active Pulse
t2h CPURST Driven Inactive After PCIRST# is
t2i CPURST Valid Delay from PCICLK Rising 2 25 ns 29
t2j PWROK, RSMRST# Rise Time 10 ns 3
t3a Valid Delay from PCICLK 2 25 ns 7
t3b Active Pulse Width 3 PCICLK 5
t3c Inactive Pulse Width 4 PCICLK 5
t3d Active Pulse Width 2 PCICLK 5
t3e Inactive Pulse Width 4 PCICLK 5
t3f Valid Setup to PCICLK 10 ns 6
t3g Valid Hold from PCICLK 4 ns 6
t3h Valid Delay from PCICLK 2 25 ns 7
t3i STPCLK# Inactive Pulse Width 5 PCICLK 5
NOTES:
1. The USBCLK is a 48 MHz that expects a 40/60% duty cycle.
2. The maximum high time (t2b Max) provide a simple guaranteed method for devices to detect bus idle
3. t2j is measured as a transition time through the threshold region Vol=0.8V and Voh=2.0V.
SMCLK Operating Frequency 10 16 KHz
RESET TIMINGS
SUS_STATx# is Driven Inactive.
Width. Initiated via the RC Register.
Driven Inactive.
SMI#
EXTSMI#
STPCLK#
conditions.
REF=5V ±±5%, VCC=3.3V ±±0.3V, TCASE=0°C to +85°C)
1 RTCCLK 3
1 ms 4
1 RTCCLK 3
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Table 6. ISA Bus and X-Bus Timings
Functional Operating Range (V
Sym Parameter Min Max Units Type Size Notes Figure
PIIX4 AS MASTER TIMINGS
BALE
t4a BALE Pulse Width 50 ns M,I/O 8,16 8,9,10,
t4b BALE Driven Active from MEMx#, Iox#
Inactive
LA[23:17]
t5a LA[23:17] Valid Setup to BALE Inactive 150 ns M 8,16 7 8,9
t5b LA[23:17] Valid Hold from BALE
Inactive
t5c LA[23:17] Valid Setup to MEMx# Active 150 ns M 16 9
t5d LA[23:17] Valid Setup to MEMx# Active 173 ns M 8 8
t5e LA[23:17] Invalid from MEMx# Active 39 ns M 16 9
t5f LA[23:17] Invalid from MEMx# Active 39 ns M 8 8
SA[19:0], SBHE#
t6a SA[19:0], SBHE# Valid Setup to
MEMx# Active
t6b SA[19:0], SBHE# Valid Setup to Iox#
Active
t6c SA[19:0], SBHE# Setup to MEMx#,
Iox# Active
t6d SA[19:0], SBHE# Valid Setup to BALE
Inactive
t6e SA[19:0], SBHE# Valid Hold from
MEMx#, Iox# Inactive
MEMR#, MEMW#, IOR# AND IOW#
t7a MEMx# Active Pulse Width (std) 225 ns M 16 9
t7b Iox# Active Pulse Width (std) 160 ns I/O 16 11
t7c MEMx# Active Pulse Width (nws) 105 ns M 16 1 9
t7d MEMx# or Iox# Active Pulse Width
(std)
t7e MEMx# or Iox# Active Pulse Width
(nws)
t7f MEMx# Inactive Pulse Width 103 ns M 16 9
REF=5V ±±5%, VCC=3.3V ±±0.3V, TCASE=0°C to +85°C)
11
44 ns M,I/O 8,16 8,9,10,
11
26 ns M 8,16 8,9
34 ns M 16 13,15 9
100 ns I/O 16 11
100 ns M,I/O 8 9
37 ns M,I/O 8,16 13,15 8,9,10,
11
41 ns M,I/O 8,16 8,9,10,
11
520 ns M,I/O 8 8,10
160 ns M,I/O 8 1 8,10
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Table 6. ISA Bus and X-Bus Timings
Functional Operating Range (V
Sym Parameter Min Max Units Type Size Notes Figure
t7g MEMx# Inactive Pulse Width 163 ns M 8 8
t7h Iox# Inactive Pulse Width 163 ns I/O 8,16 10,11
t7i MEMx#, Iox# Driven Inactive from
IOCHRDY Active
SMEMR# and SMEMW#
t8a SMEMR# & SMEMW# Propagation
Delay from MEMR# and MEMW#
Read Data
t9a Read Data Driven from MEMR#, IOR#
Active
t9b Read Data Valid Setup to MEMR#,
IOR#
t9c Read Data Valid Hold from MEMR#,
IOR# Inactive
t9d Read Data Tri-Stated from MEMR# and
IOR# Inactive
Write Data
t10a Write Data Valid Setup to MEMW#
Active
Write Data Valid Setup to IOW# Active
Write Data Valid Setup to IOW# Active
t10b Write Data Valid Hold from MEMW#,
IOW# Inactive
t10c Write Data Tri-Stated from MEMW#,
IOW# Inactive
t10d Write Data Driven Valid after Read
MEMR#, IOR# Inactive
MEMCS16#
t11a MEMCS16# Driven Active from
LA[23:17] Valid
t11b MEMCS16# Inactive from LA[23:17]
Valid
t11c MEMCS16# Valid Hold from LA[23:17]
Invalid
REF=5V ±±5%, VCC=3.3V ±±0.3V, TCASE=0°C to +85°C)
120 ns M,I/O 8,16 8,9,10,
16 ns M 8,16 8,9
0 ns M,I/O 8,16 8,9,10,
24 ns M,I/O 8,16 8,9,10,
0 ns M,I/O 8,16 8,9,10,
41 ns M,I/O 8,16 8,9,10,
-40
-40
+23
45 ns M,I/O 8,16 8,9,10,
105 ns M,I/O 8,16 8,9,10,
41 ns M,I/O 8,16 8,9,10,
94 ns M 16 9
91 ns M 8 8
0 ns M 16 9
ns
ns
ns
M,I/O
M,I/O
M,I/O
8,16
8
16
11
11
11
11
11
8,9,10,
11
11
11
11
13
82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS E
PRELIMINARY
Table 6. ISA Bus and X-Bus Timings
Functional Operating Range (V
Sym Parameter Min Max Units Type Size Notes Figure
t11d MEMCS16# Driven Active from
SA[19:2] Valid
IOCS16#
t12a IOCS16# Driven Active from Valid
SA[19:0]
t12b IOCS16# Inactive from Valid SA[19:0] 91 ns I/O 8 10
t12c IOCS16# Valid Hold from SA[19:0]
Invalid
t12d IOCS16# Driven Active from Iox Active 80 ns I/O 16 11
ZEROWS#
t13a ZEROWS# Driven Active from MEMx#
Active
t13b ZEROWS# Driven Active from MEMx#,
Iox# Active
t13c ZEROWS# Driven Active from
LA[23:17] Valid
t13d ZEROWS# Driven Active from
LA[23:17] Valid
ZEROWS#
t13e ZEROWS# Driven Active from
SA[19:0], SBHE# Valid
t13f ZEROWS# Driven Active from
SA[19:0], SBHE# Valid
AEN
t14a AEN Valid Setup to Iox# Driven Active 111 ns I/O 8,16 10,11
t14b AEN Valid Setup to BALE Driven
Inactive
t14c AEN Valid Hold from Iox# Driven
Inactive
IOCHRDY
t15a IOCHRDY Driven Valid from MEMx#,
Iox# Active
t15b IOCHRDY Driven Valid from MEMx#,
Iox# Active
REF=5V ±±5%, VCC=3.3V ±±0.3V, TCASE=0°C to +85°C)
35 ns M 16 9
123 ns I/O 16 11
0 ns I/O 16 11
16 ns M 16 9
80 ns M,I/O 8 8
180 ns M 16 9
300 ns M 8 8
80 ns M 16 9
200 ns M,I/O 8 8,10
111 ns I/O 8,16 10,11
41 ns I/O 8,16 10,11
78 ns M,I/O 16 9,11
366 ns M,I/O 8 8,10
14
E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS
PRELIMINARY
Table 6. ISA Bus and X-Bus Timings
Functional Operating Range (V
Sym Parameter Min Max Units Type Size Notes Figure
t15e IOCHRDY Inactive Pulse Width 0.12 15.6 µs M,I/O 8,16 8,9,10,
PIIX4 AS SLAVE TIMINGS
LA[23:17]
t16a LA[23:17] Valid Setup to MEMx# Active 23 ns M 16 12
SA[19:0],SBHE#
t17a SA[19:0],SBHE# Setup to MEMx#
Active
t17b SA[19:0],SBHE# Setup to Iox# Active 89 ns I/O 8 13
t17c SA[19:0],SBHE# Valid Hold from
MEMx#, Iox# Inactive
MEMR#, MEMW#, IOR#, IOW#
t18a MEMx# Active Pulse Width 214 ns M 16 12
t18b Iox# Active Pulse Width 509 ns I/O 8 13
t18c MEMx# Inactive Pulse Width 92 ns M 16 12
t18d Iox# Inactive Pulse Width 152 ns I/O 8 13
Read Data
t19a Read Data Valid from IOCHRDY
Active
t19b Read Data Valid from IOR# Active 69 ns I/O 8 11 13
t19c Read Data Valid Hold from MEMR#,
IOR# Inactive
t19d Read Data Tri-State from MEMR#,
IOR# Inactive
Write Data
t20a Write Data Valid Setup to MEMW#,
IOW# Active
t20b Write Data Valid Hold from MEMW#,
IOW# Inactive
MEMCS16#
t21a MEMCS16# Driven Active from Valid
LA[23:17]
t21b MEMCS16# Float from Valid LA[23:17] 31 ns M 16 12
REF=5V ±±5%, VCC=3.3V ±±0.3V, TCASE=0°C to +85°C)
11
23 ns M 16 12
30 ns M,I/O 8,16 12,13
69 ns M,I/O 8,16 12,13
0 ns M,I/O 8,16 12,13
55 ns M,I/O 8,16 12,13
-54 ns M,I/O 8,16 12,13
14 ns M,I/O 8,16 12,13
65 ns M 16 12
15
82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS E
PRELIMINARY
Table 6. ISA Bus and X-Bus Timings
Functional Operating Range (V
Sym Parameter Min Max Units Type Size Notes Figure
t21c MEMCS16# Valid Hold from LA[23:17]
Invalid
IOCHRDY
t22a IOCHRDY Inactive from MEMx#, Iox#
Active
t22b IOCHRDY Float from IOCHRDY
Rising
t22c IOCHRDY Inactive Pulse Width 0.12 2.5 µs M,I/O 8,16 12,13
INTERRUPT AND NMI TIMINGS
NMI Timing
t23a SERR#, IOCHK# Active to NMI Driven
Active
Interrupt Timing
t24a IRQx Inactive Pulse Width 100 ns 15
ISA BUS MASTER TIMINGS
DACK#
t26a DACK#, Inactive from DREQ Inactive 240 ns 16
Tri-Stating and Driving the Bus
t27a PIIX4 Tri-States Address, Data, and
Control Signals from DACK#, Active
t27b PIIX4 Drives Address, Data, and
Control Signals from DACK#, Inactive
SMEMR# and SMEMW#
t28a SMEMR# and SMEMW# Active (falling
edge) from MEMR# and MEMW#
Active (falling edge)
t28b SMEMR# and SMEMW# Inactive
(rising edge) from MEMR# and
MEMW# Inactive (rising edge)
DATA SWAP LOGIC TIMING
(ISA MASTER TO ISA SLAVE)
t29a SD[7:0] to SD[15:8] Propagation Delay 26 ns 17
t29b SD[15:8] to SD[7:0] Propagation Delay 26 ns 17
REF=5V ±±5%, VCC=3.3V ±±0.3V, TCASE=0°C to +85°C)
0 ns M 16 12
50 ns M,I/O 8,16 12,13
85 ns M,I/O 8,16 4 12,13
200 ns 14
30 ns 16
71 ns 16
25 ns 16
35 ns 16
16
E 82371AB (PIIX4) PCI ISA IDE XCELERATOR TIMING SPECIFICATIONS
PRELIMINARY
Table 6. ISA Bus and X-Bus Timings
Functional Operating Range (V
Sym Parameter Min Max Units Type Size Notes Figure
t29c PIIX4 Drives Data Bus from IOR#,
IOW#, MEMR# or MEMW# Active
t29d PIIX4 Tri-States Bus from IOR#,
MEMR#, or SMEMR# Inactive
t29e PIIX4 Tri-States Bus from IOW#,
MEMW#, or SMEMW# Inactive
DMA COMPATIBLE TIMINGS
DREQ
t30a DREQ Active Hold from IOR# Active 558 ns 5 19
t30b DREQ Active Hold from IOW# Active 315 ns 5 18
DACK#
t31a DACK# Active to IOR# Active 73 ns 19
t31b DACK# Active to IOW# Active 312 ns 18
t31c DACK# Active Hold from IOR# Inactive 100 ns 19
t31d DACK# Active Hold from IOW# Inactive 155 ns 18
AEN and BALE
t32a AEN Active to Iox# Active 111 ns 18,19
t32b AEN and BALE Inactive from Iox#
Inactive
LA[23:19], SA[19:0], SBHE#
t33a LA[23:19],SA[19:0], SBHE# Valid Setup
to MEMx# Active
t33b LA[23:19],SA[19:0], SBHE# Valid Hold
from MEMx# Inactive
MEMR#, MEMW#, IOR#, IOW#
t34a IOW# and MEMW# Active Pulse Width 465 ns 18,19
t34b MEMR# Active Pulse Width 495 ns 18
t34c IOR# Active Pulse Width 760 ns 19
t34d IOW# Inactive Pulse Width
(continuous)
t34e IOR# Inactive Pulse Width (continuous) 160 ns 19
t34f IOR# Active to MEMW# Active 230 ns 19
t34g MEMR# Active to IOW# Active -26 ns 18
REF=5V ±±5%, VCC=3.3V ±±0.3V, TCASE=0°C to +85°C)
26 ns 2 17
2 55 ns 2,3 17
2 60 ns 2,3 17
41 ns 18,19
99 ns 18,19
51 ns 18,19
465 ns 18
17
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