INTELBRAS IDX80, la-3291 Schematics

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4

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Project Name: PecosII

D D

(IDX80)
PCB Serial Number:

LA-3291

PecosII Schematics Document

C C

Intel Merom Dual Core LV1.33G&1.5G
/Yonah Single Core ULV 1.06G&1.2G + Calistoga GM + ICH7-M

B B

2007-01-08

REV: X0.5

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Cover Sheet

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

153Monday, January 08, 2007

X 0.5

5

4

3

2

1

DC-DC

page 37

D D

VCCP&
CPU_CORE

page 46

Merom Dual Core LV
/Yonah Single Core ULV

Block Diagram

CPU Thermal Sensor
G781F

page 6

Clock Generator
ICS9LPRS325AKLF

page 5

Fan Control x1

page 6

479 uFCBGA CPU

Docking
CRT

page 36

CRT port

FSB

HD#[0..63]HA#[3..31]

CRT CONN.

page 19

DVI CONN

page 18

Hydis

C C

SIM
card

LCD 12.1"
XGA/SXGA+

page 24

Mini Card
WWAN

page 24

DVI Controller
CH7307

LVDS CONN.

page 18

page 17

Mini Card
WLAN

page 24

3.3V 33MHz

SDVO

LVDS port

PCIE BUS

PCIE BUS

PCIE x1

PCI Bus

Intel Calistoga GM

1466 FCBGA

page 9, 10, 11, 12, 13, 14

DMI x4

1.5V

ICH7-M

652 BGA

page 20, 21, 22, 23

page 6, 7, 8

533/667MHz

DDR2

Channel A

SO-DIMM x 1

4 BANK

1.8V 533/667MHz

Channel B

DDR2

SO-DIMM x 1

4 BANK

USB 2.0 48MHz/480Mb
Azalia 3.3V

PATA100

HDD 1.8"

page 24

page 15

page 16

USBPORT0
USBPORT 1
USBPORT 2

USBPORT 3
USBPORT 4
USBPORT 5

USBPORT 6

USBPORT 7

On M/B
On M/B

WWAN

Finger Printer
LLANO DOCK

Travel DOCK

LLANO DOCK

LLANO DOCK

page 32

page 32

page 24

page 36

page 36

page 36

page 36

page 36

B B

CardBus
R5C843

PCMCIA Slot

page 26

express

page 26

card

page 25

SD Socket

page 26

SMSC

page 35

LPC47N217

LPC Bus

Embedded Controller

3.3V 33MHz

ENE KB910L

page 33

TPM

page 32

SLB9635TT

X Bus

Docking
HP&MIC

page 36

ROM DAUGHTER BOARD

page 28

USB 2.0
Controller

Port 0

CardBus

page 25

page 27

Port 1

WLAN

page 24

Port 2

Bluetooth

page 27

Gigabit Lan
88E8053

Transformer
& RJ45

page 29

Docking
RJ45

page 36

A A

SST39VF080

Digitizer

5

4

FIR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Azalia Codec
STAC9220

page 30

AMP & HP &
MIC

page 31

page 34

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

Block Diagram

PecosII-IDX80-LA3291

1

X 0.5

of

253Monday, January 08, 2007

5

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3

2

1

External PCI Devices

DEVICE

D D

IDSEL #

AD20
AD21USB controller

REQ/GNT #

2 A,BCARD BUS

0

PIRQ

E,F,G

Power Management table

Signal +1.8VS

State

+12VALW
+5VALW
+3VALW

+3V_LAN

+1.8V

+5VS
+3VS

+2.5VS
+1.5VS
+0.9VS
+VCCP
+CPU_CORE

Symbol Note

ON

S1

S3

S5 S4/AC

S5 S4/AC don't exist

Note1 : +3V_LAN is ON only with AC power available, otherwise it is OFF.

ON ON

ON note1 ON

ON note1

OFF

ON

OFF

ONONS0

OFF

OFFOFF

OFF

Voltage Rails

: means Digital Ground

C C

: means Analog Ground

: Question Area Mark.(Wait check)

@: means don't stuff, just reserve

DB@: means jsut stuff when Mini-PCI E Debug card function enable
DVI_7307@: means just stuff when use CH7307 controller

DVI_1362@: means just stuff when use Sil1362 controller

9220@: means just populate when mount 9220 on board;
depopulate when mount 9228 on board

9228@: means just populate when mount 9228 on board;

B B

depopulate when mount 9220 on board
LV@: means just populate when mount Merom/Yonah LV DC CPU on board;

depopulate when mount Yonah ULV SC CPU on board

Buffer@: means just populate when buffer generate V_DDR_MCH_REF;
depopulate when 1.8V divider generate V_DDR_MCH_REF

1.8_divider@: means just populate when 1.8V divider generate V_DDR_MCH_REF;
depopulate when buffer generate V_DDR_MCH_REF

1@: means just populate 0ohm resistors on board;

2@: means just populate MAX9890 & related components on board;

3220@: means populate 0ohm resistors when mount Agilent 3220,unpopulate 0ohm resistors when mount other

Power Plane

VIN
B+
+VCC_CORE
+VCCP
+0.9VS
+1.5VS
+1.8V

+2.5VS
+3VALW
+3VS 3.3V switched power rail
+5VALW
+5VS
+12VALW
RTCVCC

+3V_LAN

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Description

Adapter power supply (19V)
AC or battery power rail for power circuit
Core voltage for CPU

1.05V power rail for Processor I/O and MCH core power

0.9V switched power rail for DDRII Vtt

1.5V switched power rail for PCI-E interface

1.8V power rail for DDRII

1.8V switched power rail+1.8VS ON

2.5V switched power rail for MCH video PLL

3.3V always on power rail

5V always on power rail
5V switched power rail
12V always on power rail

3.3V LAN power rail

S0-S1

N/A
N/A
ON
ON
ON
ON
ON

ON
ON
ON
ON
ON
ON
ONRTC power

ON

S3

N/A
N/A

OFF
OFF
ON
OFF OFF
OFF
ON ON*
OFF
ON
OFF
ON ON*
ON

ON*

S5

N/A
N/A
OFFOFF
OFFOFF
OFF
OFF
OFF

OFF

OFF
ON*
OFF

ON

ON*

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Notes&Revision

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

353Monday, January 08, 2007

X 0.5

ADAPTER

5

4

3

2

1

B+

VS

ACIN

D D

DOCK

DOCK_IN

MAINPWRON

+3VALW +5VALW +12VALW

MAX1902 MAX8743 ISL6269

SYSON
SUSP#

VCCP_ON#

+1.8VP

+1.5VSP

+VCCP

EC_ON#

SUSP#P

LDO
G965

APL5331

SUSP

LDO
XC61CN

SUSP

+2.5VSP

A BATTERY

C C

A OR B BATTERYA OR B BATTERY

MAX1908
CHARGER

+3VS

FSTCHG

IREF

+5VS

BRIDGE BATTERY

SUSP#

+0.9VSP

B BATTERY

A OR B BATTERY

B B

BATT+

FSTCHG

MAX1538

BATSELB_A#

+1.8VS

+VCCP_OK

H_DPRSLPVR

H_DPRSTP#

H_PSI#

VR_ON

VGATE
CLK_ENABLE#
H_PROCHOT#

MAX8770

VID0
VID1
VID2

VID3
VID4
VID5
VID6

BATTERY SELECTOR

VSB

RTC_VREF

POWER SOURCE

+VCC_CORE

BATT+

VIN

A A

5

4

G920AT24U

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

RTC BATT

CHARGER SOURCE

2

Compal Electronics, Inc.(KunShan)

Title

Power rail

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

453Monday, January 08, 2007

X 0.5

5

PCI

SRC

CPU

FSLA

FSLB

FSLC

CLKSEL1

CLKSEL2

0

0

FSB Frequency Selet:

D D

CPU Driven

(Default)

*

533MHz

667MHz

0

1

Stuff

No Stuff

Stuff

No Stuff

Stuff

No Stuff

CLKSEL0

1

1

MHz

133

166

CLK_Ra

CLK_Rd

CLK_Rd

CLK_Ra

CLK_Rd

CLK_Ra

MHz

100

100

CLK_Rb

CLK_Re

CLK_Re

CLK_Rb

CLK_Rf

CLK_Rb

MHz

33.3

33.3

CLK_Rc

CLK_Rf

CLK_Rf

CLK_Rc

CLK_Rc

+3VS

FBMA-L11-201209-221LMA30T_0805

+3VS

FBMA-L11-201209-221LMA30T_0805

CLK_Re

+VCCP

12

@

R506

J1

12

12

R503

@

+VCCP

+VCCP

+3VS

5

R439

56_0402_5%

CLK_Rd

1 2

R443

1K_0402_5%

12

R450
1K_0402_5%

12

R460
1K_0402_5%

1 2

R464

1K_0402_5%

12

R471

@

0_0402_5%

CLK_Re

12

R482
1K_0402_5%

1 2

R488

1K_0402_5%

12

R495

@

0_0402_5%

CLK_Rf

12

12

12

MCH_CLKSEL0 <9>

MCH_CLKSEL1 <9>

MCH_CLKSEL2 <9>

Pin 43/44,47/48 function select

FCTSEL1: 0 DOT96/LCD100 *
1 27M/SRC0

R442

8.2K_0402_5%

C C

B B

A A

FSLA

FSLC

1 2

R447

0_0402_5%

CLK_Ra

FSLB

1 2

R466

0_0402_5%

CLK_Rb

R487

8.2K_0402_5%

1 2

R491

0_0402_5%

CLK_Rc

10K_0402_5%

CLK_ENABLE#

300_0402_5%

NO SHORT PADS

CPU_BSEL0<7>

CPU_BSEL1<7>

CPU_BSEL2<7>

C395

1 2

C396 22P_0402_50V8J

1 2

+3VS

12

R497
10K_0402_5%

@

FCTSEL1

12

R504

10K_0402_5%

22P_0402_50V8J

CLK_48M_USB<27>
CLK_48M_ICH<22>

CLK_14M_ICH<22>

CLK_PCI_PCM<25>
CLK_PCI_EC<33>

CLK_PCI_USB<27>
CLK_PCI_SIO<35>

CLK_14M_SIO<35>

DREFCLK<9>
DREFCLK#<9>

CLK_PCI_ICH<20>

CLK_ENABLE#<46>

ICH_SMBCLK<6,15,16,22,24>

ICH_SMBDATA<6,15,16,22,24>

4

+CK_VDD_MAIN1

L14

1 2

+CK_VDD_MAIN2

L15

1 2

12

14.31818MHZ_20P_6X1430004201
Y1

CLK_48M_USB

CLK_48M_ICH

CLK_PCI_PCM FCTSEL1
CLK_PCI_EC SEL_48M
CLK_PCI_USB

CLK_14M_SIO SEL_PCI5

DREFCLK
DREFCLK#

CLK_ENABLE#

ICH_SMBCLK

ICH_SMBDATA

Pin28/29 function select

+3VS

12

R502

10K_0402_5%

DB@

SEL_PCI6

SEL_PCI5/6: 0 CLKREQ5/6#,
1 PCICLK5/6

4

1

C384

10U_0805_10V4Z

2

1

C388

10U_0805_10V4Z

2

+CK_VDD_MAIN1

C397
C399

R22 12_0402_5%
R21 12_0402_5%

0_0402_5%

+3VS

12

R498

10K_0402_5%

SEL_PCI5

3

L19

1

C385

0.1U_0402_16V4Z

2

1

C389

0.1U_0402_16V4Z

2

+CK_VDD_DP

+CK_VDD_REF

1 2

0.1U_0402_16V4Z

+CK_VDD_48

1 2

0.1U_0402_16V4Z

12

FSLA

12

FSLB
FSLCCLK_14M_ICH

12

R44933_0402_5%

12

R47433_0402_5%

12

R46933_0402_5%

SEL_24M

12

R47533_0402_5%

SEL_PCI6CLK_PCI_SIO

12

R49333_0402_5%

12

R46233_0402_5%

DOCTT

12

R486

DOCTC

12

R4890_0402_5%

ITP_ENCLK_PCI_ICH

12

R45833_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

C386

0.1U_0402_16V4Z

1

1

C390

0.1U_0402_16V4Z

2

U46

1

VDDSRC

49

VDDSRC

54

VDDSRC

65

VDDSRC

30

VDDPCI

36

VDDPCI

12

VDDCPU

18

VDDREF

40

VDD48

20

X1

19

X2

41

USB_48MHz/FSLA

45

FSLB/TEST_MODE/24Mhz

23

REF0/FSLC/TEST_SEL

34

PCICLK4/FCTSEL1

33

SEL_48M/PCICLK3

32

SEL_24M/PCICLK2

27

SEL_PCI6/PCICLK1

22

SEL_PCI5/REF1

43

DOTT_96MHz/27MHz_Nonspread

44

DOTC_96MHz/27MHz_spread

37

ITP_EN/PCICLK_F0

39

VTT_PWRGD#/PD

9

GND

16

SMBCLK

17

SMBDAT

4

GNDSRC

15

GNDCPU

21

GNDREF

31

GNDPCI

35

GNDPCI

42

GND48

68

GNDSRC

73

THRM_PAD

74

THRM_PAD

75

THRM_PAD

76

THRM_PAD

ICS9LPRS325CKLFT_MLF72

2

C387

0.1U_0402_16V4Z

1

R430

+CK_VDD_REF

1 2

1_0805_1%

+CK_VDD_48

1 2

R431

2.2_0805_1%

VDDA
GNDA

PCI_SRC_STOP#

CPU_STOP#

CPUCLKT1LP
CPUCLKC1LP

CPUCLKT0LP
CPUCLKC0LP

CPUCLKT2_ITP/SRCCLKT10LP

CPUCLKC2_ITP/SRCCLKC10LP

SRCCLKT9LP
SRCCLKC9LP

CLKREQ9#
SRCCLKT8LP
SRCCLKC8LP

CLKREQ8#
SRCCLKT7LP
SRCCLKC7LP

CLKREQ7#/48Mhz_1

SRCCLKT6LP
SRCCLKC6LP

CLKREQ6#
SRCCLKT5LP
SRCCLKC5LP

CLKREQ5#/PCICLK6

SRCCLKT4LP
SRCCLKC4LP

CLKREQ4#
SRCCLKT3LP
SRCCLKC3LP

CLKREQ3#/PCICLK5

SRCCLKT2LP
SRCCLKC2LP

CLKREQ2#
SRCCLKT1LP
SRCCLKC1LP

CLKREQ1#

LCD100/96/SRC0_TLP

LCD100/96/SRC0_CLP

3

7
8

H_STP_PCI#

25

H_STP_CPU#

24

CK_CPU

11

CK_CPU#

10

14
13

CK_ITP

6

CK_ITP#

5

CK_SRC9

3

CK_SRC9#

2

CLKREQA#

72

CK_SRC8

70

CK_SRC8#

69

CLKREQB#

71
66
67

ICS_48MHz CLK_48M_SD

38
63
64
62
60
61

PCICLK6 CLK_DEBUG_PORT

29

CK_SRC4

58

CK_SRC4#

59

CLKREQC#

57

CK_SRC3

55

CK_SRC3#

56
28

CK_SRC2

52
53
26
50
51
46

CK_SRC0

47

CK_SRC0#

48

1 2

+3VS

FBMA-L11-201209-221LMA30T_0805

L4

1 2

FBMA-L11-201209-221LMA30T_0805

C415 0.1U_0402_16V4Z

R476 33_0402_5% DB@

+3VS

1 2

H_STP_PCI# <22>
H_STP_CPU# <22>

1 2

R43 0_0402_5%

1 2

0_0402_5%

R44

1 2

R51 0_0402_5%

1 2

R52 0_0402_5%

1 2

R53 0_0402_5%

1 2

R54 0_0402_5%
R55

0_0402_5%

1 2

1 2

R56

12

10K_0402_5%

R448

1 2

R62 0_0402_5%

1 2

0_0402_5%

R63

R463

1 2

R459

12

1 2

R64

1 2

R65 0_0402_5%

R483 10K_0402_5%

1 2

R66

1 2

R67 0_0402_5%

12

R477 33_0402_5%

1 2

0_0402_5%

R68

1 2

R69

0_0402_5%

1 2

0_0402_5%

R71

1 2

R72 0_0402_5%

+CK_VDD_DP

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLKCK_MCH
CLK_MCH_BCLK#CK_MCH#

CLK_CPU_XDP
CLK_CPU_XDP#

CLK_PCIE_WAN
CLK_PCIE_WAN#

0_0402_5%

CLK_PCIE_MINI
CLK_PCIE_MINI#

10K_0402_5%

12

33_0402_5%

CLK_MCH_3GPLL

0_0402_5%

CLK_MCH_3GPLL#

12

CLK_PCIE_ICH

0_0402_5%

CLK_PCIE_ICH#
CLK_PCI_TPMPCICLK5
CLK_PCIE_LAN
CLK_PCIE_LAN#CK_SRC2#

DREF_SSCLK
DREF_SSCLK#

2

1

C391

10U_0805_10V4Z

2

CLK_CPU_BCLK <6>
CLK_CPU_BCLK# <6>

CLK_MCH_BCLK <9>
CLK_MCH_BCLK# <9>

CLK_CPU_XDP <6>
CLK_CPU_XDP# <6>

CLK_PCIE_WAN <24>
CLK_PCIE_WAN# <24>

+3VS

CLKREQA# <24>

CLK_PCIE_MINI <24>
CLK_PCIE_MINI# <24>

+3VS

CLK_48M_SD <25>

CLK_DEBUG_PORT <24>
CLK_MCH_3GPLL <9>
CLK_MCH_3GPLL# <9>

CLKREQC# <9>

+3VS

CLK_PCIE_ICH <22>
CLK_PCIE_ICH# <22>
CLK_PCI_TPM <32>
CLK_PCIE_LAN <28>
CLK_PCIE_LAN# <28>

DREF_SSCLK <9>
DREF_SSCLK# <9>

2

1

C392

0.1U_0402_16V4Z

2

CLKREQB# <24>

1

1

C393

0.1U_0402_16V4Z

2

1

C394

0.1U_0402_16V4Z

2

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_XDP
CLK_CPU_XDP#

CLK_PCIE_WAN
CLK_PCIE_WAN#

CLK_PCIE_MINI
CLK_PCIE_MINI#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DREF_SSCLK
DREF_SSCLK#
DREFCLK
DREFCLK#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_LAN
CLK_PCIE_LAN#

R96

R97

R98

R99

R100
R101

R102
R103

R104
R105

R107
R106

R109
R108

R111

R110
R113

R112

R115
R114

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

Pin38 function select

+3VS

12

R532

10K_0402_5%

SEL_48M

12

R501

10K_0402_5%

@

SEL_48M: 0 CLKREQ7 ,
1 48MHz output

Pin5/6 function select

+3VS

12

R505

10K_0402_5%

ITP_EN

12

R500
10K_0402_5%

@

ITPEN: 0 SRC10 Pair ,
1 CPU_ITP Pair

Compal Electronics, Inc.(KunShan)

Title

Clock Generator

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

Pin45 function select

SEL_24M

R499
10K_0402_5%

1 2

SEL_24M: 0 Test mode ,
1 24MHz

1

553Monday, January 08, 2007

X 0.5

of

5

H_A#[3..31]<9>

D D

H_REQ#[0..4]<9>

H_ADSTB#0<9>
H_ADSTB#1<9>

C C

R519

1 2

+VCCP

56_0402_5%

B B

In order to for Yonah B-0 silicon to boot,
due to issue in the reset sequence. needed
for processor.

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

CLK_CPU_BCLK<5>
CLK_CPU_BCLK#<5>

H_ADS#<9>
H_BNR#<9>
H_BPRI#<9>
H_BR0#<9>
H_DEFER#<9>
H_DRDY#<9>
H_HIT#<9>
H_HITM#<9>

H_LOCK#<9>
H_RESET#<9>

H_RS#[0..2]<9>

H_TRDY#<9>

XDP_DBRESET#<22>

H_DBSY#<9>
H_DPSLP#<21>
H_DPRSTP#<21,46>
H_DPWR#<9>

H_PROCHOT#<46>

H_PWRGOOD<21>
H_CPUSLP#<9,21>

1K_0402_5%

1 2

1 2

@

H_THERMTRIP#<9,21>

R521
R522 51_0402_5%

A A

R954

68_0402_5%

+VCCP

CLK_CPU_BCLK
CLK_CPU_BCLK#

12

H_PROCHOT#

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

H_ADS#
H_BNR#
H_BPRI#
H_BR0#

H_DEFER#

H_DRDY#
H_HIT#
H_HITM#

H_IERR#
H_LOCK#
H_RESET#

H_RS#0

H_RS#1

H_RS#2
H_TRDY#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

XDP_DBRESET#

H_DBSY#

H_DPSLP#

H_DPRSTP#

H_DPWR#

XDP_BPM#4

XDP_BPM#5

H_PROCHOT#
H_PWRGOOD

H_CPUSLP#

XDP_TCK

XDP_TDI

XDP_TDO

TEST1

TEST2

XDP_TMS

XDP_TRST#

H_THERMDA
H_THERMDC

H_THERMTRIP#

12

R527

56_0402_5%

U8A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

BCLK1

H1

ADS#

E2

BNR#

G5

BPRI#

F1

BR0#

H5

DEFER#

F21

DRDY#

G6

HIT#

E4

HITM#

D20

IERR#

H4

LOCK#

B1

RESET#

F3

RS0#

F4

RS1#

G3

RS2#

G2

TRDY#

AD4

BPM0#

AD3

BPM1#

AD1

BPM2#

AC4

BPM3#

C20

DBR#

E1

DBSY#

B5

DPSLP#

E5

DPRSTP#

D24

DPWR#

AC2

PRDY#

AC1

PREQ#

D21

PROCHOT#

D6

PWRGOOD

D7

SLP#

AC5

TCK

AA6

TDI

AB3

TDO

C26

TEST1

D25

TEST2

AB5

TMS

AB6

TRST#

A24

THERMDA

A25

THERMDC

C7

THERMTRIP#

YONAH-ULV_FCBGA479~D

+3VS

12

R526
1K_0402_5%

1

C

Q2

2

B

2SC2411KT146_SOT23

E

3

YONAH-ULV

HOST CLK

CONTROL

MISC

THERMAL
DIODE

PROCHOT#

4

DATA GROUP

LEGACY CPU

PROCHOT# <33>

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#

DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

3

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23

H_D#12

H26

H_D#13

F26

H_D#14

K22

H_D#15

H25

H_D#16

N22

H_D#17

K25

H_D#18

P26

H_D#19

R23

H_D#20

L25

H_D#21

L22

H_D#22

L23

H_D#23

M23

H_D#24

P25

H_D#25

P22

H_D#26

P23

H_D#27

T24

H_D#28

R24

H_D#29

L26

H_D#30

T25

H_D#31

N24

H_D#32

AA23

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

W25

H_D#37

U23

H_D#38

U25

H_D#39

U22

H_D#40

AB25

H_D#41

W22

H_D#42

Y23

H_D#43

AA26

H_D#44

Y26

H_D#45

Y22

H_D#46

AC26

H_D#47

AA24

H_D#48

AC22

H_D#49

AC23

H_D#50

AB22

H_D#51

AA21

H_D#52

AB21

H_D#53

AC25

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24

H_D#58

AE21

H_D#59

AD21

H_D#60

AE25

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26

H_DINV#0

J26

H_DINV#1

M26

H_DINV#2

V23

H_DINV#3

AC20

H_DSTBN#0

H23

H_DSTBN#1

M24

H_DSTBN#2

W24

H_DSTBN#3

AD23

H_DSTBP#0

G22

H_DSTBP#1

N25

H_DSTBP#2

Y25

H_DSTBP#3

AE24

H_A20M#

A6

H_FERR#

A5

H_IGNNE#

C4

H_INIT#

B3

H_INTR

C6

H_NMI

B4

H_STPCLK#

D5

H_SMI#

A3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H_D#[0..63] <9>

H_DINV#0 <9>
H_DINV#1 <9>
H_DINV#2 <9>
H_DINV#3 <9>

H_DSTBN#[0..3] <9>

H_DSTBP#[0..3] <9>

H_A20M# <21>
H_FERR# <21>
H_IGNNE# <21>
H_INIT# <21>
H_INTR <21>
H_NMI <21>

H_STPCLK# <21>
H_SMI# <21>

ITP-XDP Connector

@

JP2

1

XDP_BPM#5
XDP_BPM#4

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

R514

H_PWRGOOD_RH_PWRGOOD CLK_CPU_XDP

12

1K_0402_5%

+VCCP +VCCP

ICH_SMBDATA<5,15,16,22,24>

ICH_SMBCLK<5,15,16,22,24>

C401

0.1U_0402_16V4Z

ICH_SMBDATA
ICH_SMBCLK

XDP_TCK

12

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

Thermal Sensor G781F

C403

2200P_0402_50V7K

SMB_EC_CK2<24,33,36,39>
SMB_EC_DA2<24,33,36,39>

Place U2 near the top and LCD side
for using it's local thermal sensor to
monitor the LCD back side temperature

+5VS

FAN_SPEED1<33>

+3VS

FAN_PWM<33>

2

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TD0

TRST#

TDI

TMS

GND17

H_THERMDA

1

2

H_THERMDC

SMB_EC_CK2

SMB_EC_DA2

1 2

R523

10K_0402_5%

@

1 2

1000P_0402_50V7K

C406

1 2

R524 8.2K_0402_5%

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

CLK_CPU_XDP#

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE

U2

2

D+

3

D-

8

SCLK

7

SDATA

G781F_SOP8

R525

1 2

100_0402_1%

1

+3VS

R507 1K_0402_5%

XDP_DBRESET#_R

This shall place near CPU

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_TRST#
XDP_TCK

+3VS

ALERT#

THERM#

10U_0805_10V4Z

D1

CH355PT_SOD323

2 1

R508 56_0402_5%
R509

R510 56_0402_5%
R511 56_0402_5%
R512 56_0402_5%
R513 56_0402_5%

1K_0402_1%

R515

1 2

R516

200_0402_1%

R517 0_0402_5%

1 2

1

C402

0.1U_0402_16V4Z

2

1

VDD1

6

THERM#

4
5

GND

+5VS

1

C404

2

2

G

Compal Electronics, Inc.(KunShan)

Title

Yonah1/2-GTL/ITP

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1 2

1 2
1 2
1 2
1 2
1 2
1 2

H_RESET#H_RESET#_R
XDP_DBRESET#XDP_DBRESET#_R

12

12

1

C405

0.1U_0402_16V4Z

2

MOLEX_53780-0310

13

D

Q1
FDN359AN_NL_SOT23

S

@

56_0402_1%

R518

10K_0402_5%

@

JP3

1

1

2

2

3

3

+VCCP

CLK_CPU_XDP <5>
CLK_CPU_XDP# <5>

X 0.5

of

653Monday, January 08, 2007

5

4

3

2

1

+VCCP

12

R529

V_CPU_GTLREF

D D

1K_0402_1%

12

R528

2K_0402_1%

Close to CPU pin AD26
within 500mils.

+VCC_CORE

R530

100_0402_1%

1 2

R531

100_0402_1%

1 2

Close to CPU pin
within 500mils.

VCCSENSE

VSSSENSE

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

C C

B B

166

00

0

12

12

R533

27.4_0402_1%

R534

54.9_0402_1%

R535

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

1

C407

2

0.01U_0402_16V7K

CPU_BSEL0

1

1

12

R536

27.4_0402_1%

12

54.9_0402_1%

1

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

C408

10U_0805_10V4Z

1

2

V_CPU_GTLREF

CPU_BSEL0<5>
CPU_BSEL1<5>
CPU_BSEL2<5>

H_PSI#<46>
CPU_VID0<46>

CPU_VID1<46>
CPU_VID2<46>
CPU_VID3<46>
CPU_VID4<46>
CPU_VID5<46>
CPU_VID6<46>

VCCSENSE<46>
VSSSENSE<46>

+VCCP

+VCC_CORE

VCCSENSE

VSSSENSE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2

CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0

COMP1

COMP2

COMP3

U8B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

YONAH-ULV

T6

VCCP

R6

VCCP

K21

VCCP

J21

VCCP

M21

VCCP

N21

VCCP

T21

VCCP

R21

VCCP

V21

VCCP

W21

VCCP

V6

VCCP

G21

VCCP

AE6

PSI#

AD6

VID0

AF5

VID1

AE5

VID2

AF4

VID3

AE3

VID4

AF2

VID5

AE2

VID6

AD26

GTLREF

B22

BSEL0

B23

BSEL1

C21

BSEL2

R26

COMP0

U26

COMP1

U1

COMP2

V1

COMP3

E7

VCC

AB20

VCC

AA20

VCC

AF20

VCC

AE20

VCC

AB18

VCC

AB17

VCC

AA18

VCC

AA17

VCC

AD18

VCC

AD17

VCC

AC18

VCC

AC17

VCC

AF18

VCC

AF17

VCC

D2

RSVD

F6

RSVD

D3

RSVD

C1

RSVD

AF1

RSVD

D22

RSVD

C23

RSVD

C24

RSVD

AA1

RSVD

AA4

RSVD

AB2

RSVD

AA3

RSVD

M4

RSVD

N5

RSVD

T2

RSVD

V3

RSVD

B2

RSVD

C3

RSVD

T22

RSVD

B25

RSVD

YONAH-ULV_FCBGA479~D

AB26

VSS

AA25

VSS

AD25

VSS

AE26

VSS

AB23

VSS

AC24

VSS

AF24

VSS

AE23

VSS

AA22

VSS

AD22

VSS

AC21

VSS

AF21

VSS

AB19

VSS

AA19

VSS

AD19

VSS

AC19

VSS

AF19

VSS

AE19

VSS

AB16

VSS

AA16

VSS

AD16

VSS

AC16

VSS

AF16

VSS

AE16

VSS

AB13

VSS

AA14

VSS

AD13

VSS

AC14

VSS

AF13

VSS

AE14

VSS

AB11

VSS

AA11

VSS

AD11

VSS

AC11

VSS

AF11

VSS

AE11

VSS

AB8

VSS

AA8

VSS

AD8

VSS

AC8

VSS

AF8

VSS

AE8

VSS

AA5

VSS

AD5

VSS

AC6

VSS

AF6

VSS

AB4

VSS

AC3

VSS

AF3

VSS

AE4

VSS

POWER, GROUNG, RESERVED SIGNALS AND NC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

+VCC_CORE

U8C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

YONAH-ULV

AD12

VCC

AC12

VCC

AF12

VCC

AE12

VCC

AB10

VCC

AB9

VCC

AA10

VCC

AA9

VCC

AD10

VCC

AD9

VCC

AC10

VCC

AC9

VCC

AF10

VCC

AF9

VCC

AE10

VCC

AE9

VCC

AB7

VCC

AA7

VCC

AD7

VCC

AC7

VCC

B20

VCC

A20

VCC

F20

VCC

E20

VCC

B18

VCC

B17

VCC

A18

VCC

A17

VCC

D18

VCC

D17

VCC

C18

VCC

C17

VCC

F18

VCC

F17

VCC

E18

VCC

E17

VCC

B15

VCC

A15

VCC

D15

VCC

C15

VCC

F15

VCC

E15

VCC

B14

VCC

A13

VCC

D14

VCC

C13

VCC

F14

VCC

E13

VCC

B12

VCC

A12

VCC

D12

VCC

C12

VCC

F12

VCC

E12

VCC

B10

VCC

B9

VCC

A10

VCC

A9

VCC

D10

VCC

D9

VCC

C10

VCC

C9

VCC

F10

VCC

F9

VCC

E10

VCC

E9

VCC

B7

VCC

A7

VCC

F7

VCC

YONAH-ULV_FCBGA479~D

POWER, GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Yonah2/2-PWR/GND

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

753Monday, January 08, 2007

X 0.5

5

+VCC_CORE

D D

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(South side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C409
22U_0805_6.3V6M

C419
22U_0805_6.3V6M

C429

22U_0805_6.3V6M

4

1

C410
22U_0805_6.3V6M

2

1

C420
22U_0805_6.3V6M

2

1

C430

22U_0805_6.3V6M

2

1

LV@

C411
22U_0805_6.3V6M

2

1

LV@

C421
22U_0805_6.3V6M

2

1

LV@

C433
22U_0805_6.3V6M

2

1

LV@

C412
22U_0805_6.3V6M

2

1

LV@

C422
22U_0805_6.3V6M

2

1

LV@

C434
22U_0805_6.3V6M

2

1

LV@

C413
22U_0805_6.3V6M

2

1

LV@

C423
22U_0805_6.3V6M

2

1

C425
22U_0805_6.3V6M

@

2

3

1

LV@

C414
22U_0805_6.3V6M

2

1

LV@

C424
22U_0805_6.3V6M

2

1

C426
22U_0805_6.3V6M

@

2

1

C418
22U_0805_6.3V6M

@

2

1

C428
22U_0805_6.3V6M

@

2

1

C427
22U_0805_6.3V6M

@

2

2

1

C431
22U_0805_6.3V6M

@

2

1

C432
22U_0805_6.3V6M

@

2

1

C458
22U_0805_6.3V6M

@

2

1

C C

Place these capacitors on L8
(South side,Secondary Layer)

B B

330U_D2E_2.5VM_R9

+VCC_CORE

1

C435
22U_0805_6.3V6M

2

LV@

330U_D2E_2.5VM_R9

+VCCP

1

+

@

C447

2

1

2

+VCC_CORE

C442

C448

0.1U_0402_10V6K

1

C436
22U_0805_6.3V6M

2

1

+

2

1

2

1

2

1

+

C443

2

330U_D2E_2.5VM_R9

C449

0.1U_0402_10V6K

LV@

C439
22U_0805_6.3V6M

1

C450

0.1U_0402_10V6K

2

1

LV@

C440
22U_0805_6.3V6M

2

C446

330U_D2E_2.5VM_R9

1

C451

0.1U_0402_10V6K

2

1

+

2

1

C437
22U_0805_6.3V6M

@

2

330U_D2E_2.5VM_R9

1

LV@

+

C441

2

1

C452

0.1U_0402_10V6K

2

1

C438
22U_0805_6.3V6M

@

2

North Side SecondarySouth Side Secondary

1

2

C453

0.1U_0402_10V6K

Place these inside
socket cavity on L8
(North side
Secondary)

Mid Frequence Decoupling

1

C444
22U_0805_6.3V6M

@

2

1

C445
22U_0805_6.3V6M

@

2

ESR <= 1.5m ohm
Capacitor > 1980uF

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Yonah bypass

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

853Monday, January 08, 2007

X 0.5

5

H_D#[0..63]<6>

D D

C C

+VCCP

12

12

R539

R540

54.9_0402_1%

H_XSCOMP/H_YSCOMP trace
width and spacing is 5/20.

B B

A A

54.9_0402_1%

12

R543

24.9_0402_1%

+VCCP

12

R551

100_0402_1%

12

R556

200_0402_1%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

12

R544

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

H_VREF

1

C457

2

0.1U_0402_16V4Z

5

U3A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#

K11

HD14#

G4

HD15#

T10

HD16#

W11

HD17#

T3

HD18#

U7

HD19#

U9

HD20#

U11

HD21#

T11

HD22#

W9

HD23#

T1

HD24#

T8

HD25#

T4

HD26#

W7

HD27#

U5

HD28#

T9

HD29#

W6

HD30#

T5

HD31#

AB7

HD32#

AA9

HD33#

W4

HD34#

W3

HD35#

Y3

HD36#

Y7

HD37#

W5

HD38#

Y10

HD39#

AB8

HD40#

W2

HD41#

AA4

HD42#

AA7

HD43#

AA2

HD44#

AA6

HD45#

AA10

HD46#

Y8

HD47#

AA1

HD48#

AB4

HD49#

AC9

HD50#

AB11

HD51#

AC11

HD52#

AB3

HD53#

AC2

HD54#

AD1

HD55#

AD9

HD56#

AC1

HD57#

AD7

HD58#

AC6

HD59#

AB5

HD60#

AD10

HD61#

AD4

HD62#

AC8

HD63#

J13

HVREF0

K13

HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING

W1

HYSWING

CALISTOGA_FCBGA1466~D

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HADSTB#0
HADSTB#1

HOST

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#

HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

12

R549

12

R554

100_0402_1%

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

D8
G8
B8
F8
A8

B9
C13

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

221_0603_1%

1

2

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

H_SWNG0

C455

0.1U_0402_16V4Z

4

H_A#[3..31] <6>

H_REQ#[0..4] <6>

H_ADSTB#0 <6>
H_ADSTB#1 <6>

CLK_MCH_BCLK# <5>

CLK_MCH_BCLK <5>

H_DSTBN#[0..3] <6>

H_DSTBP#[0..3] <6>

H_DINV#0 <6>
H_DINV#1 <6>
H_DINV#2 <6>
H_DINV#3 <6>

H_RESET# <6>
H_ADS# <6>
H_TRDY# <6>

H_DPWR# <6>
H_DRDY# <6>
H_DEFER# <6>

H_HITM# <6>
H_HIT# <6>

H_LOCK# <6>
H_BR0# <6>
H_BNR# <6>
H_BPRI# <6>
H_DBSY# <6>
H_CPUSLP# <6,21>

H_RS#[0..2] <6>

+VCCP+VCCP

12

R550

221_0603_1%

12

R555

100_0402_1%

3

DMI_TXN0<22>
DMI_TXN1<22>
DMI_TXN2<22>
DMI_TXN3<22>

DMI_TXP0<22>
DMI_TXP1<22>
DMI_TXP2<22>
DMI_TXP3<22>

DMI_RXN0<22>
DMI_RXN1<22>
DMI_RXN2<22>
DMI_RXN3<22>

DMI_RXP0<22>
DMI_RXP1<22>
DMI_RXP2<22>
DMI_RXP3<22>

M_CLK_DDR0<15>
M_CLK_DDR1<15>
M_CLK_DDR2<16>
M_CLK_DDR3<16>

M_CLK_DDR#0<15>
M_CLK_DDR#1<15>
M_CLK_DDR#2<16>
M_CLK_DDR#3<16>

DDR_CKE0_DIMMA<15>
DDR_CKE1_DIMMA<15>
DDR_CKE2_DIMMB<16>
DDR_CKE3_DIMMB<16>

DDR_CS0_DIMMA#<15>
DDR_CS1_DIMMA#<15>
DDR_CS2_DIMMB#<16>
DDR_CS3_DIMMB#<16>

+1.8V

R537 80.6_0402_1%

1 2
1 2

R538

R541 0_0402_5%

H_DPRSLPVR<22,46>

V_DDR_MCH_REF<15,16>

H_SWNG1

1

C456

2

0.1U_0402_16V4Z

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V_DDR_MCH_REF

Use +1.8V divide voltage for V_DDR_MCH_REF, R545/R548 use 100_0402_1%
Use buffer to generate V_DDR_MCH_REF, R545/R548 use 1K_0402_1%

1 2

PLT_RST#<18,20,22,24,28,32,33,35>

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

R446

1 2

0_0805_5%

1.8_divider@

3

M_ODT0<15>
M_ODT1<15>
M_ODT2<16>
M_ODT3<16>

80.6_0402_1%

V_DDR_MCH_REF

PM_BMBUSY#<22>

EC_EXTTS#0<15,16,33>

H_THERMTRIP#<6,21>

R542 100_0402_1%

MCH_ICH_SYNC#<20>

1

C454

0.1U_0402_16V4Z

2

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

PM_BMBUSY#

EC_EXTTS#0
PM_EXTTS#1

H_THERMTRIP#

PWROK

PWROK<22,33,34>

PLTRST_R#

12

+1.8V

12

VREF

R545

12

R548

Stuff R546 & R547 for A1 Calistoga

1K_0402_1%

1K_0402_1%

AE35
AF39

AG35

AH39

AC35
AE39
AF35

AG39

AE37
AF41

AG37

AH41

AC37
AE41
AF37

AG41

AY35

AW7

AW40
AW35

AY40
AU20

AT20
BA29
AY29

AW13
AW12

AY21

AW21

AL20
AF10

BA13
BA12
AY20
AU21

AK41

AH33
AH34

Layout Note:
Route as short
as possible

U3B

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0

AR1

SM_CK1
SM_CK2
SM_CK3

SM_CK0#

AT1

SM_CK1#

AY7

SM_CK2#
SM_CK3#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

AV9

SM_RCOMPN

AT9

SM_RCOMPP

AK1

SM_VREF0
SM_VREF1

G28

PM_BMBUSY#

F25

PM_EXTTS0#

H26

PM_EXTTS1#

G6

PM_THERMTRIP#
PWROK
RSTIN#

K28

ICH_SYNC#

CALISTOGA_FCBGA1466~D

12

12

R546

R547

40.2_0402_1% @

40.2_0402_1% @

2

DMI

DDR MUXING

M_OCDOCMP0
M_OCDOCMP1

2

PM

10U_1206_6.3V7K

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16

CFG

CFG17
CFG18
CFG19
CFG20

G_CLKP
G_CLKN

D_REF_CLKN
D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

CLK_REQ#

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESERVED

+1.8V

Buffer@

1

C932

2

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

1

Description at page13.

MCH_CLKSEL0

K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#M_CLK_DDR0

AF33
A27

A26
C40

D41
H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

MCH_CLKSEL1
MCH_CLKSEL2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

DREFCLK#
DREFCLK

DREF_SSCLK#
DREF_SSCLK

CLKREQC#

VREF

EC_EXTTS#0

PM_EXTTS#1

MCH_CLKSEL0 <5>
MCH_CLKSEL1 <5>

MCH_CLKSEL2 <5>

PAD
PAD

CFG5 <13>

PAD

CFG7 <13>

PAD

CFG9 <13>

PAD
PAD

CFG12 <13>

CFG13 <13>

PAD
PAD

CFG16 <13>

PAD

CFG18 <13>

CFG19 <13>

CFG20 <13>

CLK_MCH_3GPLL <5>

CLK_MCH_3GPLL# <5>

DREFCLK# <5>

DREFCLK <5>

DREF_SSCLK# <5>

DREF_SSCLK <5>

CLKREQC# <5>

U1

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

V_DDR_MCH_REF

1

C931
10U_1206_6.3V7K

2

Buffer@

T1
T2

T3
T4
T5

T6

T7
T8

T9

NC
NC
NC
TP

Buffer@

R552

12

10K_0402_5%

R553

12

10K_0402_5%@

6
5
7
8
9

Calistoga1/6-GTL/DMIDDRMUX

PecosII-IDX80-LA3291

1

+3VS

2

Buffer@

C680
1U_0603_10V4Z

1

953Monday, January 08, 2007

+5VALW

X 0.5

of

5

D D

DDR_A_BS#0<15>
DDR_A_BS#1<15>
DDR_A_BS#2<15> DDR_B_BS#2<16>

DDR_A_DM[0..7]<15>

DDR_A_DQS[0..7]<15>

C C

B B

DDR_A_DQS#[0..7]<15>

DDR_A_MA[0..13]<15>

DDR_A_CAS#<15>
DDR_A_RAS#<15>
DDR_A_WE#<15>

T10 PAD T11 PAD
T12 PAD

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

AU12
AV14
BA20

AJ33

AM35

AL26

AN22

AM14

AK33
AT33
AN28

AM22

AN12

AK32
AU33

AN27
AM21
AM12

AY16

AU14
AW16

BA16

BA17

AU16

AV17

AU17
AW17

AT16

AU13

AT17

AV20

AV12

AY13
AW14

AY14

AK23

AK24

AG5

AN3
AH5

AL9
AR3
AH4

AN8
AP3

AL8

U3D

SA_BS0
SA_BS1
SA_BS2

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_WE#
SA_RCVENIN#
SA_RCVENOUT#

Route to a via next to ball

CALISTOGA_FCBGA1466~D

4

DDR_A_D0

AJ35

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

3

DDR_A_D[0..63] <15>

DDR_B_BS#0<16>
DDR_B_BS#1<16>

DDR_B_DM[0..7]<16>

DDR_B_DQS[0..7]<16>

DDR_B_DQS#[0..7]<16>

DDR_B_MA[0..13]<16>

DDR_B_CAS#<16>
DDR_B_RAS#<16>
DDR_B_WE#<16>

T13 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

Route to a via next to ball

2

U3E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8

SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39

DDR SYS MEMORY B

SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D0

AK39

1

DDR_B_D[0..63] <16>

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Calistoga2/6-DDRA&B

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

10 53Monday, January 08, 2007

X 0.5

5

4

3

2

1

PEGCOMP trace width

D D

+3VS

LCTLA_CLK

1 2

R37 10K_0402_5%

LCTLB_DATA

C C

B B

1 2

R42

R586

R585 10K_0402_5%

1 2

1 2

10K_0402_5%

LCD_I2C_CLK

10K_0402_5%

LCD_I2C_DAT

ENVDD<17>

3VDDCCL<19>
3VDDCDA<19>

CRT_VSYNC<19>
CRT_HSYNC<19>

CRT_B<19>
CRT_G<19>
CRT_R<19>

SDVO_SDAT<18>
SDVO_SCLK<18>

LVDSA_D0+<17>
LVDSA_D1+<17>
LVDSA_D2+<17>

LVDSA_D0-<17>
LVDSA_D1-<17>
LVDSA_D2-<17>

LVDSB_D0+<17>
LVDSB_D1+<17>
LVDSB_D2+<17>

LVDSB_D0-<17>
LVDSB_D1-<17>
LVDSB_D2-<17>

LVDSCLKA+<17>
LVDSCLKA-<17>
LVDSCLKB+<17>
LVDSCLKB-<17>

GM_PWM<17>

ENABLT<17,33>

LCD_I2C_CLK<17>

LCD_I2C_DAT<17>

ENVDD

R558

1 2

R559

3VDDCCL
3VDDCDA

R560
R561

R562
R563
R564

R565 change to 226ohm
required by Motion

12
12

12

150_0402_5%

12

150_0402_5%

12

150_0402_5%

SDVO_SDAT
SDVO_SCLK

LVDSA_D0+
LVDSA_D1+
LVDSA_D2+

LVDSA_D0­LVDSA_D1­LVDSA_D2-

LVDSB_D0+
LVDSB_D1+
LVDSB_D2+

LVDSB_D0­LVDSB_D1­LVDSB_D2-

LVDSCLKA+
LVDSCLKA­LVDSCLKB+
LVDSCLKB-

GM_PWM
ENABLT
LCTLA_CLK

LCTLB_DATA
LCD_I2C_CLK
LCD_I2C_DAT

LVDD_EN

12

0_0402_5%

1.5K_0402_1%

+1.5VS

39_0402_5%
39_0402_5%

1 2

R565 226_0402_1%

U3C

H27
H28

B37
B34
A36

C37

B35
A37

F30

D29

F28

G30
D30

F29
A32

A33
E26
E27

D32

J30
H30
H29
G26
G25

F32

LIBG

B38
C35
C33
C32

A16
C18

A19

J20

B16

B18

B19

J29

K30

C26
C25

H23
G23

E23
D23
C22

B22

A21

B21

J22

CALISTOGA_FCBGA1466~D

SDVOCTRL_DATA
SDVOCTRL_CLK

LA_DATA0
LA_DATA1
LA_DATA2

LA_DATA#0
LA_DATA#1
LA_DATA#2

LB_DATA0
LB_DATA1
LB_DATA2

LB_DATA#0
LB_DATA#1
LB_DATA#2

LA_CLK
LA_CLK#
LB_CLK
LB_CLK#

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

TVDAC_A
TVDAC_B
TVDAC_C

TV_IREF
TV_IRTNA

TV_IRTNB
TV_IRTNC

TV_DCONSEL1
TV_DCONSEL0

DDCCLK
DDCDATA

VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED
RED#

CRT_IREF

LVDS

TV CRT

and spacing is 18/25 mils.

EXP_COMPI

EXP_COMPO

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

PCI-EXPRESS GRAPHICS

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D40
D38

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

PEGCOMP

SDVOB_INT-

SDVOB_INT+

SDVO_R­SDVO_G­SDVO_B­SDVO_CLK-

SDVO_R+
SDVO_G+
SDVO_B+
SDVO_CLK+

C460

C464

1 2

1 2

R557

24.9_0402_1%

1 2

SDVOB_INT- <18>

SDVOB_INT+ <18>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

C461

C462

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

C465

C466

+1.5VS_PCIE

1 2

0.1U_0402_16V4Z

1 2

C463 0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

1 2

C467

0.1U_0402_16V4Z

SDVOB_R- <18>
SDVOB_G- <18>
SDVOB_B- <18>
SDVOB_CLK- <18>

SDVOB_R+ <18>
SDVOB_G+ <18>
SDVOB_B+ <18>
SDVOB_CLK+ <18>

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Calistoga3/6-VGA/LVDS

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

11 53Monday, January 08, 2007

X 0.5

5

+VCCP

D D

1

+

330U_D2E_2.5VM_R9

C C

B B

C477

C484

C495

2

1

1

C485

2

2

2.2U_0805_16V4Z

4.7U_0805_10V4Z

MCH_A6

1

C492

2

0.47U_0603_10V7K

1

MCH_D2

2

1

0.22U_0603_10V7K

C497

0.22U_0603_10V7K

+1.5VS

C498

0.47U_0603_10V7K

MCH_AB1

1

2

2

U3H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

VTT33

L12

VTT34

R11

VTT35

P11

VTT36

N11

VTT37

M11

VTT38

R10

VTT39

P10

VTT40

N10

VTT41

M10

VTT42

P9

VTT43

N9

VTT44

M9

VTT45

R8

VTT46

P8

VTT47

N8

VTT48

M8

VTT49

P7

VTT50

N7

VTT51

M7

VTT52

R6

VTT53

P6

VTT54

M6

VTT55

A6

VTT56

R5

VTT57

P5

VTT58

N5

VTT59

M5

VTT60

P4

VTT61

N4

VTT62

M4

VTT63

R3

VTT64

P3

VTT65

N3

VTT66

M3

VTT67

R2

VTT68

P2

VTT69

M2

VTT70

D2

VTT71

AB1

VTT72

R1

VTT73

P1

VTT74

N1

VTT75

M1

VTT76

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

CALISTOGA_FCBGA1466~D

P O W E R

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG

VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS

VSSA_LVDS

VCCA_MPLL

VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCDQ_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

4

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+2.5VS

+1.5VS_3GPLL
+2.5VS

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

+1.5VS_MPLL

+1.5VS

+1.5VS

+1.5VS

+1.5VS

1

2

W=40 mils

C482

0.1U_0402_16V4Z

1

C493

2

0.1U_0402_16V4Z

+1.5VS

1

C496

2

0.1U_0402_16V4Z

+2.5VS

C468

Should be placed near GMCH

0.1U_0402_16V4Z

+1.5VS_PCIE

10U_0805_6.3V6M

1

C470

1

2

1

C479

C480

2

0.022U_0402_16V7K

1

+2.5VS

C483

0.01U_0402_16V7K

2

+3VS

1

2

1

2

0.1U_0402_16V4Z

C486

0.1U_0402_16V4Z

+

C469

2

220U_D2_4VM

1

2

1

C494
10U_0805_6.3V6M

2

3

L1

1 2

BLM21PG600SN1D_0805

C471

10U_0805_6.3V6M

L3

1 2

BLM18PG181SN1D_0603

+1.5VS

1

1

C487

10U_0805_6.3V6M

2

2

+1.5VS

+1.5VS

+1.5VS_3GPLL

+2.5VS

D17

21

+VCCP

CH751H-40PT_SOD323

MBK1608301YZF_0603

1 2

MBK1608301YZF_0603

+1.5VS

1 2

C474

2

R566

0.5_0805_1%

3GRLL_R

1 2

1

1

C475

2

2

10U_1206_6.3V6M

0.1U_0402_16V4Z

L2

BLM18PG600SN1D_0603

+1.5VS

12

C476

1

2

0.1U_0402_16V4Z

C472

+2.5VS

1

1

C473

2

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

1

close pin B30

+2.5VS

1

C481

2

0.1U_0402_16V4Z

close pin G41

L5

L7

L8

C499

C500

1

+

2

470U_D2_2.5VM

1

+

2

470U_D2_2.5VM

+1.5VS_DPLLA

1

C503

2

0.1U_0402_16V4Z

+1.5VS_DPLLB

1

C504

2

0.1U_0402_16V4Z

+1.5VS

+1.5VS

MBK1608301YZF_0603

1 2

MBK1608301YZF_0603

1 2

+1.5VS_HPLL

L6

C501

C491

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C490

2

0.1U_0402_16V4Z

+1.5VS_MPLL

1

C502

2

1

2

1

2

0.1U_0402_16V4Z

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Calistoga4/6-PWR

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

12 53Monday, January 08, 2007

X 0.5

5

4

3

2

1

Strap Pin Table

CFG[3:17] have internal pull up

+VCCP

D D

1

C513

C512

2

0.22U_0603_10V7K

1

C519

C520

2

330U_D2E_2.5VM_R9

1

C524

+

2

220U_D2_4VM

1

+

2

0.22U_0603_10V7K

1U_0603_10V4Z

1

2

1

2

+VCCP

1

2

C525

+

1

C511

2

0.22U_0603_10V7K

no caps required by the
Rev1.501 check list

10U_0805_6.3V6M

1

C518

2

10U_0805_6.3V6M

C C

C533

330U_D2E_2.5VM_R9

B B

U3F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+1.5VS

VCCSM_LF2
VCCSM_LF1

C535

+1.8V

0.47U_0603_10V7K

1

1

C536

2

2

0.47U_0603_10V7K

Place near pin AV1 & AJ1

A A

+VCCP

U3G

AA33

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5

AA32

VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14

AA31

VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22

AA30

VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

L30

VCC33

AA29

VCC34

Y29

VCC35

W29

VCC36

V29

VCC37

U29

VCC38

R29

VCC39

P29

VCC40

M29

VCC41

L29

VCC42

AB28

VCC43

AA28

VCC44

Y28

VCC45

V28

VCC46

U28

VCC47

T28

VCC48

R28

VCC49

P28

VCC50

N28

VCC51

M28

VCC52

L28

VCC53

P27

VCC54

N27

VCC55

M27

VCC56

L27

VCC57

P26

VCC58

N26

VCC59

L26

VCC60

N25

VCC61

M25

VCC62

L25

VCC63

P24

VCC64

N24

VCC65

M24

VCC66

AB23

VCC67

AA23

VCC68

Y23

VCC69

P23

VCC70

N23

VCC71

M23

VCC72

L23

VCC73

AC22

VCC74

AB22

VCC75

Y22

VCC76

W22

VCC77

P22

VCC78

N22

VCC79

M22

VCC80

L22

VCC81

AC21

VCC82

AA21

VCC83

W21

VCC84

N21

VCC85

M21

VCC86

L21

VCC87

AC20

VCC88

AB20

VCC89

Y20

VCC90

W20

VCC91

P20

VCC92

N20

VCC93

M20

VCC94

L20

VCC95

AB19

VCC96

AA19

VCC97

Y19

VCC98

N19

VCC99

CALISTOGA_FCBGA1466~D

P O W E R

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V

VCCSM_LF4
VCCSM_LF5

C509

Place near pin AT41 & AM41

C526

Place near pin BA23

C531

10U_0805_6.3V6M

C534

Place near pin BA15

1

2

0.47U_0603_10V7K

1

C514

2

1

2

0.47U_0603_10V7K

1

2

10U_0805_6.3V6M

1

2

0.47U_0603_10V7K

C510

0.1U_0402_16V4Z

0.47U_0603_10V7K

C532

1

2

C515

1

2

0.1U_0402_16V4Z

C527

1

2

@

+1.8V

1

C517

C516

2

0.1U_0402_16V4Z

1

+

2

330U_D2E_2.5VM_R9

1

2

0.1U_0402_16V4Z

SDVO_CTRLDATA

(PCIE/SDVO select)

CFG[2:0]

CFG5

CFG7

CFG9

CFG[11,10]

CFG[13:12]

CFG16

CFG18

CFG19

CFG20

CFG[19:18] have internal pull down

011 = 667MT/s FSB
001 = 533MT/s FSB

0 = DMI x 2
1 = DMI x 4

0 = Reserved
1 = Mobile Yonah CPU

0 = Lane Reversal Enable
1 = Normal Operation

(Default)

*

(Default)

*

(Default)

*

Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

0 = 1.05V
1 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

*

(Default)

(Default)

*

*

1 = SDVO Device Present

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

R567 2.2K_0402_5%

CFG5<9>

R568 2.2K_0402_5%

CFG7<9>

R569 2.2K_0402_5%

CFG9<9>

R570 2.2K_0402_5%

CFG12<9>

R571 2.2K_0402_5%

CFG13<9>

R572 2.2K_0402_5%

CFG16<9>

R573

CFG18<9>

R574

CFG19<9>

R575

CFG20<9>

*

1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2
1 2

(Default)

@
@
@

@
@
@

@

1K_0402_5%

@

1K_0402_5%

@

1K_0402_5%

(Default)

*

(Default)

*

+3VS

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Calistoga5/6-PWR/GND

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

13 53Monday, January 08, 2007

X 0.5

5

4

3

2

1

U3I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

D D

C C

B B

A A

VSS4

M41

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

L39

VSS35

J39

VSS36

H39

VSS37

G39

VSS38

F39

VSS39

D39

VSS40

AT38

VSS41

AM38

VSS42

AH38

VSS43

AG38

VSS44

AF38

VSS45

AE38

VSS46

C38

VSS47

AK37

VSS48

AH37

VSS49

AB37

VSS50

AA37

VSS51

Y37

VSS52

W37

VSS53

V37

VSS54

T37

VSS55

R37

VSS56

P37

VSS57

N37

VSS58

M37

VSS59

L37

VSS60

J37

VSS61

H37

VSS62

G37

VSS63

F37

VSS64

D37

VSS65

AY36

VSS66

AW36

VSS67

AN36

VSS68

AH36

VSS69

AG36

VSS70

AF36

VSS71

AE36

VSS72

AC36

VSS73

C36

VSS74

B36

VSS75

BA35

VSS76

AV35

VSS77

AR35

VSS78

AH35

VSS79

AB35

VSS80

AA35

VSS81

Y35

VSS82

W35

VSS83

V35

VSS84

T35

VSS85

R35

VSS86

P35

VSS87

N35

VSS88

M35

VSS89

L35

VSS90

J35

VSS91

H35

VSS92

G35

VSS93

F35

VSS94

D35

VSS95

AN34

VSS96

AK34

VSS97

AG34

VSS98

AF34

VSS99

CALISTOGA_FCBGA1466~D

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

U3J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Calistoga6/6-GND

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

14 53Monday, January 08, 2007

X 0.5

5

DDR_A_DQS#[0..7]<10>
DDR_A_D[0..63]<10>
DDR_A_DM[0..7]<10>
DDR_A_DQS[0..7]<10>
DDR_A_MA[0..13]<10>

D D

Layout Note:
Place near JP4

Add C611, C612 follow Motion's request

+1.8V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0805_16V4Z
C541

1

2

0.1U_0402_16V4Z

1

2

C550

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

5

1

2

2.2U_0805_16V4Z

C551

+0.9VS

1

2

0.1U_0402_16V4Z

1

2

2.2U_0805_16V4Z

C542

C543

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C554

C553

C552

RP2 56_0404_4P2R_5%

DDR_CKE0_DIMMA

14

DDR_A_BS#2

23

RP4 56_0404_4P2R_5%

DDR_A_MA7

14

DDR_A_MA6

23

RP6 56_0404_4P2R_5%

DDR_A_MA12

14

DDR_A_MA9

23

RP8 56_0404_4P2R_5%

DDR_A_MA4

14

DDR_A_MA2

23

RP10 56_0404_4P2R_5%

DDR_A_MA0

14

DDR_A_BS#1

23

RP12 56_0404_4P2R_5%

M_ODT0

14

DDR_A_MA13

23

RP13 56_0404_4P2R_5%

DDR_CKE1_DIMMA

14

DDR_A_MA11

23

1

C544

2

0.1U_0402_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C C

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9VS

0.1U_0402_16V4Z

B B

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_MA10
DDR_A_BS#0

DDR_A_WE#

A A

DDR_A_CAS#

M_ODT1
DDR_CS1_DIMMA#

C540

1

C539

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C548

C549

RP1

RP3

RP5

RP7

RP9

RP11

0.1U_0402_16V4Z

1

1

2

1

2

C555

C546

C545

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C557

C556

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C611

C547

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C559

C558

Layout Note:
Place these resistor
closely JP4,all
trace length Max=1.5"

4

0.1U_0402_16V4Z

1

2

C560

3

+1.8V

JP4

1

VREF

3

DDR_A_D0
DDR_A_D4

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

+1.8V

1

C612

2

1

C528

+

220U_D2_4VM

@

2

DDR_CKE0_DIMMA<9>

DDR_A_BS#2<10>

DDR_A_BS#0<10>
DDR_A_WE#<10>

DDR_A_CAS#<10>

DDR_CS1_DIMMA#<9>

M_ODT1<9>

ICH_SMBDATA<5,6,16,22,24>

ICH_SMBCLK<5,6,16,22,24>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_A_D21
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D22
DDR_A_D19

DDR_A_D25
DDR_A_D24

DDR_A_DM3

DDR_A_D27
DDR_A_D30

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10

DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#

DDR_CS1_DIMMA#

M_ODT1
DDR_A_D34

DDR_A_D38
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D39

DDR_A_D35
DDR_A_D45

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D52

DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D51
DDR_A_D55

DDR_A_D56
DDR_A_D61

DDR_A_DM7
DDR_A_D58

DDR_A_D59

ICH_SMBDATA
ICH_SMBCLK

+3VS

1

C561

0.1U_0402_16V4Z

3

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2R-TR

SO-DIMM A

REVERSE

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

NC

A7
A6

A4
A2
A0

NC

2

+1.8V

V_DDR_MCH_REF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_D7
DDR_A_D1

DDR_A_DM0
DDR_A_D5

DDR_A_D6
DDR_A_D12

DDR_A_D13
DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_D9

DDR_A_D15

DDR_A_D20
DDR_A_D16

R579 0_0402_5%@

1 2

DDR_A_DM2
DDR_A_D18

DDR_A_D23
DDR_A_D29

DDR_A_D28
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D26

DDR_A_D31
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D33

DDR_A_DM4
DDR_A_D37

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D46
DDR_A_D48

DDR_A_D49
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D50

DDR_A_D54
DDR_A_D60

DDR_A_D57
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R577

R578

10K_0402_5%

10K_0402_5%

2

12

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

C537

2

M_CLK_DDR0 <9>
M_CLK_DDR#0 <9>

EC_EXTTS#0

DDR_CKE1_DIMMA <9>

DDR_A_BS#1 <10>
DDR_A_RAS# <10>
DDR_CS0_DIMMA# <9>

M_ODT0 <9>

M_CLK_DDR1 <9>
M_CLK_DDR#1 <9>

EC_EXTTS#0 <9,16,33>

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

V_DDR_MCH_REF <9,16>

1

C538

2

DDRII SO-DIMM A

PecosII-IDX80-LA3291

1

X 0.5

of

1

15 53Monday, January 08, 2007

5

DDR_B_DQS#[0..7]<10>
DDR_B_D[0..63]<10>
DDR_B_DM[0..7]<10>

DDR_B_DQS[0..7]<10>
DDR_B_MA[0..13]<10>

D D

Layout Note:
Place near JP5

Add C619, C625 follow Motion's request

+1.8V

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

2

1

2

C574

RP14

RP16

RP18

RP20

RP23

RP25

C565

0.1U_0402_16V4Z

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C566

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C576

C575

+0.9VS

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

5

2.2U_0805_16V4Z

C567

1

C568

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C578

C577

RP15 56_0404_4P2R_5%

14
23

RP17 56_0404_4P2R_5%

14
23

RP19 56_0404_4P2R_5%

14
23

RP21 56_0404_4P2R_5%

14
23

RP24 56_0404_4P2R_5%

14
23

RP26 56_0404_4P2R_5%

14
23

RP28

14
23

56_0404_4P2R_5%

0.1U_0402_16V4Z

1

C569

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C579

DDR_B_MA9
DDR_B_MA12

DDR_B_MA11
DDR_CKE3_DIMMB

DDR_B_MA5
DDR_B_MA8

DDR_B_MA6
DDR_B_MA7

DDR_B_MA2
DDR_B_MA4

DDR_B_MA13
M_ODT2

DDR_B_BS#2
DDR_CKE2_DIMMB

0.1U_0402_16V4Z

C580

0.1U_0402_16V4Z

1

1

C570

C571

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C582

C581

2.2U_0805_16V4Z
C564

1

2

C C

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9VS

0.1U_0402_16V4Z

1

2

C573

B B

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_BS#1
DDR_B_MA0

DDR_CS2_DIMMB#
DDR_B_RAS#

DDR_B_CAS#

A A

DDR_B_WE#

DDR_CS3_DIMMB#
M_ODT3

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C619

C572

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C584

C583

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"

4

3

+1.8V

JP5

1

VREF

3

DDR_B_D0
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D7
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

0.1U_0402_16V4Z

1

C625

2

DDR_CKE2_DIMMB<9>

DDR_B_BS#2<10>

DDR_B_BS#0<10>
DDR_B_WE#<10>

DDR_B_CAS#<10>

1

2

C585

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_CS3_DIMMB#<9>

M_ODT3<9>

ICH_SMBDATA<5,6,15,22,24>

ICH_SMBCLK<5,6,15,22,24>

3

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D22

DDR_B_D23
DDR_B_D24

DDR_B_D25
DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10

DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D37

DDR_B_D36
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D35

DDR_B_D34
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D47
DDR_B_D48

DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D60
DDR_B_D61

DDR_B_DM7
DDR_B_D58

DDR_B_D59

ICH_SMBDATA

ICH_SMBCLK

+3VS

C586

0.1U_0402_16V4Z

1

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

QTC_C111A-040SP31

SO-DIMM B
STANDARD

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

2

+1.8V

V_DDR_MCH_REF

2

DDR_B_D4

4

DDR_B_D1

6
8

DDR_B_DM0

10
12

DDR_B_D6

14

DDR_B_D2

16
18

DDR_B_D12

20

DDR_B_D13

22
24

DDR_B_DM1

26
28

M_CLK_DDR3

30

M_CLK_DDR#3

32
34

DDR_B_D14

36

DDR_B_D15

38
40

42

DDR_B_D16DDR_B_D21

44

DDR_B_D18

46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

R634 0_0402_5%@

DDR_B_DM2
DDR_B_D17

DDR_B_D19
DDR_B_D26

DDR_B_D28
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D33
DDR_B_D32

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D43

DDR_B_D46
DDR_B_D49

DDR_B_D52
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D56

DDR_B_D57
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

2

1 2

10K_0402_5%

12

R581

2.2U_0805_16V4Z

M_CLK_DDR3 <9>
M_CLK_DDR#3 <9>

EC_EXTTS#0

DDR_CKE3_DIMMB <9>

DDR_B_BS#1 <10>
DDR_B_RAS# <10>
DDR_CS2_DIMMB# <9>

M_ODT2 <9>

M_CLK_DDR2 <9>
M_CLK_DDR#2 <9>

R580

1 2

10K_0402_5%

1

2

Title

Size Document Number Rev

Custom

Date: Sheet

V_DDR_MCH_REF <9,15>

0.1U_0402_16V4Z

1

C562

C563

2

EC_EXTTS#0 <9,15,33>

+3VS

Compal Electronics, Inc.(KunShan)

DDRII SO-DIMM B

PecosII-IDX80-LA3291

1

X 0.5

of

16 53Monday, January 08, 2007

1

5

4

3

2

1

D

13

R587
150K_0402_5%

12

R593

10K_0402_5%

PID0

12

R640

@

100K_0402_5%

ID0

ID1

0
0
1
1

R330
10K_0402_5%

1 2

R315
220_0402_5%

1 2

21

Reserve

0

N-Trig

1

TouchPanel

0

Digitizer

1

+3VS

1

C589

0.1U_0402_16V4Z

2

config

Close to JP6

PID1

0
0
1
1

S

D

1 3

3

ID1<22>

@

PID0

Toshiba SXGA+

0
1
0
1

G

2

AO3413_SOT23
Q65

R641

10K_0402_5%

R633

100K_0402_5%

config

Toshiba XGA
Hydis SXGA+

Hydis XGA

+LCDVDD

R290

12

0_0603_5%

Reserved for EMI

J2

2 1

R636

1 2

ENABLT<11,33>
BKOFF#<33>

NO SHORT 2x2m

J3

2 1

NO SHORT 2x2m

ID0 <22>

100K_0402_5%

1
2

1 2

B
A

R591 0_0402_5%@

1 2

R592

CTSB#<35>
DTRB#<35>

+3VS

12

12

R589

10K_0402_5%

ID0ID1

12

12

R588
100K_0402_5%@

INVT_PWM<33>

GM_PWM<11>

+3VS

C610

1 2

5

U19

P

4

Y

G

TC7SH08FUF_SSOP5

3

0_0402_5%

2

10U_0805_10V4Z

LCD_I2C_CLK<11>
LCD_I2C_DAT<11>

LVDSCLKB+<11>
LVDSCLKB-<11>

LVDSB_D2+<11>
LVDSB_D2-<11>

LVDSB_D1+<11>
LVDSB_D1-<11>

LVDSB_D0+<11>
LVDSB_D0-<11>

LVDSCLKA+<11>
LVDSCLKA-<11>

LVDSA_D2+<11>
LVDSA_D2-<11>

LVDSA_D1+<11>
LVDSA_D1-<11>

LVDSA_D0+<11>
LVDSA_D0-<11>

@

4.7K_0402_5%

0.1U_0402_16V4Z

PSOT24C-LF_T7_SOT23-3

1

2

DIGI_RST#<33>

DIGISUSP<33>
RXDB#<35>
TXDB<35>

PDCT<33>

C681

+3VS

PWM_CTL

D45

1

2

R590

2

600mA

+LCDVDD+

1

C588

C587

0.1U_0402_16V4Z

2

10U_0805_10V4Z

PID1

R262 0_0603_5%

1 2

R263 0_0603_5%

1 2

LCD_I2C_CLK
LCD_I2C_DAT

ID0

PID0

PDCT

ID1
LVDSCLKB+
LVDSCLKB-

LVDSB_D2+
LVDSB_D2-

LVDSB_D1+
LVDSB_D1-

LVDSB_D0+
LVDSB_D0-

LVDSCLKA+
LVDSCLKA-

LVDSA_D2+
LVDSA_D2-

LVDSA_D1+
LVDSA_D1-

LVDSA_D0+
LVDSA_D0-

+3VS

12

3

1

B+

DISPOFF#

Compal Electronics, Inc.(KunShan)

Title

LCD Conn&Inverter /LED dimming control

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

LCD CONN.

R291

12

0_0603_5%

Reserved for EMI

Invert_B+

DAC_BRIG<33>

JP6

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7

46

6

45

5

44

4

43

3

42

2

41

1

IPEX_20143-040E

Invert_B+

1

C591

2

0.01U_0603_50V4Z

MOLEX_53780-0790

1

1

2

JP7

1
2
3
4
5
6
7

17 53Monday, January 08, 2007

C592

0.1U_0603_25V7K

of

X 0.5

+12VALW +LCDVDD

+LCDVDD

R583

470_0402_5%

D D

ENVDD<11>

C C

+5VALW

12

R924

22K_0402_5%

13

D

Q16

2N7002_SOT23

B B

+5VALW

BATTERY CHARGE

A A

CHARGE_LED#<33>

CHARGE_LED#

5

2

G

S

12

R6
510_0402_5%

R364
120_0402_5%

1 2

21

D15

HT-170Y-DT_0805

LED_PWM

S

D

1 3

BATTERY FULL

1 2

R712

1 2

R642

G

2

AO3413_SOT23
Q64

HT-170NB-DTP/C_BLUE_0805

BATT_LED#<33>

0_0402_5%

@

0_0402_5%

GM_PWM

INVT_PWM

BATT_LED#

ENVDD

D

S

12

LED_PWM_R

+5VALW

1 2

1 2

21

D19

12

13

Q4

2

2N7002_SOT23

G

22K

2

22K

R635
100K_0402_5%

R331
10K_0402_5%

R317
220_0402_5%

4

+12VALW

12

13

12

R582

R584
100K_0402_5%

100K_0402_5%

13

D

Q5

2

G

S

2N7002_SOT23

Q6
DTC124EKAT146_SOT23

S

D

1 3

0.01U_0402_16V7K

10K_0402_5%

PID1<22> PID0 <22>

@

100K_0402_5%

G

2

AO3413_SOT23
Q66

POWER ON

HT-170NB-DTP/C_BLUE_0805

PWR_LED#<33>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

R717

PID1

R716

PWR_LED#

C590

+3VS

12

12

D16

Q3
AO3402_SOT23

S

G

2

12

+5VALW

5

4

3

2

1

DVI CONTROLLER

D D

1

C595
10U_0805_10V4Z

DVI_1362@

2

1

C600
10U_0805_10V4Z

DVI_7307@

2

1

C607

10U_0805_10V4Z

DVI_1362@

2

2.7K_0402_5%

DVI_DDC_CLK1362_SCL_DDC

DVI_1362@

DVI_TX2+

DVI_CLK+

DVI_CLK-

DVI_DDC_DAT
DVI_DDC_CLK

R282

L9

1 2

0_0603_5%DVI_1362@

L10

1 2

0_0603_5%DVI_7307@

L11

1 2

0_0603_5%DVI_1362@

+2.5VS

12

DVI_DETECT

12

10K_0402_5%

+1.8VS

+2.5VS

+3VS

R625
16K_0402_5%

+5VS
+5VS

DVI_DVDD_1.8V

1

1

C593

0.1U_0402_16V4Z

DVI_1362@

C598

0.1U_0402_16V4ZDVI_7307@

0.1U_0402_16V4Z

DVI_1362@

SDVO_SDAT
SDVO_SCLK

+5VS +5VS

12

R624
16K_0402_5%

DVI_TX0-

DVI_TX0+

DVI_TX1-

DVI_TX1+

DVI_TX2-

SDVO_SDAT
SDVO_SCLK

2

IO1

1

GND

2

IO1

1

GND

2

IO1

1

GND

DVI_CLK+

DVI_CLK-

DVI_TX1+

DVI_TX1-

DVI_TX0+

DVI_TX2+

DVI_DDC_DAT

R594

300_0402_1%@

1

1 2

C596

@

0.1U_0402_16V4Z

2

R604

300_0402_1%@

1

1 2

C603

@

0.1U_0402_16V4Z

2

SDVO_SDAT <11>
SDVO_SCLK <11>

R629 0_0402_5%

DVI_CLK-

DVI_AVDD_3V

U4

SDVOB_INT+
SDVOB_INT-

SDVOB_R+
SDVOB_R-

SDVOB_G+
SDVOB_G-

SDVOB_B+
SDVOB_B-

SDVOB_CLK+
SDVOB_CLK-

AS
RESET#
VSWING

ATPG
SCEN

12

R621
10K_0402_5%

DVI_7307@

R627
1K_0402_5%@

R631
1K_0402_5%

DVI_1362@

DVI_V2

DGND7DGND30AGND31AGND39AGND45TGND18TGND24AGND_PLL

ThermmaoGND

49

I2C_ADD

W=20 mils

13

D

2

G

S

1

28

21

TVDD15TVDD

DVDD12DVDD

AVDD_PLL

DVI_DETECT#

Q11

2N7002_SOT23

R598 0_0402_5%DVI_7307@

1 2

R599 0_0402_5%DVI_1362@

1 2

DVI_V9 DVI_DVDD_2.5V

R602 0_0402_5%DVI_7307@

1 2

R603 0_0402_5%DVI_1362@

1 2

48

DVI_CLK-

AVDD36AVDD42AVDD

6

12

R632
0_0402_5%

DVI_7307@

13

TLC#

TLC

TDC0#

TDC0

TDC1#

TDC1

TDC2#

TDC2

HPDET

SC_DDC
SD_DDC

SC_PROM
SD_PROM

SPD
SPC

NC

NC

CH7307C-DEF_LQFP48

35

34

DVI_V4

DVI_V3 DVI_DVDD_1.8V

DVI_CLK+

14

DVI_TX0-

16

DVI_TX0+

17

DVI_TX1-

19

DVI_TX1+

20

DVI_TX2-

22

DVI_TX2+

23

DVI_DETECT

29

DVI_V6

11
10

9
8

5
4

R623

1 2

1K_0402_5%DVI_1362@

1 2

R626 0_0402_5%DVI_1362@

Note:
Install DVI-Ra 1K_0402_5% for SiI1362
Install DVI-Ra 0_0402_5% for CH7307

DVI_DETECT# <20>

R606 0_0402_5%DVI_7307@
R607 0_0402_5%DVI_1362@

DVI_V1

R608 0_0402_5%DVI_7307@

R609 0_0402_5%DVI_1362@

1362_SDA_DDC
1362_SCL_DDC

R611 0_0402_5%DVI_7307@

R613 0_0402_5%DVI_7307@

R615 0_0402_5%DVI_1362@

R617 0_0402_5%DVI_1362@

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

DVI_DVDD_2.5VDVI_V10
DVI_DVDD_1.8V

DVI_AVDD_3V

DVI_TX0-

DVI_TX2-

+5VS

DVI_DDC_CLK

DVI_DDC_CLK
DVI_AVDD_3V
DVI_DDC_DAT
DVI_DVDD_1.8V

+5VS

D39

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4

+5VS

D41

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4

D43

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4

DVI_DVDD_2.5V
DVI_DVDD_1.8V

DVI_DVDD_2.5V DVI_V5

SDVOB_INT+<11>
SDVOB_INT-<11>

C C

DVI_AVDD_3V

+2.5VS

12

R622

10K_0402_5%

@

12

AS

R628
0_0402_5%

DVI_1362@

B B

DVI-Rb

R610

1 2

300_0402_5%DVI_1362@

1.2K_0402_5%

DVI_7307@

R616

12

R596 0_0402_5%DVI_7307@

1 2

R597 0_0402_5%DVI_1362@

1 2

R600 0_0402_5%DVI_7307@

1 2

R601 0_0402_5%DVI_1362@

1 2

C601

0.1U_0402_16V4Z

1 2
1 2

C602 0.1U_0402_16V4Z

SDVOB_R+<11>
SDVOB_R-<11>

SDVOB_G+<11>
SDVOB_G-<11>

SDVOB_B+<11>
SDVOB_B-<11>

SDVOB_CLK+<11>
SDVOB_CLK-<11>

PLT_RST#<9,20,22,24,28,32,33,35>

0_0402_5%

DVI_1362@

12

R619

R618
10K_0402_5%

DVI_7307@

1 2

DVI_AVDD_3V

AS

DVI_V8
DVI_V7

1 2

32
33

37
38

40
41

43
44

46
47

25
27

26

DVI_1362@

R620
0_0402_5%

+3VS

3
2

12

12

DVI-Ra

Note: Address = 0x70
Install DVI-Rb 0_0402_5% for SiI1362
Note: Address = 0x72
Install DVI-Rb 10K_0402_5% for CH7307

DVI_DETECT

A A

150P_0402_50V8J

1 2

DVI_1362@

+5VS

D40

4

VIN

DVI_TX1-

3

IO2

PRTR5V0U2X_SOT143-4

+5VS

D42

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4

+5VS

D44

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4

DVI_TX0+

12

1

2

DVI_TX0-

DVI_TX2+

1

1 2

2

DVI_TX2-

C608

DVI_DDC_DAT1362_SDA_DDC

IO1

GND

IO1

GND

IO1

GND

R595

300_0402_1%@

C597

@

0.1U_0402_16V4Z

R605

300_0402_1%@

C604

@

0.1U_0402_16V4Z

1

2

DVI_TX1+

2
1

DVI_CLK+

2
1

DVI_DETECT

2
1

C594

DVI_1362@

2

2

0.1U_0402_16V4Z

DVI_DVDD_2.5V

1

1

C599

2

2

0.1U_0402_16V4ZDVI_7307@

DVI_AVDD_3V

1

C606

C605

2

DVI_1362@

0.1U_0402_16V4Z

R612 2.7K_0402_5%

1 2

R614

1 2

1 2

R630 0_0402_5%

JP8

1

21

2

22

3

23

4

24

5

25

6

26

7

27

8

28

9

29

10

30

11

31

12

32

13

33

14

34

15

35

16

36

17

37

18

38

19

39

20

40

JAE_DD2R040HP2

1

2

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

DVI CONN

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

18 53Monday, January 08, 2007

X 0.5

5

+2.5VS

3

D D

CRT_R_MB

CRT_G_MB

CRT_B_MB

1

R637

133_0402_1%
133_0402_1%
133_0402_1%

C C

CRT_HSYNC<11>

B B

CRT_VSYNC<11>

A A

2

CRT_HSYNC

CRT_VSYNC

R638

C613

6P_0402_50V8K
6P_0402_50V8K
6P_0402_50V8K

+5VS

+5VS

A2Y

A2Y

FBMA-L11-201209-170LMT
FBMA-L11-201209-170LMT

FBMA-L11-201209-170LMT

R639

1

2

1

5

P

G

74AHCT1G125GW_SOT353-5

3

1

5

P

G

74AHCT1G125GW_SOT353-5

3

5

A2Y

3

5

A2Y

3

1

C614

2

R145

1 2

1K_0402_5%

CRT_HSYNCMB

4

OE#

U51

R146

1 2

1K_0402_5%

CRT_HSYNCDOCK

4

OE#

U5

R147

1 2

1K_0402_5%

1

P

CRT_VSYNCMB

4

OE#

U52

G

74AHCT1G125GW_SOT353-5

R148

1 2

1K_0402_5%

1

P

CRT_VSYNCDOCK

4

OE#

U7

G

74AHCT1G125GW_SOT353-5

1 2

1 2

1 2

C615

@

L12

L13

L16

39_0402_5%

39_0402_5%

39_0402_5%

2

D3

DAN217_SC59

1

1

C616

6P_0402_50V8K

2

R1154

R1155

R1158

R1159

39_0402_5%

4

2

3

D4

@

DAN217_SC59

1

1

C617

6P_0402_50V8K

2

+5VS

3

@

DAN217_SC59

1

HSYNC

12

CRT_HSYNC_DOCK

12

+5VS

3

@

DAN217_SC59

1

VSYNC

12

CRT_VSYNC_DOCK

12

3

@

DAN217_SC59

1

1

2

2

D34

2

D35

2

D31

CRTR

CRTG

CRTB

C618

6P_0402_50V8K

CRT_HSYNC_DOCK <36>

CRT_VSYNC_DOCK <36>

3

+3VS

R141

2.2K_0402_5%

1 2

3VDDCDA<11>

3VDDCCL<11>

3VDDCCL

To DOCK

3VDDCDA_R<36>

3VDDCCL_R<36>

R142

2.2K_0402_5%

1 2

CRT_R<11>
CRT_G<11>
CRT_B<11>

+5VS

G

2

13

D

S

Q8
BSS138W-7-F_SOT323~D

S

+5VS

0.1U_0402_16V4Z

1

C633

C671

2

0.1U_0402_16V4Z

C620

0.1U_0402_16V4Z

1.1A 6V UL/CSA/TUV

G

2

Q49
BSS138W-7-F_SOT323~D

1

2

CRT_R
CRT_G
CRT_B

F1

M_SEN#<22,36>

13

D

1

C672

2

0.1U_0402_16V4Z

+5VS

2

21

2 1

RB491D_SOT23

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C677

2

16

VCC

4

DA

7

DB

9

DC

12

DD

8

GND

PI5V330QE_QSOP16

D29

C609

M_SEN#
CRTR

3VDDCDA_R3VDDCDA
CRTG

HSYNC
CRTB

VSYNC

3VDDCCL_R

1

2

DOCKEN

S1A
S2A
S1B
S2B
S1C
S2C
S1D
S2D

U6

EN

IN

CRTVCC

1

2

15
1

2
3
5
6
11
10
14
13

R143

R144

2.2K_0402_5%

2.2K_0402_5%

1 2

1 2

1: TO DOCK
0: TO MB

+3VS

R371

10K_0402_5%

1 2

DOCKEN_VGA

CRT_R_MB

CRT_R_DOCK

CRT_G_MB

CRT_G_DOCK

CRT_B_MB

CRT_B_DOCK

1

2

+3VS

1 2

C343

100P_0402_50V8J

R372
10K_0402_5%

JP12

6

11

1
7

12

16

2

17

8

13

3
9

14

4
10
15

5

ALLTO_C10510-115A5-L_15P

DOCKEN_VGA <33,34>

CRT_R_DOCK <36>
CRT_G_DOCK <36>
CRT_B_DOCK <36>

1

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

CRT CONN

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

19 53Monday, January 08, 2007

X 0.5

+3VS

5

4

3

2

1

R644
R645
R646

D D

C C

B B

R647
R648
R649
R650
R651
R652
R653
R654

+3VS

R656
R657
R658
R659
R660
R661
R663
R664
R665
R666
R667

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

8.2K_0402_5%

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_REQ4#
PCI_REQ3#
DVI_DETECT#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#

PCI_AD[0..31]<25,27>

PCI_PIRQA#<25>

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U9B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

Interrupt I/F

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

AE5

RSVD[1]

AD5

RSVD[2]

AG4

RSVD[3]

AH4

RSVD[4]

AD9

RSVD[5]

ICH7_BGA652~D

PCI

REQ4# / GPIO22

GNT4# / GPIO48

GPIO1 / REQ5#

GPIO17 / GNT5#

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC

MCH_SYNC#

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

AE9
AG8
AH8
F21
AH20

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

PCI_REQ2#
PCI_GNT2#
PCI_REQ3#

PCI_REQ4#
DVI_DETECT#

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

PCI_FRAME#

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

PCI_PIRQE#PCI_PIRQA#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_REQ0# <27>
PCI_GNT0# <27>

PCI_REQ2# <25>

PCI_GNT2# <25>

DVI_DETECT# <18>

PCI_C/BE#0 <25,27>
PCI_C/BE#1 <25,27>
PCI_C/BE#2 <25,27>
PCI_C/BE#3 <25,27>

PCI_IRDY# <25,27>
PCI_PAR <25,27>

PCI_DEVSEL# <25,27>
PCI_PERR# <25,27>

PCI_SERR# <25,27>

PCI_STOP# <25,27>
PCI_TRDY# <25,27>
PCI_FRAME# <25,27>

CLK_PCI_ICH <5>

PCI_PME# <34>

PCI_PIRQE# <27>
PCI_PIRQF# <27>
PCI_PIRQG# <27>PCI_PIRQC#<25>

MCH_ICH_SYNC# <9>

PCI_PCIRST#

PCI_PLTRST#

+3VS

5

U10

1

P

B

2

A

G

TC7SH08FUF_SSOP5

12

+3VS

1

B

2

A

12

3

@

5

U11

P

G

TC7SH08FUF_SSOP5

3

@

R655
0_0402_5%

R662
0_0402_5%

Place closely pin A9

CLK_PCI_ICH

R669

10_0402_5%@

1 2
1

C621

8.2P_0402_50V8D@

2

PCI_RST#

4

Y

PLT_RST#

4

Y

PCI_RST# <25,27>

PLT_RST# <9,18,22,24,28,32,33,35>

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

ICH7M1/4-PCI Interface

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

20 53Monday, January 08, 2007

X 0.5

5

C622

18P_0402_50V8J

12

Y2

2

IN

NC

3

OUT

NC

32.768KHZ_12.5PF_1TJS125BJ4A421P
C623

18P_0402_50V8J

1 2

1M_0402_5%

R688

R672

12

1 2

1 2
1 2

1 2

12

12

R689

4.7K_0402_5%

PDIORDY
IDEIRQ

12

R686
332K_0402_1%

ICH_INTVRMEN

12

R687

0_0402_5%@

R671

1 2

20K_0402_5%

CMOS_CLR1

1 2

NO SHORT PADS

C624

1U_0603_10V4Z

1 2

ICH_AZ_CODEC_BITCLK<30>

ICH_AZ_CODEC_SYNC<30>
ICH_AZ_CODEC_RST#<30>
ICH_AZ_CODEC_SDIN0<30>

ICH_AZ_CODEC_SDOUT<30>

+RTCVCC

+3VS

8.2K_0402_5%

PDIORDY<24>
IDEIRQ<24>

D D

C C

B B

+RTCVCC

+RTCVCC

Pull high to enable the
internal Vccsus1_5
suspend regulator. pull
low to disable it--ICH_INTVRMEN

1
4

R67733_0402_5%

R67933_0402_5%
R68033_0402_5%

ICH_AZ_CODEC_SDIN0

R68433_0402_5%

PDDACK#<24>
PDIOW#<24>
PDIOR#<24>

12

4

ICH_RTCX1

R670
10M_0402_5%

ICH_RTCX2
ICH_RTCRST#
ICH_INTVRMEN

SM_INTRUDER#

ACZ_BCLK

ACZ_SYNC

ACZ_RST# H_SMI#

ACZ_SDOUT

PDDACK#
PDIOW#
PDIOR#

AF18

AG2

AG6

AH10

AG10

AG16

AH16
AF16
AH15
AF15

AB1
AB2

AA3

W4

Y5

W1

Y1
Y2

W3

V3
U3
U5

V4
T5

U7
V6
V7

U1
R6

R5
T2

T3
T1

T4

AF3
AE3

AH2
AF7

AE7
AH6
AF1

AE1

U9A

RTXC1
RTCX2

RTCRST#
INTVRMEN

INTRUDER#

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LAN_RXD0

LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT

SATALED#

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_CLKN
SATA_CLKP

SATARBIASN
SATARBIASP

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

ICH7_BGA652~D

RTC

GPIO49 / CPUPWRGD

LAD0
LAD1
LAD2
LAD3

LDRQ0#

LPCCPU

LDRQ1# / GPIO23

LFRAME#

LAN

A20GATE

A20M#

CPUSLP#

TP1 / DPRSTP#

TP2 / DPSLP#

FERR#

IGNNE#

INIT3_3V#

INIT#

INTR

AC-97/AZALIA

RCIN#

SMI#

STPCLK#

THERMTRIP#

DA0
DA1
DA2

DCS1#
DCS3#

SATA

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8

DD9
DD10
DD11
DD12
DD13

IDE

DD14
DD15

DDREQ

AA6
AB5
AC4
Y6

AC3
AA5

AB3

AE22
AH28

AG27
AF24

AH25
AG26
AG24
AG22

AG21
AF22
AF25

AG23
AF23

AH24

NMI

AH22
AF26

AH17
AE17
AF17

AE16
AD16

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

AE15

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_DRQ#0

LPC_FRAME#

GATEA20
H_A20M#

H_CPUSLP_R#
DPRSLP#

H_DPSLP#
H_FERR#
H_PWRGOOD
H_IGNNE#
H_INIT#

H_INTR

KBRST#

H_NMI

R682

0_0402_5%

THRMTRIP_ICH#

PDA0
PDA1
PDA2

PDCS1#
PDCS3#

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

PDDREQ

3

LPC_DRQ#0 <35>

LPC_FRAME# <24,32,33,35>

GATEA20 <33>

H_A20M# <6>

R676
R674 0_0402_5%

R675

H_FERR# <6>
H_PWRGOOD <6>
H_IGNNE# <6>
H_INIT# <6>

H_INTR <6>

R678

KBRST# <33>
H_SMI# <6>

H_NMI <6>

H_STPCLK#

12

1 2

24.9_0402_1%

PDA0 <24>
PDA1 <24>
PDA2 <24>

PDCS1# <24>
PDCS3# <24>

PDDREQ <24>

LPC_AD0 <24,32,33,35>
LPC_AD1 <24,32,33,35>
LPC_AD2 <24,32,33,35>
LPC_AD3 <24,32,33,35>

10K_0402_5%

R673

12

@

0_0402_5%

12
12

56_0402_5%

12

+3VS

10K_0402_5%

12

H_STPCLK# <6>

R683

PDD[0..15]

+3VS

H_CPUSLP# <6,9>
H_DPRSTP# <6,46>

H_DPSLP# <6>

+VCCP

+VCCP

12

R681
56_0402_5%

R683 must be placed close to U9.AF26
within 2" and R681 must be placed close
to R683 within 2".

H_THERMTRIP# <6,9>

PDD[0..15] <24>

2

1

CHGRTC

+RTCVCC

R691

1 2

100_0603_1%

2

C626

0.1U_0402_16V4Z

1

A A

5

4

2

3

BAS40-04_SOT23

D8

BATT1.2

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R690

1 2

511_0603_1%

BATT1.1

W=20mils

BATT1

+-

1 2

RTCBATT

3

Compal Electronics, Inc.(KunShan)

Title

ICH7M2/4-RTC/LPC/IDE/Azalia

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

2

Date: Sheet

1

21 53Monday, January 08, 2007

X 0.5

of

5

4

3

2

1

+3VS

12

12

R702

2.2K_0402_5%

D D

+3VS

C C

+3VALW

B B

A A

R706

R709

R710

R711

R713

R714

ICH_SMBDATA<5,6,15,16,24>
ICH_SMBCLK<5,6,15,16,24>

8.2K_0402_5%

1 2

10K_0402_5%

1 2

8.2K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

ICH_SMBDATA

SB_THERM#

SIRQ

PM_CLKRUN#

LINKALERT#

XDP_DBRESET#

EC_SCI#

R703

2.2K_0402_5%
2N7002_SOT23
Q9

D

S

13

S

G

2

PCIE_WAKE#<24>

G

LAN_WAKE#<28>

D

13

Q10

2

ICH_SMB_DATA
ICH_SMB_CLKICH_SMBCLK

2N7002_SOT23

+3VS

BSS138_NL_SOT23-3

+3V_LAN

R1345

1 2

0_0402_5%

+3VALW +3VALW

+3VALW

D

13

1 2

1 2

12

R697
10K_0402_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10K_0402_5%

1K_0402_5%

S

Q71

PCIE_RXN1<28>
PCIE_RXP1<28>
PCIE_TXN1<28>
PCIE_TXP1<28>

PCIE_RXN2<24>
PCIE_RXP2<24>
PCIE_TXN2<24>
PCIE_TXP2<24>

PCIE_RXN3<24>
PCIE_RXP3<24>
PCIE_TXN3<24>
PCIE_TXP3<24>

R696

R576

G

2

2.2K_0402_5%

+3VALW

SIRQ<25,32,33,35>

EC_THRM#<33>

ICH_SPKR<30>
SUS_STAT#<32,35>
XDP_DBRESET#<6>

PM_BMBUSY#<9>
EC_SCI#<33>
H_STP_PCI#<5>

H_STP_CPU#<5>
EC_FLASH#<34>

IDERST_HD#<24>

PM_CLKRUN#<25,27,32,33,35>

12

R694

R701

1 2

8.2K_0402_5%

SIRQ

D10

VGATE_INTEL<33,46>

M_SEN#<19,36>
USB_SMI#<27>

12
12

12
12

12
12

USB_OC#0<32>
USB_OC#1<32>

USB_OC#4<34>
USB_OC#6<34>

USB_OC#7<34>

12

R695

2.2K_0402_5%

ICH_SMB_CLK
ICH_SMB_DATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

ICH_RI#

ICH_SPKR
SUS_STAT#
XDP_DBRESET#

PM_BMBUSY#

EC_SCI#

H_STP_PCI#
H_STP_CPU#

EC_FLASH#
IDERST_HD#

PM_CLKRUN#

ID0<17>
ID1<17>

ICH_PCIE_WAKE#
SB_THERM#

21

RB751V_SOD323

VGATE_INTEL

M_SEN#
USB_SMI#

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1

C631

PCIE_C_TXP1

C632

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2

C629

PCIE_C_TXP2

C630

PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3

C661

PCIE_C_TXP3

C670

ID0
ID1

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

U9C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0 / BM_BUSY#

B23

GPIO11 / SMBALERT#

AC20

GPIO18 / STPPCI#

AF21

GPIO20 / STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32 / CLKRUN#

AC19

GPIO33 / AZ_DOCK_EN#

U2

GPIO34 / AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7_BGA652~D

U9D

F26

PERn1

F25

PERp1

E28

PETn1

E27

PETp1

H26

PERn2

H25

PERp2

G28

PETn2

G27

PETp2

K26

PERn3

K25

PERp3

J28

PETn3

J27

PETp3

M26

PERn4

M25

PERp4

L28

PETn4

L27

PETp4

P26

PERn5

P25

PERp5

N28

PETn5

N27

PETp5

T25

PERn6

T24

PERp6

R28

PETn6

R27

PETp6

R2

SPI_CLK

P6

SPI_CS#

P1

SPI_ARB

P5

SPI_MOSI

P2

SPI_MISO

D3

OC0#

C4

OC1#

D5

OC2#

D4

OC3#

E5

OC4#

C3

OC5# / GPIO29

A2

OC6# / GPIO30

B3

OC7# / GPIO31

ICH7_BGA652~D

GPIO21 / SATA0GP

SMB

GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

SATA

GPIO

SYS

Clocks

GPIO

GPIO16 / DPRSLPVR

TP0 / BATLOW#

PWRBTN#
LAN_RST#

POWER MGT

GPIO

RSMRST#

GPIO35 / SATAREQ#

Need update symbol

V26

DMI0RXN

V25

DMI0RXP

U28

DMI0TXN

U27

DMI0TXP

Y26

DMI1RXN

Y25

DMI1RXP

W28

DMI1TXN

W27

DMI1TXP

PCI-EXPRESS

DIRECT MEDIA INTERFACE

DMI_IRCOMP

SPI

USB

DMI2RXN

DMI2RXP
DMI2TXN
DMI2TXP

DMI3RXN

DMI3RXP
DMI3TXN
DMI3TXP

DMI_CLKN
DMI_CLKP

DMI_ZCOMP

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

USBP5P

USBP6N

USBP6P

USBP7N

USBP7P

USBRBIAS#

USBRBIAS

AB26
AB25
AA28
AA27

AD25
AD24
AC28
AC27

AE28
AE27

C25
D25

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

D2
D1

R733

AF19

R742

AH18

R743

AH19

R745

AE19

CLK_14M_ICH

AC1

CLK14
CLK48

SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25

GPIO38
GPIO39

CLK_48M_ICH

B2

ICH_SUSCLK

C20

SLP_S3#

B24

SLP_S4#

D23

SLP_S5#

F22

PWROK

AA4

H_DPRSLPVR

AC22

PM_BATLOW#

C21

EC_PBTNOUT#

C23

PLT_RST#

C19

EC_RSMRST#

Y4

R708

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_IRCOMP
USBP0-

USBP0+
USBP1­USBP1+
USBP2­USBP2+
USBP3­USBP3+
USBP4­USBP4+
USBP5­USBP5+
USBP6­USBP6+
USBP7­USBP7+

USBRBIAS

R715

This is only supported USBRBIAS value for the Intel
82801GM and is required to properly configure the
USB interface drive strength.

8.2K_0402_5%

1 2

8.2K_0402_5%

1 2

8.2K_0402_5%

1 2

8.2K_0402_5%

1 2

1 2

R704 10K_0402_5%

10K_0402_5%

1 2

EC_SWI#
EC_SMI#

PID0
PID1

DMI_RXN0 <9>
DMI_RXP0 <9>
DMI_TXN0 <9>
DMI_TXP0 <9>

DMI_RXN1 <9>
DMI_RXP1 <9>
DMI_TXN1 <9>
DMI_TXP1 <9>

DMI_RXN2 <9>
DMI_RXP2 <9>
DMI_TXN2 <9>
DMI_TXP2 <9>

DMI_RXN3 <9>
DMI_RXP3 <9>
DMI_TXN3 <9>
DMI_TXP3 <9>

CLK_PCIE_ICH# <5>
CLK_PCIE_ICH <5>

24.9_0402_1%

1 2

USBP0- <32>
USBP0+ <32>
USBP1- <32>
USBP1+ <32>
USBP2- <24>
USBP2+ <24>
USBP3- <36>
USBP3+ <36>
USBP4- <36>
USBP4+ <36>
USBP5- <36>
USBP5+ <36>
USBP6- <36>
USBP6+ <36>
USBP7- <36>
USBP7+ <36>

R719 22.6_0402_1%

1 2

Within 500 mils

+3VS

CLK_14M_ICH <5>
CLK_48M_ICH <5>

T15 PAD

SLP_S3# <33>
SLP_S4# <33>
SLP_S5# <33>
PWROK <9,33,34>

H_DPRSLPVR <9,46>

EC_PBTNOUT# <33>
PLT_RST# <9,18,20,24,28,32,33,35>
EC_RSMRST# <27,33>

EC_SWI# <33>
EC_SMI# <33>

PID0 <17>
PID1 <17>

Within 500 mils

+1.5VS

CLK_48M_ICH

12

R692
10_0402_5%

@

1

C627

4.7P_0402_50V8C

@

2

if the susclk duty cycle is
beyond the 30-70% range, it
indicate a poor oscillation signal

PM_BATLOW# <33>

R705

12

8.2K_0402_5%

USB_OC#3
USB_OC#0
USB_OC#1
USB_OC#2

USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

RP27

4 5
3 6
2 7
1 8

10K_0804_8P4R_5%

RP29

4 5
3 6
2 7
1 8

10K_0804_8P4R_5%

+3VALW

CLK_14M_ICH

12

R693
10_0402_5%

@

1

C628

4.7P_0402_50V8C

@

2

+3VALW

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

ICH7M3/4-USB/DMI/PCIE/PM/GP

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

22 53Monday, January 08, 2007

X 0.5

5

4

3

2

1

ICH_V5REF_RUN

D D

+3VS+5VS

21

12

+3VALW+5VALW

12

D11
CH751H-40PT_SOD323

ICH_V5REF_RUN

1

C642

0.1U_0402_16V4Z

2

21

D12
CH751H-40PT_SOD323

ICH_V5REF_SUS

1

C650

0.1U_0402_16V4Z

2

+1.5VS

R721

100_0402_5%

R722

C C

10_0402_5%

B B

A A

+1.5VS

Place closely pin AG28 within 100mlis.

R723

1 2

0.5_0805_1%

+3VALW

0.1U_0402_16V4Z

L17

1 2

BLM21PG600SN1D_0805

L18

1 2

BLM18AG601SN1D_0603

+1.5VS

+3VS

1

C665

+1.5VS

2

0.1U_0402_16V4Z

C658

220U_D2_4VM

1

2

10U_0805_10V4Z

C667

1

+

C637

2

0.1U_0402_16V4Z

+1.5VS_DMIPLL+1.5VS_DMIPLLR

C659

0.01U_0402_16V7K

1

C662

2

1

2

C638

1

2

0.1U_0402_16V4Z

1

2

Place closely pin
D28,T28,AD28.

Place closely pin AG5.

Place closely pin AG9.

0.1U_0402_16V4Z

1

C639

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VS

0.1U_0402_16V4Z

+1.5VS

C664

1U_0603_10V4Z

T19 PAD
T20 PAD

+3VALW

ICH_V5REF_SUS

1

C640

2

+3VS

1

C651

2

+1.5VS_DMIPLL

1

C660

2

1

2

ICH_AA2
ICH_Y7

0.1U_0402_16V4Z

C668

G10

AD17

F6

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28

D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22

L23
M22
M23

N22

N23

P22

P23

R22

R23

R24

R25

R26

T22

T23

T26

T27

T28

U22

U23

V22

V23
W22
W23

Y22

Y23

B27

AG28

AB7
AC6
AC7
AD6

AE6

AF5

AF6
AG5
AH5

AD2

AH11
AB10

AB9

AC10
AD10
AE10
AF10

AF9
AG9
AH9

E3
C1

AA2

Y7
V5

V1
W2
W7

1

2

U9F

V5REF[1]
V5REF[2]
V5REF_Sus
Vcc1_5_B[1]

Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc3_3[1]
VccDMIPLL
Vcc1_5_A[1]

Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

VccSATAPLL
Vcc3_3[2]
Vcc1_5_A[10]

Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

VccSus3_3[19]
VccUSBPLL
VccSus1_05/VccLAN1_05[1]

VccSus1_05/VccLAN1_05[2]
VccSus3_3/VccLAN3_3[1]

VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

ICH7_BGA652~D

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]

Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

Vcc3_3 / VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]

Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

VccRTC
VccSus3_3[1]
VccSus3_3[2]

VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]

VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

Vcc1_5_A[19]
Vcc1_5_A[20]

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

Vcc1_5_A[24]
Vcc1_5_A[25]

VccSus1_05[1]
VccSus1_05[2]

VccSus1_05[3]

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

U6
R7
AE23

AE26
AH26

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

W5
P7
A24

C24
D19
D22
G19

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7
C28

G20
A1

H6
H7
J6
J7

+VCCP

C635

1U_0603_10V4Z

ICH_K7
ICH_C28

ICH_G20

0.1U_0402_16V4Z

1

C636

2

1

C647

2

0.1U_0402_16V4Z

1

C652

0.1U_0402_16V4Z

2

1

C656

0.1U_0402_16V4Z

2

+1.5VS

C663

1 2

0.1U_0402_16V4Z

+1.5VS

1

C666

0.1U_0402_16V4Z

2

1

1

+

C634

2

330U_D2E_2.5VM_R9

2

CRB use 270uF

+3VALW

+3VS

1

C645

0.1U_0402_16V4Z

2

1

1

C649

C648

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C653

0.1U_0402_16V4Z

2

1

C657

0.1U_0402_16V4Z

2

T16PAD
T17PAD

T18PAD

+VCCP

+3VS

+3VALW

+3VALW

C643

1 2

0.1U_0402_16V4Z

1 2

C644

0.1U_0402_16V4Z

1 2

C646

4.7U_0805_10V4Z

+3VS

1

C641

0.1U_0402_16V4Z

2

+RTCVCC

1

1

C655

C654

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

A4

A23

B1

B8
B11
B14
B17
B20
B26
B28

C2

C6
C27
D10
D13
D18
D21
D24

E1

E2

E4

E8
E15

F3

F4

F5
F12
F27
F28

G1
G2
G5
G6

G9
G14
G18
G21
G24
G25
G26

H3
H4

H5
H24
H27
H28

J1

J2

J5

J24
J25

J26
K24
K27
K28

L13

L15

L24

L25

L26

M3
M4

M5
M12
M13
M14
M15
M16
M17
M24
M27
M28

N1
N2
N5

N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26

P3

P4
P12
P13
P14
P15
P16
P17
P24
P27

U9E

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]

ICH7_BGA652~D

VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

ICH7M4/4-PWR/GND

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

23 53Monday, January 08, 2007

X 0.3

5

+3VS

MOTION<33>
F_FALL<33>

D D

1

C685

C686

0.1U_0402_16V4Z

2

C C

B B

22P_0402_50V8J

A A

MOTION G_CK2

F_FALL G_DA2 SMB_EC_DA2

1

1

C684

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

2

SMB_EC_CK1<33,34,39>

SMB_EC_DA1<33,34,39>

SMB_EC_DA1

CLK_DEBUG_PORT

12

R966

@

33_0402_5%

1

@

C933

2

SMB_EC_CK2<6,33,36,39>

SMB_EC_DA2<6,33,36,39>

U56

1

GND

2

VDD

3

MOTION

4

FF

5

Output X

6

Output Z
Output Y7RESET

1

KXP84-2050_DFN14

C683

0.1U_0402_16V4Z

SM BUS Addr. 0011 000

2

SMB_EC_CK1

Q54

+5VS

Q57

D

S

2N7002_SOT23

G

2

+5VS

SMB_EC_CK2

SMB_EC_DA2

D

1 3

+5VS

10K_0402_5%

Q56

D

1 3

1 3

SMB_EC_DA1

1 3

Thermal_Pad

SCL/SCLK

SDA/SDO

ADDR0/SDI

10K_0402_5%

Q55

D

1 3

G

2

+5VS

S

2N7002_SOT23

G

2

R959

S

2N7002_SOT23

G

2

10K_0402_5%

Q20
2N7002_SOT23

D

1 3

G

2

+5VS

Q22

2N7002_SOT23

D

S

G

2

+5VS

2N7002_SOT23

+3VS

12

12

R730

R725

IO VDD

R955

S

EC_CK1

15
14

NC

13
12
11
10
9

CS#

8

+5VS

1 2

4.7K_0402_5%

4.7K_0402_5%

R968

1 2

C687 10U_0805_10V4Z

R720

8.2K_0402_5%

1 2

R913

10K_0402_5%

1 2

4
5

10K_0402_5%

12

U54

SCLK
SDA

TC74A1-5.0VCT_SOT23-5

SM BUS Addr. 1001 001

Thermal Sensor for inverter

EC_DA1

+5VS

R958
10K_0402_5%

1 2

1 2

SDA

SCLKSMB_EC_CK1

U14

1

SDA

2

SCLK

3

ALERT

4

GND

MCP9803T-M/MSG_MSOP8

SM BUS Addr. 1001 110

Thermal Sensor for CPU, Place near the CPU

+5VS

S

R902

EC_CK2

EC_DA2

1 2

R903
10K_0402_5%

1 2

4
5

TC74A1-5.0VCT_SOT23-5

SM BUS Addr. 1001 001

4

SCLK

5

SDA

TC74A2-5.0VCT_SOT23-5

SM BUS Addr. 1001 010

Thermal Sensor for SO-DIMM

5

VDD
GND

SCLK
SDA

4

Q61

D

S

S

+3VS

+5VS

3
2
1

NC

8

VDD

7

A0

R728

6

A1

R957

5

A2

R956 10K_0402_5%

U35

3

VDD

2

GND

1

NC

U36

3

VDD

2

GND

1

NC

4

13

G

2N7002_SOT23

2

+3VS

Q69

D

13

G

2N7002_SOT23

2

+3VS

0.1U_0402_16V4Z

1 2

C927

+5VS

1 2

1 2

0_0402_5%

10K_0402_5%

+5VS

1 2

+5VS

1 2

SMB_EC_CK2

C928

0.1U_0402_16V4Z

12
12

C877

0.1U_0402_16V4Z

C878

0.1U_0402_16V4Z

PLT_RST#<9,18,20,22,28,32,33,35>

IDERST_HD#<22>

SMB_EC_CK1
SMB_EC_DA1

SM BUS Addr. 1001 010

Thermal Sensor for charger

+5VS

UIM_VPP

UIM_DATA UIM_CLK

C682 4.7U_0805_10V4Z

12

UIM_VCC

12

@

C749 0.1U_0402_16V4Z

UIM_RST
UIM_VPP
UIM_CLK

D5

UIM_DATA

3

+3VS

DAN217_SC59

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

UIM_PWR

1

2

3

PIDERST#

R752

1 2

PDIOR#<21>
PDA0<21>
PDCS3#<21>
PDA1<21>

+3VS

+3VS

C669

12

0.1U_0402_16V4Z

5

U12

1

P

B

2

A

G

TC7SH08FUF_SSOP5

3

R726

1 2

0_0402_5%@

U55

4

VDD

SCLK

5

GND

SDA

NC

TC74A2-5.0VCT_SOT23-5

Symbol update

D2

1
2

6

CH1

CH4

5

Vn

Vp

4

CH23CH3

NUP4301MR6T1G_TSOP6

JP9

1

VCC(C1)

2

GND(C5)

3

RST(C2)

4

VPP(C6)

5

CLK(C3)

6

I/O(C7)

7

SW1

8

SW2

9

GND1

10

GND2

YAMAI_FMS006Z-2101-0

LPC_FRAME#<21,32,33,35>
LPC_AD0<21,32,33,35>
LPC_AD1<21,32,33,35>
LPC_AD2<21,32,33,35>
LPC_AD3<21,32,33,35>

PLT_RST#<9,18,20,22,28,32,33,35>

3

PDD[0..15]<21>

JP10

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

SUYIN_127212FA040G200ZX

PCIE_RXN3
PCIE_RXP3

Y

3
2
1

R724

4

1 2

@

10K_0402_5%

PIDERST#

+5VALW

22_0402_5%

PDD7
PDD5
PDD6
PDD3
PDD15
PDD9

PDD0
PDD4
PDD2
PDD1

PDIOR#
PDA0

PDA1

PCIE_RXN3<22>
PCIE_RXP3<22>

C924

1 2

0.1U_0402_16V4Z

Wireless SW

+3VS

UIM_RST

PCIE_RXN2<22>
PCIE_RXP2<22>

R777

1 2

R778
R779 0_0402_5%
R781 0_0402_5%DB@
R782 0_0402_5%
R783 0_0402_5%

1 2
1 2
1 2

1 2

1 2

DB@
DB@

DB@
DB@

add these for Port 80H debug card

0_0402_5%DB@

0_0402_5%

DB_LPC_FRAME#

DB_LPC_AD0
DB_LPC_AD1
DB_LPC_AD2
DB_LPC_AD3
DB_LPC_RST#

PDD[0..15]

PCIE_WAKE#<22>

CLKREQA#<5>

CLK_PCIE_WAN#<5>
CLK_PCIE_WAN<5>

R786 0_0402_5%

1 2
1 2

R785 0_0402_5%

PCIE_TXN3<22>
PCIE_TXP3<22>

WL_SW#

2

3

D38
PSOT24C-LF_T7_SOT23-3

1

PCIE_WAKE#<22>
WLAN_ACTIVE<27>

BT_ACTIVE<27>
CLKREQB#<5>

CLK_PCIE_MINI#<5>
CLK_PCIE_MINI<5>

CLK_DEBUG_PORT<5>

R773

1 2

PCIE_RXP2

1 2

R774 0_0402_5%

PCIE_TXN2<22>
PCIE_TXP2<22>

2

PDD10
PDD11
PDD12

PDDREQ
PDIOW#
PDD8

PDDACK#
PDD13
PDCS1#
PDD14

PDIORDY
IDEIRQ
PDA2PDCS3#

PCSEL

R727 470_0402_5%

PCIE_WAKE#

CLKREQA#

CLK_PCIE_WAN#
CLK_PCIE_WAN

PCIE_C_RXN3
PCIE_C_RXP3

PCIE_TXN3
PCIE_TXP3

+3VS

PCIE_WAKE#

WLAN_ACTIVE
BT_ACTIVE

CLKREQB#

CLK_PCIE_MINI#
CLK_PCIE_MINI

DB_LPC_RST#
CLK_DEBUG_PORT

0_0402_5%

PCIE_C_RXN2PCIE_RXN2
PCIE_C_RXP2

PCIE_TXN2
PCIE_TXP2

2

Place caps. near HDD
CONN.

Layout Note: +VPHDD trace
width 60 mil

500mA

1

C675

10U_0805_10V4Z

2

R729

5.6K_0402_5%@

12

33P_0402_50V8J

C673

1 2

PDDREQ <21>
PDIOW# <21>

PDDACK# <21>
PDCS1# <21>

PDIORDY <21>
IDEIRQ <21>

PDA2 <21>

+3VS

1

C674

2

1000P_0402_50V7K

Mini-Express Card---WWAN

JP28

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S52N-7F~N

WL_SW#

WL_SW#<33>

MOLEX_53780-0290

GND2

1
2

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8

JP14

2
4
6

UIM_PWR

8

UIM_DATA

10

UIM_CLK

12

UIM_RST

14

UIM_VPP

16
18

WWANOFF#

20
22
24
26
28
30
32
34

USBP2-

36

USBP2+

38
40
42
44
46
48
50
52

54

1
2

WWANOFF# <33>
PLT_RST# <9,18,20,22,28,32,33,35>

+3V_LAN

ICH_SMBCLK <5,6,15,16,22>

ICH_SMBDATA <5,6,15,16,22>

USBP2- <22>
USBP2+ <22>

Place C37 close to JP28

Mini-Express Card ---WLAN

JP13

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX_AS0B226-S52N-7F~N

2

2

4

4

6

6

DB_LPC_FRAME#

8

8

DB_LPC_AD3

10

10

DB_LPC_AD2

12

12

DB_LPC_AD1

14

14

DB_LPC_AD0

16

16

18

18

WLANOFF#

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

NEC_USBP1-

36

36

NEC_USBP1+

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

GND2

Compal Electronics, Inc.(KunShan)

Title

MINI Card Slot/PIDE&Thermal sensor

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

WLANOFF# <33>
PLT_RST# <9,18,20,22,28,32,33,35>

+3V_LAN

ICH_SMBCLK <5,6,15,16,22>

ICH_SMBDATA <5,6,15,16,22>

NEC_USBP1- <27>
NEC_USBP1+ <27>

1

12

+3VS

1

+

2

1

1

C676

0.1U_0402_16V4Z

2

PDDREQ

+1.5VS +3VS

C37
330U_D3L_6.3VM_R25M

of

24 53Monday, January 08, 2007

+3VS+1.5VS

X 0.5

5

Layout notice:
apply shield GND
for CLK_PCI_PCM to
reduce external noise.

CLK_PCI_PCM

D D

R26

100K_0402_5%

C C

B B

Pull down UDIO4 to
disable MS function

A A

+3VS

12

1

2

PCM_CLK_EN#<33>

12

R744
10_0402_5%

@

1

C706
15P_0402_50V8J

2

@

GBRST#

C27
1U_0402_6.3V6K

PCI_C/BE#3<20,27>
PCI_C/BE#2<20,27>
PCI_C/BE#1<20,27>
PCI_C/BE#0<20,27>

PCI_PAR<20,27>

PCI_FRAME#<20,27>
PCI_TRDY#<20,27>
PCI_IRDY#<20,27>
PCI_STOP#<20,27>
PCI_DEVSEL#<20,27>

PCI_PERR#<20,27>
PCI_SERR#<20,27>

PCI_REQ2#<20>
PCI_GNT2#<20>

PCI_RST#<20,27>

PM_CLKRUN#<22,27,32,33,35>

+3V_R5C843

PCM_PME#<34>
PCM_SPK#<30>
HWSPND#<33>

+3V_R5C843

CLK_PCI_PCM<5>

CLK_PCI_PCM CLK_PCI_PCM_R

1 2

R28 0_0402_5%

1 2

R29 100K_0402_5%@

PCI_PIRQA#<20>
PCI_PIRQC#<20>

PCM_PME#
PCM_SPK#

1 2

R33

1 2

R27

PCM_CLK_EN#

CLK_PCI_PCM

1 2

R60

5

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0

PCI_PAR

PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#

CB_IDSEL

PCI_PERR#

PCI_SERR#

PCI_REQ2#
PCI_GNT2#

CLK_PCI_PCM_R

PCI_RST#
GBRST#

SIRQ<22,32,33,35>

R46

10K_0402_5%

1 2
1 2

10K_0402_5%

R45

1 2

0_0402_5%

R34

10K_0402_5%
100K_0402_5%

U48

1

OE#

2

A

3

GND

SN74CBTD1G125_SC70-5

0_0402_5%@

U15A

M2

AD31

M1

AD30

N5

AD29

N4

AD28

N2

AD27

N1

AD26

P5

AD25

P4

AD24

R4

AD23

R2

AD22

R1

AD21

T2

AD20

T1

AD19

U2

AD18

U1

AD17

V1

AD16

T7

AD15

V7

AD14

W7

AD13

R8

AD12

T8

AD11

V8

AD10

W8

AD9

R9

AD8

V9

AD7

W9

AD6

T11

AD5

V11

AD4

W11

AD3

T12

AD2

V12

AD1

W12

AD0

P2

C/BE3#

W2

C/BE2#

W6

C/BE1#

T9

C/BE0#

V6

PAR

V3

FRAME#

W4

TRDY#

V4

IRDY#

V5

STOP#

T5

DEVSEL#

P1

IDSEL

W5

PERR#

T6

SERR#

M4

REQ#

M5

GNT#

K1

PCICLK

L4

PCIRST#

G2

GBRST#

L5

CLKRUN#

J2

INTA#

K4

INTB#

K2

INTC#

J4

UDIO0/SERIRQ#

H1

UDIO1

H2

UDIO2

H4

UDIO3

H5

UDIO4

G1

UDIO5

G4

RI_OUT#/PME#

F1

SPKROUT

F2

HWSPND#

F4

TEST

R5C843-CSP208P_CSP208~D

+5VS

5

VCC

CLK_PCI_PCM_R

4

B

R5C843

CSTSCHG/BVD1(STSCHG#/RI#)

CCLKRUN#/WP(IOIS16#)

CAUDIO/BVD2(SPKR#/LED)

SI1303DL-T1-E3_SOT323-3~D @

4

CAD31/CDATA10

CAD30/CDATA9
CAD29/CDATA1
CAD28/CDATA8
CAD27/CDATA0

CAD26/CADR0
CAD25/CADR1
CAD24/CADR2
CAD23/CADR3
CAD22/CADR4
CAD21/CADR5
CAD20/CADR6

CAD19/CADR25

CAD18/CADR7
CAD17/CADR24
CAD16/CADR17

CAD15/IOWR#

CAD14/CADR9

CAD13/IORD#

CAD12/CADR11

CAD11/OE#

CAD10/CE2#

CAD9/CADR10
CAD8/CDATA15

CAD7/CDATA7
CAD6/CDATA13

CAD5/CDATA6
CAD4/CDATA12

CAD3/CDATA5
CAD2/CDATA11

CAD1/CDATA4

CAD0/CDATA3

CC/BE3#/REG#

CC/BE2#/CADR12

CC/BE1#/CADR8

CC/BE0#/CE1#

CPAR/CADR13

CFRAME#/CADR23

CTRDY#/CADR22

CIRDY#/CADR15

CSTOP#/CADR20

CDEVSEL#/CADR21

RESERVED/CADR19

CPERR#/CADR14

CSERR#/WAIT#

CREQ#/INPACK#

CGNT#/WE#

CCLK/CADR16

CINT#/RDY(IREQ#)

CRST#/RESET

CCD1#/CD1#
CCD2#/CD2#

CVS1/VS1#
CVS2/VS2#

RESERVED/CDATA14

RESERVED/CDATA2
RESERVED/CADR18

PCM_CLK_EN#

4

S1_D10

B19

S1_D9

C18

S1_D1

D19

S1_D8

D18

S1_D0

E19

S1_A0

E16

S1_A1

F18

S1_A2

F15

S1_A3

G18

S1_A4

G15

S1_A5

H18

S1_A6

H15

S1_A25

J18

S1_A7

J16

S1_A24

J15

S1_A17

P16

S1_IOWR#

P19

S1_A9

R19

S1_IORD#

P18

S1_A11

R18

S1_OE#

T19

S1_CE2#

T18

S1_A10

U19

S1_D15

U18

S1_D7

W17

S1_D13

V17

S1_D6

W16

S1_D12

V16

S1_D5

W15

S1_D11

V15

S1_D4

T15

S1_D3

R14

S1_REG#

F16

S1_A12

K18

S1_A8

P15

S1_CE1#

V19

S1_A13

N15

S1_A23

K16

S1_A22

L16

S1_A15

K15

S1_A20

M16

S1_A21

L18

S1_A19

N19

S1_A14

N18

S1_WAIT#

G16

S1_INPACK#

G19

S1_WE#

M15

S1_BVD1

E18

S1_WP

A18

S1_A16

L19

S1_RDY#

M18

S1_RST

H19

S1_BVD2

F19

S1_CD1#

T14

S1_CD2#

D15

S1_VS1

R16

S1_VS2

H16

S1_D14

W18

S1_D2

C19

S1_A18

N16

1 2

R451 0_0402_5%

Q67

D

S

1 3

G

2

3

PCI_AD[0..31]<20,27>

S1_A[0..25]

S1_D[0..15]

USB signals, impedance 90 ohm

S1_IOWR# <26>
S1_IORD# <26>
S1_OE# <26>

S1_CE2# <26>

S1_REG# <26>

S1_CE1# <26>

S1_WAIT# <26>
S1_INPACK# <26>
S1_WE# <26>
S1_BVD1 <26>
S1_WP <26>

S1_RDY# <26>

S1_RST <26>

0.01U_0402_25V4Z

1 2

C71

S1_BVD2 <26>

S1_VS1 <26>

S1_VS2 <26>

0.01U_0402_25V4Z

PCI_AD20_R PCI_AD20CB_IDSEL

1 2

R848 100_0402_1%

+3VS

S1_CD1#
SD_DET#

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

1

P

B

2

A

G

3

S1_A[0..25] <26>

S1_D[0..15] <26>

Layout notice: apply Shield GND
for L19 signal S1_A16

C71,C188, C208 close to
JP33 cardbus connector

S1_CD1# <26>

270P_0402_50V7K

10K_0402_5%

R36

1 2

S1_CD2# <26>

CARD_INSERT# <33>

270P_0402_50V7K

@

2

2

@

C208

C188

1

1

1

C30

2

U49

CARD_INSERT#

4

Y

TC7SH08FUF_SSOP5

3

C8

NEC_USBP0+<27>
NEC_USBP0-<27>

VCC5EN#<26>

+3V_R5C843

VCC3EN#<26>

10U_0805_6.3V4Z

1

C7

2

+3V_R5C843

@

C9

VPPEN0<26>
VPPEN1<26>

R50

100K_0402_5%

0.01U_0402_25V4Z

1

2

1

2

C6

10U_0805_6.3V4Z

C15

+3V_R5C843

NEC_USBP0+

NEC_USBP0-

VPPEN0
VPPEN1

VCC5EN#
VCC3EN#

12

1

2

1

2

0.01U_0402_25V4Z

C5

0.1U_0402_16V7K

C14

C25

12

100K_0402_5%

+3V_R5C843

10U_0805_6.3V4Z

1

C4

2

0.01U_0402_25V4Z

0.01U_0402_25V4Z

1

1

C18

C23

2

2

0.01U_0402_25V4Z

0.01U_0402_25V4Z

1

1

C13

2

2

0.01U_0402_25V4Z

0.01U_0402_25V4Z

1

1

C24

2

2

U15B

D11

CPS

A16

XI

B16

XO

A14

FIL0

B12

TPAP0

A12

TPAN0

B13

TPBP0

A13

TPBN0

B10

TPAP1

A10

TPAN1

B11

TPBP1

A11

TPBN1

D12

TPBIAS0

D10

TPBIAS1

D13

VREF

B14

REXT

V14

USBDP

W14

USBDM

V13

VPPEN0

W13

VPPEN1

R13

VCC5EN#

T13

VCC3EN#

R7

REGEN#

R5C843-CSP208P_CSP208~D

R24

2

+3VS +3V_R5C843

1 2

R445 0_0805_5%

0.01U_0402_25V4Z

0.01U_0402_25V4Z

1

C2

C3

2

0.01U_0402_25V4Z

1

2

1

C506

2

0.47U_0603_10V7K

R5C843

2

0.01U_0402_25V4Z

1

C17

2

+3V_R5C843

MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

0.01U_0402_25V4Z

1

2

B1
A2
A3
B3
B4
A5
B5
D5
A6
B6
D6
E6
A7
B7
D7
E7
A8
B8
D8
E8

1

C1

2

1

C505

2

0.47U_0603_10V7K

1

U15C

F5

VCC_3V1

G5

VCC_3V2

J19

VCC_3V3

K19

VCC_3V4

R5C843

W3

VCC_PCI3V1

R11

VCC_PCI3V2

R12

VCC_PCI3V3

A4

VCC_MD3V

R6

VCC_RIN1

E13

VCC_RIN2

L1

VCC_ROUT1

E14

VCC_ROUT2

E10

AVCC_PHY1

E11

AVCC_PHY2

A17

AVCC_PHY3

B17

AVCC_PHY4

A9

AGND1

B9

AGND2

D9

AGND3

D14

AGND4

A15

AGND5

B15

AGND6

J1

GND1

J5

GND2

K5

GND3

E9

GND4

R10

GND5

T10

GND6

V10

GND7

W10

GND8

L15

GND9

M19

GND10

R5C843-CSP208P_CSP208~D

SD_DET#

SD_WP#
SD_PWREN

EXT_48M
MDIO08 SD_CMD

MDIO10
MDIO11
MDIO12
MDIO13

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

0_0402_5%

R31

1 2
1 2

12

33_0402_5%

12

33_0402_5%

12

33_0402_5%

12

33_0402_5%

12

33_0402_5%

12

33_0402_5%

1 2

C359 100P_0402_50V8J

1 2

C360 100P_0402_50V8J

1 2

C361 100P_0402_50V8J

1 2

C362 100P_0402_50V8J

1 2

C363 100P_0402_50V8J

CLK_48M_SD

12

R699
10_0402_5%

@

1

C679

4.7P_0402_50V8C

@

2

0_0402_5%@

SD_CLK_RSD_CLK
SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3

R480
R30
R472

R473
R478
R479

R32

CARDBUS_R5C843

PecosII-IDX80-LA3291

1

SD_DET# <26>

SD_WP# <26>
SD_PWREN <26>

CLK_48M_SD <5>

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9

SD_CMD <26>

SD_CLK_R <26>

SD_DAT0 <26>
SD_DAT1 <26>
SD_DAT2 <26>
SD_DAT3 <26>

of

25 53Monday, January 08, 2007

L2
C1
D1
E1
C2
D2
E2
E4
E12

X 0.5

5

4

3

2

1

CARDBUS SOCKET

S1_A[0..25]

S1_D[0..15]

S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_CE1#
S1_A10
S1_OE#
S1_A11
S1_A9
S1_A8
S1_A13
S1_A14
S1_WE#
S1_RDY#

S1_A16
S1_A15
S1_A12
S1_A7
S1_A6
S1_A5
S1_A4
S1_A3
S1_A2
S1_A1
S1_A0
S1_D0
S1_D1
S1_D2
S1_WP S1_CD2#

1

0.1U_0402_16V7K

2

VPPEN1<25>
VPPEN0<25>

VCC3EN#

VCC3EN#<25>

VCC5EN#

VCC5EN#<25>

JP33

1

1

35

2

2

36

3

3

37

4

4

38

5

5

39

6

6

40

7

7

41

8

8

42

9

9

43

10

10

44

11

11

45

12

12

46

13

13

47

14

14

48

15

15

49

16

16

50

17

17

51

18

18

52

19

19

53

20

20

54

21

21

55

22

22

56

23

23

57

24

24

58

25

25

59

26

26

60

27

27

61

28

28

62

29

29

63

30

30

64

31

31

65

32

32

66

33

33

67

34

34

68

FCI_62597-00B_RB

U26

11

VCC3IN

VCCOUT
VCCOUT

13

VCC5IN

VCCOUT

15

VCC5IN

VPPOUT

6

NC

4

EN1

3

EN0

2

VCC3_EN

1

VCC5_EN

R5531V002-E2-FA_SSOP16

FLG

GND

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

NC
NC

14

10U_0805_6.3V4Z

12
9

8

10
7

5
16

S1_CD1#
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15
S1_CE2#
S1_VS1
S1_IORD#
S1_IOWR#
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21

S1_A22
S1_A23
S1_A24
S1_A25
S1_VS2
S1_RST
S1_WAIT#
S1_INPACK#
S1_REG#
S1_BVD2
S1_BVD1
S1_D8
S1_D9
S1_D10

+S1_VCC

1

C11

2

1

C36

2

0.1U_0402_16V7K

S1_CD1# <25>

S1_CE2# <25>

S1_VS1 <25>

S1_IORD# <25>

S1_IOWR# <25>

+S1_VCC
+S1_VPP

S1_VS2 <25>
S1_RST <25>
S1_WAIT# <25>
S1_INPACK# <25>
S1_REG# <25>
S1_BVD2 <25>
S1_BVD1 <25>

S1_CD2# <25>

1

C10

0.01U_0402_25V4Z

2

+S1_VPP

1

C12

0.01U_0402_25V4Z

2

SD_CLK_R<25>

10P_0402_50V8J

Close to SD socket

C371

1

2

SD_CLK_R

SD SOCKET

+SD_VCC

JP32

SD_DAT2<25>
SD_DAT3<25>

SD_CMD<25>

SD_DAT0<25>
SD_DAT1<25>

SD_DET#<25>

SD_WP#<25>

+3V_R5C843

Q15

5

IN

SD_PWREN<25>

4

ON/OFF#

AAT4250IGV-T1_SOT23-5

OUT
GND

1
2
3

N.C

Closer to JP32

9

SD5

1

SD1

2

SD2

3

Vss1

4

Vdd

5

SDCLK

6

Vss2

7

SD3

8

SD4
MMC_DET#10Wr_Pt_Vss

MOLEX_67600-0001

+SD_VCC

12

R643

C40

1

C35

1

150K_0402_5%

0.1U_0402_16V7K

1U_0402_6.3V6K

2

2

14

Wr_Pt

13

Vss4

12

Vss3

11

S1_CE1#<25>
S1_OE#<25>

S1_WE#<25>
S1_RDY#<25>

S1_WP<25>

+5VS

1

0.1U_0402_16V7K

2

S1_A[0..25]<25>

S1_D[0..15]<25>

+S1_VCC
+S1_VPP

C41

+3VS

D D

C C

B B

C38

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

PCMCIA Slot/SD

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

26 53Monday, January 08, 2007

X 0.5

5

NEC_USBP1+
NEC_USBP1­NEC_USBP0+
NEC_USBP0-

NEC_USBP3+

D D

NEC_USBP3­NEC_USBP2+
NEC_USBP2-

SI1303DL-T1-E3_SOT323-3~D @

C C

USB_CLK_EN#<33>

USB_CLK_EN#<33>

B B

RP54

1 8
2 7
3 6
4 5

15K_1206_8P4R_5%

RP55

1 8
2 7
3 6
4 5

15K_1206_8P4R_5%

1 2

R452

0_0402_5%

Q68

D

S

1 3

G

2

USB_CLK_EN#

USB_CLK_EN#

CLK_PCI_USB<5>

CLK_48M_USB<5>

CLK_PCI_USB

SN74CBTD1G125_SC70-5

CLK_PCI_USB CLK_PCI_USB_R

CLK_48M_USB CLK_48M_USB_R

1 2

R75

USB_CLK_EN#

CLK_48M_USB

1 2

R74 0_0402_5%

0_0402_5%@

SN74CBTD1G125_SC70-5

@

CLK_48M_USB

12

R698
10_0402_5%

@

1

C678

4.7P_0402_50V8C

@

2

VCC

VCC

B

100_0402_1%

5

4

B

5

4

R856

PCI_AD21

12

+5VS

CLK_PCI_USB_R

+5VS

CLK_48M_USB_R

PCI_AD21_RUSB_IDSEL

U50

1

OE#

2

A

3

GND

U53

1

OE#

2

A

3

GND

BT MODULE CONN

+3VS

C742

1 2

0.1U_0402_16V4Z

BT_ACTIVE<24>

WLAN_ACTIVE<24>

BTDIS#<33>

A A

BT_ACTIVE
NEC_USBP2+
NEC_USBP2-

WLAN_ACTIVE

Bluetooth Cable

Mini Card Pin5

Mini Card Pin3

BT_ACTIVE JP27.1

WLAN_ACTIVE JP27.4

5

JP15

1
2
3
4
5
6
7
8

MOLEX_53780-0890

4

CLK_PCI_USB

NEC_USBP4-

NEC_USBP4+

NEC_USB_OC#0
NEC_USB_OC#1
NEC_USB_OC#2
NEC_USB_OC#3

NEC_USB_OC#4

EC_RSMRST#<22,33>

4

12

R748
10_0402_5%

@

1

C707
15P_0402_50V8J

2

@

R322

1 2

15K_0402_5%

R323

1 2

15K_0402_5%

RP30

4 5
3 6
2 7
1 8

10K_0804_8P4R_5%

R324

1 2

10K_0402_5%

EC_RSMRST#

PCI_RST#

PM_CLKRUN#<22,25,32,33,35>

3

1

C72

2

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

VCCRST#

0_0402_5%

+3V_NECUSB

0.1U_0402_16V4Z

2

@

1

A6
B6
C5
A5
C4
B5
A4
B4
C1
C2
D2
D1
D3
E1
E3
F2

J1

J2
K3
K1

L3
K2

L1

L2
M1
N3
M3
N4
P4
N5
P5
M5

C3
F1

J3
M2

J4
F3
F4
G1
G3
B3
G2
C6
D6
H2
H1
C7
B7
A7
A8
B8
D9

L6

L7

P6
M6

C9

N6

R313
0_0402_5%

@

1 2

2

0.1U_0402_16V4Z

C356

1

C350

0.1U_0402_16V4Z

U27

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

CBE3#
CBE2#
CBE1#
CBE0#

PAR
FRAME#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
REQ0#
GNT0#
PERR#
SERR#
INTA#
INTB#
INTC#
PCLK
VBBRST#
PME#

SMI#
LEGC

N.C.
N.C

VCCRST#

CRUN#

2

C352

1

H3

M4

C8

VDD_PCI

VDD_PCI

VDD_PCI

USB 2.0 CONTROLLER
uPD720101F1-EA8
FBGA144

VSS

VSS

VSS

VSS

VSS

B1

N1

P10

B14

N14

H14

R826

1 2

+3VS

0_0805_5%

+3V_NECUSB

PCI_AD[0..31]<20,25>

+3V_NECUSB

+3V_NECUSB

PCI_C/BE#3<20,25>
PCI_C/BE#2<20,25>
PCI_C/BE#1<20,25>
PCI_C/BE#0<20,25>

PCI_PAR<20,25>
PCI_FRAME#<20,25>
PCI_IRDY#<20,25>
PCI_TRDY#<20,25>
PCI_STOP#<20,25>

PCI_DEVSEL#<20,25>
PCI_REQ0#<20>
PCI_GNT0#<20>
PCI_PERR#<20,25>
PCI_SERR#<20,25>
PCI_PIRQE#<20>
PCI_PIRQF#<20>

1 2

0_0402_5%@

R321

1 2

R320

0_0402_5%

USB_SMI#<22>

PCI_RST#<20,25>

USB_SMI#

+3V_NECUSB

PCI_RST#

PM_CLKRUN#

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCI_PIRQG#<20>

USB_PME#<34>

R344
R345

R342

R343

R346

1 2

R312

@

10U_0805_6.3V4Z

1.5K_0402_5%

12

1.5K_0402_5%

12

1.5K_0402_5%

12
12

1.5K_0402_5%

1.5K_0402_5%

12

@

0_0402_5%

1 2

R314

PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0

PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
USB_IDSEL
PCI_DEVSEL#
PCI_REQ0#
PCI_GNT0#
PCI_PERR#
PCI_SERR#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
CLK_PCI_USB_R

VBBRST#

USB_PME#

3

0.1U_0402_16V4Z

VSS

2

R260

1 2

0_0603_5%

10U_0805_6.3V4Z

2

C353

1

P2

P3

P12

A13

A12

A3

VDD

VDD

VDD

VDD

VDD

VDD

VSS

VSS

VSS

VSS

VSS

VSS

A2

B2

N2

B13

N13

M11

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

E2

N8

L13

VDD

VDD

VDD

VSS

VSS

VSS

L12

D12

H12

C354

J13

G4

VDD

VSS

C355

1

USB_AVDD

D7

G12

H13

F13

D13

H4

N10

N12

VDD

VDD

VDD

VDD

VDD

VDD

AVDD

AVDD

NANDTEST

VSS

AVSS

VSS

VSS

J11

F11

AVSS

D8

P13

M12

AVSS

2

10U_0805_6.3V4Z

2

2

1

1

2

XT1/SCLK

AVSS(R)

NTEST1

SRMOD

C77

RSDM1

DM1
DP1

RSDP1

RSDM2

DM2
DP2

RSDP2

RSDM3

DM3
DP3

RSDP3

RSDM4

DM4
DP4

RSDP4

RSDM5

DM5
DP5

RSDP5

RREF

OCI1
OCI2
OCI3
OCI4
OCI5

PPON1
PPON2
PPON3
PPON4
PPON5

SMC

AMC

TEB

TEST

SRCLK

SRDTA

C78

2

R261

1 2

0_0603_5%

CLK_48M_USB_R

L9
P8

NEC_USBP0-_R

M14

NEC_USBP0-

M13

NEC_USBP0+

L14

NEC_USBP0+_R

K13

NEC_USBP1-_R

K14

NEC_USBP1-

K12

NEC_USBP1+

J14

NEC_USBP1+_R

J12

NEC_USBP2-_R

H11

NEC_USBP2-

G11

NEC_USBP2+

G13

NEC_USBP2+_R

G14

NEC_USBP3-_R

F12

NEC_USBP3-

F14

NEC_USBP3+

E12

NEC_USBP3+_R

E14

NEC_USBP4-_R

E13

NEC_USBP4-

D14

NEC_USBP4+

C13

NEC_USBP4+_R

C14

P11
N11

B12
B11
B10
A10
B9

C12
A11
C11
C10
A9

M8
M7

P7
N7
L8
M10

M9
N9
P9

1 2

R73

USB_AVDD

2

C351

@
1
2

@

1

NEC_USB_OC#0
NEC_USB_OC#1
NEC_USB_OC#2
NEC_USB_OC#3
NEC_USB_OC#4

R341

R340

0.1U_0402_16V4Z

C349

0.1U_0402_16V4Z

XT2

uPD720101F1-EA8-A_FBGA144

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

2

0.1U_0402_16V4Z
C357

1

@

0_0402_5%
R318 36_0603_1%

1 2

R319 36_0603_1%

1 2

R304 36_0603_1%

1 2

R305 36_0603_1%

1 2

R306 36_0603_1%

1 2

R307 36_0603_1%

1 2

R308 36_0603_1%@

1 2

R309 36_0603_1%@

1 2

R310

1 2

R311 36_0603_1%@

1 2

R329

1 2

9.1K_0402_1%

AVSS

+3V_NECUSB

1.5K_0402_5%

12
12

1.5K_0402_5%

BT&USB CONTROLLER

PecosII-IDX80-LA3291

1

USB_AVDD

10U_0805_6.3V4Z

10U_0805_6.3V4Z

C358

1

1

C79

C80

2

2

AVSS

NEC_USBP0- <25>
NEC_USBP0+ <25>

NEC_USBP1- <24>
NEC_USBP1+ <24>

+3VS

ACES_85201-0405

@

1
2
3
4

JP29

X 0.5

of

1

27 53Monday, January 08, 2007

2

0.1U_0402_16V4Z

1

36_0603_1%@

5

4

3

2

1

12

1

C48

12

1

C50

4.7U_0805_10V4Z

1

C54

0.1U_0402_16V4Z

2

+3V_LAN

3

Q50

BCP69_SOT223

2

4

1

2

+3V_LAN

3

2

4

1

2

+3V_LAN

2

1

2

C57

0.1U_0402_16V4Z

1

PLACE PNP TO CHIP ACAP
CTRL12 PIN TRACE IS
25MIL

40mil

1

+1.2V_LAN

C73

0.1U_0402_16V4Z

2

PLACE PNP TO CHIP ACAP
CTRL25 PIN TRACE IS
25MIL

Q53

BCP69_SOT223

40mil

+2.5V_LAN

1

C51

0.1U_0402_16V4Z

2

C55

0.1U_0402_16V4Z

+LAN_AVDDL

R288

0_0603_5%

2

C58

0.1U_0402_16V4Z

1

+2.5V_LAN

12

+LAN_AVDD

R289

0_0603_5%

12

2

C49

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

C46

PCIE_RXP1<22>
PCIE_RXN1<22>
PCIE_TXP1<22>
PCIE_TXN1<22>

CLK_PCIE_LAN<5>

CLK_PCIE_LAN#<5>

D D

+3V_LAN

12

R47

4.7K_0402_5%

LAN_WAKE#<22>

C C

LAN_WAKE#

1

C70
18P_0402_50V8J

2

PLT_RST#<9,18,20,22,24,32,33,35>

LAN_MDI0+<29>
LAN_MDI0-<29>
LAN_MDI1+<29>
LAN_MDI1-<29>
LAN_MDI2+<29>
LAN_MDI2-<29>
LAN_MDI3+<29>
LAN_MDI3-<29>

+3V_LAN

Y8

1 2

25MHZ_20PF_6X25000017

PCIE_RXP1
PCIE_RXN1
PCIE_TXP1
PCIE_TXN1
LAN_WAKE#
CLK_PCIE_LAN
CLK_PCIE_LAN#

PLT_RST#

LAN_MDI0+
LAN_MDI0­LAN_MDI1+
LAN_MDI1­LAN_MDI2+
LAN_MDI2­LAN_MDI3+
LAN_MDI3-

R39
R76 0_0402_5%
R78

@

R77
R79

R81 4.75K_0402_1%

1 2

1 2
1 2
1 2
1 2

1 2

XTALOXTALI

10K_0402_5%

0_0402_5%
0_0402_5%
0_0402_5%@

1

C69
18P_0402_50V8J

2

PCIE_MAR_T+

1 2

PCIE_MAR_T-

1 2

C47 0.1U_0402_16V4Z

VPD_CLK
VPD_DATA

XTALI
XTALO

MAR_DISABLE
MAR_VAUX

MAR_VMAIN

MAR_RSET
LAN_CTRL25
LAN_CTRL12

4.7K_0402_5%

VPD_CLK
VPD_DATA

TRACE TO IC IS 25MIL

B B

U13

49

TX_P

50

TX_N

54

RX_P

53

RX_N

6

WAKEn

55

REFCLKP

56

REFCLKN

5

PERSTn

17

MDIP0

18

MDIN0

20

MDIP1

21

MDIN1

26

MDIP2

27

MDIN2

30

MDIP3

31

MDIN3

38

VPD_CLK

41

VPD_DATA

34

SPI_DO

35

SPI_DI

37

SPI_CLK

36

SPI_CS

15

XTALI

14

XTALO

10

LOM_DISABLEn

12

VAUX_AVLBL

11

SWITCH_VCC

47

VMAIN_AVLBL

9

SWITCH_VAUX

24

HSDACP

25

HSDACN

16

RSET

4

CTRL25

3

CTRL12

88E8053-NNC1C000_QFN64

+3V_LAN

12

12

R40

R41

4.7K_0402_5%

PCI-E

LED

TEST

POWER

Media

&

GROUND

EEPROM

FLASH
MEMORY

CLOCK

Analog

C56 0.1U_0402_16V4Z

1 2

8
7
6
5

AT24C16AN-10SU-2.7_SO8~N

VCC
WP
SCL
SDA

GND

A0
A1
A2

LAN_ACT#

59

LED_ACTn

LED_LINKn

TESTMODE

TSTPT
VDD25

AVDDL
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL
AVDDL

AVDD

VDDO_TTL
VDDO_TTL
VDDO_TTL
VDDO_TTL
VDDO_TTL

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

EPAD

SMCLK/NC

SMDATA/NC

60
62
63

46
29

TP1 PAD

64
19

22
28
32
51
52
57

23
1

8
40
45
61

2
7
13
33
39
44
48
58

65
42

43

LED_LINK10/100n

LED_LINK1000n

9 Vias to Ground at least.

U20

1
2
3
4

LAN_LINK#

+LAN_AVDDL

+LAN_AVDD

40 mil

LAN_ACT# <29>

LAN_LINK# <29>

2

+2.5V_LAN

C60

0.1U_0402_16V4Z

1

2

C59

0.1U_0402_16V4Z

1

+3V_LAN
+1.2V_LAN

1

C75

0.1U_0402_16V4Z

2

2

1

1

C52

0.1U_0402_16V4Z

2

C74

0.1U_0402_16V4Z

LAN_CTRL12

LAN_CTRL25

2

C61

0.1U_0402_16V4Z

1

4.7K_0402_5%

4.7K_0402_5%

1

C53

0.1U_0402_16V4Z

2

2

1

R38

4.7U_0805_10V4Z

R35

C62

0.1U_0402_16V4Z

+3VALW

2 1

12

13

D

Q51

S

2N7002_SOT23

PAD-SHORT 2x2m

6
2

1

Q52

+12VALW

+3VALW

12

R793

10K_0402_5%

A A

LAN_EN#<33>

LAN_EN#

5

10K_0402_5%

2

G

R794

PJP25

D

S

45

SI3456BDV-T1-E3_TSOP6

G

3

1

C750

0.01U_0402_16V7K

2

+3V_LAN

+1.2V_LAN

2

C63

0.1U_0402_16V4Z

1

2

C64

0.1U_0402_16V4Z

1

2

C65

0.1U_0402_16V4Z

1

2

C66

0.1U_0402_16V4Z

1

2

C67

0.1U_0402_16V4Z

1

2

C68

0.1U_0402_16V4Z

1

Note: Place Bypass Cap. with every power pin ACAP.

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

88E8053

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

28 53Monday, January 08, 2007

X 0.5

5

4

3

2

1

Close to Chip side

D D

C C

B B

A A

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

LAN_MDI0- LAN_MDI0-R

1 2

@

1 2

@

1 2

0_0603_5%

LAN_MDI2- LAN_MDI2-R

LAN_MDI2+ LAN_MDI2+R

LAN_MDI3- LAN_MDI3-R

LAN_MDI3+ LAN_MDI3+R

@

1 2

0_0603_5%

@

1 2

0_0603_5%

@

1 2

0_0603_5%

@

1 2

0_0603_5%

@

R818

1 2

0_0603_5%

R819

@

0_0603_5%

R820

0_0603_5%

R821

R822

R823

R824

R825

12

C776

12

C777

12

C780

12

C781

LAN_MDI0+RLAN_MDI0+

LAN_MDI1-RLAN_MDI1-

LAN_MDI1+RLAN_MDI1+

12

R801 49.9_0402_1%

12

R802 49.9_0402_1%

12

R803 49.9_0402_1%

12

R804 49.9_0402_1%

12

R805 49.9_0402_1%

12

R806 49.9_0402_1%

12

R807 49.9_0402_1%

12

R808 49.9_0402_1%

LAN_MDI0+
LAN_MDI0­LAN_MDI1+
LAN_MDI1­LAN_MDI2+
LAN_MDI2­LAN_MDI3+
LAN_MDI3-

SW_LAN_TX+
SW_LAN_TX-

SW_LAN_RX+

SW_LAN_TX2+
SW_LAN_TX2-

SW_LAN_RX3+
SW_LAN_RX3-

DOCKEN

LAN_MDI0-<28>

LAN_MDI0+<28>
LAN_MDI1-<28>

LAN_MDI1+<28>

LAN_MDI2-<28>

LAN_MDI2+<28>

LAN_MDI3-<28>

LAN_MDI3+<28>

1: TO DOCK
0: TO RJ45

1 2

C782 0.01U_0402_16V7K

1 2

C783 0.01U_0402_16V7K

1 2

C784 0.01U_0402_16V7K

1 2

C785 0.01U_0402_16V7K

+3V_LAN

LAN_MDI0-

LAN_MDI0+

LAN_MDI1-

LAN_MDI1+

LAN_MDI2-

LAN_MDI2+

LAN_MDI3-

LAN_MDI3+

DOCKEN<33>

Layout Notice : Place ckoke as
close PI3L500 as possible

+2.5V_LAN

12

R809

0_0603_5%

WCM-2012-900T_4P~D

1

4

WCM-2012-900T_4P~D

1

4

WCM-2012-900T_4P~D

1

4

WCM-2012-900T_4P~D

1

4

1
2
3

4
5

7
8
9

10
11
12

R800

1 2

0_0805_5%

L26

1 2

BLM18AG601SN1D_0603 @

@

0.047U_0402_16V7K

1

4
1

4
1

4

1

4

DOCKEN

T21

TCT1

MCT1

TD1+

MX1+

TD1-

MX1-

TCT2

MCT2

TD2+

MX2+

TD2-6MX2­TCT3

MCT3

TD3+

MX3+

TD3-

MX3-

TCT4

MCT4

TD4+

MX4+

TD4-

MX4-

BOTH_GST5009-V LF

C271

0.001U_0402_50V7M

1 2

2

3
2

3
2

3

2

3

L22

L23

L24

2

L25

3

24
23
22

21
20
19

18
17
16

15
14
13

C778

2

3
2

3
2

3

RJ45_MDI0+
RJ45_MDI0-

RJ45_MDI1+
RJ45_MDI1-SW_LAN_RX-

RJ45_MDI2+
RJ45_MDI2-

RJ45_MDI3+
RJ45_MDI3-

LAN_SW_VCC

1

2

C779

0.1U_0603_16V7K

LAN_ACT#<28>
LAN_LINK#<28>

1 2

R810

1 2

R811

1 2

R812

1 2

R813

1000P_1206_2KV7K

0B1

VDD04VDD110VDD218VDD327VDD438VDD550VDD6

1B1
2B1

3B1
4B1

5B1
6B1

7B1

0LED1
1LED1
2LED1

0B2
1B2

2B2
3B2

4B2
5B2

6B2
7B2

0LED2
1LED2
2LED2

55

RJ45_MDI3­RJ45_MDI3+
RJ45_MDI1­RJ45_MDI2­RJ45_MDI2+
RJ45_MDI1+
RJ45_MDI0­RJ45_MDI0+

LAN ANALOG
SWITCH

48
47

43
42

37
36

32
31

22
23
52

46
45

41
40

35
34

30
29

25
26
51

PI3L500ZFE_TQFN56

FROM NIC

SW_LAN_TX­SW_LAN_TX+

SW_LAN_RX­SW_LAN_RX+

SW_LAN_TX2­SW_LAN_TX2+

SW_LAN_RX3­SW_LAN_RX3+

DOCK_LAN_TX­DOCK_LAN_TX+

DOCK_LAN_RX+
DOCK_LAN_TX2-

DOCK_LAN_TX2+
DOCK_LAN_RX3-

DOCK_LAN_RX3+
DOCK_LAN_ACT#
DOCK_LAN_LINK#

1

56

C786

U24

2

A0

3

A1

7

A2

8

A3

11

A4

12

A5

14

A6

15

A7

17

SEL

19

LED0

20

LED1

54

LED2

5

NC

GND01GND16GND29GND313GND416GND521GND624GND728GND833GND939GND1044GND1149GND1253GND13

2

1

2

LAN_MDI0-R
LAN_MDI0+R

LAN_MDI1-R
LAN_MDI1+R

LAN_MDI2-R
LAN_MDI2+R

LAN_MDI3-R

LAN_MDI3+R DOCK_LAN_RX-

75_0402_1%

75_0402_1%

75_0402_1%

75_0402_1%

TO
RJ45

DOCK_LAN_TX- <36>
DOCK_LAN_TX+ <36>

DOCK_LAN_RX- <36>
DOCK_LAN_RX+ <36>

DOCK_LAN_TX2- <36>
DOCK_LAN_TX2+ <36>

DOCK_LAN_RX3- <36>

DOCK_LAN_RX3+ <36>
DOCK_LAN_ACT# <36>
DOCK_LAN_LINK# <36>

JP16

9

SHLD1

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

SHLD2

ALLTOP_C10068-10804

TO
DOCK

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Magnetics & RJ45

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

29 53Monday, January 08, 2007

X 0.5

5

4

3

2

1

C791

0.1U_0402_16V4Z

1

1

2

2

10U_0805_6.3V6M

PORT_A_R_HP

PORT_D_R_HP

PORT_F_R_HP

VDDA

VDDA

1

C787

4.7U_0805_10V4Z

2

C792

0.1U_0402_16V4Z

SENSE_A
SENSE_B

PORT_A_L_HP

PORT_B_L

PORT_B_R

PORT_C_L
PORT_C_R

PORT_D_L_HP

PORT_E_L

PORT_E_R

PORT_F_L_HP

VREFOUT_A

VREFOUT_B
VREFOUT_C
VREFOUT_D

CD_L
CD_G
CD_R

PC_BEEP

AVSS1
AVSS3

1

C788

0.1U_0402_16V4Z

2

1@

R23

MB_HP_R1
MB_HP_L1 MB_HP_L

SENSE_A

13

SENSE_B

34

MB_HP_L1

39

MB_HP_R1

41

MB_MIC_L

21
22

23
24

35
36

14
15

16
17

37
28
29
32
18
19
20
12

26
42

HP_OUT_L

HP_OUT_R

INT_MIC1
INT_MIC3

INT_SPK_L

INT_SPK_R

C21

0.33U_0603_16V4Z

INT_MIC3

INT_MIC2
PC_BEEP

MB_MIC_L <31>
MB_MIC_R <31>

DOCK_MIC <36>

HP_OUT_L <36>
HP_OUT_R <36>

INT_MIC1 <36>
INT_MIC3 <31>

INT_SPK_L <31>

INT_SPK_R <31>

VrefOut_B <31>

INT_MIC3 <31>

INT_MIC2 <36>

0_0603_5%

1 2

1@

R25

1 2

0_0603_5%

ShutDown#

2@

U47

C1

SHDN#
INLB1OUTL

B3

INR

A2

GND

MAX9890AEBL+T_UCSP9

Port A for MB HP

Port B for MB ext mic

Port C for DOCK/B ext mic

Port D for DOCK/B HP

Port E for INT_MIC1
and INT_MIC3

Port F for internal speaker

CD input pins for
INT_MIC2 and INT_MIC3

OUTR

CEXT

VCC

VDDA

VDDA

R19

SENSE_A

R962

20K_0603_1%

VDDA

12

PC_BEEP

12

@

D18

1SS355_SOD323

1 2

R16 0_0603_5%

1 2

R17 0_0603_5%

1 2

R18 0_0603_5%

R20

5.11K_0402_1%~D

SENSE_B

C19

R963

39.2K_0603_1%

MB_HP_PLUG# <31>

MIC_SENSE <31>

@

R815
100K_0402_5%

1

2

Analog ground

1

1

2

2

C20

0.1U_0402_16V4Z

0.1U_0402_16V4Z

For MB EXT MIC

C795

0.1U_0402_16V4Z

Place bypass capacitor
close to CODEC Pin26

For MB HP

2@

R57

100K_0402_5%

1 2
13

D

S

VDDA

R49

100K_0402_5%

1 2

DOCK_HP_PLUG#

13

D

S

ShutDown#

1

2

2N7002_SOT23

@

2N7002_SOT23

Q59

2

G

2N7002_SOT23

PCM_SPK#<25>

ICH_SPKR<22>

Q62

2

G

BEEP#<33>

MB_HP_PLUG#

MB_HP_R

VDDA

1

C39

2@

2

1U_0603_16V6K

C2
A1
A3
C3
B2

NC

1

2

2@

C798

0.1U_0402_16V4Z

MB_HP_R <31>
MB_HP_L <31>

For DOCK HP

HP_PLUG#<31,36>

ShutDown# <33>

@

C416
22U_0805_6.3V6M

NOTE: Place pull-up
resistors close to
CODEC Pin25

R960

5.11K_0402_1%~D

For DOCK MIC

13

Q58

D

R814

R816

R817

2

G

S

2K_0402_5%

2K_0402_5%

2K_0402_5%

DIS_INTMIC<36>

12

C796

12

12

1 2

C793

C794

1 2

1 2

2N7002_SOT23

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

Digital ground

5.11K_0402_1%~D

R961

10K_0603_1%

Q60

13

D

2

G

S

+5VALW

w=40mil

1

1

2

L21

1 2

R746

1 2

22_0402_5%

1

C33

2

10U_0805_6.3V6M

C790

0.1U_0402_16V4Z

2

0_0402_5%

VDDC

1

C16

2

1U_0603_16V6K

@

R747

1 2

33_0402_5%

ICH_AZ_CODEC_SYNC

ICH_AZ_CODEC_RST#

2

C26

1

9220@

820P_0603_50V7K

R48

@

C32

9220@

C789

4.7U_0805_10V4Z

D D

SUSP#<33,37,39>

+3VS

MBK1608301YZF_0603

Place decoupling
caps as close to
Codec as possible.

@

C22

27P_0402_50V8J

C C

ICH_AZ_CODEC_BITCLK<21>
ICH_AZ_CODEC_SDIN0<21>

ICH_AZ_CODEC_SDOUT<21>
ICH_AZ_CODEC_SYNC<21>
ICH_AZ_CODEC_RST#<21>

1

C31

2

10U_0805_6.3V6M

GPIO pin

B B

9228@

0.1U_0402_16V4Z

U18

1

VIN

BYPASS

3

EN

TPS793475DBVR_SOT23-5

1

C800

2

0.1U_0402_16V4Z

1

C797

2

0.1U_0402_16V4Z

ICH_AZ_CODEC_BITCLK MB_MIC_R
SDATA_IN
ICH_AZ_CODEC_SDOUT

AFILT2

2

1

820P_0603_50V7K

MIC_SEL<33>

VDDC

C799

1

2

CAP2

AFILT1

9228@

VDDA

R61

0_0402_5%

9228@

R59

9220@

R58

0_0402_5%

Io= 200mA
Vo= 4.65V ~ 4.85V
w=30mil

5

VOUT

4

2

GND

GNDA<31,36>

U22

25

AVDD1

38

AVDD2

1

DVDD_CORE1

9

DVDD_CORE3

6

BIT_CLK

8

SDATA_IN

5

SDATA_OUT

10

SYNC

11

RESET#

33

CAP2

27

VREF_FILT

30

AFILT1

31

AFILT2

3

VOLUME_DOWN

2

VOLUME_UP

45

GPIO0

46

GPIO1

44

GPIO2

47

GPIO3/SPDIFIN/EAPD

48

SPDIF_OUT

43

0_0402_5%

PLL_CAP

40

NC

4

DVSS2

7

DVSS3

STAC9220X5TAEA6XR_LQFP48~D

1

2

C34

STAC9220

Item

C26,C32

STAC9220

POP

R58,C799 DE_POP POP

R59

R61

A A

POP DE_POP

DE_POP

STAC9228

DE_POP

POP

5

DIS_INTMIC DOCK_MIC

H

L ENABLE

INT_MIC1
INT_MIC2
INT_MIC3

(PIN 23/24)

DISABLE ENABLE

DISABLE

4

MB_HP_PLUG#

(EAPD function)

H

L

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

INT_SPK_L PIN16
INT_SPK_R PIN17

ENABLE

DISABLE

3

MIC_SEL
(PIN 46) (PIN 14) (PIN 20) (PIN 15,18)

L (Landscape)

H (Portrait)

INT_MIC1 INT_MIC2 INT_MIC3

ENABLE ENABLE

DISABLE

DISABLE

ENABLE ENABLE

2

MIC2

O

MIC3MIC1

OO

Compal Electronics, Inc.(KunShan)

Title

Azalia Codec STAC9220

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

30 53Monday, January 08, 2007

X 0.5

5

+5VS

Gain Setting

12

D D

GAIN0
GAIN1

12

R827

10K_0402_5%

@

R829

10K_0402_5%

12

R828
10K_0402_5%

12

R830
10K_0402_5%

@

GAIN0 GAIN1

*

0

1

+5VAMP

0

1

0

11

W=30mils

C821

0.47U_0603_16V4Z

C823

0.47U_0603_16V4Z

VDDA

5

U31

P

B

Y

A

G

TC7SH08FUF_SSOP5

3

1

C817

0.1U_0402_16V4Z

2

7

RIN+

17

RIN-

9

LIN+

5

LIN-

19

SHUTDOWN

4

D33

4

IO1

VIN

3

GND

IO2

PRTR5V0U2X_SOT143-4

20

2
1

1

C C

INT_SPK_R<30>

INT_SPK_L<30>

VDDA

12

R2

HP_PLUG#<30,36>

MB_HP_PLUG#<30>

100K_0402_5%

+5VS

5

U30

1

P

B

2

A

G

3

TC7SH08FUF_SSOP5

4
3

PRTR5V0U2X_SOT143-4

5

B B

A A

0.1U_0402_16V4Z

12

R1

100K_0402_5%@

4

Y

MUTE#<33>

D32

IO1

VIN

GND

IO2

C816

1 2

1 2

1 2

1 2

2
1

2

C822

0.1U_0402_16V4Z

C824

0.1U_0402_16V4Z

1
2

4

AV(inv)

6dB0

10dB

15.6dB

21.6dB

15

6

16

VDD

PVDD1

PVDD2

GND41GND311GND213GND1

TPA6017A2PWPRG4_TSSOP20~N

INPUT

IMPEDANCE

90K ohm

70K ohm

45K ohm

25K ohm

L35

1 2

BLM21PG221SN1D_0805

U16

2

GAIN0

3

GAIN1

18

ROUT+

14

ROUT-

4

LOUT+

8

LOUT-

12

NC

10

BYPASS

Speaker

INTSPK_R+
INTSPK_R-

MOLEX_53780-0290

INTSPK_L­INTSPK_L+

4

+5VS

1

C818
10U_0805_10V4Z

2

GAIN0
GAIN1

INTSPK_R+

INTSPK_R-

INTSPK_L+

INTSPK_L-

BYPASS

1

C830

2

4.7U_0805_10V4Z

JP17

1

1

2

2

JP18

2

2

1

1

MOLEX_53780-0290

3

Compal P/N: SCVL080C000

INT_MIC_3

PORTA_3RMB_HP_R

PORTA_3LMB_HP_L

R5

12

0.22U_0603_10V7K

C815

1 2

C42

1 2

C826

+

1 2

220U_D2_4VM

C827

+

1 2

220U_D2_4VM

C828

10U_0805_10V4Z

4.02K_0603_1%

C45

PORTB_2R

2.2U_0805_25V6K

PORTB_2L

2.2U_0805_25V6K

@

20K_0402_5%

20K_0402_5%

1

2

R846

INT_MIC3<30>

1

C819

0.1U_0402_16V4Z

2

R700

4.99_0402_1%

3

VrefOut_B

MB_MIC_L

1 2

R707

4.99_0402_1%

1 2

1 2

4.02K_0603_1%

MB_HP_R<30>

MB_HP_L<30>

1

C831

2

0.1U_0402_16V4Z

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VrefOut_B<30>

MB_MIC_R<30>

MB_MIC_L<30>

PORTA_2R

PORTA_2L

R844

R841

12

1 2

1 2

12

1 2

2

L36
FBMA-L11-160808-700LMT

L42

BK1608HM601-T_0603

1 2

L47

BK1608HM601-T_0603

1 2

12

R845
20K_0402_5%

R840

4.02K_0603_1%
L48

BLM18AG601SN1D_0603

1 2

L51

BLM18AG601SN1D_0603

1 2

12

@

R847

20K_0402_5%

2

VDDA

1

2

1

R831

1 2

4.7K_0402_5%

Internal MIC3

ACES_85201-0405

INTMIC3

GNDA<30,36>

1
2
3
4

JP19

DVT2 swap pin

MB HP

PORT A

JP20

6

MB_HP_PLUG#<30>

PORTA_1R

PORTA_1L

1

1

C835

C836

2

2

0.01U_0402_25V4Z

0.01U_0402_25V4Z

MB_HP_PLUG#

5
4
3
2

1

SUYIN_010030FR006G100ZL

MB ext MIC

PORT B

JP21

6
5

4
3
2

1

SUYIN_010030FR006G100ZL

31 53Monday, January 08, 2007

1

X 0.5

of

C834

MIC_SENSE<30>

PORTB_1RMB_MIC_R

PORTB_1L

1

C833

2

220P_0402_50V7K

220P_0402_50V7K

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

MIC_SENSE

AMP & Audio JACK

PecosII-IDX80-LA3291

5

4

3

2

1

1A

OC1#
OUT1
OUT2
OC2#

R951

0_0402_5%

USB_0S USB_1S

8
7
6
5

12

WAKE_PWR_EN# <33,36>

1 2

R15

1 2

R14

0.1U_0402_16V4Z

47_0402_5%

47_0402_5%

C29

1

2

1

2

USB_OC#0

USB_OC#1

C28

0.1U_0402_16V4Z

USB_OC#0 <22>

USB_OC#1 <22>

USB Over Current

+5VALW

D D

1

C690

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

W=40mils

1

C691

2

U29

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062DR_SO8~D

12

R953
0_0402_5% @

USB_0S USB_0

L49

W=40mils

1 2

FBMA-L11-451616-800LMA10T

0.1U_0402_16V4Z

USBP0-<22>
USBP0+<22>

C838

1

2

1

+

C837
150U_D2_6.3VM

2

0.001U_0402_50V7M

USBP0-

R849
R850

C839

1 2
1 2

2

1

0_0603_5%
0_0603_5%

C329

3.3P_0402_50V8J

@

D27

VIN
IO2

IO1

GND

USB20_N0_R
USB20_P0_RUSBP0+

2
1

4
3

PRTR5V0U2X_SOT143-4

1

2

USB Port 0

1

C330

2

3.3P_0402_50V8J@

JP22

1

56

VCC

2

D-

3

D+

4

GND

SUYIN_020173MR004S583ZL

Required by Motion
for ESD protect

USB Port 1

USB_1S USB_1

L50

W=40mils

1 2

FBMA-L11-451616-800LMA10T

C840

0.1U_0402_16V4Z

TPM

C C

LPC_AD0<21,24,33,35>
LPC_AD1<21,24,33,35>
LPC_AD2<21,24,33,35>
LPC_AD3<21,24,33,35>
LPC_FRAME#<21,24,33,35>
PLT_RST#<9,18,20,22,24,28,33,35>

SIRQ<22,25,33,35>

CLK_PCI_TPM<5>

PM_CLKRUN#<22,25,27,33,35>

B B

C855

C854

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PLT_RST#

LPCPD#
SIRQ
CLK_PCI_TPM

PM_CLKRUN#

TPM_XTALO
TPM_XTALI

SLB 9635 TT 1.2_TSSOP28

C856

26
23
20
17
22
16
28
27
21

15

7

14
13

1

2

0.1U_0402_16V4Z

U17

LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
LPCPD#
SERIRQ
LCLK

SLB 9635 TT 1.2

CLKRUN#

PP

XTALO
XTALI/32K IN

+3VS +3VALW

10

19

24

5

VSB

VDD

VDD

VDD

GPIO

GPIO2

TEST1

TESTB1/BADD

GND

GND

GND

GND

4

11

18

25

1

C853

0.1U_0402_16V4Z

2

6
2

8
9

3

NC

12

NC

1

NC

PAD

T23
T22

PAD
R854 0_0603_5%

R860 4.7K_0402_5%@

1 2

BADDR

1 2

R858

12

+3VS

4.7K_0402_5%

Base I/O Address

0 = 02Eh

1 = 04Eh(Default)

*

USBP1-<22>
USBP1+<22>

1

2

1

+

C841
150U_D2_6.3VM

2

0.001U_0402_50V7M

USBP1­USBP1+

R851
R852

C842

2

1

1 2
1 2

C331

@

4
3

PRTR5V0U2X_SOT143-4

0_0603_5%
0_0603_5%

1

2

3.3P_0402_50V8J

D28

VIN
IO2

IO1

GND

USB20_N1_R
USB20_P1_R

2
1

JP23

1

56

VCC

2

D-

3

D+

4

GND

1

2

3.3P_0402_50V8J@

SUYIN_020173MR004S583ZL

1 2

SUS_STAT#
TPM_LPCPD#

R855

@

0_0402_5%

1 2

+3VS

C929

5

1

P

B

2

A

G

3

0.1U_0402_16V4Z
U32

LPCPD#

4

Y

TC7SH08FUF_SSOP5

C332

SUS_STAT#<22,35>
TPM_LPCPD#<33>

CLK_PCI_TPM

12

R859

@

33_0402_5%

1

@

C857

A A

22P_0402_50V8J

5

2

10M_0402_5%

4

TPM_XTALI

R952

TPM_XTALO

1 2

C925

18P_0402_50V8J

12

32.768KHZ_12.5PF_1TJS125BJ4A421P

1
4

Y7

C926 18P_0402_50V8J

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

IN
OUT

1 2

2

NC

3

NC

3

Compal Electronics, Inc.(KunShan)

Title

TPM/USB Port x2

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

2

Date: Sheet

1

32 53Monday, January 08, 2007

X 0.5

of

5

FBMA-L11-160808-601LMT_200mA_10%

1 2

L44

L43

ECAGND

12

FBMA-L11-160808-601LMT_200mA_10%

D D

CLK_PCI_EC

R281
33_0402_5%

@
1 2
2

C345

15P_0402_50V8J

1

@

+3VALW

C C

12

R297

10K_0402_5%

SASBTN#

SSBTN:User button as,
ALT+CTL+Delete

@

ACES_85201-0405

1
2
3
4

JP24

B B

A A

R391

10K_0402_5%

TP3
PAD

+3VALW

12

R380
10K_0402_5%

WL_SW#

+3VALW

12

EC_TXD

EC_TXD

+3VALW

+5VALW

EC_PBTNOUT#<22>

12

R293
10K_0402_5%

KSI_USER#

5

PM_BATLOW#<22>
SLP_S4#<22>

EC_RSMRST#<22,27>
SLP_S3#<22>
SLP_S5#<22>

EC_AVCC+3VALW

2

C337

0.1U_0402_16V4Z

1

R276

1 2

+3VALW

47K_0402_5%

0.1U_0402_16V4Z

SLP_S4#

EC_RSMRST#

SLP_S3# SLP_S3#_R
SLP_S5#

EC_PBTNOUT#

C344

R87 0_0402_5%@

1 2
1 2

R82

1 2

R86

1 2

R83

1 2

R84

1 2

R85

+5VALW

1

2

0_0402_5%

0_0402_5%
0_0402_5%
0_0402_5%

0_0402_5%

+3VALW

GATEA20<21>
KBRST#<21>

SIRQ<22,25,32,35>

LPC_FRAME#<21,24,32,35>

LPC_AD3<21,24,32,35>
LPC_AD2<21,24,32,35>
LPC_AD1<21,24,32,35>
LPC_AD0<21,24,32,35>

CLK_PCI_EC<5>

EC_SCI#<22>

PM_CLKRUN#<22,25,27,32,35>

HWSPND#<25>
EC_EXTTS#0<9,15,16>
PWR_GD<38>
DIGI_RST#<17>
SASBTN#<36>
DIGISUSP<17>

FPR_PWRON#<36>
CHGSEL<40>

F_FALL<24>
CARD_INSERT#<25>
MOTION<24>

SMB_EC_DA2<6,24,36,39>
SMB_EC_CK2<6,24,36,39>
SMB_EC_DA1<24,34,39>
SMB_EC_CK1<24,34,39>

WAKE_PWR_EN#<32,36>
PWR_LED#<17>
KSI_USER#<36>
CHARGE_LED#<17>
BATT_LED#<17>
MUTE#<31>

WL_SW#<24>

SYSON<37,45>

BKOFF#<17>
VCCP_ON#<43>
EC_SMI#<22>

EC_SWI#<22>
BTDIS#<27>
SUSP#<30,37,39>

PME#<34>

10K_0804_8P4R_5%

4

+3VALW

1

C338

0.1U_0402_16V4Z

2

KSI0<36>
KSI1<36>
KSI2<36>
KSI3<36>
KSI4<36>
KSI5<36>
KSI6<36>
KSI7<36>

RP22

FSEL#

18

FRD#

27
36
45

SMB_EC_DA1

R2774.7K_0402_5%

12

SMB_EC_CK1

R2784.7K_0402_5%

12

SMB_EC_DA2

R2794.7K_0402_5%

12

SMB_EC_CK2

R2804.7K_0402_5%

12

4

0.1U_0402_16V4Z

1

C339

2

GATEA20
KBRST#
SIRQ

LPC_FRAME#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_EC

PLT_RST#
ECRST#
EC_SCI#

PM_CLKRUN#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

HWSPND#
EC_EXTTS#0
PWR_GD
DIGI_RST#
SASBTN#
DIGISUSP
PM_BATLOW#_RPM_BATLOW#

SLP_S4#_R

FPR_PWRON#
CHGSEL
BDID0
BDID1
BDID2
F_FALL
CARD_INSERT#
MOTION

SMB_EC_DA2
SMB_EC_CK2
SMB_EC_DA1
SMB_EC_CK1

EC_TXD
WAKE_PWR_EN#
PWR_LED#
KSI_USER#
CHARGE_LED#
BATT_LED#
MUTE#
WL_SW#
SYSON

EC_RSMRST#_R

BKOFF#
VCCP_ON#

SLP_S5#_R

EC_SMI#
EC_SWI#
BTDIS#
SUSP#

EC_PBTNOUT#_R

PME#

CRY1
CRY2

3

0.1U_0402_16V4Z

1

2

1000P_0402_50V7K

1

C340

U33

1
2
3
5
6
9

10
12
14
15
42
24
44

63
64
65
66
67
68
69
70

47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
89
90

88
87
86
85

34
35
38
40

99
101
100
102
104

4
7

8
16
17
18
19
20
21
22
23

140
138

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C341

2

GA20/ GPIO00/GA20
KBRST#/GPIO01/KBRST#
SERIRQ
LPC_FRAME# / LFRAME#
LPC AD3/LAD3
LPC AD2/LAD2
LPC AD1/LAD1
LPC AD0/LAD0
CLK_PCI_EC/PCICLK
PCIRST#
EC RST#/ ECRST#
EC SCI#/SCI#/GPIO0E
PM_CLKRUN#/ CLKRUN#

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPI032
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPI035
KSI6/GPIO36
KSI7/GPIO37

KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
EC URXD/KSO16/GPIO48
EC UTXD/KSO17/GPIO49

EC SMD2/ GPIO47/SDA2
EC SMC2/GPIO46/SCL2
EC SMD1/GPIO44/SDA1
EC SMC1/GPIO44/SCL1

PCM_SPK#/EMAIL_LED#/ GPIO16
SB_SPKR/PWR_SUSP_LED#/ GPIO17
PWRLED#/ GPIO19
NUMLED#/ GPIO1A
BATT CHGI LED#/ E51CS#
BATT LOW LED#/ E51MR0
CAPS LED#/ E51TMR1
ARROW LED#/ E51 INT0
SYSON/GPIO56/ E51 INT1

EC_RSMRST#/ GPIO02
BKOFF#/GPIO03
PM SLP S3#/GPIO04
EC LID OUT#/GPIO06
PM SLP S05#/ GPIO07
EC SMI#/GPIO08
EC SWI#/GPIO09
LID SW#/ GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC PME#/GPIO0D

XCLKO
XCLKI

C342

2

1000P_0402_50V7K

Host

INTERFACE

key Matrix

scan

EC_AVCC

11

127

141

26

105

VCC

VCC

VCC/ EC VCC

VCC / EC VCC

VCC / EC VCC37VCC / EC VCC

PWR

FAN/PWM

INVT_PWM/GPIO0F/PWM1

FAN SPEED1/GPIO14/FANFB1
FAN SPEED2/GPIO15/FANFB2

PS2 interface

Address

SM BUS

GND13GND28GND

GND

GND

GND

39

103

129

139

+3VALW

12

R295

10K_0402_5%

ROTA90#

3

75

BATTEMP/AD0/GPIO38

BATT OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD BID0/AD3/GPIO3B

AD INtput or GPI

EC_AVCC / AVCC
DAC_BRIG/DA0/GPIO3D

EN DFAN1/DA1/GPIO3D

IREF2/DA2

EN DFAN2/DA3/ GPIO3F

DA output or GPO

BEEP#/GPIO10/PWM2

OUT BEEP/GPIO12/PWM3

ACOFF/GPIO18/PWM4

PSCLK1
PSDAT1
PSCLK2
PSDAT2
PSCLK3
PSDAT3

ADB0/D0
ADB1/D1

ADB3/ D3

KBA10/A10
KBA11/A11
KBA12/A12
KBA13/A13
KBA14/A14
KBA15/A15
KBA16/A16
KBA17/A17
KBA18/A18
KBA19/A19

SELIO2#/ GPIO43

SELIO#/ GPIO50

FRD#/RD#

FWR#/WR#

FSEL#/SELMEM#

EC ON/ GPIO1B

AC IN/ GPIO1C

ECTHERM#/GPIO11

ONOFF/GPIO18

PCMRST#/GPIO1E

WL OFF#/GPIO1F

ALI/MH#/GPIO40

FSTCHG/GPIO41

VR ON/ GPIO42
GPIO57/GPIO57
GPIO58/GPIO58
GPIO59/GPIO59

AGND

77

ECAGND

ADB2/D2
ADB4/D4

ADB5/D5
ADB6/D6
ADB7/D7

KBA0/A0
KBA1/A1
KBA2/A2
KBA3/A3
KBA4/A4
KBA5/A5
KBA6/A6
KBA7/A7
KBA8/A8
KBA9/A9

KB910LQF A1_LQFP144~N

Data
BUS

BUS

71
72
73
74

76
78
79
80

25
27
30
31
32
33

91
92
93
94
95
96

125
126
128
130
131
132
133
134
111
112
113
114
115
116
117
118
119
120
121
122
123
124
110
109
108
107
106
98

84
97
135
136
144

41
43
29
36
45
46

81
82
83
137
142
143

BATT_TEMP1
BATT_OVP
DS_DOCKED_ID
BATT_TEMP2

DAC_BRIG
BATSELB_A#
IREF
MIC_SEL

INVT_PWM
FAN_PWM
BEEP#
ACOFF
FAN_SPEED1
PDCT

ShutDown#_L

WWANOFF#
PCM_CLK_EN#
LAN_EN#
TPM_LPCPD#
USB_CLK_EN#

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

PWROK
PROCHOT#
FRD#
FWR#
FSEL#

EC_ON
ACIN
EC_THRM#
ON/OFF
DOCKEN
WLANOFF#

DOCKEN_VGA
FSTCHG
VR_ON
ENABLT
VGATE_INTEL
ROTA90#

2

BATT_TEMP1
BATT_TEMP2 ECAGND
BATT_OVP ECAGND

DS_DOCKED_ID

BATT_TEMP1 <39>
BATT_OVP <41>
DS_DOCKED_ID <36>
BATT_TEMP2 <39>

DAC_BRIG <17>
BATSELB_A# <41>PLT_RST#<9,18,20,22,24,28,32,35>
IREF <40>
MIC_SEL <30>

INVT_PWM <17>
FAN_PWM <6>
BEEP# <30>
ACOFF <40>
FAN_SPEED1 <6>
PDCT <17>

0_0402_5%

ShutDown#

1 2

R88

2@

WWANOFF# <24>
PCM_CLK_EN# <25>
LAN_EN# <28>
TPM_LPCPD# <32>
USB_CLK_EN# <27>

PWROK <9,22,34>
PROCHOT# <6>
FRD# <34>
FWR# <34>
FSEL# <34>

EC_ON <34>
ACIN <40,42>
EC_THRM# <22>
ON/OFF <34>
DOCKEN <29>
WLANOFF# <24>

DOCKEN_VGA <19,34>
FSTCHG <40,41>
VR_ON <37,46>
ENABLT <11,17>

VGATE_INTEL <22,46>

ROTA90# <36>

ShutDown# <30>

2

C334
C348
C335
C336
R270

ADB[0..7]

KBA[0..19]

1 2
1 2
1 2
1 2

1 2

1

ECAGND

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

ECAGNDDS_DOCKED_ID

0.01U_0402_16V7K

4.7K_0402_5%

R332

10K_0402_5%

PCM_CLK_EN#

ADB[0..7] <34>

KBA[0..19] <34>

+3VALW

12

R299

10K_0402_5%

TPM_LPCPD#

32.768K +-10PPM Q13MC20610009

+3VS

12

10P_0402_50V8J

3

NC

2

NC

Y3

10P_0402_50V8J

R333

10K_0402_5%

USB_CLK_EN#

BDID0
BDID1
BDID2

C347

+3VS

C346

@

OUT

12

R327

R267

12

IN

12

+3VALW

10K_0402_5%

4
1

12

1K_0402_5%

1 2

20M_0603_5%@

0_0603_5%

@

10K_0402_5%

12

@

R326

10K_0402_5%

R157

1K_0402_5%

1 2

BDID2 BDID1 BDID0 Version

000
00
00
0
0
0
10

0
0
01

Rework

0.4

10
11

0

101
111

0
11

Compal Electronics, Inc.(KunShan)

Title

ENE KB910

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

R285

R298

0.1

0.2

0.3

0.4

0.5

1.0

33 53Monday, January 08, 2007

R286

R325

R70

@

1K_0402_5%

12

12

PDCT

12

12

10K_0402_5%

1 2

Phase

EVT1

EVT2

DVT1

Rework
DVT2

Reserve

DVT2

PVT

MP

Reserve

Reserve

of

CRY1

CRY2

X 0.5

5

4

3

2

1

NM24C164 Address definition: 1 A2 A1# A0 B2 B1 B0 R/W#

100_0402_5%

100_0402_5%

100_0402_5%

G

2

Q21

S

+3VALW

1

C881

2

0.1U_0402_16V4Z

+3VALW

+3VALW

12

R895
10K_0402_5%

@

R899

PCIPME#

1 2

0_0402_5%

+3VALW

R905

100K_0402_5%

1 2

13

D

1

C882

10U_0805_10V4Z

2

2
1

R906 0_0402_5%@

BIOS/B Conn

KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWE#

BIOS_RST#

KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1 KBA0

JP25

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

ACES_88072-4071_40P

+3VALW

5

U37

P

I0
I1

G

TC7SH32FU_SSOP5

3

1 2

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

PCI_PME# <20>PME#<33>

FWE#

4

O

KBA17

KBA19
KBA10
ADB7
ADB6
ADB5
ADB4

+3VALW

ADB3
ADB2
ADB1
ADB0
FRD#

FSEL#

+3VALW

12

R896

3
2

22K

2

22K

100K_0402_5%

ON/OFF
EC_ON#

13

Q19

DTC124EKAT146_SOT23

WHEN R=33K,Vbe=0.8V

WHEN R=0,Vbe=1.35V

DOCK_USB_OC#4<36>

DOCK_USB_OC#2<36>

DOCKEN_VGA#

DOCK_USB_OC#3<36>

R904

22K_0402_5%

1 2

+3VALW

R909

1 2

13

D

2

G

S

D23

1

DAN202U_SC70

D D

C C

B B

DOCKEN_VGA<19,33>

SW1

1 2

HSS111_4P

R901

22K_0402_5%

EC_ON ECON

EC_ON<33>

DOCKEN_VGA

ON/OFFBTN#

+3VALW

12

ON/OFFBTN#

2

3

D36
PSOT24C-LF_T7_SOT23-3

1

10K_0402_5%

2N7002_SOT23

Q23

Power BTN

1

C876

1000P_0402_50V7K

2

DOCK_USB_OC#4

ON/OFF <33>
EC_ON# <44>

12

D24
RLZ20A TE-11_LL34

10K_0402_5%

10K_0402_5%

DOCK_USB_OC#2

10K_0402_5%

DOCK_USB_OC#3

R907

1 2

U38A

R908

1 2

U38B

R910

1 2

U38C

10

12
13

1
2

4
5

9

U38D

+3VALW

A
B

+3VALW

A
B

+3VALW

A
B

+3VALW

A
B

14

P

G

7

14

P

G

7

14

P

G

7

14

P

G

7

SMB_EC_CK1<24,33,39>

SMB_EC_DA1<24,33,39>

TC74LCX32FTF_TSSOP14

USB_OC#4

3

O

1

C879

0.1U_0402_16V4Z

2

TC74LCX32FTF_TSSOP14

USB_OC#6

6

O

1

C880

0.1U_0402_16V4Z

2

TC74LCX32FTF_TSSOP14

USB_OC#7

8

O

1

C883

0.1U_0402_16V4Z

2

TC74LCX32FTF_TSSOP14

11

O

USB_OC#4 <22>

USB_OC#6 <22>

USB_OC#7 <22>

C875

1 2

0.1U_0402_16V4Z

+3VALW

8

VCC

7

WP

6

SCL

5

SDA

AT24C16AN-10SU-2.7_SO8~N

EC I2C Bus Address:
24C164: 1011xxx R/W#
24C16: 1010xxx R/W#

+3VALW

12

R894

U34

A0
A1
A2

GND

FSEL#<33>
FRD#<33>

100K_0402_5%

1
2
3
4

U39

21

A0

20

A1

19

A2

18

A3

17

A4

16

A5

15

A6

14

A7

8

A8

7

A9

36

A10

6

A11

5

A12

4

A13

3

A14

2

A15

1

A16

READY/BUSY#

40

A17

13

A18

37

A19

22

CE#

24

OE#

9

WE#

SST39VF080-70-4C-EIE_TSOP40~N

@

FSEL#
FRD#

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

FWE#

PCM_PME#<25>

USB_PME#<27>

PWROK<9,22,33>

EC_FLASH#<22>

FWR#<33>

VCC0
VCC1

RP#

NC0
NC1

GND0
GND1

ADB[0..7]

KBA[0..19]

31
30

25

D0

26

D1

27

D2

28

D3

32

D4

33

D5

34

D6

35

D7

10
11

NC

12
29
38

23
39

ADB[0..7]<33>

KBA[0..19]<33>

1 2

R897

1 2

R900

1 2

R921

PWROK

EC_FLASH# EC_FLASH_T#

2N7002_SOT23

FWR#

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

R912

1 2

10K_0402_5%

BIOS_RST#

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

EC Extend I/O&BIOS

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

34 53Monday, January 08, 2007

X 0.5

5

D D

+3VS

1

C885

0.1U_0402_16V4Z

C C

0.1U_0402_16V4Z

2

33_0402_5%

22P_0402_50V8J

1

C886

1000P_0402_50V7K

2

12

R915

@

1

@

C889

22P_0402_50V8J

2

C887

R916

@

33_0402_5%

@

C890

1

4.7U_0805_10V4Z

2

PLT_RST#<9,18,20,22,24,28,32,33>

CLK_PCI_SIOCLK_14M_SIO

12

1

2

C888

Strap pin Pin # Description

BADDR 33

B B

BASE Address Selection

"0": 2E~2F (Default)

"1": 4E~4F

4

1

2

R914

PLT_RST# PLT_RST_R#

1 2

LPC_AD0<21,24,32,33>
LPC_AD1<21,24,32,33>
LPC_AD2<21,24,32,33>
LPC_AD3<21,24,32,33>

LPC_FRAME#<21,24,32,33>
LPC_DRQ#0<21>

22_0402_5%

SUS_STAT#<22,32>

PM_CLKRUN#<22,25,27,32,33>

CLK_PCI_SIO<5>

CLK_14M_SIO<5>

4.7K_0402_5%

SIRQ<22,25,32,33>

R917

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ#0

SUS_STAT#
PM_CLKRUN#

CLK_PCI_SIO
SIRQ

CLK_14M_SIO

LPC47N217_SYSOPT

12

3

U40

10

LAD0

12

LAD1

13

LAD2

14

LAD3

15

LFRAME#

16

LDRQ#

17

PCI_RESET#

18

LPCPD#

19

CLKRUN#

20

PCI_CLK

21

SER_IRQ

6

IO_PME#

9

CLK14

CLOCK

23

GPIO40

24

GPIO41

25

GPIO42

27

GPIO43

28

GPIO44

29

GPIO45

30

GPIO46

31

GPIO47

32

GPIO10

33

GPIO11/SYSOPT

34

GPIO12/IO_SMI#

35

GPIO13/IRQIN1

36

GPIO14/IRQIN2

40

GPIO23

8

VSS

22

VSS

43

VSS

52

VSS

LPC47N217-JV_STQFP64

LPC I/F

GPIO

POWER

RXD1

TXD1
DSR1#
RTS1#
CTS1#
DTR1#

RI1#

DCD1#

SERIAL I/F

IRRX2

FIR

IRTX2

IRMODE/IRRX3

INIT#

SLCTIN#

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

SLCT

PE
BUSY
ACK#

PARALLEL I/F

ERROR#

ALF#

STROBE#

VTR
VCC
VCC
VCC
VCC

2

RXDB#

62

TXDB

63
64
1

CTSB#

2

DTRB#

3
4
5

IRRX

37

IRTXOUT

38

IRMODE

39
41

42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61

7
11
26
45
54

+3VALW

+3VS

RXDB# <17>
TXDB <17>

CTSB# <17>

DTRB# <17>

FOR LPC SIO DEBUG PORT

JP26

ACES_85201-2005@

+5VS

1

1

2

2

3

3

4

4

5

5

CLK_14M_SIO

6

6

LPC_AD0

7

7

LPC_AD1

8

8

LPC_AD2

9

9

LPC_AD3

10

10

LPC_FRAME#

11

11

LPC_DRQ#0

12

12

PLT_RST#

13

13

14

14

CLK_PCI_SIO

15

15

SIRQ

16

16

17

17

18

18

19

19

20

20

1

+3VS

Place the debug port under MINI card

+3VS

R283
47K_0402_5%

@

1 2

IRRX

+3VS

1

C892

@

10U_0805_10V4Z

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

10U_0805_10V4Z

R920

47_1206_5%

1 2

12

C893

R967
10K_0402_5%

@

1

1

2

2

+IR_3VS

(30mil)

C894

0.1U_0402_16V4Z

2

22U_1206_10V4Z

FIR

+3VS

(60mil)

1

C891

2

IRRX IRMODE

2
4
6
8

SD/MODE: SHUTDOWN MODE, HIGH ACTIVE
MODE: HIGH/LOW SPEED SELECT

R3

4.7_1206_5%

1 2
@

R918

4.7_0603_5%

1 2
1 2

@

R919

U41

IRED_C

SD/MODE

RXD
VCC
GND

HSDL-3220_8P

PCB Footprint : TFDU6101E

R294 0_0603_5%

3220@

Compal Electronics, Inc.(KunShan)

Title

SMSC LPC47N217/FIR

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

4.7_0603_5%

IRED_A

TXD

MODE

12

+IR_ANODE

1
3
5
7

(60mil)

IRTXOUT

1

2

R969
10K_0402_5%

@

1 2

C507

@

0.47U_0603_10V7K

X 0.5

of

1

35 53Monday, January 08, 2007

5

4

ALS/MIC & Finger Print combine CONN

+3VS

3

2

1

D D

G

2

Q70

D

1 3

GNDA<30,31>

SASBTN#<33>

USBP3+<22>
USBP3-<22>

R731

S

+3VS

S

G

2

+3VS

Q72

2N7002_SOT23

2N7002_SOT23

INTMIC1

D

1 3

D

C895

13

C896

2

@

1

SMB_EC_DA2

SMB_EC_CK2

L45

1 2

FBM-11-160808-700T_0603

1

C897

2

0.1U_0402_10V6K

SMB_EC_DA2<6,24,33,39>

SMB_EC_CK2<6,24,33,39>

INT_MIC1<30>

+3VS

C C

AO3413_SOT23

FPR_PWRON#<33>

1 2

0.22U_0603_10V7K

Q25

S

G

2

4.7U_0603_6.3V6M

12

4.7K_0402_5%

SMB_EC_DA2_ALS

SMB_EC_CK2_ALS

VDDA

GNDA

USBP3+

USBP3-

12

R732

+3VS

4.7K_0402_5%

3

1

2

ACES_85201-1205

12
11
10
9
8
7
6
5
4
3
2
1

JP34

SASBTN#

D37
PSOT24C-LF_T7_SOT23-3

DOCKING BD.

JP27

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

ACES_88363-08001

DOCK_LAN_ACT#<29>

DOCK_USB_OC#2<34>
DOCK_USB_OC#3<34>
DOCK_USB_OC#4<34>

HP_PLUG#

HP_OUT_L
HP_OUT_R

DOCK_LAN_TX2­DOCK_LAN_TX2+

DOCK_LAN_RX3­DOCK_LAN_RX3+

DOCK_LAN_TX­DOCK_LAN_TX+

DOCK_LAN_RX­DOCK_LAN_RX+

USBP4+<22>
USBP4-<22>

USBP6+<22>
USBP6-<22>

USBP7+<22>
USBP7-<22>

USBP5+<22>
USBP5-<22>

R302
R301

DS_DOCKED_ID

DOCK_LAN_ACT#
DOCK_LAN_LINK#

USBP4+
USBP4-

USBP6+
USBP6-

USBP7+
USBP7-

USBP5+
USBP5-

DOCK_USB_OC#2
DOCK_USB_OC#3
DOCK_USB_OC#4

0_0603_5%

1 2
1 2

0_0603_5%

D_HP_OUT_L

D_HP_OUT_R

DOCK_LAN_TX2-<29>
DOCK_LAN_TX2+<29>

DOCK_LAN_RX3-<29>
DOCK_LAN_RX3+<29>

DOCK_LAN_TX-<29>
DOCK_LAN_TX+<29>

DOCK_LAN_RX-<29>
DOCK_LAN_RX+<29>

DOCK_LAN_LINK#<29>

HP_PLUG#<30,31>
HP_OUT_L<30>
HP_OUT_R<30>

DS_DOCKED_ID<33>

41

41

DOCKC_IN

42

42

43

43

44

44

45

45

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

61

61

62

62

63

63

D_DOCK_MIC DOCK_MIC

64

64

65

65

66

66

67

67

68

68

69

69

70

70

71

71

72

72

73

73

74

74

75

75

76

76

77

77

78

78

79

79

80

80

HCB4532KF-800T90_1812

L20

0.1U_0805_25V7M

+5V_DOCK

+2.5V_LAN

+3VALW
VDDA

R303
R922 0_0402_5%

CRT_B_DOCKC

CRT_VSYNC_DOCK
CRT_HSYNC_DOCK

19vdc_2.25A

DOCK_IN

12

2

2

C898

1

1

0.1U_0805_25V7M

GNDA

12
12

0_0603_5%

ROTA90#

M_SEN#
3VDDCDA_R
3VDDCCL_R

Reserved for EMI

1 2

R292 0_0603_5%

1 2

R296 0_0603_5%

1 2

R300 0_0603_5%

CRT_VSYNC_DOCK <19>
CRT_HSYNC_DOCK <19>

C903

DIS_INTMIC

GNDA <30,31>

DIS_INTMIC

ROTA90# <33>

M_SEN# <19,22>

3VDDCDA_R <19>

3VDDCCL_R <19>

CRT_B_DOCK
CRT_G_DOCKCRT_G_DOCKC
CRT_R_DOCKCRT_R_DOCKC

5.1K_0402_5%
R923

1 2

DOCK_MIC <30>

DIS_INTMIC <30>

CRT_B_DOCK <19>
CRT_G_DOCK <19>
CRT_R_DOCK <19>

Need to update the Symbol

C899

C901

+5V_DOCK

1

2

+3VS

1

2

1

C900

0.1U_0402_16V4Z

2

1

C902

0.1U_0402_16V4Z

2

B B

INT_MIC2 INTMIC2

INT_MIC2<30>

0.22U_0603_10V7K

To BTN Board

C904

1 2

L46

1 2

FBM-11-160808-700T_0603

+5VALW

KSI0

KSI0<33>

KSI1

KSI1<33>

KSI2

KSI2<33>

KSI3

KSI3<33>

KSI4

KSI4<33>

KSI5

KSI5<33>

KSI6

KSI6<33>

KSI7

KSI7<33>

KSI_USER#<33>

KSI_USER#

GNDA

GNDA
VDDA

JP30

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

ACES_87151-2205

+5VALW

R964

330K_0402_5%

WAKE_PWR_EN#<32,33>

WAKE_PWR_EN#

1 2

R965 22K_0402_5%

1 2

C930

1

2

Q63
AO3413_SOT23

S

0.47U_0603_16V7K

+5V_DOCK

D

13

G

2

12

R970

22K_0402_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

To support wake up from Docking.

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Docking Conn /FingerPrinter /Button board Conn

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

36 53Monday, January 08, 2007

X 0.5

5

D D

+1.8V +1.8VS

U42

8

D

7

D

6

D

5

D

1

+

C907
100U_D2_6.3VM

2

C C

1

AO4468_SO8
C908
10U_1206_6.3V7K

2

+1.8V to +1.8VS Transfer

1

1

S

2

S

3

S

4

G

C905

10U_0805_10V4Z

2

1

C909

0.1U_0402_16V4Z

2

1

2

13

D

Q33

S

C906

0.1U_0402_16V4Z

1 2

R931

SUSP

2

2N7002_SOT23

G

4

100K_0402_1%

+12VALW

3

+5VS +3VS +2.5VS +1.8VS +1.5VS +0.9VS

12

R926
470_0402_5%

@

13

D

Q28

SUSP SUSP SUSP SUSP

2

2N7002_SOT23

G

S

@

+VCC_CORE +VCCP

VR_ON#

2

G

D

S

+1.8V

D

S

12

13

Q27

12

13

Q34

R925
470_0402_5%

SUSP

2

2N7002_SOT23

G

R932
470_0402_5%

@

SYSON#

2

G

2N7002_SOT23

@

12

13

D

Q29

S

R927
470_0402_5%

@

2

2N7002_SOT23

G

@

12

R933
330_0402_5%@

13

D

Q35
2N7002_SOT23

@

S

2

12

13

D

Q30

S

R928
470_0402_5%

@

2

2N7002_SOT23

G

@

VR_ON#

12

R929
470_0402_5%

@

13

D

Q31

2

2N7002_SOT23

G

S

@

12

R934
330_0402_5%

@

13

D

Q36

2

2N7002_SOT23

G

@

S

12

13

D

Q32

S

1

R930
470_0402_5%

@

SUSP

2

2N7002_SOT23

G

@

+3VALW +3VS

U43

8

D

7

D

6

D

5

D

1

+

C912
100U_D2_6.3VM

2

B B

1

+

C917
100U_D2_6.3VM

2

A A

5

1

AO4468_SO8
C913
10U_1206_6.3V7K

2

U44

8

D

7

D

6

D

5

D

1

AO4468_SO8

C918
10U_1206_6.3V7K

2

+3VALW to +3VS Transfer

1

1

S

2

S

3

S

4

G

+5VS+5VALW

1

S

2

S

3

S

4

G

1

2

C910
10U_0805_10V4Z

2

1

C914

0.1U_0402_16V4Z

2

+5VALW to +5VS Transfer

1

C915

0.1U_0402_16V4Z

2

C919

0.1U_0402_16V4Z

1

C911

0.1U_0402_16V4Z

2

R937 56K_0402_5%

13

D

Q37

G

S

1

C916

10U_0805_10V4Z

2

1 2

R938 47K_0402_5%

13

D

Q40

2

G

2N7002_SOT23

S

1 2

SUSP

2

2N7002_SOT23

SUSP

4

+12VALW

+12VALW

+5VALW

12

R936
10K_0402_5%

SYSON#

13

2

2

G

G

D

S

+3VALW

1 2

13

D

S

Q38
2N7002_SOT23

R939

100K_0402_5%@

VR_ON#

Q41
2N7002_SOT23

@

SYSON

SYSON<33,45>

VR_ON

VR_ON<33,46>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

SUSP<43>

SUSP#<30,33,39>

+5VALW

12

13

SUSP

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

2

Date: Sheet

D

2

G

S

DC-DC interface

PecosII-IDX80-LA3291

SUSP

R940
100K_0402_5%

Q42

2N7002_SOT23

2

G

+5VALW

12

13

D

S

R935

10K_0402_5%

Q39
2N7002_SOT23

SUSP#P <43,45>

1

C920

0.1U_0402_16V4Z

2

1

X 0.5

of

37 53Monday, January 08, 2007

5

4

3

2

1

+1.8VS

R941

D D

C C

1K_0402_5%

1 2

R942

330_0402_5%

2

1 2

Q44
MMBT3904_NL_SOT23

3 1

560K_0402_5%

+1.5VS

R948

10K_0402_5%

330_0402_5%

1 2

VCCP_POK<43>

330_0402_5%

R947

R949

1 2

2

3 1

+3VS+3VS

R943

1 2

Q43

2

MMBT3904_NL_SOT23

3 1

+5VS

12

R946

180K_0402_5%

12

1

0.1U_0402_16V4Z

2

+2.5VS+2.5VS

R950

330_0402_5%

2

Q48

MMBT3904_NL_SOT23

+3VALW

14

P

1

G

7

C923

1 2

Q47
MMBT3904_NL_SOT23

3 1

U45A

O2I

74LVC14APW_TSSOP14

1 2

47K_0402_5%

+3VALW

1

2

14

U45C

P

5

O6I

G

74LVC14APW_TSSOP14

7

+3VALW

14

U45D

P

9

O8I

G

74LVC14APW_TSSOP14

7

R944

C922

0.1U_0402_16V4Z

+3VALW

14

U45B

P

3

G

74LVC14APW_TSSOP14

1

7

C921

0.1U_0402_16V4Z

2

13

2

G

13

2

G

O4I

D

Q45
2N7002_SOT23

S

D

Q46
2N7002_SOT23

S

D25

21

RB751V_SOD323

J6

2 1

NO SHORT 2x2m

+3VS

12

R945

10K_0402_5%

PWR_GD

PWR_GD <33>

1

CF13

H16
HOLEA

H13
HOLEB

H29
HOLEE

1

1

CF11

CF7

1

CF14

1

1

H12
HOLEA

1

H3
HOLED

1

CF1

CF3

1

1

H51
HOLEE

1

H8

H14
HOLEA

1

H22
HOLED

1

HOLEA

1

H10
HOLED

H6
HOLEA

1

H19
HOLED

1

1

X 0.5

38

1

53Monday, January 08, 2007

of

CF8

CF10

B B

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

CLIP1

1

Antenna_CLIP

1

1

CF12

FD1

H25
HOLEC

1

H18
HOLEA

1

H2
HOLEA

1

1

FD2

1

H9
HOLEA

1

H27
HOLEA

1

H4
HOLEA

1

CF9

1

1

FD3

1

1

H26
HOLEA

1

H5
HOLEA

1

2

1

H17
HOLEA

CF4

FD6

1

H7
HOLEB

1

1

1

CF5

FD5

H20
HOLEA

1

H11
HOLEB

1

CF6

CF2

1

1

FD4

1

1

H1
HOLEE

1

H21
HOLEA

1

H15
HOLEB

1

Compal Electronics, Inc.(KunShan)

Title

POWER OK CKT

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

5

4

3

2

1

12

PC6

560P_0402_50V7K

PQ4

IRLML5103_SOT23

S

1 2

13

PQ5
DTC115EUA_SC70

DOCK_IN

G

D D

+12VALW

1 2

PQ3

2

G

1 2

100K_0402_5%

560P_0402_50V7K

PR21

2

P1

12

PC3

PR8

22.1K_0402_1%

1 2

PR13

57.6K_0402_1%

1 2
13

D

S

MOLEX_53780-0290

PR19

10K_0402_5%

12

13

12P_0402_50V8J

PJPC1

1
2

12

PQ6
DTC115EUA_SC70

PC4

2

B

2

B

PACIN

12

C

E

PJPD1

1

2

4

G

5

G

3

SINGA_2DC-S028B200

C C

PR11

43.2K_0402_1%

12

40.2K_0402_1%

12

PH1

100K_0603_1%_TH11-4H104FT

2

1

3

PD2

B B

DAN217_SC59

1
2
3

PR7

22.1K_0402_1%

PR12

12

RHU002N06_SOT323

PC9

0.1U_0603_25V7K

SPOK

SPOK<42>

SUSP#<30,33,37>

P1

SUSP#

PL1

FBMA-L18-453215-900LMA90T_1812

1 2

12

PR9
442_0402_1%

1 2
31

E

PQ1
2SA1037AK_SC59

C

1

PQ2
2SC2412K_SC59

3

PD3

1SS355TE-17_SOD323-2

1 2

2

G

PC5

12P_0402_50V8J

PR15

100K_0402_5%

2

13

D

PQ7

S

RHU002N06_SOT323

PR34

3.4K_0402_1%

1 2

PR10

3.92K_0402_1%

1 2

12

PR1

10_1206_5%

12

PD1
RLZ24B_LL34

D

13

2

B540C_SMC

PD26

2 1

B540C_SMC

PD27

2 1

PD4

RB160L-40_SOD106

12

VIN

BATT_A

12

PC1

0.01U_0402_25V7K

PJP1 battery connector

SMART
Battery:

1.BAT+

2.ID

3.B/I

4.TS

5.SMD

6.SMC

7.GND

BATT_B

12

0.01U_0402_25V7K

B+

PJP2 battery connector

SMART
Battery:

VSB

1.BAT+

2.ID

3.B/I

4.TS

5.SMD

6.SMC

7.GND

PL2

FBMA-L18-453215-900LMA90T_1812

1 2

PC2

1000P_0402_50V7K

PL3

FBMA-L18-453215-900LMA90T_1812

1 2

1000P_0402_50V7K

PC8

PC7

SUYIN_250263MR007G107ZL

BATT_A+

BATT_A+

12

PJP1

1

1
2
3
4
5
6
7

SUYIN_250263MR007G110ZR

12

PJP2

1
2
3
4
5
6
7

2
3
4
5
6
7

BATT_B+

BATT_B+

1K_0402_5%

1K_0402_5%

PR16

PR3

12

12

1 2

1K_0402_5%

1 2
1 2

PR5 100_0402_5%

1 2

100_0402_5%

1 2

1K_0402_5%

1 2

1 2

PR18 100_0402_5%

1 2

PR20

100_0402_5%

BATT_TEMP1

PR2

PR4

6.49K_0402_1%

PR6

BATT_TEMP2

PR14

PR17

6.49K_0402_1%

BATT_TEMP1 <33>

+3VALW

SMB_EC_DA1 <24,33,34>

SMB_EC_CK1 <24,33,34>

BATT_TEMP2 <33>

+3VALW

SMB_EC_DA2 <6,24,33,36>
SMB_EC_CK2 <6,24,33,36>

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

PWR-Vin/bridge Batt/RTC

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

39 53Monday, January 08, 2007

X 0.5

5

4

3

2

1

Iadp=0~2.38A(45.23W)

Charger

4

PC15

0.1U_0603_25V7K

12

13

D

S

PR155

10K_0402_1%

1 2

PR42

158K_0603_1% @

P2

1
2
36

12

12

PR33

100K_0402_1%

PACIN

12

PQ8

AO4407_SO8

47K

2

47K

13

PQ12

DTC115EUA_SC70

RHU002N06_SOT323

PD29

RLZ4.3B_LL34

8
7

5

1 3

PR27

150K_0402_5%

PQ16

ACIN<33,42>

PACIN

2

G

12

VIN

D D

DTA144EUA_SC70

12

PR23

47K_0402_5%

13

D

2

G

S

PQ14

RHU002N06_SOT323

C C

ACOFF#

PACIN

B B

ACON<44>

2

1SS355_SOD323

1 2

PR38

22K_0402_5%

1 2

PQ11

PD10

PQ9

AO4407_SO8

1
2
3 6

4

PR24

200K_0402_1%

PC17

1U_0603_10V6K

215K_0402_1%

PR29

12

12

DTC115EUA_SC70

12

PC18

0.1U_0402_16V7K

PR40

10K_0402_5%

PQ17

1908LDO

8
7

5

0.1U_0603_25V7K@

12

PR31

9.31K_0402_1%

15K_0402_1%

12

13

1908LDO

2

PC13

1SS355_SOD323

VIN

12

PR32

12

P3

PD7

1 2

PR41

100K_0402_1%

FSTCHG<33,41>

12

12

0.1U_0603_25V7K

ICTL

12

0_0402_5%

1 2

PR22

1
2

0.01_2512_1%

PC16

PC23

0.01U_0402_16V7K

PR43

4
3

12

12

PR28

0_0402_5%

REF_MAX1908

VCTL

0_0402_5%

PR35

0.1U_0402_16V7K

B+

FBMA-L18-453215-900LMA90T_1812

1 2

PC14

0.1U_0603_25V7K@

PU1

1

DCIN

17

12

CELLS

4

REF

3

CLS

12

REFIN

15

VCTL

13

ICTL

11

ACOK#

8

SHDN#

10

12

ACIN

9

ICHG

28

IINP

7

CCV

CCI

6

CCI

PR39

1 2

10K_0402_1%

12

12

PC26

PC28

0.001U_0402_50V7M

PL4

CCS

5

MAX1908-CCS

12

PC27

0.001U_0402_50V7M

PQ10

AO4407_SO8

1
2

1

PC10

2

10U_1206_25V6M

CSSP

CSSN

DHI

DLO

BST

DLOV

LDO

CSIP
CSIN

BATT

PGND

GND

20

14

PC12

PC11

2

2

10U_1206_25V6M

10U_1206_25V6M

27
29

TP

26

DHI

25

LX

23

LX

DLO

21

BST

24

22
2

1908LDO
19
18
16

MAX1908ETI+T_QFN28

CSIP

8
7
6
5

PR186 0_0402_5%

PC24
1U_0603_10V6K

1 2

BATT+

AO4916_SO8

G2
D1/S2/K
D1/S2/K
D1/S2/K

PQ15

12

33_1206_5%

PR36

S1/A

12

1

D2

2

D2

3

G1

4

PC25
1U_0805_25V4Z

1 2

1

1

3 6

PR26

10K_0402_5%

ACOFF#

16UH_D104C-919AS-160M_3.7A_20%

1 2
12

1 2

PC19

0.1U_0603_25V7K

PD9
1SS355_SOD323

4

47K_0402_5%

1 2

1 2
13

10K

10K

PQ13

DTC114EKA_SC59

PL5

8
7

5

PR25

2

12

1 2

PR30

1
2

0.015_2512_1%

VIN

PD5

RLZ22B_LL34@

PD6
1SS355_SOD323 @

1 2

PD8

1SS355_SOD323

4
3

ACOFF

BATT+

12

PC20

4.7U_1206_25V6K

<33>

12

12

PC22

PC21

4.7U_1206_25V6K

4.7U_1206_25V6K

PR44

100K_0402_5%

PR47

PR46

VIN

12

12

PR48
20K_0402_1%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

IREF <33>

12

PR37

100K_0402_1%

ICTL

12

PR184
100K_0402_1%

A A

CHGSEL<33>

+12VALW

12

PR262

100K_0402_1%

13

D

PQ49

2

RHU002N06_SOT323

G

S

13

PQ51
DTC115EUA_SC70

2

5

1908LDO

12

12

PR163

84.5K_0402_1%

PR164

100K_0402_1%

PACIN

VCTL

4

150K_0402_1%

681K_0402_1%

1 2

PR45

10K_0402_5%

12

PC29

0.1U_0402_16V7K

1 2

1 2

Vin Detector(Detector Point:pin10 of PU1)
typ.

L-->H V 17.85V V
H-->L V 16.98V V

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Charge voltage

4S CC-CV MODE : 17.4V for 2800mAH Battery
4S CC-CV MODE : 16.8V for 2600mAH,2400mAH Battery

Charge mode

CC-CV

Pulse charge.

Title

Size Document Number Rev

Custom

2

Date: Sheet

Change voltage.VCTL

1908LDO.

2.0769V PR164=100K

16.8V

17.0V

Note.

PR163=0,PR164=@
PR163=160K

Compal Electronics, Inc.(KunShan)

PWR-Changer MAX1908ETI

PecosII-IDX80-LA3291

1

40 53Monday, January 08, 2007

X 0.5

of

5

4

3

2

1

PACIN

12

PR50

412K_0603_1%

D D

C C

B B

A A

PC121

0.1U_0402_16V7K

12

PQ18

FDS4935_SO8

BATT_B BATT_A

RTCVREF

BATT+

3

1

2

4

S1

S2

G2

G1

D2

D1

D2

D1

8

5

7

6

8

5

7

6

D2

D1

D2

D1

G2

S1

S2

G1

2

3

1

4

RHU002N06_SOT323

1 2

100K_0402_1%

309K_0402_1%

PQ19

FDS4935_SO8

PQ25

PR51

PR49

D

S

12

1 2

3K_0402_5%

1 2

PR93
2K_0402_5%

1 2

13

G

VS

8

3

P

+

2

-

G

4

PC122

0.01U_0402_16V7K

PR91

2

PU7A

O

LM393DG_SO8

1 2

13

D

S

VL

1 2

1

PR166

10K_0402_1%

1U_0805_25V4Z

3K_0402_5%

RHU002N06_SOT323

PC30

PR92

1 2

PR101
2K_0402_5%

PQ26

2

G

1 2

PR165

10K_0402_1%

PACIN

1SS355TE-17_SOD323-2

VIN

MAX1538ETI+T_QFN28

12

PD30

1 2

PD31

1 2

PU2

11

ADPIN

12

ADPPWR

13

REVBLK

16

EXTLD

14

ADPBLK

18

DISBAT

17

CHGIN

19

CHGA

20

CHGB

23

DISB

24

DISA

22

BATB

25

BATA

29

TP

27

PR59

100K_0402_1%

@

PC33

1 2

1 2

0.047U_0603_50V7K

BATT_UVM <44>

1SS355TE-17_SOD323-2

GND

NA

PC34

10

AIRDET

MINVA

1

1 2

@

0.047U_0603_50V7K

12

12

9

ACDET

PR58

66.5K_0402_1%

PR160

10K_0402_1%

PC120

0.01U_0402_16V7K

CHRG

BATSEL

RELRN

OUT2
OUT1
OUT0

BATSUP

NC2
NC1

VDD

MINVB

2

12

5
3

4

8
7
6

26
21

15

28

1 2

PR54

0_0402_5%

PC32

PR167

0_0402_5%

1 2

PR52

0_0402_5%@

1 2

1538VCC

12

PC31

1U_0805_25V4Z

1538VDD

12

1U_0603_10V6K

7

0

1908LDO

VS

8

PU3B

5

P

+

6

-

G

LM358DT_SO8

4

PR55

100K_0402_5%

1 2

PR56

100K_0402_5%

1 2

PR57

100K_0402_5%

1 2

1538VDD

BATT_OVP<33>

1 2

PR53

0_0402_5%

FSTCHG <33,40>
BATSELB_A# <33>

OVP voltage :
LI-4S :17.8V----BATT-OVP=1.9758V(4.2V CELL)

LI-4S :18V-----BATT-OVP=1.998V(4.35V CELL)
BATT-OVP=0.111*BATT+

BATT+

VS

12

8

PU3A

3

P

+

1

0

2

-

G

LM358DT_SO8

4

12

PR60
845K_0603_1%

12

PC35

PR61
300K_0603_0.1%

0.01U_0402_25V7Z

12

PR62
143K_0402_1%

12

PC36

0.01U_0402_25V7Z

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

PWR-Batt Select & OVP

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

41 53Monday, January 08, 2007

X 0.5

5

4

3

2

1

B+

+3VALWP Choke DCR = 37m .

Current limit Threshold Min.=80 mV Mx.=120mV.
OCP Min.= 80mV/1.27K*(2.8K+1.27K)/37=6.929A
OCP Max.=120mV/1.27K*(2.8K+1.27K)/37=10.394A

PC38

Change from 2.2U to 10U for S3 noise issue

D D

2200P_0402_50V7K@

C C

+3VALWP

PC53

1

B B

+

2

150U_D2E_6.3VM_R18

PL6

FBMA-L18-453215-900LMA90T_1812

1 2

B+++

12

PC41

PD15

PR76

1 2

SKUL30-02AT_SMA

3.57K_0402_1%

2 1

12

PC42
10U_1206_25V6M

PL8

4.7UH_PCMC063T-4R7MN_5.5A_20%

1 2

1 2

12

PR79

10K_0402_1%

PR69

PC52

100P_0402_25V8K

12

PC49
47P_0402_50V8J

1M_0402_1%

1 2

PQ20

1

D2

2

D2

3

G1

4

S1/A

AO4916_SO8

1 2

PR67

2.8K_0402_1%
PR68

1.27K_0402_1%

FB3

47K_0402_5%@

0.1U_0603_25V7K

1 2

D1/S2/K
D1/S2/K
D1/S2/K

ACIN<33,40>

PR168

PC39

BST31

8

G2

7
6
5

LX3

12

0.47U_0603_16V7K
PC50

12

PR72

619_0402_1%

1 2

1 2

PR73

10K_0402_5%

PR75

300K_0402_5% @

VS

12

PR122

0_0402_5%

12

12

DL3

12

PC59
1U_0805_25V4Z

@

12

PR64
0_0402_5%

DH3

12

PC54

1000P_0402_50V7K

25
27
26

24

1
2

3
10
23

7
28

12

PC58

2.2U_0805_10V6K

PD13

PR185

10_1206_5%

12

PU4

BST3
DH3
LX3

DL3

CSH3
CSL3
FB3
SKIP#
SHDN#

TIME/ON5
RUN/ON3

VS

VL

1 2
12

1SS355TE-17_SOD323-2

PC46

0.1U_0603_25V7K

22

V+

GND

8

MAINPWRON <44>

2

3

PD12
CHP202UPT_SOT323-3

1

4.7U_0805_6.3V6K
PC43

12

ACIN

21

4

12OUT

VL

5

VDD

18

BST5

16

DH5

17

LX5

19

DL5

20

PGND

14

CSH5

13

CSL5

12

FB5

15

SEQ

9

REF

6

SYNC

11

RESET#

PR77

0_0402_5%

MAX1902EAI+T_SSOP28

PR193

2.7K_1206_5%

@

2

G

PQ40

RHU002N06_SOT323@

1 2

SPOK <39>

BST51

+12VALWP

12

12

13

D

S

VDD_MAX1902

12

PC48

4.7U_1206_25V6K

BST5

2.5VREF

PC55

4.7U_0805_6.3V6K

PR66

1 2

FB5

1 2

0_0402_5%

DH5

PC40

0.1U_0603_25V7K

LX5

DL5

PC51

0.47U_0603_16V7K

8
7
6
5

12

PQ21

G2
D1/S2/K
D1/S2/K
D1/S2/K

AO4916_SO8

12

PR74
698_0402_1%

12

PR78

10.2K_0402_1%

12

D2
D2
G1

S1/A

12

PR81
10K_0402_1%

470P_0805_100V7K@

1 2

FLYBACKSNB

12

PR63
22_1206_5%@

B+++

1
2
3
4

12

12

PC44

PC45

2200P_0402_50V7K

10U_1206_25V6M

@

12

PR71

1.54K_0402_1%

PC57
100P_0402_25V8K

PD16

SKS10-04AT_TSMA

+5VALWP Choke DCR = 40m .

+3.3V/+5V/+12V

PC37

10U_1206_25VAK

1 2

12

PD11
EC11FS2_SOD106

PL7

9UH_SDT-1204P-9R0-120 GP_4.5A_20%

1 4

3 2

12

PC47
47P_0402_50V8J

12

PR70
2M_0402_1%

1

+

PC56

2

2 1

150U_D2E_6.3VM_R18

+5VALWP

Current limit Threshold Min.=80 mV Mx.=120mV.

OCP Min.= 80mV/0.698K*(1.54K+0.698K)/40=6.412A

A A

RS2(PR64)=RS1(PR58)*RS3(PR61)/(RS1+RS3)

OCP Max.=120mV/0.698K*(0.698K+1.54K)/40=9.593A

L/RL(DCR)=RS1*RS3(PR61)/(RS1+RS3)*Cs(PC56)

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

PWR-+3.3V/5V/12V

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

42 53Monday, January 08, 2007

X 0.5

5

4

3

2

1

12

+12VALWP

+5VALWP

+1.8VP

+2.5VSP

+VCCPP

+0.9VSP

+1.5VSP

+2.5VSP

+2.5VSP

PC119
22U_1206_6.3V6M

PJP3

2MM

PJP4

3MM

PJP5

3MM

PJP6

3MM

PJP7

3MM

PJP8

3MM

PJP9

3MM

PJP10

3MM

21

+12VALW

21

+5VALW

21

+3VALW+3VALWP

21

+1.8V

21

+2.5VS

21

+VCCP

+0.9VS

21

21

+1.5VS

+3VALW

12

PC118

XC61CN0902MR

1

VDDIN

4.7U_0805_6.3V6K

SUSP#P<37,45>

PU14

PWDOUT
VSS

3

1 2

1000P_0402_50V7K@

PR80

0_0402_5%

PC67

2

12

5

4

5

4

+1.8V

D D

SUSP<37>

C C

PL22

FBMA-L11-322513-201LMA40T_1210

1 2

B+

B B

PR269

0_0402_5%

VCCP_ON#<33>

A A

1 2

1 2

PR84

0_0402_5%

12

12

PC61
10U_1206_6.3V7K

13

D

2

G

S

PC184

10U_1206_25VAK

12

PC189

0.22U_0603_16V7K@

PR83

1K_0402_1%

PQ23

RHU002N06_SOT323

6269_VCC

12

PC187

2.2U_0603_6.3V6K

12

PR82

1K_0402_1%

12

22U_1206_10V6M@

12

PC62

0.1U_0603_25V7K

PR268

0_0402_5%

1 2

12

PC191

22P_0402_50V8J

PC63

PU5

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8

12

12

6269_VCC

1

VIN

2

VCC

3

FCCM

4

EN

12

PR271

49.9K_0402_1%

12

6
5

NC

7

NC

8

NC

9

TP

+0.9VSP

PC64
22U_1206_10V6M

PR264

1K_0402_1%

1 2

17

16

GND

PGOOD

PU16

ISL6269CRZ-T_QFN16

COMP5FB6FSET

PC192
6800P_0402_25V7K

PR274

2K_0402_1%

15

PHASE

PR272

57.6K_0402_1%

12

12

PHASE_6269

14

UG

7

12

+3VALW

PC60
1U_0603_10V6K

PR265

1 2

0_0603_5%

BOOT_6269

13

BOOT

PVCC

LG

PGND

ISEN

VO

8

12

PC190

0.01U_0402_25V7K

+VCCPP

1000P_0402_50V7K

12

@

4.7_0603_5%

4.7_0603_5%

1 2

12

2.2U_0603_6.3V6K

11

10

ISEN_6269

9

6.49K_0402_1%

12

PC88

UG_6269

1 2

PC185 0.1U_0603_25V7K

+5VS

PR266

PR267

6269_VCC

PC186

1 2

LG_6269

PR270

1 2

PR273

1.5K_0402_1%

1 2

PU12

EN_2.5VSP

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

VIN2VO

1

EN

5

GND

6

GND

G965-18ADJP1UF_SO8

VCCP_POK <38>

PQ52

SI4800BDY-T1-E3_SO8

2.2UH_SSC-10030D3-2R2_7A_20%
PL23

PQ53
SI4810BDY-T1-E3_SO8

3

GND
GND

12

3
4

ADJ

7
8

12

PR156

11K_0402_1%

12

PR157

10K_0402_1%

+VCCPP

1

+

PC188

330U_D2E_2.5VM

2

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

+0.9VSP&VCCP&+2.5

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

43 53Monday, January 08, 2007

X 0.5

5

PH2 under CPU botten side :

CPU thermal protection at 80 degree C

D D

C C

B B

A A

Recovery at 44(45) degree C

VL VL

12

PR96

VSB

BATT_A

BATT_B

200_0805_5%

CHGRTCP

2.15K_0402_1%

12

PC76

1000P_0402_50V7K

RB751V-40TE17_SOD323-2

12

PR104

EC_ON#<34>

12

PH2

10KB_0603_1%_TH11-3H103FT

PD28

PD19

RLS4148_LLDS2

PD21

RLS4148_LLDS2

PR106

100K_0402_5%

1 2

PR108

22K_0402_5%

12

PC86
1U_0805_25V4Z

PR97

16.9K_0402_1%

1 2

PC77

1U_0603_10V6K

12

12

12

G920AT24U_SOT89

2

IN

TM_REF1

12

1 2

PU9

GND

1

OUT

12

1538VCC

12

3

47K_0402_1%

1 2

5

+

6

-

12

PR98

150K_0402_1%

PR99
150K_0402_1%

TP0610K-T1-E3_SOT23

PC85

0.22U_1206_25V7K

RTCVREF

12

PC87

4.7U_0805_6.3V6K

VS

PR94

8

PU7B

P

O

G

LM393DG_SO8

4

VL

PQ27

2

1 2

560_0402_5%

7

PR109

4

PR95
47K_0402_1%

12

PC75

0.1U_0603_25V7K

VIN

1 2
12

13

12

1 2

PD20
RLS4148_LLDS2

PR102
33_1206_5%

VS

PC83

0.1U_0603_25V7K

MAINPWRON

ACIN

BATT ONLY

3

VL

12

PR65
100K_0402_5%

2
3

PD33

D

S

10K_0402_5%

PQ22
RHU002N06_SOT323

13

2

G

PR204

1

0.1U_0603_25V7K

BATT_UVM<41>

MAINPWRON<42>

ACON<40>

RB715F_SOT323

Precharge detector

Min. typ. Max.
H-->L 14.556V 14.807V 15.372V
L-->H 15.276V 15.836V 16.411V

Precharge detector

1 2

VL

PC147

PC73

12

D

S

0.022U_0402_16V7K

VL

12

PR86
470K_0402_1%

PQ24

RHU002N06_SOT323

13

2

G

PD17

RLS4148_LLDS2

PU13A

1

O

LM393DG_SO8

12

VL

12

VIN

VS

8

P

G

4

2

12

RLS4148_LLDS2

PR192

2M_0402_1%

12

12

PC71

3

+

2

-

12

PC69

1000P_0402_50V7K

PR209

34K_0402_1%

PR210

66.5K_0402_1%

PC78

1 2

0.022U_0402_16V7K
PR87
470K_0402_1%

PD32

12

0.1U_0603_25V7K

12

VL

12

PR88

7

12

13

D

S

1 2

VS

47K_0402_1%

PU13B
LM393DG_SO8

8

5

P

+

O

6

-

G

4

PR200

1.5K_1206_5%

1 2

PR201

1.5K_1206_5%

1 2

PR202

1.5K_1206_5%

1 2

PR203

1.5K_1206_5%

1 2

B+

PR206

140K_0402_1%

RHU002N06_SOT323

PQ35

2

G

13

VL

PR205
412K_0603_1%

12

PR207

634K_0603_1%

1 2

47K_0402_5%

PQ43
DTC115EUA_SC70

PR208

2

12

PC79

B+

12

1000P_0402_50V7K

100P_0402_50V8J

PC146

BATT_B

12

PR89
287K_0402_1%

12

PR90
499K_0402_1%

PACIN

1

+5VALW

Min. typ. Max.

1 2

PR110

560_0402_5%

CHGRTC

H-->L 5.044V 5.096V 5.205V
L-->H 6.008V 6.124V 6.243V

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

RTC Batt&OTP&Pre-charge

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

44 53Monday, January 08, 2007

X 0.5

5

D D

12

PC148

2200P_0402_50V7K

@

PQ44

1

C C

PL18

1 2

1

+

PC157

2

150U_D2E_6.3VM_R18

4.7UH_MPL73-4R7_5.5A_20%

12

PC158

4.7U_0805_6.3V6K

@

+1.8VP

B B

D2

2

D2

3

G1

4

S1/A

AO4916_SO8

DL1_1.8VP

D1/S2/K
D1/S2/K
D1/S2/K

12

PC149

4.7U_1206_25V6K

8

G2

7
6
5

4

0.1U_0603_25V7K
PC155

LX1_1.8VP

SYSON<33,37>

2

12

0.01U_0402_25V7K@

1

PD34
DAP202U_SOT323

3

1 2

PR211

0_0402_5%

DH1_1.8VP

PR216

0_0402_5%

PC161

BST1_1.8VP

12

12

12

PU10

BST1
DH1
LX1

DL1
CS1

OUT1
FB1

ON1

OVP

8

0.22U_0603_10V7K

1U_0805_25V4Z

4

V+

GND

23

0.1U_0603_25V7K
PC153

25
26
27

24
28

1
2

11

MAX8743EEI+T_QSOP28~N

PC154

12

PC162

22

SKIP

6

PR212

20_0603_5%

1 2

VCC_MAX8743

9

VDD

UVP

VCC

BST2

DH2

LX2
DL2
CS2

OUT2

FB2

ON2

PGOOD

TON

ILIM2
ILIM1

REF

10

33K_0402_1%

PR219

REF_MAX8743

12

15K_0402_1%

PR218

3

21
19

18
17
20
16

15
14
12

7
5

13
3

+5VALW

12
12

12

PC100

4.7U_0805_6.3V6K

0_0402_5%

1 2

PR213

BST2_1.5VSP

ILIM2_1.5VSP

ILIM1_1.8VP

12

PR220

100K_0402_1%

DH2_1.5VSP

12

PR221

PC156

0.1U_0603_25V7K

12

100K_0402_1%

FB2_1.5VSP

1 2

0_0402_5%

PR217

LX2_1.5VSP

2

PQ45

8

G2

D2

7

D2

D1/S2/K

6

G1

D1/S2/K

5

D1/S2/K

S1/A

AO4916_SO8

DL2_1.5VSP

SUSP#P <37,43>

1
2
3
4

4.7UH_MPL73-4R7_5.5A_20%

1 2

1845_B+

12

PC150

PL19

2200P_0402_50V7K

@

PR215

10K_0402_1%

PJP11
3MM

12

PC151

21

4.7U_1206_25V6K

12

PC152

4.7U_1206_25V6K

12

PR214

5.1K_0402_1%

12

1

B+

+1.5VSP

1

12

+

PC159

PC160

2

4.7U_0805_6.3V6K

@

150U_D2E_6.3VM_R18

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

+1.5VSP & +1.8VP

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

45 53Monday, January 08, 2007

X 0.5

5

D D

PR225

13K_0402_1%

NTC

@

PH4

100K_0603_1%_TH11-4H104FT

1 2
1 2
1 2

CLK_ENABLE#

1 2

1 2

1 2

SHDN#

DPRSLPVR

DPRSTP#

PR246

2K_0402_1%

PWRGD_CPU

CLKEN#

PR257

12
12
12
12
12
12

PSI#

0_0402_5%@

1 2

PR226 0_0402_5%
PR228 0_0402_5%
PR229 0_0402_5%
PR230 0_0402_5%
PR232 0_0402_5%
PR234 0_0402_5%

C C

B B

A A

PR235 0_0402_5%

PR239 499_0402_1%
PR240 0_0402_5%
PR241 0_0402_5%

PR249

0_0402_5%

VGATE_INTEL<22,33>

CLK_ENABLE#<5>

1 2

0_0402_5%
PR252

1 2

VR_ON<33,37>

1 2

PR254

0_0402_5%

PWRGD_CPU

PR261,PQ54 will be populated
when MAX8870 Rev0.2 is used.

2

PQ54

G

H_DPRSLPVR<9,22>

H_DPRSTP#<6,21>

+3VS

+3VS

CPU_VID0<7>
CPU_VID1<7>
CPU_VID2<7>
CPU_VID3<7>
CPU_VID4<7>
CPU_VID5<7>
CPU_VID6<7>

H_PSI#<7>

2K_0402_1%

1 2

10K_0402_5%@

1 2

H_PROCHOT#<6>

PR261
2K_0402_1%@

1 2

13

D

S

PR245

PR255

RHU002N06_SOT323@

1 2

D0_CPU

D1_CPU
D2_CPU

D3_CPU
D4_CPU

D5_CPU

D6_CPU

PR238 71.5K_0402_1%

PC173470P_0402_50V7K

1 2

PC175 0.22U_0603_16V7K

Tsw=Cton(Rton+6.5k) Cton=16.26pf
f=1/Tsw=1/Cton(Rton+6.5K)
=1/16.26pf(200k+6.5k)=297.824khz
Rton=PR224

VRHOT

12

PR223
10_0402_5%

VCC_CPU

12
12

REF_CPU

PR258
10K_0402_5%

1 2

POUT

PC180

0.1U_0402_16V7K

1 2

4

PC170

2.2U_0603_6.3V6K

1 2

PU15

19

Vcc

6

THRM

31

D0

32

D1

33

D2

34

D3

35

D4

36

D5

37

D6

7

TIME

9

CCV

11

REF

39

DPRSLPVR

40

DPRSTP

3

PSI

2

PWRGD

1

CLKEN

38

SHDN

5

VRHOT

4

POUT

MAX8770GTL+_TQFN40

VSSSENSE<7>

+5VS

PR222

12

0_1206_5%

PC169

2.2U_0603_6.3V6K

VDD
TON

BST1

DH1

LX1

DL1

PGND1

GND
CSP1
CSN1

FB

CCI

DH2

BST2

LX2

DL2

PGND2

CSP2
CSN2

GNDS

41

VSSSENSE

1 2

25
8
30
29
28
26
27
18
17
16
12
10
21
20
22
24
23
14
15
13

TP

PC179

100_0402_5%

10_0402_5%

VDD_CPU

DH1_CPU
LX1_CPU
DL1_CPU

CSP1_CPU
CSN1_CPU
FB_CPU
CCI_CPU

CSN2_CPU

1 2

PR256

PR259

200K_0402_5%

1000P_0402_50V7K

PR224

1 2

12

12

1 2

12

PC163

0_0402_5%

PR227

+5VS

3

0.01U_0402_25V7Z

0.22U_0603_16V7K
PC171

BSTM1_CPUBST1_CPU

1 2

For ULV CPU, PR247 value 8.87K, P/N:SD034887180
For LV CPU, PR247 value 3.65K, P/N: SD034365180

PQ47

IRF7832PBF_SO8

PR244 1K_0402_1%@

PR247 3.65K_0402_1%

1 2

NTC

PR250

3K_0603_1%@

1 2

PR253

20K_0402_1%

5

4

2

1 2

1 2

S

D8D7D6D

S1S3G

CPU_B+

5

PQ48

4

IRF7832PBF_SO8

DL1_CPU

1 2

PR251
3K_0603_1%@

470P_0402_50V8J

PR260 0_0402_5%

1 2

PQ46

3 5

241

D8D7D6D

S1S3G

S

2

PR243 0_0402_5%

1 2

1 2

PC178

2

PC183

15U_D2_25VM_R90

SI7840DP-T1-E3_SO8

12

4.7_1206_5%

PR231

@

12

PC172

680P_0402_50V7-K

@

PC176 1000P_0402_50V7K@

PC177
4700P_0402_25V7K

1 2

1

+

2

12

PC164

10U_1206_25VAK

For windows idle mode noise issue

PL21

P_0.36H_ETQP4LR36WFC_24A_20%

PR233

3.48K_0402_1%

1 2

7.68K_0402_1%

PR237

1 2

10KB_0603_1%_TH11-3H103FT

PC174 0.22U_0603_16V7K

1 2

1 2

PR248 100_0402_5%

1 2

1 2

12

PC166

PC165

10U_1206_25VAK

12

NTC

PH5

CPU_VCC_SENSE

1

PL20

FBMA-L11-322513-201LMA40T_1210

12

12

10U_1206_25VAK

PR236

PC167

0.1U_0603_25V7K

12

10_0402_5%

12

12

PC168

2200P_0402_50V7K

VCCSENSE

PR2420_0402_5%

12

1

+

47U_25V_M

2

PC181

<7>

47U_25V_M

PC182

B+

1

+

2

+VCC_CORE

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

PWR-CPU-CORE

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

46 53Monday, January 08, 2007

X 0.5

5

D D

C C

4

3

2

1

B B

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Power up Sequence

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

47 53Monday, January 08, 2007

X 0.5

5

4

3

2

1

HW P.I.R LIST

Change item

1. ADD 100K ohm pull-down resistor on ENVDD

D D

2. ADD one more Panel ID, PID0 to support more panel

3. Add R791, Del R877

4. Add R46,R31,R32,JP32 and Q12, Del JP31

5. Change the net of R22 pin 2 from CLK_48M_SC to CLK_48M_SD

6. Add R37,R42 to pull high LCTLA_CLK & LCTLB_DATA Follow Intel Rev 1.601 design check list

7. Add U19, C610, Delete D26,D30 and populate R636 Follow Intel Rev 1.601 design check list to pull down ENABLT

8. Delete R668,R732 No need these pull high resistor for setting the Boot BIOS destination P20 1/12/06

9.Add an unpopulated resistor R676 Reserved for the future. P21

10. Unpopulate R895

11. Swap the USB port 3 and port 4 to the docking connector JP27

C C

12. Add R48 and C800

13. C26,C32,R59,R60 only populate for 9220;
R59,C798,R58,C799,R61populate for 9204

14. change C826/827 from 47uF to 220 uF

15. Depopulate C846/C847

16. Change cardbus signals SPKROUT and HWSPND# pull
high power to +3V_R5C843 from +3VALW

17. Add JP31,U19 and related components; delete JP32,Q12
and relatied components

18. Add layout notice for CCLK/CARD16

19. Add C71 Follow FAE check list request P25

20. Pull cardbus signals TPBP0/TPBN0/TPBP1/TPBN1 to ground

21. Remove U28 and add R1/Q12

22. Signal mute# change into mute Match Item 21 request

B B

23. Delete R879, R880 and cancel the net of DDR_ID0, DDR_ID1

24. JP1 and Add U8 Update the package of CPU from uFCPGA to uFCBGA

25. Delete U21, ADD U27 Change the USB HUB to USB controlller

26. Delete U1, Add U46

27. Move the net ACOFF from U33 pin31 to U33 pin80
Add the net LED_PWM

28. Delete tlhe R953

29. Delete tlhe R951, R853

30.update the Docking connector's symbol

31.Del U23 and relative components, add U47 and relative components

A A

Follow Intel suggestions 9/05/05
Reqired by Mothion

Use LED signal from Minicard to control RF LED directly, Reqired by Mothion

Support SD card function and cancel the Smart card function P25, P26

Support SD card function and cancel the Smart card function

Use the internal pull high of ICH7

Follow Motion's request

Tune regulator power sequence to insure AVDD rail should come up after the DVDD rail

For 9220 and 9204 co-layout P30

Follow Sigmatel suggestions P31 1/14/06 X0.1
Follow Sigmatel suggestions

Follow FAE check list request P25

Follow Motion change: add SC, delete SD
Follow FAE check list request

Follow FAE check list request P25 1/19/06

Follow motion request: shutdown amplifier to save power in S3 state

Delete the unused DDR_ID0 and DDR_ID1

Change the clock Gen to compal part
Use the PMW signals from EC to contol the brighness of LED P33,P36

Follow Intel USA suggestions

Follow Motion's request

Change the Docking con from 100 pins to 80pins

Change the Smart card controller from O2 to Omnikey
Remove the Smart card function

Change reason

Page#

P18
P18

P28, P34

P5

P11 1/12/06

P17

Date Revision

X0.1

9/05/05
9/28/05
1/11/06

1/12/06

1/12/06

X0.1

X0.1
X0.1

X0.1
X0.1

X0.1

X0.1

P34

P36

P30

1/12/06

1/12/06

1/12/06

1/14/06

1/14/06

X0.1

X0.1

X0.1

X0.1

X0.1

P31 1/14/06 X0.1

X0.1

X0.1
X0.1
X0.1

P26
P25

1/16/06

1/17/06
1/19/06

1/19/06

X0.1

P31 1/24/06

X0.1

P31,P33 1/24/06 X0.1

P33

P33

P27

2/13/06

2/13/06 X0.1

2/21/06

P5 2/21/06

2/21/06

P22 X0.1

P32

P36

P26

P26

3/01/06

3/02/06

3/02/06

3/03/06

3/07/0632.Del U27&JP31 and relative components

X0.1

X0.1
X0.1

X0.1

X0.1

X0.1

X0.1

X0.1

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Hardware PIR list

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

48 53Monday, January 08, 2007

X 0.5

5

4

3

2

1

HW P.I.R LIST

Change item

33.Add Q15, JP32 and relative components

34.Del LED_PWM, Add PWM_CTL to Q14 pin 2

D D

35. Add the location for R775,R777,R778,R782,R781,R783 and R476

36. Reassign the pin net of Docking

37. Add CF13,CF14 and Del H23, H24,H28,CL2,CL3

38. Add the locations for C431,C432,C425,C426,C427
C458,C437,C438C444,C445

39. Change the net of R747.2 from ICH_AZ_CODEC_SDIN0
to SDATA_IN

40. Add C271 Connect GND and LAN shield P29 3/15/06 X0.1

41. change +0.9V to +0.9VS for VTT of DDR

42.Populate R918

43.Delete Q12, add U31 and unpopulate R1, change MUTE to MUTE#

C C

44.Add R73, R74 For debug use only

45. Update JP24 symbol

46.ADD D34,D35,D36,D37,D38,D39,D40,D41,D42,D43,D44

47.Delete R772

48.Delete Q7, Add D45

49.Add R472,R473,R478,R479,C359,C360,C361,C362

50.Add R951, R953, R964, R965, C930 and Q63

51.Delete R775 ;pin10,pin12,pin14,pin16 of JP13 net swap Delete the useless power and change error the LPC nets for port 80H debug card

52.Add R2 To pull high HP_PLUG# to give it a stable status. P31

53.Add R480, C363

54.Add C611, C612,C619,C625

B B

55.Add H51, JP12,JP22,JP23

56.Add C633,C671,C672,C677 Follow motion's request

57.unpopulate R73

58.reasssign the docking usb ports to ICH7

59.Delete Q62,Q13,R776,R780,R791,R924

60.Add D6,D9,D13,R4,R7,R8 Support the LEDs change to M/B

61.Add two nets of WLAN_SW_EN, WWAN_SW_EN on U33,JP30

62.Change nets of JP6.24, JP6.36 from GND to +3vs, add R263,R262 follow motion's request of reserving 4 power wires for N-trig

63.Change Q52, from AO3402 to SI3456,
JP13&JP28 pin24 from+3VALW to +3V_LAN

64.Change +3VALW of U27 to +3VS,Del R315, change USB_SMI#

A A

from U9.E21 to U9.AC18, populate R346,R320, unpopulate R312,R321

65.Swap the nets of U46.16&U46.17

66.Add R641, R633, change the net of PID1 to ID0 add ID0, ID1 two hw strap pins to identify the N-Trig Wacom or TouchKo

Follow Motion's request add SD card feature

Follow Motion's solution for LED dimming control P17

Reserve the locations for Port 80H debug card when debugging
Put the anlog power and analog GND together to get get better placement and return loop.
New PCB and new feature requirement
Reserve the locations for 10uF caps in case of world wide shortage of 22uF caps

Correct the net error

Power net error

follow Vishay's suggestion

to avoid the current leakage when MUTE ative and no Headphone plugging in S0 P31

Use small footprint for layout space saving

Add the location of ESD protection Diode for HSYNC, VSYNC, ON/OFFBTN#, WL_SW# and DVI signal lines.

remove the dual pull-up resistors for WL_SW#

update symbol

Add these components for signal quality of SD. P25

To support usb wake up from docking and wake up function can be selected by user.

To reduce the SD_CMD's overshoot and undershoot

Follow Motion's request

Add a hole to fix HDD FPC, symbols of VGA connentor and usb connectors update for ME requirement

To solve the issue of system hangup when enable NEC controller
To support DOS mode for all docking ports P22,P36

Remove LEDs for HDD,B/T and WWAN,WLAN

Follow SED request for supprting antenna's switching

To support WOWLAN & WOL in AC only mode P28,P24

For more power saving and extendeing the life of bridge batter in S3 mode
modify the wrongly connected SMbus of clock Gen, to solve the issue of C3 hang up P5

Change reason

Page#

P26

Date Revision

3/07/06
3/09/06

P24, P5

3/09/06

P36 3/13/06

3/13/06

P8
P30

3/13/06

3/15/06

P16 3/21/06

P35 X0.1

3/21/06

3/22/06

P27

P33

P19,P34,P36,
P24,P18

P24

P17

3/24/06 X0.1

3/24/06

3/30/06

3/31/06 X0.1

4/07/06

4/10/06 X0.1

P32,P36

5/12/06

P24

5/12/06 X0.2

P25

5/15/06

P15,P16 5/15/06 X0.2

P38,P19,P32

P49,P17

5/24/06

5/24/06 X0.2

P49,P27 5/26/06

5/26/06

P17,P27,P24

5/26/06

P17 5/29/06

P33,P36

P17

5/29/06

6/01/06

6/06/06

P27,P22

6/06/06
6/06/06

P17,P22

6/07/06

X0.1
X0.1

X0.1
X0.1

X0.1P38
X0.1
X0.1

X0.1

X0.1

X0.1

X0.1

X0.1

X0.2
X0.25/12/06

X0.2

X0.2

X0.2

X0.2

X0.2
X0.2

X0.2

X0.2

X0.2

X0.2
X0.2

X0.2

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Hardware PIR list

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

49 53Monday, January 08, 2007

X 0.5

5

4

3

2

1

HW P.I.R LIST

Change item

67.Change R8 from 150ohm to 2.2K

68.Swap cardbus controller U15B pinV14/W14 net names

D D

69.Change H26/H27 size from 110 to 165 Solve standoff too big & hole too small to dock-MB/B can not fix well issue

70.Add PID and ID table; change LCD connector symbol

71.Delete H50

72.Change block diagram

73.Add R3, unpopulate R918/R919

74.Populate R17/R18

75.Change R11 to L21

76.Change U42/U43/U44 from AO4422 to AO4468 AO4422 will EOL, AO4468 will substitute it

77.Add new JP34, delete old JP29/JP34

78. Add mark LV@ on +VCC_CORE 12*22U & 2*330U

C C

decoupling capacitors

79. Add unpopulate R698/C678 Following Motion requirement for providing EMI

80. Add unpopulate R699/C679

81. Add series resistors R700/R707

82. Change C835/C836 from 220pF to 0.01U

83. Change L27/L28/L29/L30/L31/L32/L33/L34 to L22/L23/L24/L25
co-layout with R818/R819/R820/R821/R822/R823/R824/R825

84. Add unpopulate JP29 on side of NEC controller For Motion requirement

85.Change H18 size from C276D110 to C197D110

86. Add C74/C75

87. Delete R57,R69,C798

88. Add U1/C680/C931/C932/R446 Adding buffer to generate V_DDR_MCH_REF to solve SODIM sometime can not boot issue P9

B B

89. Change R81 from 4.87K to 4.75K

90. Change C69/C70 from 27pF to 18pF Following Marvell requirement to optimize LAN chip usage

91. Change transformer T21 from GST5009-LF to GST5009-V

92. Change U16/U31 power supply from +5VALW to +5VS Save power in S3 state and reduce speakers output noise P31

93.Add R23/R25/U47/C39/C798/R57/Q62 footprint on board

94. Delete Q61, R685, R668, Q14, D6, D9, D13, R7, R8, R4.
Add R924, Q16, R712, R642, R6, Q64, R364, D15, R331, Q66,
R317, D19, R330, Q65, R315, D16.

95. Change J2, J3 size, change J6 to Jump type.

96. Add C681, R717, R716.
Change JP6.40 from GND to PID1.
Add signal PID1 to ICH7.AE20.

97. Add R718, Q11.

A A

Add signal DVI_DETECT# to ICH7. AD21.

98. Change R34 from un-mounted to mounted.
Add U48, R60, R451, Q67, U49.

Solve LED no light issue

Solve new card can not be detected issue

Be beneficial to look at schematic; connect NC pin for EMI providing P17 7/17/06
No use

Follow Motion requirement P2

Solving Irda communication information occur error issue P35

Follow EMI requirement
Follow EMI requirement

Solving DFX issue

For Motion requirement

Following Motion requirement for providing EMI P25 8/1/06

Following Sigmatel requirement

Following Sigmatel requirement

Follow EMI requirement

For ME change requirement
Following Motion requirement

Co-layout Trinity and delete co-layout Colorado with STAC9220

Following Marvell requirement to optimize LAN chip usage

Following Marvell requirement to optimize LAN chip usage

Reserve for reduce headphone pop niose

As Motion requirement. Add LED brightness control function.

Follow factory DFX requirement.

Follow Motion requirement. Add one pin to support panel ID.

Follow Motion requirement. Add DVI plug detect function to ICH.

Follow Motion requirement. Add power saving function for Ricoh controller.

Change reason

Page#

P17
P25

P38

P38

Date Revision

7/17/06

7/17/06 X0.3

7/17/06 X0.3

7/17/06

7/27/06

7/31/06

P30 7/31/06

P30

P37

P36

P8

7/31/06

7/31/06

7/31/06

7/31/06

P27 8/1/06

P31

P31

P29

P27
P38

P28

P30

8/1/06

8/1/06

8/1/06

8/2/06
8/2/06

8/2/06

8/4/06

8/7/06

P28 8/14/06

P28

P29

8/14/06

8/14/06

8/14/06 X0.3

P30

P17

P17

P17

P22

P18

P22

P25

8/16/06

9/29/06

9/29/06

9/29/06

9/29/06

9/29/06

X0.3

X0.3
X0.3

X0.3

X0.3

X0.3

X0.3

X0.3

X0.3

X0.3

X0.3

X0.3

X0.3
X0.3

X0.3

X0.3

X0.3

X0.3

X0.3

X0.3

X0.3

X0.3

X0.3

X0.3

X0.4

X0.4

X0.4

X0.4

X0.4

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Hardware PIR list

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

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HW P.I.R LIST

Change item

99. Add R826, R452, Q68, U50, R75, U53.
Change U27 power supply from +3VS to +3V_NECUSB.

D D

100. Delete R287.
Add R87, R82, R86, R83, R84, R85.

101. Add R333, R332.
Add signal PCM_CLK_EN#, USB_CLK_EN#, Card_Insert#.

102. Add location CLIP1

103. Add R294

104. Add U56, C686, C685, C684, C683, R725,
R730, R720, R968, C687, Q61, Q69, U57.
Add signal G_SENSOR to EC.

105. Swap EC U33 pin35 and pin80

106. Delete EC U33 pin62 project _ID net name

107. Delete U57,change U33 pin62/pin90 net name Follow vender review result to change

C C

108. Delete EC U33 pin91/pin92 net name

109. JP30 pin4 and pin6 pull down to ground

110. Buletooth USBP2+/- change into NEC_USBP2+/-;
JP28 NEC_USBP2+/- change into USBP2+/-

111.Change U33 pin46 net name from RFOFF# to WLANOFF#
Change U33 pin92 net name from WWAN_SW_EN to WWANOFF#
Change JP13 net name from RFOFF# to WLANOFF#
Change JP28 net name from RFOFF# to WWANOFF#

112. H9 connect to digital ground from analog ground

113. Add C416

114. Add unpopulate C507

115. Delete R328,R316, project_ID related table

116. R327/R326 populate, R267/r157 unpopulate

B B

117. Add unpopulate R966/C933

118. Change BIOS/B connector from E&T_1009-E40L-00R
to ACES_88072-4071_40P

119. Change USB connector from SUYIN_020173MR004S500ZL
to SUYIN_020173MR004S583ZL

120. JP19,
change Pin1 to GNDA;
change Pin2 to INTMIC3;
change Pin3 to GNDA;

121. JP34;
Move Pin11 --> Pin9
Move Pin10 --> Pin11
Move Pin9 --> Pin10

122. Change H26/H27 size form C276D165 to C276D173

123. Add unpopulate R283/R967 and R969 Follow SMSC schematics review

124. Change L42/L47 from BLM18AG601SND1 to BK1608HM601-T

A A

125. Swap EC U33 pin27 and pin30

126. Delete R718, delete U9 pinAD21 net to NC the pin ,
change net PCI_REQ5# into DVI_DETECT#

Follow Motion requirement. Add power saving function for NEC controller.

For debug. P33

Follow Motion requirement. Add power saving function for NEC controller and Ricoh controller.

For deal with antenna routing conveniently P38

FIR part change

Add G-Sensor function

Solve +5V_DOCK turn on/off condition validity

No use

No use
No use

Swap WWAN and BT, ensure WWAN to be used under DOS mode

Separate WLAN and WWAN on/off control signal

Antenna pass through H9 area, provide signal being interfere P38

Delay shutdown ramp up time to solve headphone pop-noise

For HSDL-3220 FIR reserve capacitor P35

No use

Correct BDID configuration
Add AC ternimation for EMI providing

Solving BIOS/B connect stably with MB

Solving USB connector stability when inserting USB device

Solve the MIC(3rd) noise issue;

Solve the MIC(Mic2) 'click' noise issue;

Solve the docking CRT signal instability issue

Follow IDT AP test feedback result
Solving fan noise, pin30 PWM can not be programming to 30KHz
Solving DVI can be automatically detected by system when inserting

Change reason

Date RevisionPage#

P27

P33

P35

P24

P36

P33

P24, P33

P33
P36

P24, P27 11/01/06

P24, P33

P30 11/01/06

P33

P33
P24
P34

P32

P36

P31 11/08/06 X0.4

P38

P35

P31

P33

P18, P20,P22

9/29/06

9/29/06

9/29/06

10/16/06
10/17/06

10/17/06

11/01/06
11/01/06

11/01/06

11/01/06

11/01/06

11/01/06

11/01/06

11/01/06

11/01/06

11/01/06
11/01/06 X0.4

11/06/06

11/06/06 X0.4

11/08/06

11/14/06

11/14/06

12/27/06
12/27/06 X0.5
12/28/06

X0.4

X0.4

X0.4

X0.4

X0.4

X0.4

X0.4

X0.4
X0.4

X0.4

X0.4

X0.4

X0.4

X0.4

X0.4

X0.4

X0.4

X0.4

X0.4

X0.4

X0.4
X0.4
X0.5

X0.5

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Hardware PIR list

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

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51 53Monday, January 08, 2007

X 0.5

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HW P.I.R LIST

Change item

For reviewing

128. Add Q70, Q72, R731, R732

D D

129. Re-assign MB ALS/B connector JP34 pin

130. unpopulate Q62/C416, add R88, when use MAX9890,
use U33 pin91 control shutdown pin with R88

131. Change PCIE 0.1u capacitor C631/C632/C629/C630/C661/C670
part number

132. Change FIR module U41 to agielent HSDL-3220

133. Change JP30 pin19 GND to GNDA

134. Change R965 form 100 to 22K; change C930 from 0.1U to 0.47U
and re-connect; change R964 from 100K to 330K; add R970

135. change JP34 pin assignment

136. delete signal "Blanco_USB_OC#" Avoid ESD fail on this pin

C C

Providing ALS/B leak current to +3VS

Solving the 1st array mic noise issue

Reduce HP pop noise

Solving PCIE capacitor temperature characteristic unstable issue

Use agielent FIR module to solve FIR transmition and receive fail issue

Solving 2nd array mic noise issue P36

Solving vibration issue when S3 wake up only battery supply power

Avoid record noise in internal MIC1

Change reason

Date RevisionPage#

P33127. Redefine BID
P36

P36

P33,P30

P22

P35

P36

P36

P34 01/08/07

12/28/06

12/29/06

12/29/06

12/29/06

12/29/06

12/29/06 X0.5

01/08/07

12/29/06
12/29/06

X0.5
X0.5
X0.5

X0.5

X0.5

X0.5

X0.5

X0.5

X0.5

B B

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Hardware PIR list

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

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52 53Monday, January 08, 2007

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POWER P.I.R LIST

Change item

1. Change PR39 from 1K_0402_1% to 10K_0402_1%.

2. Add PQ51,PQ49,PR262, change PR163 from 0 to

84.5K,change PR164 from 0 to 100K.

3. Del MAX8578 circuit(PU6,PQ41,PL17,PL16...),add ISL6269 solution

D D

for VCCP(PU16,PQ52,PQ53,PL22,PL23...).

4. Remove PC88 from PU14.3 to PU14.1

5. Delete PC88,PU14

For MAX1908 issue.

Add switch function to support Sanyo 4.35 cell battery.

Improve VCCP supply current from 4A to 7A. X0.1

Connection error

Use ISL6269 PGOOD as VCCP_POK.

Change reason

Page#

P40

P40

P43

P43
P43

6. ADD PC88,PU14 ,PR264 Use PU14 produce VCCP_POK.

6. ADD PR34,change PR10 form 7.32K to 3.92K

C C

Providing PR10 being destroied only one resistor as load, one resistor divide into two resistors to reduce resistor fail risk

P39

Date Revision

01/14/06
03/03/06
03/03/06

03/24/06

03/30/06

10/16/06

X0.1
X0.1

X0.1
X0.1

X0.4

B B

A A

Compal Electronics, Inc.(KunShan)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Title

Power PIR list

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

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53 53Monday, January 08, 2007

X 0.5