INTELBRAS IDX80, la-3291 Schematics

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4

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Project Name: PecosII

D D

(IDX80)
PCB Serial Number:

LA-3291

PecosII Schematics Document

C C

Intel Merom Dual Core LV1.33G&1.5G
/Yonah Single Core ULV 1.06G&1.2G + Calistoga GM + ICH7-M

B B

2007-01-08

REV: X0.5

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Cover Sheet

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

153Monday, January 08, 2007

X 0.5

5

4

3

2

1

DC-DC

page 37

D D

VCCP&
CPU_CORE

page 46

Merom Dual Core LV
/Yonah Single Core ULV

Block Diagram

CPU Thermal Sensor
G781F

page 6

Clock Generator
ICS9LPRS325AKLF

page 5

Fan Control x1

page 6

479 uFCBGA CPU

Docking
CRT

page 36

CRT port

FSB

HD#[0..63]HA#[3..31]

CRT CONN.

page 19

DVI CONN

page 18

Hydis

C C

SIM
card

LCD 12.1"
XGA/SXGA+

page 24

Mini Card
WWAN

page 24

DVI Controller
CH7307

LVDS CONN.

page 18

page 17

Mini Card
WLAN

page 24

3.3V 33MHz

SDVO

LVDS port

PCIE BUS

PCIE BUS

PCIE x1

PCI Bus

Intel Calistoga GM

1466 FCBGA

page 9, 10, 11, 12, 13, 14

DMI x4

1.5V

ICH7-M

652 BGA

page 20, 21, 22, 23

page 6, 7, 8

533/667MHz

DDR2

Channel A

SO-DIMM x 1

4 BANK

1.8V 533/667MHz

Channel B

DDR2

SO-DIMM x 1

4 BANK

USB 2.0 48MHz/480Mb
Azalia 3.3V

PATA100

HDD 1.8"

page 24

page 15

page 16

USBPORT0
USBPORT 1
USBPORT 2

USBPORT 3
USBPORT 4
USBPORT 5

USBPORT 6

USBPORT 7

On M/B
On M/B

WWAN

Finger Printer
LLANO DOCK

Travel DOCK

LLANO DOCK

LLANO DOCK

page 32

page 32

page 24

page 36

page 36

page 36

page 36

page 36

B B

CardBus
R5C843

PCMCIA Slot

page 26

express

page 26

card

page 25

SD Socket

page 26

SMSC

page 35

LPC47N217

LPC Bus

Embedded Controller

3.3V 33MHz

ENE KB910L

page 33

TPM

page 32

SLB9635TT

X Bus

Docking
HP&MIC

page 36

ROM DAUGHTER BOARD

page 28

USB 2.0
Controller

Port 0

CardBus

page 25

page 27

Port 1

WLAN

page 24

Port 2

Bluetooth

page 27

Gigabit Lan
88E8053

Transformer
& RJ45

page 29

Docking
RJ45

page 36

A A

SST39VF080

Digitizer

5

4

FIR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Azalia Codec
STAC9220

page 30

AMP & HP &
MIC

page 31

page 34

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

Block Diagram

PecosII-IDX80-LA3291

1

X 0.5

of

253Monday, January 08, 2007

5

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3

2

1

External PCI Devices

DEVICE

D D

IDSEL #

AD20
AD21USB controller

REQ/GNT #

2 A,BCARD BUS

0

PIRQ

E,F,G

Power Management table

Signal +1.8VS

State

+12VALW
+5VALW
+3VALW

+3V_LAN

+1.8V

+5VS
+3VS

+2.5VS
+1.5VS
+0.9VS
+VCCP
+CPU_CORE

Symbol Note

ON

S1

S3

S5 S4/AC

S5 S4/AC don't exist

Note1 : +3V_LAN is ON only with AC power available, otherwise it is OFF.

ON ON

ON note1 ON

ON note1

OFF

ON

OFF

ONONS0

OFF

OFFOFF

OFF

Voltage Rails

: means Digital Ground

C C

: means Analog Ground

: Question Area Mark.(Wait check)

@: means don't stuff, just reserve

DB@: means jsut stuff when Mini-PCI E Debug card function enable
DVI_7307@: means just stuff when use CH7307 controller

DVI_1362@: means just stuff when use Sil1362 controller

9220@: means just populate when mount 9220 on board;
depopulate when mount 9228 on board

9228@: means just populate when mount 9228 on board;

B B

depopulate when mount 9220 on board
LV@: means just populate when mount Merom/Yonah LV DC CPU on board;

depopulate when mount Yonah ULV SC CPU on board

Buffer@: means just populate when buffer generate V_DDR_MCH_REF;
depopulate when 1.8V divider generate V_DDR_MCH_REF

1.8_divider@: means just populate when 1.8V divider generate V_DDR_MCH_REF;
depopulate when buffer generate V_DDR_MCH_REF

1@: means just populate 0ohm resistors on board;

2@: means just populate MAX9890 & related components on board;

3220@: means populate 0ohm resistors when mount Agilent 3220,unpopulate 0ohm resistors when mount other

Power Plane

VIN
B+
+VCC_CORE
+VCCP
+0.9VS
+1.5VS
+1.8V

+2.5VS
+3VALW
+3VS 3.3V switched power rail
+5VALW
+5VS
+12VALW
RTCVCC

+3V_LAN

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Description

Adapter power supply (19V)
AC or battery power rail for power circuit
Core voltage for CPU

1.05V power rail for Processor I/O and MCH core power

0.9V switched power rail for DDRII Vtt

1.5V switched power rail for PCI-E interface

1.8V power rail for DDRII

1.8V switched power rail+1.8VS ON

2.5V switched power rail for MCH video PLL

3.3V always on power rail

5V always on power rail
5V switched power rail
12V always on power rail

3.3V LAN power rail

S0-S1

N/A
N/A
ON
ON
ON
ON
ON

ON
ON
ON
ON
ON
ON
ONRTC power

ON

S3

N/A
N/A

OFF
OFF
ON
OFF OFF
OFF
ON ON*
OFF
ON
OFF
ON ON*
ON

ON*

S5

N/A
N/A
OFFOFF
OFFOFF
OFF
OFF
OFF

OFF

OFF
ON*
OFF

ON

ON*

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Notes&Revision

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

353Monday, January 08, 2007

X 0.5

ADAPTER

5

4

3

2

1

B+

VS

ACIN

D D

DOCK

DOCK_IN

MAINPWRON

+3VALW +5VALW +12VALW

MAX1902 MAX8743 ISL6269

SYSON
SUSP#

VCCP_ON#

+1.8VP

+1.5VSP

+VCCP

EC_ON#

SUSP#P

LDO
G965

APL5331

SUSP

LDO
XC61CN

SUSP

+2.5VSP

A BATTERY

C C

A OR B BATTERYA OR B BATTERY

MAX1908
CHARGER

+3VS

FSTCHG

IREF

+5VS

BRIDGE BATTERY

SUSP#

+0.9VSP

B BATTERY

A OR B BATTERY

B B

BATT+

FSTCHG

MAX1538

BATSELB_A#

+1.8VS

+VCCP_OK

H_DPRSLPVR

H_DPRSTP#

H_PSI#

VR_ON

VGATE
CLK_ENABLE#
H_PROCHOT#

MAX8770

VID0
VID1
VID2

VID3
VID4
VID5
VID6

BATTERY SELECTOR

VSB

RTC_VREF

POWER SOURCE

+VCC_CORE

BATT+

VIN

A A

5

4

G920AT24U

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

RTC BATT

CHARGER SOURCE

2

Compal Electronics, Inc.(KunShan)

Title

Power rail

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

453Monday, January 08, 2007

X 0.5

5

PCI

SRC

CPU

FSLA

FSLB

FSLC

CLKSEL1

CLKSEL2

0

0

FSB Frequency Selet:

D D

CPU Driven

(Default)

*

533MHz

667MHz

0

1

Stuff

No Stuff

Stuff

No Stuff

Stuff

No Stuff

CLKSEL0

1

1

MHz

133

166

CLK_Ra

CLK_Rd

CLK_Rd

CLK_Ra

CLK_Rd

CLK_Ra

MHz

100

100

CLK_Rb

CLK_Re

CLK_Re

CLK_Rb

CLK_Rf

CLK_Rb

MHz

33.3

33.3

CLK_Rc

CLK_Rf

CLK_Rf

CLK_Rc

CLK_Rc

+3VS

FBMA-L11-201209-221LMA30T_0805

+3VS

FBMA-L11-201209-221LMA30T_0805

CLK_Re

+VCCP

12

@

R506

J1

12

12

R503

@

+VCCP

+VCCP

+3VS

5

R439

56_0402_5%

CLK_Rd

1 2

R443

1K_0402_5%

12

R450
1K_0402_5%

12

R460
1K_0402_5%

1 2

R464

1K_0402_5%

12

R471

@

0_0402_5%

CLK_Re

12

R482
1K_0402_5%

1 2

R488

1K_0402_5%

12

R495

@

0_0402_5%

CLK_Rf

12

12

12

MCH_CLKSEL0 <9>

MCH_CLKSEL1 <9>

MCH_CLKSEL2 <9>

Pin 43/44,47/48 function select

FCTSEL1: 0 DOT96/LCD100 *
1 27M/SRC0

R442

8.2K_0402_5%

C C

B B

A A

FSLA

FSLC

1 2

R447

0_0402_5%

CLK_Ra

FSLB

1 2

R466

0_0402_5%

CLK_Rb

R487

8.2K_0402_5%

1 2

R491

0_0402_5%

CLK_Rc

10K_0402_5%

CLK_ENABLE#

300_0402_5%

NO SHORT PADS

CPU_BSEL0<7>

CPU_BSEL1<7>

CPU_BSEL2<7>

C395

1 2

C396 22P_0402_50V8J

1 2

+3VS

12

R497
10K_0402_5%

@

FCTSEL1

12

R504

10K_0402_5%

22P_0402_50V8J

CLK_48M_USB<27>
CLK_48M_ICH<22>

CLK_14M_ICH<22>

CLK_PCI_PCM<25>
CLK_PCI_EC<33>

CLK_PCI_USB<27>
CLK_PCI_SIO<35>

CLK_14M_SIO<35>

DREFCLK<9>
DREFCLK#<9>

CLK_PCI_ICH<20>

CLK_ENABLE#<46>

ICH_SMBCLK<6,15,16,22,24>

ICH_SMBDATA<6,15,16,22,24>

4

+CK_VDD_MAIN1

L14

1 2

+CK_VDD_MAIN2

L15

1 2

12

14.31818MHZ_20P_6X1430004201
Y1

CLK_48M_USB

CLK_48M_ICH

CLK_PCI_PCM FCTSEL1
CLK_PCI_EC SEL_48M
CLK_PCI_USB

CLK_14M_SIO SEL_PCI5

DREFCLK
DREFCLK#

CLK_ENABLE#

ICH_SMBCLK

ICH_SMBDATA

Pin28/29 function select

+3VS

12

R502

10K_0402_5%

DB@

SEL_PCI6

SEL_PCI5/6: 0 CLKREQ5/6#,
1 PCICLK5/6

4

1

C384

10U_0805_10V4Z

2

1

C388

10U_0805_10V4Z

2

+CK_VDD_MAIN1

C397
C399

R22 12_0402_5%
R21 12_0402_5%

0_0402_5%

+3VS

12

R498

10K_0402_5%

SEL_PCI5

3

L19

1

C385

0.1U_0402_16V4Z

2

1

C389

0.1U_0402_16V4Z

2

+CK_VDD_DP

+CK_VDD_REF

1 2

0.1U_0402_16V4Z

+CK_VDD_48

1 2

0.1U_0402_16V4Z

12

FSLA

12

FSLB
FSLCCLK_14M_ICH

12

R44933_0402_5%

12

R47433_0402_5%

12

R46933_0402_5%

SEL_24M

12

R47533_0402_5%

SEL_PCI6CLK_PCI_SIO

12

R49333_0402_5%

12

R46233_0402_5%

DOCTT

12

R486

DOCTC

12

R4890_0402_5%

ITP_ENCLK_PCI_ICH

12

R45833_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

C386

0.1U_0402_16V4Z

1

1

C390

0.1U_0402_16V4Z

2

U46

1

VDDSRC

49

VDDSRC

54

VDDSRC

65

VDDSRC

30

VDDPCI

36

VDDPCI

12

VDDCPU

18

VDDREF

40

VDD48

20

X1

19

X2

41

USB_48MHz/FSLA

45

FSLB/TEST_MODE/24Mhz

23

REF0/FSLC/TEST_SEL

34

PCICLK4/FCTSEL1

33

SEL_48M/PCICLK3

32

SEL_24M/PCICLK2

27

SEL_PCI6/PCICLK1

22

SEL_PCI5/REF1

43

DOTT_96MHz/27MHz_Nonspread

44

DOTC_96MHz/27MHz_spread

37

ITP_EN/PCICLK_F0

39

VTT_PWRGD#/PD

9

GND

16

SMBCLK

17

SMBDAT

4

GNDSRC

15

GNDCPU

21

GNDREF

31

GNDPCI

35

GNDPCI

42

GND48

68

GNDSRC

73

THRM_PAD

74

THRM_PAD

75

THRM_PAD

76

THRM_PAD

ICS9LPRS325CKLFT_MLF72

2

C387

0.1U_0402_16V4Z

1

R430

+CK_VDD_REF

1 2

1_0805_1%

+CK_VDD_48

1 2

R431

2.2_0805_1%

VDDA
GNDA

PCI_SRC_STOP#

CPU_STOP#

CPUCLKT1LP
CPUCLKC1LP

CPUCLKT0LP
CPUCLKC0LP

CPUCLKT2_ITP/SRCCLKT10LP

CPUCLKC2_ITP/SRCCLKC10LP

SRCCLKT9LP
SRCCLKC9LP

CLKREQ9#
SRCCLKT8LP
SRCCLKC8LP

CLKREQ8#
SRCCLKT7LP
SRCCLKC7LP

CLKREQ7#/48Mhz_1

SRCCLKT6LP
SRCCLKC6LP

CLKREQ6#
SRCCLKT5LP
SRCCLKC5LP

CLKREQ5#/PCICLK6

SRCCLKT4LP
SRCCLKC4LP

CLKREQ4#
SRCCLKT3LP
SRCCLKC3LP

CLKREQ3#/PCICLK5

SRCCLKT2LP
SRCCLKC2LP

CLKREQ2#
SRCCLKT1LP
SRCCLKC1LP

CLKREQ1#

LCD100/96/SRC0_TLP

LCD100/96/SRC0_CLP

3

7
8

H_STP_PCI#

25

H_STP_CPU#

24

CK_CPU

11

CK_CPU#

10

14
13

CK_ITP

6

CK_ITP#

5

CK_SRC9

3

CK_SRC9#

2

CLKREQA#

72

CK_SRC8

70

CK_SRC8#

69

CLKREQB#

71
66
67

ICS_48MHz CLK_48M_SD

38
63
64
62
60
61

PCICLK6 CLK_DEBUG_PORT

29

CK_SRC4

58

CK_SRC4#

59

CLKREQC#

57

CK_SRC3

55

CK_SRC3#

56
28

CK_SRC2

52
53
26
50
51
46

CK_SRC0

47

CK_SRC0#

48

1 2

+3VS

FBMA-L11-201209-221LMA30T_0805

L4

1 2

FBMA-L11-201209-221LMA30T_0805

C415 0.1U_0402_16V4Z

R476 33_0402_5% DB@

+3VS

1 2

H_STP_PCI# <22>
H_STP_CPU# <22>

1 2

R43 0_0402_5%

1 2

0_0402_5%

R44

1 2

R51 0_0402_5%

1 2

R52 0_0402_5%

1 2

R53 0_0402_5%

1 2

R54 0_0402_5%
R55

0_0402_5%

1 2

1 2

R56

12

10K_0402_5%

R448

1 2

R62 0_0402_5%

1 2

0_0402_5%

R63

R463

1 2

R459

12

1 2

R64

1 2

R65 0_0402_5%

R483 10K_0402_5%

1 2

R66

1 2

R67 0_0402_5%

12

R477 33_0402_5%

1 2

0_0402_5%

R68

1 2

R69

0_0402_5%

1 2

0_0402_5%

R71

1 2

R72 0_0402_5%

+CK_VDD_DP

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLKCK_MCH
CLK_MCH_BCLK#CK_MCH#

CLK_CPU_XDP
CLK_CPU_XDP#

CLK_PCIE_WAN
CLK_PCIE_WAN#

0_0402_5%

CLK_PCIE_MINI
CLK_PCIE_MINI#

10K_0402_5%

12

33_0402_5%

CLK_MCH_3GPLL

0_0402_5%

CLK_MCH_3GPLL#

12

CLK_PCIE_ICH

0_0402_5%

CLK_PCIE_ICH#
CLK_PCI_TPMPCICLK5
CLK_PCIE_LAN
CLK_PCIE_LAN#CK_SRC2#

DREF_SSCLK
DREF_SSCLK#

2

1

C391

10U_0805_10V4Z

2

CLK_CPU_BCLK <6>
CLK_CPU_BCLK# <6>

CLK_MCH_BCLK <9>
CLK_MCH_BCLK# <9>

CLK_CPU_XDP <6>
CLK_CPU_XDP# <6>

CLK_PCIE_WAN <24>
CLK_PCIE_WAN# <24>

+3VS

CLKREQA# <24>

CLK_PCIE_MINI <24>
CLK_PCIE_MINI# <24>

+3VS

CLK_48M_SD <25>

CLK_DEBUG_PORT <24>
CLK_MCH_3GPLL <9>
CLK_MCH_3GPLL# <9>

CLKREQC# <9>

+3VS

CLK_PCIE_ICH <22>
CLK_PCIE_ICH# <22>
CLK_PCI_TPM <32>
CLK_PCIE_LAN <28>
CLK_PCIE_LAN# <28>

DREF_SSCLK <9>
DREF_SSCLK# <9>

2

1

C392

0.1U_0402_16V4Z

2

CLKREQB# <24>

1

1

C393

0.1U_0402_16V4Z

2

1

C394

0.1U_0402_16V4Z

2

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_XDP
CLK_CPU_XDP#

CLK_PCIE_WAN
CLK_PCIE_WAN#

CLK_PCIE_MINI
CLK_PCIE_MINI#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DREF_SSCLK
DREF_SSCLK#
DREFCLK
DREFCLK#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_LAN
CLK_PCIE_LAN#

R96

R97

R98

R99

R100
R101

R102
R103

R104
R105

R107
R106

R109
R108

R111

R110
R113

R112

R115
R114

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

12

@

49.9_0402_1%

Pin38 function select

+3VS

12

R532

10K_0402_5%

SEL_48M

12

R501

10K_0402_5%

@

SEL_48M: 0 CLKREQ7 ,
1 48MHz output

Pin5/6 function select

+3VS

12

R505

10K_0402_5%

ITP_EN

12

R500
10K_0402_5%

@

ITPEN: 0 SRC10 Pair ,
1 CPU_ITP Pair

Compal Electronics, Inc.(KunShan)

Title

Clock Generator

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

Pin45 function select

SEL_24M

R499
10K_0402_5%

1 2

SEL_24M: 0 Test mode ,
1 24MHz

1

553Monday, January 08, 2007

X 0.5

of

5

H_A#[3..31]<9>

D D

H_REQ#[0..4]<9>

H_ADSTB#0<9>
H_ADSTB#1<9>

C C

R519

1 2

+VCCP

56_0402_5%

B B

In order to for Yonah B-0 silicon to boot,
due to issue in the reset sequence. needed
for processor.

H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil

CLK_CPU_BCLK<5>
CLK_CPU_BCLK#<5>

H_ADS#<9>
H_BNR#<9>
H_BPRI#<9>
H_BR0#<9>
H_DEFER#<9>
H_DRDY#<9>
H_HIT#<9>
H_HITM#<9>

H_LOCK#<9>
H_RESET#<9>

H_RS#[0..2]<9>

H_TRDY#<9>

XDP_DBRESET#<22>

H_DBSY#<9>
H_DPSLP#<21>
H_DPRSTP#<21,46>
H_DPWR#<9>

H_PROCHOT#<46>

H_PWRGOOD<21>
H_CPUSLP#<9,21>

1K_0402_5%

1 2

1 2

@

H_THERMTRIP#<9,21>

R521
R522 51_0402_5%

A A

R954

68_0402_5%

+VCCP

CLK_CPU_BCLK
CLK_CPU_BCLK#

12

H_PROCHOT#

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

H_ADS#
H_BNR#
H_BPRI#
H_BR0#

H_DEFER#

H_DRDY#
H_HIT#
H_HITM#

H_IERR#
H_LOCK#
H_RESET#

H_RS#0

H_RS#1

H_RS#2
H_TRDY#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

XDP_DBRESET#

H_DBSY#

H_DPSLP#

H_DPRSTP#

H_DPWR#

XDP_BPM#4

XDP_BPM#5

H_PROCHOT#
H_PWRGOOD

H_CPUSLP#

XDP_TCK

XDP_TDI

XDP_TDO

TEST1

TEST2

XDP_TMS

XDP_TRST#

H_THERMDA
H_THERMDC

H_THERMTRIP#

12

R527

56_0402_5%

U8A

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U2

A23#

R4

A24#

T5

ADDR GROUP

A25#

T3

A26#

W3

A27#

W5

A28#

Y4

A29#

W2

A30#

Y1

A31#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L5

REQ4#

L2

ADSTB0#

V4

ADSTB1#

A22

BCLK0

A21

BCLK1

H1

ADS#

E2

BNR#

G5

BPRI#

F1

BR0#

H5

DEFER#

F21

DRDY#

G6

HIT#

E4

HITM#

D20

IERR#

H4

LOCK#

B1

RESET#

F3

RS0#

F4

RS1#

G3

RS2#

G2

TRDY#

AD4

BPM0#

AD3

BPM1#

AD1

BPM2#

AC4

BPM3#

C20

DBR#

E1

DBSY#

B5

DPSLP#

E5

DPRSTP#

D24

DPWR#

AC2

PRDY#

AC1

PREQ#

D21

PROCHOT#

D6

PWRGOOD

D7

SLP#

AC5

TCK

AA6

TDI

AB3

TDO

C26

TEST1

D25

TEST2

AB5

TMS

AB6

TRST#

A24

THERMDA

A25

THERMDC

C7

THERMTRIP#

YONAH-ULV_FCBGA479~D

+3VS

12

R526
1K_0402_5%

1

C

Q2

2

B

2SC2411KT146_SOT23

E

3

YONAH-ULV

HOST CLK

CONTROL

MISC

THERMAL
DIODE

PROCHOT#

4

DATA GROUP

LEGACY CPU

PROCHOT# <33>

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#

DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#
LINT0
LINT1

STPCLK#

SMI#

3

H_D#0

E22

D0#

H_D#1

F24

D1#

H_D#2

E26

D2#

H_D#3

H22

D3#

H_D#4

F23

D4#

H_D#5

G25

D5#

H_D#6

E25

D6#

H_D#7

E23

D7#

H_D#8

K24

D8#

H_D#9

G24

D9#

H_D#10

J24

H_D#11

J23

H_D#12

H26

H_D#13

F26

H_D#14

K22

H_D#15

H25

H_D#16

N22

H_D#17

K25

H_D#18

P26

H_D#19

R23

H_D#20

L25

H_D#21

L22

H_D#22

L23

H_D#23

M23

H_D#24

P25

H_D#25

P22

H_D#26

P23

H_D#27

T24

H_D#28

R24

H_D#29

L26

H_D#30

T25

H_D#31

N24

H_D#32

AA23

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

W25

H_D#37

U23

H_D#38

U25

H_D#39

U22

H_D#40

AB25

H_D#41

W22

H_D#42

Y23

H_D#43

AA26

H_D#44

Y26

H_D#45

Y22

H_D#46

AC26

H_D#47

AA24

H_D#48

AC22

H_D#49

AC23

H_D#50

AB22

H_D#51

AA21

H_D#52

AB21

H_D#53

AC25

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24

H_D#58

AE21

H_D#59

AD21

H_D#60

AE25

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26

H_DINV#0

J26

H_DINV#1

M26

H_DINV#2

V23

H_DINV#3

AC20

H_DSTBN#0

H23

H_DSTBN#1

M24

H_DSTBN#2

W24

H_DSTBN#3

AD23

H_DSTBP#0

G22

H_DSTBP#1

N25

H_DSTBP#2

Y25

H_DSTBP#3

AE24

H_A20M#

A6

H_FERR#

A5

H_IGNNE#

C4

H_INIT#

B3

H_INTR

C6

H_NMI

B4

H_STPCLK#

D5

H_SMI#

A3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H_D#[0..63] <9>

H_DINV#0 <9>
H_DINV#1 <9>
H_DINV#2 <9>
H_DINV#3 <9>

H_DSTBN#[0..3] <9>

H_DSTBP#[0..3] <9>

H_A20M# <21>
H_FERR# <21>
H_IGNNE# <21>
H_INIT# <21>
H_INTR <21>
H_NMI <21>

H_STPCLK# <21>
H_SMI# <21>

ITP-XDP Connector

@

JP2

1

XDP_BPM#5
XDP_BPM#4

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

R514

H_PWRGOOD_RH_PWRGOOD CLK_CPU_XDP

12

1K_0402_5%

+VCCP +VCCP

ICH_SMBDATA<5,15,16,22,24>

ICH_SMBCLK<5,15,16,22,24>

C401

0.1U_0402_16V4Z

ICH_SMBDATA
ICH_SMBCLK

XDP_TCK

12

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

Thermal Sensor G781F

C403

2200P_0402_50V7K

SMB_EC_CK2<24,33,36,39>
SMB_EC_DA2<24,33,36,39>

Place U2 near the top and LCD side
for using it's local thermal sensor to
monitor the LCD back side temperature

+5VS

FAN_SPEED1<33>

+3VS

FAN_PWM<33>

2

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TD0

TRST#

TDI

TMS

GND17

H_THERMDA

1

2

H_THERMDC

SMB_EC_CK2

SMB_EC_DA2

1 2

R523

10K_0402_5%

@

1 2

1000P_0402_50V7K

C406

1 2

R524 8.2K_0402_5%

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

CLK_CPU_XDP#

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE

U2

2

D+

3

D-

8

SCLK

7

SDATA

G781F_SOP8

R525

1 2

100_0402_1%

1

+3VS

R507 1K_0402_5%

XDP_DBRESET#_R

This shall place near CPU

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_TRST#
XDP_TCK

+3VS

ALERT#

THERM#

10U_0805_10V4Z

D1

CH355PT_SOD323

2 1

R508 56_0402_5%
R509

R510 56_0402_5%
R511 56_0402_5%
R512 56_0402_5%
R513 56_0402_5%

1K_0402_1%

R515

1 2

R516

200_0402_1%

R517 0_0402_5%

1 2

1

C402

0.1U_0402_16V4Z

2

1

VDD1

6

THERM#

4
5

GND

+5VS

1

C404

2

2

G

Compal Electronics, Inc.(KunShan)

Title

Yonah1/2-GTL/ITP

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1 2

1 2
1 2
1 2
1 2
1 2
1 2

H_RESET#H_RESET#_R
XDP_DBRESET#XDP_DBRESET#_R

12

12

1

C405

0.1U_0402_16V4Z

2

MOLEX_53780-0310

13

D

Q1
FDN359AN_NL_SOT23

S

@

56_0402_1%

R518

10K_0402_5%

@

JP3

1

1

2

2

3

3

+VCCP

CLK_CPU_XDP <5>
CLK_CPU_XDP# <5>

X 0.5

of

653Monday, January 08, 2007

5

4

3

2

1

+VCCP

12

R529

V_CPU_GTLREF

D D

1K_0402_1%

12

R528

2K_0402_1%

Close to CPU pin AD26
within 500mils.

+VCC_CORE

R530

100_0402_1%

1 2

R531

100_0402_1%

1 2

Close to CPU pin
within 500mils.

VCCSENSE

VSSSENSE

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

C C

B B

166

00

0

12

12

R533

27.4_0402_1%

R534

54.9_0402_1%

R535

Length match within 25 mils
The trace width 18 mils space
7 mils

+1.5VS

1

C407

2

0.01U_0402_16V7K

CPU_BSEL0

1

1

12

R536

27.4_0402_1%

12

54.9_0402_1%

1

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

C408

10U_0805_10V4Z

1

2

V_CPU_GTLREF

CPU_BSEL0<5>
CPU_BSEL1<5>
CPU_BSEL2<5>

H_PSI#<46>
CPU_VID0<46>

CPU_VID1<46>
CPU_VID2<46>
CPU_VID3<46>
CPU_VID4<46>
CPU_VID5<46>
CPU_VID6<46>

VCCSENSE<46>
VSSSENSE<46>

+VCCP

+VCC_CORE

VCCSENSE

VSSSENSE

H_PSI#
CPU_VID0

CPU_VID1
CPU_VID2

CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0

COMP1

COMP2

COMP3

U8B

AF7

VCCSENSE

AE7

VSSSENSE

B26

VCCA

K6

VCCP

J6

VCCP

M6

VCCP

N6

VCCP

YONAH-ULV

T6

VCCP

R6

VCCP

K21

VCCP

J21

VCCP

M21

VCCP

N21

VCCP

T21

VCCP

R21

VCCP

V21

VCCP

W21

VCCP

V6

VCCP

G21

VCCP

AE6

PSI#

AD6

VID0

AF5

VID1

AE5

VID2

AF4

VID3

AE3

VID4

AF2

VID5

AE2

VID6

AD26

GTLREF

B22

BSEL0

B23

BSEL1

C21

BSEL2

R26

COMP0

U26

COMP1

U1

COMP2

V1

COMP3

E7

VCC

AB20

VCC

AA20

VCC

AF20

VCC

AE20

VCC

AB18

VCC

AB17

VCC

AA18

VCC

AA17

VCC

AD18

VCC

AD17

VCC

AC18

VCC

AC17

VCC

AF18

VCC

AF17

VCC

D2

RSVD

F6

RSVD

D3

RSVD

C1

RSVD

AF1

RSVD

D22

RSVD

C23

RSVD

C24

RSVD

AA1

RSVD

AA4

RSVD

AB2

RSVD

AA3

RSVD

M4

RSVD

N5

RSVD

T2

RSVD

V3

RSVD

B2

RSVD

C3

RSVD

T22

RSVD

B25

RSVD

YONAH-ULV_FCBGA479~D

AB26

VSS

AA25

VSS

AD25

VSS

AE26

VSS

AB23

VSS

AC24

VSS

AF24

VSS

AE23

VSS

AA22

VSS

AD22

VSS

AC21

VSS

AF21

VSS

AB19

VSS

AA19

VSS

AD19

VSS

AC19

VSS

AF19

VSS

AE19

VSS

AB16

VSS

AA16

VSS

AD16

VSS

AC16

VSS

AF16

VSS

AE16

VSS

AB13

VSS

AA14

VSS

AD13

VSS

AC14

VSS

AF13

VSS

AE14

VSS

AB11

VSS

AA11

VSS

AD11

VSS

AC11

VSS

AF11

VSS

AE11

VSS

AB8

VSS

AA8

VSS

AD8

VSS

AC8

VSS

AF8

VSS

AE8

VSS

AA5

VSS

AD5

VSS

AC6

VSS

AF6

VSS

AB4

VSS

AC3

VSS

AF3

VSS

AE4

VSS

POWER, GROUNG, RESERVED SIGNALS AND NC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

+VCC_CORE

U8C

AE18

VCC

AE17

VCC

AB15

VCC

AA15

VCC

AD15

VCC

AC15

VCC

AF15

VCC

AE15

VCC

AB14

VCC

AA13

VCC

AD14

VCC

AC13

VCC

AF14

VCC

AE13

VCC

AB12

VCC

AA12

VCC

YONAH-ULV

AD12

VCC

AC12

VCC

AF12

VCC

AE12

VCC

AB10

VCC

AB9

VCC

AA10

VCC

AA9

VCC

AD10

VCC

AD9

VCC

AC10

VCC

AC9

VCC

AF10

VCC

AF9

VCC

AE10

VCC

AE9

VCC

AB7

VCC

AA7

VCC

AD7

VCC

AC7

VCC

B20

VCC

A20

VCC

F20

VCC

E20

VCC

B18

VCC

B17

VCC

A18

VCC

A17

VCC

D18

VCC

D17

VCC

C18

VCC

C17

VCC

F18

VCC

F17

VCC

E18

VCC

E17

VCC

B15

VCC

A15

VCC

D15

VCC

C15

VCC

F15

VCC

E15

VCC

B14

VCC

A13

VCC

D14

VCC

C13

VCC

F14

VCC

E13

VCC

B12

VCC

A12

VCC

D12

VCC

C12

VCC

F12

VCC

E12

VCC

B10

VCC

B9

VCC

A10

VCC

A9

VCC

D10

VCC

D9

VCC

C10

VCC

C9

VCC

F10

VCC

F9

VCC

E10

VCC

E9

VCC

B7

VCC

A7

VCC

F7

VCC

YONAH-ULV_FCBGA479~D

POWER, GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Yonah2/2-PWR/GND

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

753Monday, January 08, 2007

X 0.5

5

+VCC_CORE

D D

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(South side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C409
22U_0805_6.3V6M

C419
22U_0805_6.3V6M

C429

22U_0805_6.3V6M

4

1

C410
22U_0805_6.3V6M

2

1

C420
22U_0805_6.3V6M

2

1

C430

22U_0805_6.3V6M

2

1

LV@

C411
22U_0805_6.3V6M

2

1

LV@

C421
22U_0805_6.3V6M

2

1

LV@

C433
22U_0805_6.3V6M

2

1

LV@

C412
22U_0805_6.3V6M

2

1

LV@

C422
22U_0805_6.3V6M

2

1

LV@

C434
22U_0805_6.3V6M

2

1

LV@

C413
22U_0805_6.3V6M

2

1

LV@

C423
22U_0805_6.3V6M

2

1

C425
22U_0805_6.3V6M

@

2

3

1

LV@

C414
22U_0805_6.3V6M

2

1

LV@

C424
22U_0805_6.3V6M

2

1

C426
22U_0805_6.3V6M

@

2

1

C418
22U_0805_6.3V6M

@

2

1

C428
22U_0805_6.3V6M

@

2

1

C427
22U_0805_6.3V6M

@

2

2

1

C431
22U_0805_6.3V6M

@

2

1

C432
22U_0805_6.3V6M

@

2

1

C458
22U_0805_6.3V6M

@

2

1

C C

Place these capacitors on L8
(South side,Secondary Layer)

B B

330U_D2E_2.5VM_R9

+VCC_CORE

1

C435
22U_0805_6.3V6M

2

LV@

330U_D2E_2.5VM_R9

+VCCP

1

+

@

C447

2

1

2

+VCC_CORE

C442

C448

0.1U_0402_10V6K

1

C436
22U_0805_6.3V6M

2

1

+

2

1

2

1

2

1

+

C443

2

330U_D2E_2.5VM_R9

C449

0.1U_0402_10V6K

LV@

C439
22U_0805_6.3V6M

1

C450

0.1U_0402_10V6K

2

1

LV@

C440
22U_0805_6.3V6M

2

C446

330U_D2E_2.5VM_R9

1

C451

0.1U_0402_10V6K

2

1

+

2

1

C437
22U_0805_6.3V6M

@

2

330U_D2E_2.5VM_R9

1

LV@

+

C441

2

1

C452

0.1U_0402_10V6K

2

1

C438
22U_0805_6.3V6M

@

2

North Side SecondarySouth Side Secondary

1

2

C453

0.1U_0402_10V6K

Place these inside
socket cavity on L8
(North side
Secondary)

Mid Frequence Decoupling

1

C444
22U_0805_6.3V6M

@

2

1

C445
22U_0805_6.3V6M

@

2

ESR <= 1.5m ohm
Capacitor > 1980uF

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Yonah bypass

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

853Monday, January 08, 2007

X 0.5

5

H_D#[0..63]<6>

D D

C C

+VCCP

12

12

R539

R540

54.9_0402_1%

H_XSCOMP/H_YSCOMP trace
width and spacing is 5/20.

B B

A A

54.9_0402_1%

12

R543

24.9_0402_1%

+VCCP

12

R551

100_0402_1%

12

R556

200_0402_1%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1

12

R544

24.9_0402_1%

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

H_VREF

1

C457

2

0.1U_0402_16V4Z

5

U3A

F1

HD0#

J1

HD1#

H1

HD2#

J6

HD3#

H3

HD4#

K2

HD5#

G1

HD6#

G2

HD7#

K9

HD8#

K1

HD9#

K7

HD10#

J8

HD11#

H4

HD12#

J3

HD13#

K11

HD14#

G4

HD15#

T10

HD16#

W11

HD17#

T3

HD18#

U7

HD19#

U9

HD20#

U11

HD21#

T11

HD22#

W9

HD23#

T1

HD24#

T8

HD25#

T4

HD26#

W7

HD27#

U5

HD28#

T9

HD29#

W6

HD30#

T5

HD31#

AB7

HD32#

AA9

HD33#

W4

HD34#

W3

HD35#

Y3

HD36#

Y7

HD37#

W5

HD38#

Y10

HD39#

AB8

HD40#

W2

HD41#

AA4

HD42#

AA7

HD43#

AA2

HD44#

AA6

HD45#

AA10

HD46#

Y8

HD47#

AA1

HD48#

AB4

HD49#

AC9

HD50#

AB11

HD51#

AC11

HD52#

AB3

HD53#

AC2

HD54#

AD1

HD55#

AD9

HD56#

AC1

HD57#

AD7

HD58#

AC6

HD59#

AB5

HD60#

AD10

HD61#

AD4

HD62#

AC8

HD63#

J13

HVREF0

K13

HVREF1

E1

HXRCOMP

E2

HXSCOMP

Y1

HYRCOMP

U1

HYSCOMP

E4

HXSWING

W1

HYSWING

CALISTOGA_FCBGA1466~D

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HADSTB#0
HADSTB#1

HOST

HCLKN
HCLKP

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HDINV#0
HDINV#1
HDINV#2
HDINV#3

HCPURST#

HADS#

HTRDY#

HDPWR#

HDRDY#

HDEFER#

HHITM#

HHIT#

HLOCK#

HBREQ0#

HBNR#

HBPRI#

HDBSY#

HCPUSLP#

HRS0#
HRS1#
HRS2#

12

R549

12

R554

100_0402_1%

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

D8
G8
B8
F8
A8

B9
C13

AG1
AG2

K4
T7
Y5
AC4
K3
T6
AA5
AC5

J7
W8
U3
AB10

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

B4
E6
D6

221_0603_1%

1

2

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

H_RS#0
H_RS#1
H_RS#2

H_SWNG0

C455

0.1U_0402_16V4Z

4

H_A#[3..31] <6>

H_REQ#[0..4] <6>

H_ADSTB#0 <6>
H_ADSTB#1 <6>

CLK_MCH_BCLK# <5>

CLK_MCH_BCLK <5>

H_DSTBN#[0..3] <6>

H_DSTBP#[0..3] <6>

H_DINV#0 <6>
H_DINV#1 <6>
H_DINV#2 <6>
H_DINV#3 <6>

H_RESET# <6>
H_ADS# <6>
H_TRDY# <6>

H_DPWR# <6>
H_DRDY# <6>
H_DEFER# <6>

H_HITM# <6>
H_HIT# <6>

H_LOCK# <6>
H_BR0# <6>
H_BNR# <6>
H_BPRI# <6>
H_DBSY# <6>
H_CPUSLP# <6,21>

H_RS#[0..2] <6>

+VCCP+VCCP

12

R550

221_0603_1%

12

R555

100_0402_1%

3

DMI_TXN0<22>
DMI_TXN1<22>
DMI_TXN2<22>
DMI_TXN3<22>

DMI_TXP0<22>
DMI_TXP1<22>
DMI_TXP2<22>
DMI_TXP3<22>

DMI_RXN0<22>
DMI_RXN1<22>
DMI_RXN2<22>
DMI_RXN3<22>

DMI_RXP0<22>
DMI_RXP1<22>
DMI_RXP2<22>
DMI_RXP3<22>

M_CLK_DDR0<15>
M_CLK_DDR1<15>
M_CLK_DDR2<16>
M_CLK_DDR3<16>

M_CLK_DDR#0<15>
M_CLK_DDR#1<15>
M_CLK_DDR#2<16>
M_CLK_DDR#3<16>

DDR_CKE0_DIMMA<15>
DDR_CKE1_DIMMA<15>
DDR_CKE2_DIMMB<16>
DDR_CKE3_DIMMB<16>

DDR_CS0_DIMMA#<15>
DDR_CS1_DIMMA#<15>
DDR_CS2_DIMMB#<16>
DDR_CS3_DIMMB#<16>

+1.8V

R537 80.6_0402_1%

1 2
1 2

R538

R541 0_0402_5%

H_DPRSLPVR<22,46>

V_DDR_MCH_REF<15,16>

H_SWNG1

1

C456

2

0.1U_0402_16V4Z

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V_DDR_MCH_REF

Use +1.8V divide voltage for V_DDR_MCH_REF, R545/R548 use 100_0402_1%
Use buffer to generate V_DDR_MCH_REF, R545/R548 use 1K_0402_1%

1 2

PLT_RST#<18,20,22,24,28,32,33,35>

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

R446

1 2

0_0805_5%

1.8_divider@

3

M_ODT0<15>
M_ODT1<15>
M_ODT2<16>
M_ODT3<16>

80.6_0402_1%

V_DDR_MCH_REF

PM_BMBUSY#<22>

EC_EXTTS#0<15,16,33>

H_THERMTRIP#<6,21>

R542 100_0402_1%

MCH_ICH_SYNC#<20>

1

C454

0.1U_0402_16V4Z

2

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_OCDOCMP0
M_OCDOCMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SMRCOMPN
SMRCOMPP

PM_BMBUSY#

EC_EXTTS#0
PM_EXTTS#1

H_THERMTRIP#

PWROK

PWROK<22,33,34>

PLTRST_R#

12

+1.8V

12

VREF

R545

12

R548

Stuff R546 & R547 for A1 Calistoga

1K_0402_1%

1K_0402_1%

AE35
AF39

AG35

AH39

AC35
AE39
AF35

AG39

AE37
AF41

AG37

AH41

AC37
AE41
AF37

AG41

AY35

AW7

AW40
AW35

AY40
AU20

AT20
BA29
AY29

AW13
AW12

AY21

AW21

AL20
AF10

BA13
BA12
AY20
AU21

AK41

AH33
AH34

Layout Note:
Route as short
as possible

U3B

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0

AR1

SM_CK1
SM_CK2
SM_CK3

SM_CK0#

AT1

SM_CK1#

AY7

SM_CK2#
SM_CK3#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

AV9

SM_RCOMPN

AT9

SM_RCOMPP

AK1

SM_VREF0
SM_VREF1

G28

PM_BMBUSY#

F25

PM_EXTTS0#

H26

PM_EXTTS1#

G6

PM_THERMTRIP#
PWROK
RSTIN#

K28

ICH_SYNC#

CALISTOGA_FCBGA1466~D

12

12

R546

R547

40.2_0402_1% @

40.2_0402_1% @

2

DMI

DDR MUXING

M_OCDOCMP0
M_OCDOCMP1

2

PM

10U_1206_6.3V7K

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16

CFG

CFG17
CFG18
CFG19
CFG20

G_CLKP
G_CLKN

D_REF_CLKN
D_REF_CLKP

CLKNC

D_REF_SSCLKN
D_REF_SSCLKP

CLK_REQ#

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8

RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

RESERVED

+1.8V

Buffer@

1

C932

2

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

1

Description at page13.

MCH_CLKSEL0

K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26

CLK_MCH_3GPLL

AG33

CLK_MCH_3GPLL#M_CLK_DDR0

AF33
A27

A26
C40

D41
H32

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

MCH_CLKSEL1
MCH_CLKSEL2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

DREFCLK#
DREFCLK

DREF_SSCLK#
DREF_SSCLK

CLKREQC#

VREF

EC_EXTTS#0

PM_EXTTS#1

MCH_CLKSEL0 <5>
MCH_CLKSEL1 <5>

MCH_CLKSEL2 <5>

PAD
PAD

CFG5 <13>

PAD

CFG7 <13>

PAD

CFG9 <13>

PAD
PAD

CFG12 <13>

CFG13 <13>

PAD
PAD

CFG16 <13>

PAD

CFG18 <13>

CFG19 <13>

CFG20 <13>

CLK_MCH_3GPLL <5>

CLK_MCH_3GPLL# <5>

DREFCLK# <5>

DREFCLK <5>

DREF_SSCLK# <5>

DREF_SSCLK <5>

CLKREQC# <5>

U1

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

V_DDR_MCH_REF

1

C931
10U_1206_6.3V7K

2

Buffer@

T1
T2

T3
T4
T5

T6

T7
T8

T9

NC
NC
NC
TP

Buffer@

R552

12

10K_0402_5%

R553

12

10K_0402_5%@

6
5
7
8
9

Calistoga1/6-GTL/DMIDDRMUX

PecosII-IDX80-LA3291

1

+3VS

2

Buffer@

C680
1U_0603_10V4Z

1

953Monday, January 08, 2007

+5VALW

X 0.5

of

5

D D

DDR_A_BS#0<15>
DDR_A_BS#1<15>
DDR_A_BS#2<15> DDR_B_BS#2<16>

DDR_A_DM[0..7]<15>

DDR_A_DQS[0..7]<15>

C C

B B

DDR_A_DQS#[0..7]<15>

DDR_A_MA[0..13]<15>

DDR_A_CAS#<15>
DDR_A_RAS#<15>
DDR_A_WE#<15>

T10 PAD T11 PAD
T12 PAD

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

AU12
AV14
BA20

AJ33

AM35

AL26

AN22

AM14

AK33
AT33
AN28

AM22

AN12

AK32
AU33

AN27
AM21
AM12

AY16

AU14
AW16

BA16

BA17

AU16

AV17

AU17
AW17

AT16

AU13

AT17

AV20

AV12

AY13
AW14

AY14

AK23

AK24

AG5

AN3
AH5

AL9
AR3
AH4

AN8
AP3

AL8

U3D

SA_BS0
SA_BS1
SA_BS2

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#
SA_RAS#
SA_WE#
SA_RCVENIN#
SA_RCVENOUT#

Route to a via next to ball

CALISTOGA_FCBGA1466~D

4

DDR_A_D0

AJ35

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8

SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39

DDR SYS MEMORY A

SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

3

DDR_A_D[0..63] <15>

DDR_B_BS#0<16>
DDR_B_BS#1<16>

DDR_B_DM[0..7]<16>

DDR_B_DQS[0..7]<16>

DDR_B_DQS#[0..7]<16>

DDR_B_MA[0..13]<16>

DDR_B_CAS#<16>
DDR_B_RAS#<16>
DDR_B_WE#<16>

T13 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

Route to a via next to ball

2

U3E

AT24

SB_BS0

AV23

SB_BS1

AY28

SB_BS2

AK36

SB_DM0

AR38

SB_DM1

AT36

SB_DM2

BA31

SB_DM3

AL17

SB_DM4

AH8

SB_DM5

BA5

SB_DM6

AN4

SB_DM7

AM39

SB_DQS0

AT39

SB_DQS1

AU35

SB_DQS2

AR29

SB_DQS3

AR16

SB_DQS4

AR10

SB_DQS5

AR7

SB_DQS6

AN5

SB_DQS7

AM40

SB_DQS0#

AU39

SB_DQS1#

AT35

SB_DQS2#

AP29

SB_DQS3#

AP16

SB_DQS4#

AT10

SB_DQS5#

AT7

SB_DQS6#

AP5

SB_DQS7#

AY23

SB_MA0

AW24

SB_MA1

AY24

SB_MA2

AR28

SB_MA3

AT27

SB_MA4

AT28

SB_MA5

AU27

SB_MA6

AV28

SB_MA7

AV27

SB_MA8

AW27

SB_MA9

AV24

SB_MA10

BA27

SB_MA11

AY27

SB_MA12

AR23

SB_MA13

AR24

SB_CAS#

AU23

SB_RAS#

AR27

SB_WE#

AK16

SB_RCVENIN#

AK18

SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8

SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39

DDR SYS MEMORY B

SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_D0

AK39

1

DDR_B_D[0..63] <16>

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Calistoga2/6-DDRA&B

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

10 53Monday, January 08, 2007

X 0.5

5

4

3

2

1

PEGCOMP trace width

D D

+3VS

LCTLA_CLK

1 2

R37 10K_0402_5%

LCTLB_DATA

C C

B B

1 2

R42

R586

R585 10K_0402_5%

1 2

1 2

10K_0402_5%

LCD_I2C_CLK

10K_0402_5%

LCD_I2C_DAT

ENVDD<17>

3VDDCCL<19>
3VDDCDA<19>

CRT_VSYNC<19>
CRT_HSYNC<19>

CRT_B<19>
CRT_G<19>
CRT_R<19>

SDVO_SDAT<18>
SDVO_SCLK<18>

LVDSA_D0+<17>
LVDSA_D1+<17>
LVDSA_D2+<17>

LVDSA_D0-<17>
LVDSA_D1-<17>
LVDSA_D2-<17>

LVDSB_D0+<17>
LVDSB_D1+<17>
LVDSB_D2+<17>

LVDSB_D0-<17>
LVDSB_D1-<17>
LVDSB_D2-<17>

LVDSCLKA+<17>
LVDSCLKA-<17>
LVDSCLKB+<17>
LVDSCLKB-<17>

GM_PWM<17>

ENABLT<17,33>

LCD_I2C_CLK<17>

LCD_I2C_DAT<17>

ENVDD

R558

1 2

R559

3VDDCCL
3VDDCDA

R560
R561

R562
R563
R564

R565 change to 226ohm
required by Motion

12
12

12

150_0402_5%

12

150_0402_5%

12

150_0402_5%

SDVO_SDAT
SDVO_SCLK

LVDSA_D0+
LVDSA_D1+
LVDSA_D2+

LVDSA_D0­LVDSA_D1­LVDSA_D2-

LVDSB_D0+
LVDSB_D1+
LVDSB_D2+

LVDSB_D0­LVDSB_D1­LVDSB_D2-

LVDSCLKA+
LVDSCLKA­LVDSCLKB+
LVDSCLKB-

GM_PWM
ENABLT
LCTLA_CLK

LCTLB_DATA
LCD_I2C_CLK
LCD_I2C_DAT

LVDD_EN

12

0_0402_5%

1.5K_0402_1%

+1.5VS

39_0402_5%
39_0402_5%

1 2

R565 226_0402_1%

U3C

H27
H28

B37
B34
A36

C37

B35
A37

F30

D29

F28

G30
D30

F29
A32

A33
E26
E27

D32

J30
H30
H29
G26
G25

F32

LIBG

B38
C35
C33
C32

A16
C18

A19

J20

B16

B18

B19

J29

K30

C26
C25

H23
G23

E23
D23
C22

B22

A21

B21

J22

CALISTOGA_FCBGA1466~D

SDVOCTRL_DATA
SDVOCTRL_CLK

LA_DATA0
LA_DATA1
LA_DATA2

LA_DATA#0
LA_DATA#1
LA_DATA#2

LB_DATA0
LB_DATA1
LB_DATA2

LB_DATA#0
LB_DATA#1
LB_DATA#2

LA_CLK
LA_CLK#
LB_CLK
LB_CLK#

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

TVDAC_A
TVDAC_B
TVDAC_C

TV_IREF
TV_IRTNA

TV_IRTNB
TV_IRTNC

TV_DCONSEL1
TV_DCONSEL0

DDCCLK
DDCDATA

VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED
RED#

CRT_IREF

LVDS

TV CRT

and spacing is 18/25 mils.

EXP_COMPI

EXP_COMPO

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

PCI-EXPRESS GRAPHICS

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D40
D38

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

PEGCOMP

SDVOB_INT-

SDVOB_INT+

SDVO_R­SDVO_G­SDVO_B­SDVO_CLK-

SDVO_R+
SDVO_G+
SDVO_B+
SDVO_CLK+

C460

C464

1 2

1 2

R557

24.9_0402_1%

1 2

SDVOB_INT- <18>

SDVOB_INT+ <18>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

C461

C462

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

C465

C466

+1.5VS_PCIE

1 2

0.1U_0402_16V4Z

1 2

C463 0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

1 2

C467

0.1U_0402_16V4Z

SDVOB_R- <18>
SDVOB_G- <18>
SDVOB_B- <18>
SDVOB_CLK- <18>

SDVOB_R+ <18>
SDVOB_G+ <18>
SDVOB_B+ <18>
SDVOB_CLK+ <18>

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Calistoga3/6-VGA/LVDS

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

11 53Monday, January 08, 2007

X 0.5

5

+VCCP

D D

1

+

330U_D2E_2.5VM_R9

C C

B B

C477

C484

C495

2

1

1

C485

2

2

2.2U_0805_16V4Z

4.7U_0805_10V4Z

MCH_A6

1

C492

2

0.47U_0603_10V7K

1

MCH_D2

2

1

0.22U_0603_10V7K

C497

0.22U_0603_10V7K

+1.5VS

C498

0.47U_0603_10V7K

MCH_AB1

1

2

2

U3H

AC14

VTT0

AB14

VTT1

W14

VTT2

V14

VTT3

T14

VTT4

R14

VTT5

P14

VTT6

N14

VTT7

M14

VTT8

L14

VTT9

AD13

VTT10

AC13

VTT11

AB13

VTT12

AA13

VTT13

Y13

VTT14

W13

VTT15

V13

VTT16

U13

VTT17

T13

VTT18

R13

VTT19

N13

VTT20

M13

VTT21

L13

VTT22

AB12

VTT23

AA12

VTT24

Y12

VTT25

W12

VTT26

V12

VTT27

U12

VTT28

T12

VTT29

R12

VTT30

P12

VTT31

N12

VTT32

M12

VTT33

L12

VTT34

R11

VTT35

P11

VTT36

N11

VTT37

M11

VTT38

R10

VTT39

P10

VTT40

N10

VTT41

M10

VTT42

P9

VTT43

N9

VTT44

M9

VTT45

R8

VTT46

P8

VTT47

N8

VTT48

M8

VTT49

P7

VTT50

N7

VTT51

M7

VTT52

R6

VTT53

P6

VTT54

M6

VTT55

A6

VTT56

R5

VTT57

P5

VTT58

N5

VTT59

M5

VTT60

P4

VTT61

N4

VTT62

M4

VTT63

R3

VTT64

P3

VTT65

N3

VTT66

M3

VTT67

R2

VTT68

P2

VTT69

M2

VTT70

D2

VTT71

AB1

VTT72

R1

VTT73

P1

VTT74

N1

VTT75

M1

VTT76

AG14

VCCAUX32

AF14

VCCAUX33

AE14

VCCAUX34

Y14

VCCAUX35

AF13

VCCAUX36

AE13

VCCAUX37

AF12

VCCAUX38

AE12

VCCAUX39

AD12

VCCAUX40

CALISTOGA_FCBGA1466~D

P O W E R

VCC_SYNC

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL

VCCA_3GBG

VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

VCCA_DPLLA
VCCA_DPLLB

VCCA_HPLL

VCCA_LVDS

VSSA_LVDS

VCCA_MPLL

VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC

VCCDQ_TVDAC

VCCHV0
VCCHV1
VCCHV2

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

4

H22

B30
C30
A30

AB41
AJ41
L41
N41
R41
V41
Y41

AC33
G41
H41

E21
F21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
H19

A23
B23
B25

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+2.5VS

+1.5VS_3GPLL
+2.5VS

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

+1.5VS_MPLL

+1.5VS

+1.5VS

+1.5VS

+1.5VS

1

2

W=40 mils

C482

0.1U_0402_16V4Z

1

C493

2

0.1U_0402_16V4Z

+1.5VS

1

C496

2

0.1U_0402_16V4Z

+2.5VS

C468

Should be placed near GMCH

0.1U_0402_16V4Z

+1.5VS_PCIE

10U_0805_6.3V6M

1

C470

1

2

1

C479

C480

2

0.022U_0402_16V7K

1

+2.5VS

C483

0.01U_0402_16V7K

2

+3VS

1

2

1

2

0.1U_0402_16V4Z

C486

0.1U_0402_16V4Z

+

C469

2

220U_D2_4VM

1

2

1

C494
10U_0805_6.3V6M

2

3

L1

1 2

BLM21PG600SN1D_0805

C471

10U_0805_6.3V6M

L3

1 2

BLM18PG181SN1D_0603

+1.5VS

1

1

C487

10U_0805_6.3V6M

2

2

+1.5VS

+1.5VS

+1.5VS_3GPLL

+2.5VS

D17

21

+VCCP

CH751H-40PT_SOD323

MBK1608301YZF_0603

1 2

MBK1608301YZF_0603

+1.5VS

1 2

C474

2

R566

0.5_0805_1%

3GRLL_R

1 2

1

1

C475

2

2

10U_1206_6.3V6M

0.1U_0402_16V4Z

L2

BLM18PG600SN1D_0603

+1.5VS

12

C476

1

2

0.1U_0402_16V4Z

C472

+2.5VS

1

1

C473

2

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

1

close pin B30

+2.5VS

1

C481

2

0.1U_0402_16V4Z

close pin G41

L5

L7

L8

C499

C500

1

+

2

470U_D2_2.5VM

1

+

2

470U_D2_2.5VM

+1.5VS_DPLLA

1

C503

2

0.1U_0402_16V4Z

+1.5VS_DPLLB

1

C504

2

0.1U_0402_16V4Z

+1.5VS

+1.5VS

MBK1608301YZF_0603

1 2

MBK1608301YZF_0603

1 2

+1.5VS_HPLL

L6

C501

C491

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C490

2

0.1U_0402_16V4Z

+1.5VS_MPLL

1

C502

2

1

2

1

2

0.1U_0402_16V4Z

A A

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Calistoga4/6-PWR

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

12 53Monday, January 08, 2007

X 0.5

5

4

3

2

1

Strap Pin Table

CFG[3:17] have internal pull up

+VCCP

D D

1

C513

C512

2

0.22U_0603_10V7K

1

C519

C520

2

330U_D2E_2.5VM_R9

1

C524

+

2

220U_D2_4VM

1

+

2

0.22U_0603_10V7K

1U_0603_10V4Z

1

2

1

2

+VCCP

1

2

C525

+

1

C511

2

0.22U_0603_10V7K

no caps required by the
Rev1.501 check list

10U_0805_6.3V6M

1

C518

2

10U_0805_6.3V6M

C C

C533

330U_D2E_2.5VM_R9

B B

U3F

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

M19

VCC100

L19

VCC101

N18

VCC102

M18

VCC103

L18

VCC104

P17

VCC105

N17

VCC106

M17

VCC107

N16

VCC108

M16

VCC109

L16

VCC110

CALISTOGA_FCBGA1466~D

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36

P O W E R

VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCC_SM100

VCC_SM101

VCC_SM102

VCC_SM103

VCC_SM104

VCC_SM105

VCC_SM106

VCC_SM107

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

+1.5VS

VCCSM_LF2
VCCSM_LF1

C535

+1.8V

0.47U_0603_10V7K

1

1

C536

2

2

0.47U_0603_10V7K

Place near pin AV1 & AJ1

A A

+VCCP

U3G

AA33

VCC0

W33

VCC1

P33

VCC2

N33

VCC3

L33

VCC4

J33

VCC5

AA32

VCC6

Y32

VCC7

W32

VCC8

V32

VCC9

P32

VCC10

N32

VCC11

M32

VCC12

L32

VCC13

J32

VCC14

AA31

VCC15

W31

VCC16

V31

VCC17

T31

VCC18

R31

VCC19

P31

VCC20

N31

VCC21

M31

VCC22

AA30

VCC23

Y30

VCC24

W30

VCC25

V30

VCC26

U30

VCC27

T30

VCC28

R30

VCC29

P30

VCC30

N30

VCC31

M30

VCC32

L30

VCC33

AA29

VCC34

Y29

VCC35

W29

VCC36

V29

VCC37

U29

VCC38

R29

VCC39

P29

VCC40

M29

VCC41

L29

VCC42

AB28

VCC43

AA28

VCC44

Y28

VCC45

V28

VCC46

U28

VCC47

T28

VCC48

R28

VCC49

P28

VCC50

N28

VCC51

M28

VCC52

L28

VCC53

P27

VCC54

N27

VCC55

M27

VCC56

L27

VCC57

P26

VCC58

N26

VCC59

L26

VCC60

N25

VCC61

M25

VCC62

L25

VCC63

P24

VCC64

N24

VCC65

M24

VCC66

AB23

VCC67

AA23

VCC68

Y23

VCC69

P23

VCC70

N23

VCC71

M23

VCC72

L23

VCC73

AC22

VCC74

AB22

VCC75

Y22

VCC76

W22

VCC77

P22

VCC78

N22

VCC79

M22

VCC80

L22

VCC81

AC21

VCC82

AA21

VCC83

W21

VCC84

N21

VCC85

M21

VCC86

L21

VCC87

AC20

VCC88

AB20

VCC89

Y20

VCC90

W20

VCC91

P20

VCC92

N20

VCC93

M20

VCC94

L20

VCC95

AB19

VCC96

AA19

VCC97

Y19

VCC98

N19

VCC99

CALISTOGA_FCBGA1466~D

P O W E R

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8

VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

+1.8V

VCCSM_LF4
VCCSM_LF5

C509

Place near pin AT41 & AM41

C526

Place near pin BA23

C531

10U_0805_6.3V6M

C534

Place near pin BA15

1

2

0.47U_0603_10V7K

1

C514

2

1

2

0.47U_0603_10V7K

1

2

10U_0805_6.3V6M

1

2

0.47U_0603_10V7K

C510

0.1U_0402_16V4Z

0.47U_0603_10V7K

C532

1

2

C515

1

2

0.1U_0402_16V4Z

C527

1

2

@

+1.8V

1

C517

C516

2

0.1U_0402_16V4Z

1

+

2

330U_D2E_2.5VM_R9

1

2

0.1U_0402_16V4Z

SDVO_CTRLDATA

(PCIE/SDVO select)

CFG[2:0]

CFG5

CFG7

CFG9

CFG[11,10]

CFG[13:12]

CFG16

CFG18

CFG19

CFG20

CFG[19:18] have internal pull down

011 = 667MT/s FSB
001 = 533MT/s FSB

0 = DMI x 2
1 = DMI x 4

0 = Reserved
1 = Mobile Yonah CPU

0 = Lane Reversal Enable
1 = Normal Operation

(Default)

*

(Default)

*

(Default)

*

Reserved

00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

0 = 1.05V
1 = 1.5V

0 = Normal Operation
1 = DMI Lane Reversal Enable

0 = No SDVO Device Present

*

(Default)

(Default)

*

*

1 = SDVO Device Present

0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.

R567 2.2K_0402_5%

CFG5<9>

R568 2.2K_0402_5%

CFG7<9>

R569 2.2K_0402_5%

CFG9<9>

R570 2.2K_0402_5%

CFG12<9>

R571 2.2K_0402_5%

CFG13<9>

R572 2.2K_0402_5%

CFG16<9>

R573

CFG18<9>

R574

CFG19<9>

R575

CFG20<9>

*

1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2
1 2

(Default)

@
@
@

@
@
@

@

1K_0402_5%

@

1K_0402_5%

@

1K_0402_5%

(Default)

*

(Default)

*

+3VS

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Calistoga5/6-PWR/GND

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

13 53Monday, January 08, 2007

X 0.5

5

4

3

2

1

U3I

AC41

VSS0

AA41

VSS1

W41

VSS2

T41

VSS3

P41

D D

C C

B B

A A

VSS4

M41

VSS5

J41

VSS6

F41

VSS7

AV40

VSS8

AP40

VSS9

AN40

VSS10

AK40

VSS11

AJ40

VSS12

AH40

VSS13

AG40

VSS14

AF40

VSS15

AE40

VSS16

B40

VSS17

AY39

VSS18

AW39

VSS19

AV39

VSS20

AR39

VSS21

AN39

VSS22

AJ39

VSS23

AC39

VSS24

AB39

VSS25

AA39

VSS26

Y39

VSS27

W39

VSS28

V39

VSS29

T39

VSS30

R39

VSS31

P39

VSS32

N39

VSS33

M39

VSS34

L39

VSS35

J39

VSS36

H39

VSS37

G39

VSS38

F39

VSS39

D39

VSS40

AT38

VSS41

AM38

VSS42

AH38

VSS43

AG38

VSS44

AF38

VSS45

AE38

VSS46

C38

VSS47

AK37

VSS48

AH37

VSS49

AB37

VSS50

AA37

VSS51

Y37

VSS52

W37

VSS53

V37

VSS54

T37

VSS55

R37

VSS56

P37

VSS57

N37

VSS58

M37

VSS59

L37

VSS60

J37

VSS61

H37

VSS62

G37

VSS63

F37

VSS64

D37

VSS65

AY36

VSS66

AW36

VSS67

AN36

VSS68

AH36

VSS69

AG36

VSS70

AF36

VSS71

AE36

VSS72

AC36

VSS73

C36

VSS74

B36

VSS75

BA35

VSS76

AV35

VSS77

AR35

VSS78

AH35

VSS79

AB35

VSS80

AA35

VSS81

Y35

VSS82

W35

VSS83

V35

VSS84

T35

VSS85

R35

VSS86

P35

VSS87

N35

VSS88

M35

VSS89

L35

VSS90

J35

VSS91

H35

VSS92

G35

VSS93

F35

VSS94

D35

VSS95

AN34

VSS96

AK34

VSS97

AG34

VSS98

AF34

VSS99

CALISTOGA_FCBGA1466~D

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

U3J

AN21

VSS200

AL21

VSS201

AB21

VSS202

Y21

VSS203

P21

VSS204

K21

VSS205

J21

VSS206

H21

VSS207

C21

VSS208

AW20

VSS209

AR20

VSS210

AM20

VSS211

AA20

VSS212

K20

VSS213

B20

VSS214

A20

VSS215

AN19

VSS216

AC19

VSS217

W19

VSS218

K19

VSS219

G19

VSS220

C19

VSS221

AH18

VSS222

P18

VSS223

H18

VSS224

D18

VSS225

A18

VSS226

AY17

VSS227

AR17

VSS228

AP17

VSS229

AM17

VSS230

AK17

VSS231

AV16

VSS232

AN16

VSS233

AL16

VSS234

J16

VSS235

F16

VSS236

C16

VSS237

AN15

VSS238

AM15

VSS239

AK15

VSS240

N15

VSS241

M15

VSS242

L15

VSS243

B15

VSS244

A15

VSS245

BA14

VSS246

AT14

VSS247

AK14

VSS248

AD14

VSS249

AA14

VSS250

U14

VSS251

K14

VSS252

H14

VSS253

E14

VSS254

AV13

VSS255

AR13

VSS256

AN13

VSS257

AM13

VSS258

AL13

VSS259

AG13

VSS260

P13

VSS261

F13

VSS262

D13

VSS265

B13

VSS264

AY12

VSS263

AC12

VSS266

K12

VSS267

H12

VSS268

E12

VSS269

AD11

VSS270

AA11

VSS271

Y11

VSS272

J11

VSS273

D11

VSS274

B11

VSS275

AV10

VSS276

AP10

VSS277

AL10

VSS278

AJ10

VSS279

CALISTOGA_FCBGA1466~D

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

Compal Electronics, Inc.(KunShan)

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Calistoga6/6-GND

Size Document Number Rev

Custom

PecosII-IDX80-LA3291

Date: Sheet

1

of

14 53Monday, January 08, 2007

X 0.5

5

DDR_A_DQS#[0..7]<10>
DDR_A_D[0..63]<10>
DDR_A_DM[0..7]<10>
DDR_A_DQS[0..7]<10>
DDR_A_MA[0..13]<10>

D D

Layout Note:
Place near JP4

Add C611, C612 follow Motion's request

+1.8V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2.2U_0805_16V4Z
C541

1

2

0.1U_0402_16V4Z

1

2

C550

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

5

1

2

2.2U_0805_16V4Z

C551

+0.9VS

1

2

0.1U_0402_16V4Z

1

2

2.2U_0805_16V4Z

C542

C543

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C554

C553

C552

RP2 56_0404_4P2R_5%

DDR_CKE0_DIMMA

14

DDR_A_BS#2

23

RP4 56_0404_4P2R_5%

DDR_A_MA7

14

DDR_A_MA6

23

RP6 56_0404_4P2R_5%

DDR_A_MA12

14

DDR_A_MA9

23

RP8 56_0404_4P2R_5%

DDR_A_MA4

14

DDR_A_MA2

23

RP10 56_0404_4P2R_5%

DDR_A_MA0

14

DDR_A_BS#1

23

RP12 56_0404_4P2R_5%

M_ODT0

14

DDR_A_MA13

23

RP13 56_0404_4P2R_5%

DDR_CKE1_DIMMA

14

DDR_A_MA11

23

1

C544

2

0.1U_0402_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C C

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9VS

0.1U_0402_16V4Z

B B

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_MA10
DDR_A_BS#0

DDR_A_WE#

A A

DDR_A_CAS#

M_ODT1
DDR_CS1_DIMMA#

C540

1

C539

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C548

C549

RP1

RP3

RP5

RP7

RP9

RP11

0.1U_0402_16V4Z

1

1

2

1

2

C555

C546

C545

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C557

C556

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C611

C547

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C559

C558

Layout Note:
Place these resistor
closely JP4,all
trace length Max=1.5"

4

0.1U_0402_16V4Z

1

2

C560

3

+1.8V

JP4

1

VREF

3

DDR_A_D0
DDR_A_D4

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

+1.8V

1

C612

2

1

C528

+

220U_D2_4VM

@

2

DDR_CKE0_DIMMA<9>

DDR_A_BS#2<10>

DDR_A_BS#0<10>
DDR_A_WE#<10>

DDR_A_CAS#<10>

DDR_CS1_DIMMA#<9>

M_ODT1<9>

ICH_SMBDATA<5,6,16,22,24>

ICH_SMBCLK<5,6,16,22,24>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_A_D21
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D22
DDR_A_D19

DDR_A_D25
DDR_A_D24

DDR_A_DM3

DDR_A_D27
DDR_A_D30

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10

DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#

DDR_CS1_DIMMA#

M_ODT1
DDR_A_D34

DDR_A_D38
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D39

DDR_A_D35
DDR_A_D45

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D52

DDR_A_D53

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D51
DDR_A_D55

DDR_A_D56
DDR_A_D61

DDR_A_DM7
DDR_A_D58

DDR_A_D59

ICH_SMBDATA
ICH_SMBCLK

+3VS

1

C561

0.1U_0402_16V4Z

3

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2R-TR

SO-DIMM A

REVERSE

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

NC

A7
A6

A4
A2
A0

NC

2

+1.8V

V_DDR_MCH_REF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_D7
DDR_A_D1

DDR_A_DM0
DDR_A_D5

DDR_A_D6
DDR_A_D12

DDR_A_D13
DDR_A_DM1
M_CLK_DDR0

M_CLK_DDR#0
DDR_A_D9

DDR_A_D15

DDR_A_D20
DDR_A_D16

R579 0_0402_5%@

1 2

DDR_A_DM2
DDR_A_D18

DDR_A_D23
DDR_A_D29

DDR_A_D28
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D26

DDR_A_D31
DDR_CKE1_DIMMA

DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D36
DDR_A_D33

DDR_A_DM4
DDR_A_D37

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D46
DDR_A_D48

DDR_A_D49
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D50

DDR_A_D54
DDR_A_D60

DDR_A_D57
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R577

R578

10K_0402_5%

10K_0402_5%

2

12

2.2U_0805_16V4Z

0.1U_0402_16V4Z

1

C537

2

M_CLK_DDR0 <9>
M_CLK_DDR#0 <9>

EC_EXTTS#0

DDR_CKE1_DIMMA <9>

DDR_A_BS#1 <10>
DDR_A_RAS# <10>
DDR_CS0_DIMMA# <9>

M_ODT0 <9>

M_CLK_DDR1 <9>
M_CLK_DDR#1 <9>

EC_EXTTS#0 <9,16,33>

Compal Electronics, Inc.(KunShan)

Title

Size Document Number Rev

Custom

Date: Sheet

V_DDR_MCH_REF <9,16>

1

C538

2

DDRII SO-DIMM A

PecosII-IDX80-LA3291

1

X 0.5

of

1

15 53Monday, January 08, 2007

5

DDR_B_DQS#[0..7]<10>
DDR_B_D[0..63]<10>
DDR_B_DM[0..7]<10>

DDR_B_DQS[0..7]<10>
DDR_B_MA[0..13]<10>

D D

Layout Note:
Place near JP5

Add C619, C625 follow Motion's request

+1.8V

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

2

1

2

C574

RP14

RP16

RP18

RP20

RP23

RP25

C565

0.1U_0402_16V4Z

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C566

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C576

C575

+0.9VS

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

5

2.2U_0805_16V4Z

C567

1

C568

1

2

2

0.1U_0402_16V4Z

1

1

2

2

C578

C577

RP15 56_0404_4P2R_5%

14
23

RP17 56_0404_4P2R_5%

14
23

RP19 56_0404_4P2R_5%

14
23

RP21 56_0404_4P2R_5%

14
23

RP24 56_0404_4P2R_5%

14
23

RP26 56_0404_4P2R_5%

14
23

RP28

14
23

56_0404_4P2R_5%

0.1U_0402_16V4Z

1

C569

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C579

DDR_B_MA9
DDR_B_MA12

DDR_B_MA11
DDR_CKE3_DIMMB

DDR_B_MA5
DDR_B_MA8

DDR_B_MA6
DDR_B_MA7

DDR_B_MA2
DDR_B_MA4

DDR_B_MA13
M_ODT2

DDR_B_BS#2
DDR_CKE2_DIMMB

0.1U_0402_16V4Z

C580

0.1U_0402_16V4Z

1

1

C570

C571

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C582

C581

2.2U_0805_16V4Z
C564

1

2

C C

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

+0.9VS

0.1U_0402_16V4Z

1

2

C573

B B

DDR_B_MA1
DDR_B_MA3

DDR_B_BS#0
DDR_B_MA10

DDR_B_BS#1
DDR_B_MA0

DDR_CS2_DIMMB#
DDR_B_RAS#

DDR_B_CAS#

A A

DDR_B_WE#

DDR_CS3_DIMMB#
M_ODT3

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C619

C572

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C584

C583

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"

4

3

+1.8V

JP5

1

VREF

3

DDR_B_D0
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D7
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

0.1U_0402_16V4Z

1

C625

2

DDR_CKE2_DIMMB<9>

DDR_B_BS#2<10>

DDR_B_BS#0<10>
DDR_B_WE#<10>

DDR_B_CAS#<10>

1

2

C585

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_CS3_DIMMB#<9>

M_ODT3<9>

ICH_SMBDATA<5,6,15,22,24>

ICH_SMBCLK<5,6,15,22,24>

3

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D22

DDR_B_D23
DDR_B_D24

DDR_B_D25
DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10

DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D37

DDR_B_D36
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D35

DDR_B_D34
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D47
DDR_B_D48

DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D60
DDR_B_D61

DDR_B_DM7
DDR_B_D58

DDR_B_D59

ICH_SMBDATA

ICH_SMBCLK

+3VS

C586

0.1U_0402_16V4Z

1

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

QTC_C111A-040SP31

SO-DIMM B
STANDARD

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

2

+1.8V

V_DDR_MCH_REF

2

DDR_B_D4

4

DDR_B_D1

6
8

DDR_B_DM0

10
12

DDR_B_D6

14

DDR_B_D2

16
18

DDR_B_D12

20

DDR_B_D13

22
24

DDR_B_DM1

26
28

M_CLK_DDR3

30

M_CLK_DDR#3

32
34

DDR_B_D14

36

DDR_B_D15

38
40

42

DDR_B_D16DDR_B_D21

44

DDR_B_D18

46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

R634 0_0402_5%@

DDR_B_DM2
DDR_B_D17

DDR_B_D19
DDR_B_D26

DDR_B_D28
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D33
DDR_B_D32

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D43

DDR_B_D46
DDR_B_D49

DDR_B_D52
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D56

DDR_B_D57
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63

2

1 2

10K_0402_5%

12

R581

2.2U_0805_16V4Z

M_CLK_DDR3 <9>
M_CLK_DDR#3 <9>

EC_EXTTS#0

DDR_CKE3_DIMMB <9>

DDR_B_BS#1 <10>
DDR_B_RAS# <10>
DDR_CS2_DIMMB# <9>

M_ODT2 <9>

M_CLK_DDR2 <9>
M_CLK_DDR#2 <9>

R580

1 2

10K_0402_5%

1

2

Title

Size Document Number Rev

Custom

Date: Sheet

V_DDR_MCH_REF <9,15>

0.1U_0402_16V4Z

1

C562

C563

2

EC_EXTTS#0 <9,15,33>

+3VS

Compal Electronics, Inc.(KunShan)

DDRII SO-DIMM B

PecosII-IDX80-LA3291

1

X 0.5

of

16 53Monday, January 08, 2007

1