INTELBRAS I400, LA-4611P Schematics

A

B

C

D

E

PJP1

14W_DCIN

14W_45@

1 1

PJP1

15W_DCIN

15W_45@

Compal Confidential

2 2

Intel Merom Processor with SiSM672/FX + DDRII + SiS968 + SiS307ELV

KSW01/91 Schematics Document

2008-08-01

ZZZ9

3 3

4 4

PCB

ZZZ1

PCB

14WDAZ@

ZZZ2

PCB

15WDAZ@

A

ZZZ3

LA-4611P

14WDA@

ZZZ8

LA-4611P

15WDA@

ZZZ4

LS-4243P

14WDA@

ZZZ10

LS-4243P

15WDA@

ZZZ5

LS-4244P

14WDA@

ZZZ11

LS-4244P

15WDA@

ZZZ6

LS-4249P

14WDA@

ZZZ12

LS-4245P

15WDA@

ZZZ13

LS-4246P

15WDA@

B

REV: 0.2

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/05/18 2009/05/18

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

KSWXX M/B LA-4611P Schematic

147Friday, August 01, 2008

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of

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Compal Confidential

Model Name : KSW01/91

Fan Control

page 4

File Name : LA-4611P

1 1

CRT

page 17

Intel Merom Processor

uPGA-478 Package

H_A#(3..35)

FSB

533MHz

page 4,5,6

H_D#(0..63)

SiS M672 /FX

LCD Conn.

page 16

SiS 307ELV

page 18

PCI-Express

TEBGA-847

page 7,8,9,10,11

Thermal Sensor

ADM1032

page 4

Memory BUS(DDRII)

Single Channel

1.8V DDRII 533/667

Clock Generator

ICS9LPRS600C+
ICS9P935

page 14,15

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

page 12,13

1GB/s MuTIOL IO Link

2 2

PCI-Express

SiS968

MII

TEBGA-570

page 19,20,21,22,23

New Card
Socket

page 30 page 29

MINI Card x1

WLAN

LAN

RTL8201CL

page 28

PCI BUS

3.3V 33 MHz

IDSEL:AD22
(PIRQG#,PIRQH#,
GNT#0, REQ#0)

USB conn x3
TO I/O/B

3.3V 48MHz

3.3V 24.576MHz/48Mhz

3.3V ATA-100
S-ATA

port 0

USB

IDE

S-ATA HDD
Conn.

page 24

Bluetooth
Conn

page 33 page 37

HD Audio

port 1

CDROM
Conn.

page 24

Web Camera

MDC 1.5
Conn

page 37

Card Reader

RTS5158E

page 26

HDA Codec

ALC268

page 35

3 in 1
socket

page 27page 34

Audio AMP

RJ45

3 3

page 28

LPC BUS

page 36

RTC CKT.

page 20

ENE KB926C

page 31

Power On/Off CKT.

page 34

Touch Pad

page 33

Int.KBD

page 32

DC/DC Int erface CKT.

page 39

I/O Conn.
Power /B.

Power Circuit DC/DC

4 4

page 40,
41,43,44,45,46

Function /B.
LID SW

page 34

BIOS

page 33

CHARGER

page 42

A

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

Block Diagrams

KSWXX M/B LA-4611P Schematic

247Friday, August 01, 2008

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Voltage Rails

DescriptionPower Plane

1 1

2 2

VIN
B+
+CPU_CORE

+1.05VS

+1.5VS
+1.8V

+2.5VS
+3VALW
+3VS
+5VALW
+5VS

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

0.9V switched power rail for DDR terminator+0.9VS ( Actual +0.9V )

1.05V switched power rail

1.5V switched power rail

1.8V power rail for DDR

1.8V switched power rail+1.8VS

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

RTC power+RTCVCC

SIGNAL

SLP_S3#SLP_S1#

HIGH HIGH HIGH

LOW

LOW

LOW

LOW LOW LOW

SLP_S4#

HIGH

LOWLOWLOW

SLP_S5#

HIGHHIGHHIGHHIGH

HIGH

HIGH

LOW

S3S1

N/A N/A N/A

OFFON

ON

ON

ON1.2V switched power rail+1.2VS

ON

ON

OFF

ON
ON

OFF
ON
ON

OFF
ON

ON

OFF

ON OFF

ONONON

+VALW

+V +VS Clock

ON

ON

ON

ON

ON

ON

ON

OFF

ON

OFF

S5

N/AN/AN/A

OFF
OFF
OFFOFFON
OFFOFF
OFFOFFON
OFF
OFF
OFF
ON*ON
OFF
ON*

ON*ONVSB always on power rail+VSB
ON

ON

OFF

OFF

OFF

ONON

LOW

OFF

OFF

OFF

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

External PCI Devices

DEVIC E REQ/GNT #

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

IDSEL #

Address

1010 000X b

PIRQ

EC SM Bus2 address

Device

ADI ADM1032

Address

1001 100X b0001 011X b

M672 SM Bus address

Device

Clock Generator

DDR DIMM0
DDR DIMM1

Address

1101 001Xb

1010 000Xb
1010 001Xb

PROJECT ID Table

3 3

14W
15W

PROJECT_ID
R424 (Pull low)
NA (Internal Pull High)

SKU ID Table

Vcc 3.3V +/- 5%

100K +/- 5%Ra

Ra~ R312

R311

8.2K_0402_5%

14_B@

R311

18K_0402_5%

14_C@

R311

33K_0402_5%

14_MP@

R311

56K_0402_5%

15_A@

R311

100K_0402_5%

15_B@

Rb~ R311

Board ID

0
1
2
3
4
5

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

6
7

2006/08/18 2007/8/18

C

Rb

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

NC

Compal Secret Data

Vmin

AD_BID

0 V

Vtyp

AD_BID

0 V 0 V

0.217 V 0.250 V 0.288 V

0.439 V

0.721 V

1.054 V

0.503 V

0.819 V

1.185 V 1.325 V

1.489 V 1.650 V 1.819 V

2.019 V

3.135V

Deciphered Date

2.200 V

3.300 V

D

V

max

AD_BID

Rb BOM Structure

0.575 V

0.926 V

2.386 V

3.465 V

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

KSWXX M/B LA-4611P Schematic

14_A@
14_B@
14_C@
14_MP@
15_A@
15_B@
15_C@
15_MP@

Notes List

R311

200K_0402_5%

15_C@

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347Friday, August 01, 2008

5

4

3

2

1

5

H_A#[3..35]
H_REQ#[0..4]
H_RS#[0..2]

H_ADSTB#0<7>

H_ADSTB#1<7>
H_A20M#<20>

H_FERR#<20>
H_IGNNE#<20>

H_STPCLK#<20>
H_INTR<20>
H_NMI<20>
H_SMI#<20>

H_STPCLK#
H_INIT#
H_IGNNE#
H_SMI#
H_A20M#
H_NMI
H_INTR
H_THERMTRIP#
H_FERR#

H_BR0#
H_RESET#
ITP_DBRESET#

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

JP36A

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Merom Ball-out Rev 1a

conn@

ADDR GROUP 0 ADDR GROUP 1

ICH

ADS#
BNR#

BPRI#

DEFER#

DRDY#

DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

XDP/ITP SIGNALS

DBR#

THERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

H CLK

BCLK[0]
BCLK[1]

RESERVED

H1
E2
G5

H5
F21
E1

F1

H_IERR#

D20

H_INIT#

B3
H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2

H_PREQ#

AC1

ITP_TCK

AC5

ITP_TDI

AA6

TDI

AB3

ITP_TMS

AB5

ITP_TRST#

AB6

ITP_DBRESET#

C20

H_PROCHOT#

D21

THERMDA_R

A24
B25

C7

A22
A21

R19 100_0402_5%SMSC@

THERMDC_R

R20 100_0402_5%SMSC@

H_THERMTRIP#

H_THERMTRIP#

C114 0.1U_0402_16V4Z

1 2

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel : Pull-up 56ohm (Mount) SiS : Pull-up 56ohm (Mount)
Intel : Pull-up 56ohm (Mount) SiS : Pull-up 56ohm (Mount)

Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Un-Mount)
Intel :Don't Pull-up SiS : Pull-up 150ohm (Mount)

4

Trace length must short

H_ADS# <7>
H_BNR# <7>
H_BPRI# <7>

H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>

H_BR0# <7>

H_INIT# <20>
H_LOCK# <7>
H_RESET# <7>

H_TRDY# <7>
H_HIT# <7>

H_HITM# <7>

R19

0_0402_5%

NS@

Intel :Pull-up 56ohm (Un-Mount) SiS : Pull-up 56ohm (Mount)

Intel :Pull-up 56ohm (Mount) SiS : Pull-up 54.9ohm (Mount)

Intel :Pull-up 56ohm (Mount) SiS : Pull-up 75ohm (Mount)

R20

Add for option
Michael 2008/5/30

Checklist r e commend 39 Ohm

0_0402_5%

NS@

EMC1402

1/29 change to EMC1402 pn

Connect SB SYS_RESET# or just left NC

1

C2

2

1 2

THERMDA
THERMDC

2200P_0402_50V7K

R18 10K_0402_5%

Address:100_1100

ITP_DBRESET#
H_PROCHOT# <20,46>

THERMDA
THERMDC

H_CLK_DP0 <14>
H_CLK_DN0 <14>

+3VS

H_THERMTRIP# <20>

FAN1 Conn

U1

EN_FAN1<31>

ADM1032ARMZ_MSOP8

MX@

R19

0_0402_5%

MX@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R20

0_0402_5%

MX@

Add for option
Michael 2008/6/12

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

+VCC_FAN1

R815

1 2

330_0402_5%

2

+3VS

+5VS

EN_FAN1_R

12

C769

0.047U_0402_16V7K

FAN_SPEED1<31>

Place close to CPU within 500mil

+1.05VS

H_PREQ#
H_IERR#
ITP_TMS
ITP_TDI
H_PROCHOT#
ITP_TCK
ITP_TRST#

C1

0.1U_0402_16V4Z

1 2

1
2
3
4

U2

1

VEN

2

VIN

3

VO

4

VSET

G990P11U_SOP8

R85 56_0402_5%@

1 2

R115 56_0402_5%

1 2

R84 56_0402_5%

1 2

R83 150_0402_1%

1 2

R113 56_0402_5%

1 2

R69 27.4_0402_1%

1 2

R61 680_0402_5%

1 2

CRB pull 75 Ohm

Add Michael 2008/5/30
for second source

U1

LM95245CIMMX NOPB MSOP 8P

NS@

U1

VDD
D+

ALERT/THERM2

D­THERM

EMC1402-1-ACZL-TR

SMSC@

C3 10U_0805_10V4Z

1 2

GND
GND
GND
GND

+3VS

12

R21
10K_0402_5%

1

C6
1000P_0402_50V7K

2

Title

Size Document Number Rev

B

Date: Sheet

SCLK

SDATA

GND

8
7
6
5

8
7
6
5

R706 10K_0402_5%

EC_SMB_CK2 <31>
EC_SMB_DA2 <31>

12

FX@

+5VS

12

D1
BAS16_SOT23-3

D2

1 2

BAS16_SOT23-3

C4 10U_0805_10V4Z

1 2

C5

1000P_0402_50V7K

1 2

40mil

+VCC_FAN1

1
2
3

4
5

ACES_85205-03001

Compal Electronics, Inc.

Merom (1/3)

KSWXX M/B LA-4611P Schematic

447Friday, August 01, 2008

1

+3VS

JP7

CONN@

of

1
2
3

GND
GND

0.1

H_A#[3..35]<7>
H_REQ#[0..4]<7>
H_RS#[0..2]<7>

D D

C C

B B

+1.05VS

CPU to SB interface

R120 56_0402_5%

1 2

R141 56_0402_5%

1 2

R128 56_0402_5%

1 2

R144 56_0402_5%

1 2

R148 56_0402_5%

1 2

R137 56_0402_5%

1 2

R140 56_0402_5%

1 2

R127 56_0402_5%

A A

1 2

R208 56_0402_5%

1 2

+1.05VS

R114 51_0402_1%

1 2

R136 56_0402_5%@

1 2

R112 150_0402_1%

1 2

5

4

3

2

1

GTL_REF

1

C368
1U_0603_10V4Z

2

D D

SiS Recommend

Close to CPU pin AD26
within 500mils.

C C

Width=20 mil

B B

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

1

C814
220P_0402_50V7K

2

H_DSTBN#0<7>
H_DSTBP#0<7>
H_DINV#0<7>

+1.05VS

R321

1K_0402_1%

R319

2K_0402_1%

1 2

1 2

H_DSTBN#1<7>
H_DSTBP#1<7>
H_DINV#1<7>

R111 1K_0402_5%@
R98 1K_0402_5%@

C364 0.1U_0402_16V4Z@

1 2

12
12

T3
T2

T23

CPU_BSEL0<14>
CPU_BSEL1<14>
CPU_BSEL2<14>

PAD
PAD

PAD

CPU_BSEL CPU_BSEL2 CPU_BSEL1

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

GTL_REF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

JP36B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

conn@

CPU_BSEL0

DATA GRP 0

DATA GRP 1

MISC

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#

DATA GRP 2DATA GRP 3

D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP0
COMP1
COMP2
COMP3

H_DPSLP#
H_DPWR#_R
H_PWRGOOD
H_CPUSLP#

001133

166

200

01

0

1

1

0

H_D#[0..63]

H_DSTBN#2 <7>
H_DSTBP#2 <7>
H_DINV#2 <7>

H_DSTBN#3 <7>
H_DSTBP#3 <7>

1 2
1 2
1 2
1 2

H_DINV#3 <7>

H_DPRSTP# <25,46>
H_DPSLP# <25>

H_PWRGOOD <7>
H_CPUSLP# <20>
H_PSI# <46>

1 2

R126 0_0402_5%

R324 27.4_0402_1%
R323 54.9_0402_1%
R42 27.4_0402_1%
R44 54.9_0402_1%

H_DPWR#_R H_DPWR#

R131
10_0402_5%

H_D#[0..63] <7>

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

@

+CPU_CORE

H_DPWR# <7>

JP36C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

conn@

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

+CPU_CORE

VCCSENSE

VSSSENSE

CPU_VID0 <46>
CPU_VID1 <46>
CPU_VID2 <46>
CPU_VID3 <46>
CPU_VID4 <46>
CPU_VID5 <46>
CPU_VID6 <46>

R27

R24 100_0402_1%

Length match within 25 mils.

Place this cap more close to
B26/C26 rather than 10UF

1

+

C80
330U_D2E_2.5VM_R9

2

20mils

1

C438

0.01U_0402_16V7K

2

1 2

1 2

100_0402_1%

VCCSENSE <46>

VSSSENSE <46>

+1.05VS

1

C432
10U_0805_10V4Z

2

+CPU_CORE

+1.5VS

The trace width/space/other is

+1.05VS

R121 56_0402_5%

A A

1 2

R143 56_0402_5%

1 2

R133 56_0402_5%@

1 2

R119 56_0402_5%@

1 2

C650 0.1U_0402_16V4Z@

1 2

5

H_CPUSLP#
H_DPSLP#
H_PWRGOOD
H_DPWR#

H_PWRGOOD

Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)

SiS Recommend
Intel :Pull-up 56ohm (Un-Mount) SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up (Connecte to ICH) SiS : Pull-up 56ohm (Un-Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Un-Mount)

Intel :Don't Pull-down SiS :Pull-down Cap (Un-Mount)

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/05/15 2009/05/15

3

Compal Secret Data

Deciphered Date

2

20/7/25.

Close to CPU pin
within 500mils.

Title

Size Document Number Rev

B

KSWXX M/B LA-4611P Schematic

Date: Sheet of

Compal Electronics, Inc.

Merom (2/3)

547Friday, August 01, 2008

1

0.1

5

4

3

2

1

+CPU_CORE

JP36D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

D D

C C

B B

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

conn@

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

1

+

C47
330U_D2E_2.5VM_R9

2

+CPU_CORE

1

C394

2

10U_0805_6.3V6M

+CPU_CORE

1

C379

2

10U_0805_6.3V6M

+CPU_CORE

1

C107

2

10U_0805_6.3V6M

+CPU_CORE

1

C77

2

10U_0805_6.3V6M

+CPU-CORE
Decoupling
SPCAP,Polymer

MLCC 0805 X5R

3 x 330uF(9mOhm/3) 3 x 330uF(9mOhm/3)

1

+

C350

2

330U_D2E_2.5VM_R9

South Side Seco ndary North Side Secondary

1

C383

10U_0805_6.3V6M

2

10U_0805_6.3V6M

1

+

C390

@

330U_D2E_2.5VM_R9

2

1

C408

10U_0805_6.3V6M

2

(Place these capacitors on South side,Secondary Layer)

1

C378

10U_0805_6.3V6M

2

1

C377

2

10U_0805_6.3V6M

10U_0805_6.3V6M

(Place these capacitors on North side,Secondary Layer)

1

C106

10U_0805_6.3V6M

2

1

C105

2

10U_0805_6.3V6M

10U_0805_6.3V6M

(Place these capacitors on South side,Primary Layer)

1

C76

10U_0805_6.3V6M

2

1

C75

2

10U_0805_6.3V6M

10U_0805_6.3V6M

(Place these capacitors on North side,Primary Layer)

C,uF ESR, mohm ESL,nH
6X330uF 9m ohm/6 1.8nH/6

32X22uF 3m ohm/32 0.6nH/32
32X10uF 3m ohm/32 0.6nH/32

+1.05VS

1

2

0.1U_0402_16V4Z

1

C97

0.1U_0402_16V4Z

2

C87

0.1U_0402_16V4Z

1

2

1

2

1

2

1

2

1

C81

0.1U_0402_16V4Z

2

+CPU_CORE

1

+

C347

330U_D2E_2.5VM_R9

2

330U_D2E_2.5VM_R9

C409

C376

C104

C74

1

C410

2

10U_0805_6.3V6M

1

C375

2

10U_0805_6.3V6M

1

C103

2

10U_0805_6.3V6M

1

C84

2

10U_0805_6.3V6M

1

C96

2

0.1U_0402_16V4Z

1

+

C155

2

1

10U_0805_6.3V6M

2

1

10U_0805_6.3V6M

2

1

10U_0805_6.3V6M

2

1

10U_0805_6.3V6M

2

1

C83

0.1U_0402_16V4Z

2

C169

@

330U_D2E_2.5VM_R9

C411

10U_0805_6.3V6M

C385

10U_0805_6.3V6M

C89

10U_0805_6.3V6M

C78

10U_0805_6.3V6M

1

C73

2

1

+

2

1

C412

10U_0805_6.3V6M

2

1

C393

10U_0805_6.3V6M

2

1

C46

10U_0805_6.3V6M

2

1

C88

10U_0805_6.3V6M

2

1

CRB no stuff. Reserved!

C392

2

1

C384

2

1

C90

2

1

C85

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/05/15 2009/05/15

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

2

Date: Sheet

Compal Electronics, Inc.

Merom (3/3)

KSWXX M/B LA-4611P Schematic

647Friday, August 01, 2008

1

0.1

of

5

+1.05VS

12

R210

75_0402_1%

D D

12

R202

150_0402_1%

C C

B B

+1.8VS +1.8VS

A A

L40

1 2

MBK1608121YZF_0603

1

C454
10U_0805_10V4Z

2

1 2

R399 0_0402_5%

1

C191

0.01U_0402_16V7K

2

1

C212

2

0.01U_0402_16V7K

1

C472

0.1U_0402_16V4Z

2

5

1

C200

0.1U_0402_16V4Z

2

H_CLK_DP1<14>
H_CLK_DN1<14>

PAD

T30

PAD

T5

H_DPWR#<5>

H_LOCK#<4>
H_DEFER#<4>
H_TRDY#<4>
H_RESET#<4>
H_PWRGOOD<5>
H_BPRI#<4>
H_BR0#<4>
H_RS#[0..2]<4>

H_ADS#<4>

H_HITM#<4>

H_HIT#<4>

H_DRDY#<4>

H_DBSY#<4>

H_BNR#<4>

H_REQ#[0..4]<4>

H_ADSTB#0<4>

H_ADSTB#1<4>

H_A#[3..35]<4>

C1XAVDD:10mA C4XAVDD:12mA

C1XAVDD

1

C481

0.01U_0402_16V7K

2

C1XAVSS

C1XAVDD
C1XAVSS

C4XAVDD
C4XAVSS

NB_GTLREF

PCREQ#
EDRDY#

H_DPWR#

H_CLK_DP1
H_CLK_DN1

H_LOCK#
H_DEFER#
H_TRDY#
H_RESET#
H_PWRGOOD
H_BPRI#
H_BR0#

H_RS#0
H_RS#1
H_RS#2

H_ADS#
H_HITM#
H_HIT#
H_DRDY#
H_DBSY#
H_BNR#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

1 2

MBK1608121YZF_0603

1

C455
10U_0805_10V4Z

2

R400 0_0402_5%

L31

1 2

B16
C17

A17
B18

W24

U24
R24
N24

R34
P32

E21

F18

G18

P30
P31
F21
P28
N30
P33

K34

M31

K33

M34

N34
N32

M33
M32

T34
R30
R29
R32
P34

U34

AA34

T32
T28
T31
T33
T30
U32
U30
V34
U29
V33
V32
V28
V31

W34

Y33

W32

V30

W30

Y34
Y28

W29

Y32
Y30

Y31
AA32
AA30
AA29
AB33
AB34
AB32
AC34
AB30
AB31

L21

L32

L34

4

U30C

C1XAVDD
C1XAVSS

C4XAVDD
C4XAVSS

HVREF
HVREF
HVREF
HVREF
HVREF

PCREQ#
EDRDY#

DPWR#

CPUCLK
CPUCLK#

HLOCK#
DEFER#
HTRDY#
CPURST#
CPUPWRGD
BPRI#
BREQ0#

RS0#
RS1#
RS2#

ADS#
HITM#
HIT#
DRDY#
DBSY#
BNR#

HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#

HASTB0#
HASTB1#

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HA32#
HA33#
HA34#
HA35#

SISM672MX-A1_TEBGA_847P

MX@

1

C470

0.1U_0402_16V4Z

2

Host

1

2

4

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

DBI0#
DBI1#
DBI2#
DBI3#

HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#

HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#

HPCOMP
HNCOMP

C4XAVDD

C479

0.01U_0402_16V7K

C4XAVSS

3

H_D#0

N29

H_D#1

M30

H_D#2

M28

H_D#3

L30

H_D#4

L29

H_D#5

K28

H_D#6

K31

H_D#7

K30

H_D#8

H31

H_D#9

G34

H_D#10

H32

H_D#11

G32

H_D#12

K32

H_D#13

F34

H_D#14

F33

H_D#15

F32

H_D#16

H28

H_D#17

J30

H_D#18

H30

H_D#19

G29

H_D#20

J29

H_D#21

G30

H_D#22

F30

H_D#23

D33

H_D#24

D34

H_D#25

B32

H_D#26

B33

H_D#27

C34

H_D#28

D31

H_D#29

A32

H_D#30

A31

H_D#31

C31

H_D#32

B30

H_D#33

C30

H_D#34

A30

H_D#35

D28

H_D#36

G28

H_D#37

C29

H_D#38

C28

H_D#39

E28

H_D#40

E27

H_D#41

C27

H_D#42

G26

H_D#43

E26

H_D#44

D26

H_D#45

B26

H_D#46

A26

H_D#47

C26

H_D#48

G22

H_D#49

C24

H_D#50

A25

H_D#51

B24

H_D#52

C25

H_D#53

A24

H_D#54

E23

H_D#55

E25

H_D#56

G24

H_D#57

D22

H_D#58

C22

H_D#59

E22

H_D#60

C23

H_D#61

A23

H_D#62

A22

H_D#63

B22

H_DINV#0

J32

H_DINV#1

E32

H_DINV#2

F27

H_DINV#3

F23

H_DSTBN#0

H33

H_DSTBN#1

E31

H_DSTBN#2

B28

H_DSTBN#3

D24

H_DSTBP#0

H34

H_DSTBP#1

D32

H_DSTBP#2

A28

H_DSTBP#3

E24

H_PCOMP

A21
C21

R175 10_0402_5%

H_NCOMP

R188 110_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H_D#[0..63] <5>

U30

S IC SISM672FXA1 TEBGA 847P

FX@

V_AVDD_PCIE_1.2V

SB_PCIE_WAKE#<21,29,30>

INT_N_A<9,19>

H_DINV#0 <5>
H_DINV#1 <5>
H_DINV#2 <5>
H_DINV#3 <5>

H_DSTBN#0 <5>
H_DSTBN#1 <5>
H_DSTBN#2 <5>
H_DSTBN#3 <5>

H_DSTBP#0 <5>
H_DSTBP#1 <5>
H_DSTBP#2 <5>
H_DSTBP#3 <5>

+1.05VS

2008/05/15 2009/05/15

3

Compal Secret Data

Deciphered Date

+1.2VS V_AVDD_PCIE_1.2V

SB_PCIE_WAKE#
INT_N_A

2

L22

1 2

MBK1608121YZF_0603

U30D

P7

PCIEAVDD

R7

PCIEAVDD

T7

PCIEAVDD

U7

PCIEAVDD

V7

PCIEAVDD

D7

PME#

G16

INTX#

E4

PERP0

E5

PERN0

F1

PERP1

G1

PERN1

H3

PERP2

H2

PERN2

H1

PERP3

J1

PERN3

K1

PERP4

PCIE

PERN4
PERP5
PERN5
PERP6
PERN6
PERP7
PERN7
PERP8
PERN8
PERP9
PERN9
PERP10
PERN10

PETN10(HDVBN1)
PERP11
PERN11

PETN11(HDVBN0)
PERP12
PERN12
PERP13
PERN13

PETN13(HDVAN2)
PERP14
PERN14

PETN14(HDVAN1)
PERP15
PERN15

PETN15(HDVAN0)

SISM672MX-A1_TEBGA_847P

MX@

HDVBP2
HDVBN2
HDVBP1
HDVBN1
HDVBP0
HDVBN0

HDVAP2
HDVAN2
HDVAP1
HDVAN1
HDVAP0
HDVAN0

AA1
AB1
AB2
AC1
AD1
AE1
AE2

AF1

AG1

K2
L1

M1

N1
N2
P1
R1
T1
T2
U1

V1
W1
W2

Y1

2

1

PCIEAVDD:77mA

1

C201

0.1U_0402_16V4Z

2

REFCLK+

REFCLK-

PETP0
PETN0
PETP1
PETN1
PETP2
PETN2
PETP3
PETN3
PETP4
PETN4
PETP5
PETN5
PETP6
PETN6
PETP7
PETN7
PETP8
PETN8

PETP9(HDVBP2)

PETN9(HDVBN2)

PETP10(HDVBP1)
PETP11(HDVBP0)

PETP12
PETN12

PETP13(HDVAP2)
PETP14(HDVAP1)
PETP15(HDVAP0)

C653 0.1U_0402_10V7K

12

C660 0.1U_0402_10V7K

12

C662 0.1U_0402_10V7K

12

C654 0.1U_0402_10V7K

12

C655 0.1U_0402_10V7K

12

C656 0.1U_0402_10V7K

12

C658 0.1U_0402_10V7K

12

C657 0.1U_0402_10V7K

12

C652 0.1U_0402_10V7K

12

C651 0.1U_0402_10V7K

12

C659 0.1U_0402_10V7K

12

C661 0.1U_0402_10V7K

12

Title

Size Document Number Rev

Custom

Date: Sheet

1

C218

0.01U_0402_16V7K

2

PCIE_CLK_NB

T5
T4

G6
H6
G4
G5
J6
K6
J4
J5
L6
M6
M4
M5
P6
R6
P4
P5
V6
W6
W4
W5
Y6
AA6
AA4
AA5
AB6
AC6
AC4
AC5
AD6
AE6
AE4
AE5

PCIE_CLK_NB#

HDVBP2
HDVBN2
HDVBP1
HDVBN1
HDVBP0
HDVBN0

HDVAP2
HDVAN2
HDVAP1
HDVAN1
HDVAP0
HDVAN0

HDVBP2_C
HDVBN2_C
HDVBP1_C
HDVBN1_C
HDVBP0_C
HDVBN0_C

HDVAP2_C
HDVAN2_C
HDVAP1_C
HDVAN1_C
HDVAP0_C
HDVAN0_C

PCIE_CLK_NB <14>
PCIE_CLK_NB# <14>

HDVBP2_C <18>
HDVBN2_C <18>
HDVBP1_C <18>
HDVBN1_C <18>
HDVBP0_C <18>
HDVBN0_C <18>

HDVAP2_C <18>
HDVAN2_C <18>
HDVAP1_C <18>
HDVAN1_C <18>
HDVAP0_C <18>
HDVAN0_C <18>

Compal Electronics, Inc.

M672MX (1/5)-HOST/PCIE

KSWXX M/B LA-4611P Schematic

1

0.1

747Friday, August 01, 2008

of

5

4

3

2

1

DDRA_SDQ[0..63]<12,13>
DDRA_SDM[0..7]<12,13>
DDRA_SMA[0..14]<12,13>

D D

C C

B B

A A

5

DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..14]

DDRA_SDQS0<12,13>
DDRA_SDQS0#<12,13>

DDRA_SDQS1<12,13>
DDRA_SDQS1#<12,13>

DDRA_SDQS2<12,13>
DDRA_SDQS2#<12,13>

DDRA_SDQS3<12,13>
DDRA_SDQS3#<12,13>

DDRA_SDQS4<12,13>
DDRA_SDQS4#<12,13>

DDRA_SDQS5<12,13>
DDRA_SDQS5#<12,13>

DDRA_SDQS6<12,13>
DDRA_SDQS6#<12,13>

DDRA_SDQS7<12,13>
DDRA_SDQS7#<12,13>

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDM0
DDRA_SDQS0
DDRA_SDQS0#

DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDM1
DDRA_SDQS1
DDRA_SDQS1#

DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDM2
DDRA_SDQS2
DDRA_SDQS2#

DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDM3
DDRA_SDQS3
DDRA_SDQS3#

DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDM4
DDRA_SDQS4
DDRA_SDQS4#

DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDM5
DDRA_SDQS5
DDRA_SDQS5#

DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDM6
DDRA_SDQS6
DDRA_SDQS6#

DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDM7
DDRA_SDQS7
DDRA_SDQS7#

4

U30B

AD31

MD0A

AD30

MD1A

AG34

MD2A

AE29

MD3A

AE32

MD4A

AF34

MD5A

AF31

MD6A

AE30

MD7A

AD28

DQM0A

AF32

DQS0A

AF33

DQS0A#

AF28

MD8A

AJ34

MD9A

AH31

MD10A

AG30

MD11A

AF30

MD12A

AG32

MD13A

AJ32

MD14A

AJ31

MD15A

AH34

DQM1A

AH32

DQS1A

AH33

DQS1A#

AK34

MD16A

AH30

MD17A

AL32

MD18A

AM33

MD19A

AK32

MD20A

AG29

MD21A

AM34

MD22A

AL31

MD23A

AJ30

DQM2A

AK33

DQS2A

AL34

DQS2A#

AM32

MD24A

AP32

MD25A

AP31

MD26A

AM29

MD27A

AK30

MD28A

AK29

MD29A

AJ27

MD30A

AK28

MD31A

AN32

DQM3A

AM30

DQS3A

AM31

DQS3A#

AK20

MD32A

AM20

MD33A

AM19

MD34A

AJ19

MD35A

AN20

MD36A

AJ21

MD37A

AP19

MD38A

AH20

MD39A

AK21

DQM4A

AK19

DQS4A

AL19

DQS4A#

AK18

MD40A

AJ17

MD41A

AK17

MD42A

AP16

MD43A

AH18

MD44A

AP18

MD45A

AN18

MD46A

AP17

MD47A

AM18

DQM5A

AL17

DQS5A

AM17

DQS5A#

AN16

MD48A

AK16

MD49A

AN14

MD50A

AJ15

MD51A

AP15

MD52A

AM16

MD53A

AK15

MD54A

AP14

MD55A

AH16

DQM6A

AL15

DQS6A

AM15

DQS6A#

AL13

MD56A

AM13

MD57A

AM12

MD58A

AJ13

MD59A

AM14

MD60A

AK14

MD61A

AN12

MD62A

AH14

MD63A

AK13

DQM7A

AP12

DQS7A

AP13

DQS7A#

SISM672MX-A1_TEBGA_847P

MX@

D1XAVDD
D1XAVSS

D4XAVDD
D4XAVSS

MA0A
MA1A
MA2A
MA3A
MA4A
MA5A
MA6A
MA7A
MA8A

MA9A
MA10A
MA11A
MA12A

DRAM

MA13A
MA14A
MA15A
MA16A
MA17A

RASA#
CASA#

WEA#

FWDSDCLKOA

FWDSDCLKOA#

CS0A#
CS1A#
CS2A#
CS3A#

ODT0A
ODT1A
ODT2A
ODT3A

CKEA0
CKEA1
CKEA2
CKEA3

DDRVREF0
DDRVREF1

DDRCOMP
DDRCOMN

OCDVREFP
OCDVREFN

S3AUXSW#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D1XAVSS

B15

D4XAVDD

AP11

D4XAVSS

AP10

DDRA_SMA0

AH24

DDRA_SMA1

AP25

DDRA_SMA2

AM25

DDRA_SMA3

AL25

DDRA_SMA4

AP26

DDRA_SMA5

AM26

DDRA_SMA6

AN26

DDRA_SMA7

AK25

DDRA_SMA8

AP27

DDRA_SMA9

AP28

DDRA_SMA10

AK24

DDRA_SBS0

AN24

DDRA_SBS1

AP24

DDRA_SBS2

AM28

DDRA_SMA11

AM27

DDRA_SMA12

AN28

DDRA_SMA13

AP21
AP29

DDRA_SRAS#

AM23

DDRA_SCAS#

AP22

DDRA_SWE#

AJ23

CLK_INT

AK12

CLK_INC

AH12

DDRA_SCS0#

AP23

DDRA_SCS1#

AH22

DDRA_SCS2#

AM22

DDRA_SCS3#

AM21

DDRA_ODT0

AK22

DDRA_ODT1

AP20

DDRA_ODT2

AN22

DDRA_ODT3

AL21

DDRA_CKE0

AN30

DDRA_CKE1

AP30

DDRA_CKE2

AH26

DDRA_CKE3

AK27

DDRVREF

AD18
AD23

DDRCOMP

AJ25

DDRCOMN

AK26

OCDVREFP

AH28

OCDVREFN

AJ29

S3AUXSW#

B6

2006/08/18 2007/8/18

3

DDRA_SBS0 <12,13>
DDRA_SBS1 <12,13>
DDRA_SBS2 <12,13>

DDRA_SRAS# <12,13>
DDRA_SCAS# <12,13>
DDRA_SWE# <12,13>

CLK_INT <15>
CLK_INC <15>

DDRA_SCS0# <12>
DDRA_SCS1# <12>
DDRA_SCS2# <13>
DDRA_SCS3# <13>

DDRA_ODT0 <12>
DDRA_ODT1 <12>
DDRA_ODT2 <13>
DDRA_ODT3 <13>

DDRA_CKE0 <12>
DDRA_CKE1 <12>
DDRA_CKE2 <13>
DDRA_CKE3 <13>

R226 36_0402_1%
R227 36_0402_1%

S3AUXSW# <31>

Compal Secret Data

Deciphered Date

+1.8V

2

D1XAVDD

A15

+1.8VS

1 2

MBK1608121YZF_0603

1

C456
10U_0805_10V4Z

2

R409 0_0402_5%

+1.8VS

1 2

MBK1608121YZF_0603

1

C583
10U_0805_10V4Z

2

R473 0_0402_5%

+1.8V

12

R276

1K_0402_1%

12

R501

1K_0402_1%

+1.8V +1.8V

12

R277

40.2_0402_1%

12

R224
36_0402_1%

L41

1

C480

0.1U_0402_16V4Z

1 2

L52

1 2

OCDVREFP OCDVREFN

Title

Size Document Number Rev

Custom

Date: Sheet of

2

1

C579

0.1U_0402_16V4Z

2

1

C251

0.1U_0402_16V4Z

2

1

C238

2

0.1U_0402_16V4Z

KSWXX M/B LA-4611P Schematic

D1XAVDD:7mA

D1XAVDD

1

C471

0.01U_0402_16V7K

2

D1XAVSS

D4XAVDD:10mA

D4XAVDD

1

C578

0.01U_0402_16V7K

2

D4XAVSSDDRA_SMA14

DDRVREF

1

2

12

R511
36_0402_1%

12

R228

40.2_0402_1%

C233
1U_0603_10V4Z

Place C233
under M672MX
solder side.

Compal Electronics, Inc.

M672MX (2/5)-DDR

847Friday, August 01, 2008

1

0.1

5

4

3

2

1

+1.8VS

L24

1 2

MBK1608121YZF_0603

1

C252
10U_0805_10V4Z

2

D D

C C

B B

A A

1 2

R231 0_0402_5%

+1.8VS

12

R232
150_0402_1%

12

R229

49.9_0402_1%

+1.8VS

1 2

MBK1608121YZF_0603

1

C467
10U_0805_10V4Z

2

1 2

R396 0_0402_5%

+1.8VS

1 2

MBK1608121YZF_0603

1

C491
10U_0805_10V4Z

2

1 2

R415 0_0402_5%

+1.8VS

1

C453

@

10U_0805_10V4Z

2

1 2

R383 0_0402_5%

L65

L45

R395

3.3_0402_5%

1

C250

0.1U_0402_16V4Z

2

1

C67

0.1U_0402_16V4Z

2

1

C249

0.1U_0402_16V4Z

2

1

2

1

2

1

2

5

Z4XAVDD:10mA

1

C248

0.01U_0402_16V7K

2

Z_VREF

VGA_CRT_HSYNC<17>
VGA_CRT_VSYNC<17>

GMCH_CRT_CLK<17>
GMCH_CRT_DATA<17>

DCLKAVDD:5mA

1

C468

0.1U_0402_16V4Z

C469

0.01U_0402_16V7K

2

ECLKAVDD:5mA

C484

0.1U_0402_16V4Z

1 2

C178 0.1U_0402_16V4Z

1 2

C177 0.1U_0402_16V4Z

C461

@

1U_0603_10V4Z

1

C485

0.01U_0402_16V7K

2

1

C463

@

0.1U_0402_16V4Z

2

7/30 modified to @

Z4XAVDD

Z4XAVSS

DCLKAVDD

DCLKAVSS

ECLKAVDD

ECLKAVSS

VCOMP
VVBWN

DACAVDD1

DACAVSS1

VGA_CRT_HSYNC
VGA_CRT_VSYNC

GMCH_CRT_CLK
GMCH_CRT_DATA

+1.8VS

1

2

DACAVDD1:73mA

DACAVDD1 Spec.
Voltage : 1.5V +/- 5%
Current : 100mA

ZAD[0..16]<19>

+3VS

12

R178
390_0402_5%

INT_N_A<7,19>

REF_CLK0<14>

5/20 reserved by Ivan

R177

1 2

0_0402_5%
C174
10U_0805_10V4Z

1 2

R406 0_0402_5%

4

1

2

ZAD[0..16]

R472 56_0402_5%

+1.8VS

12

R179
390_0402_5%

@

1 2

C166 0.1U_0402_16V4Z

1 2

C167 0.1U_0402_16V4Z

@

R230 56_0402_5%

DACAVDD2:73mA

1

C490
1U_0603_10V4Z

1 2

R174 130_0402_5%

C483

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Z_CLK0<14>

ZDREQ<19>
ZUREQ<19>

ZSTB_DP0<19>
ZSTB_DN0<19>
ZSTB_DP1<19>
ZSTB_DN1<19>

1 2
1 2

VGA_CRT_R<17>
VGA_CRT_G<17>
VGA_CRT_B<17>

R184 0_0402_5%

1 2

R185 0_0402_5%

1 2

R183 0_0402_5%

1 2

R182 0_0402_5%

1 2

R196 0_0402_5%

1 2

R195 0_0402_5%

1 2

VCOMP
VVBWN

DACAVDD2

DACAVSS2

VRSET

3

Z_CLK0
ZDREQ

ZUREQ
ZSTB_DP0

ZSTB_DN0
ZSTB_DP1
ZSTB_DN1

ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16

Z_VREF
Z_COMP_P
Z_COMP_N

Z4XAVDD
Z4XAVSS

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

A_HSYNC
A_VSYNC

A_DDC1CLK
A_DDC1DAT

VCOMP
VVBWN
VRSET

INTA#
VOSCI
DACAVDD1

DACAVSS1
DACAVDD2

DACAVSS2
DCLKAVDD

DCLKAVSS

ECLKAVDD
ECLKAVSS

2006/08/18 2007/8/18

Compal Secret Data

U30A

AH10

ZCLK

AP8

ZDREQ

AN8

ZUREQ

AM7

ZSTB0

AL7

ZSTB0#

AP4

ZSTB1

AP5

ZSTB1#

AK10

ZAD0

AM6

ZAD1

AK11

ZAD2

AJ11

ZAD3

AP7

ZAD4

AJ9

ZAD5

AP6

ZAD6

AN6

ZAD7

AK9

ZAD8

AM4

ZAD9

AK6

ZAD10

AK8

ZAD11

AN4

ZAD12

AK7

ZAD13

AL5

ZAD14

AM5

ZAD15

AM8

ZAD16

AL9

ZVREF

AP9

ZCMP_P

AM9

ZCMP_N

AM10

Z4XAVDD

AN10

Z4XAVSS

D13

ROUT

C12

GOUT

C13

BOUT

F12

HSYNC

G12

VSYNC

D11

VGPIO0

E12

VGPIO1

D15

VCOMP

C15

VVBWN

C14

VRSET

F13

INTA#

F11

VOSCI

A12

DACAVDD1

B12

DACAVSS1

A13

DACAVDD2

B13

DACAVSS2

B10

DCLKAVDD

A11

DCLKAVSS

A9

ECLKAVDD

B8

ECLKAVSS

SISM672MX-A1_TEBGA_847P

MX@

Deciphered Date

ASL

ENTEST

TESTMODE0
TESTMODE1
TESTMODE2

TRAP0
TRAP1
TRAP2

TRAP3
TRAP4
TRAP5
TRAP6
TRAP7
TRAP8
TRAP9

TRAP10

AUXOK

PWROK

PCIRST#

AGPSTOP#
AGPBUSY#

VBVSYNC

VBHSYNC

VBHCLK

VBCLK

VBCAD

VACLK

NC0
NC1

2

F15
D16

E16
F16
D17
E17
F17

AC32
AD34
AB28
AD32
AD33
AE34
AC30
AC29

A5
C6
A7

G14
A6

D8
F7

E7
C8

E9
D9

NB_ENTEST

AUX_PWRGD
SB_PWRGD
NB_RST#

AGPSTOP#
AGPBUSY#

VBVSYNC
VBHSYNC

VBHCLK
VBCLK

VBCAD

R193 4.7K_0402_5%

1 2

AUX_PWRGD <20,31>
SB_PWRGD <20,31>
NB_RST# <18,19>

AGPSTOP# <20>
AGPBUSY# <20>

VBVSYNC <18>
VBHSYNC <18>

VBHCLK <18>
VBCLK <18>

R559 33_0402_5%

VBCAD <18>

1 2

For SiS VB 307 use only

AH2
AG3

AGPBUSY#
AUX_PWRGD
SB_PWRGD

R258 4.7K_0402_5%

1 2

C180 0.1U_0402_16V4Z
C181 0.1U_0402_16V4Z

Title

Size Document Number Rev

Custom

KSWXX M/B LA-4611P Schematic

Date: Sheet of

VACLKH_VACLK

1 2
1 2

VACLK <18>

+3VS

Compal Electronics, Inc.

M672MX (3/5)-ASL

1

0.1

947Friday, August 01, 2008

5

U30E

4

3

2

1

+1.8V

D D

+1.8VS

C C

+1.8VS

B B

A A

+1.8VS

+1.2VS

+1.2VALW

+1.8VALW

5

W23

VCCM

Y23

VCCM

AA23

VCCM

AB23

VCCM

AC23

VCCM

AC18

VCCM

AC20

VCCM

AC16

VCCM

AD16

VCCM

AD17

VCCM

AD19

VCCM

AD20

VCCM

AD21

VCCM

AD22

VCCM

AJ22

VCCM

AJ24

VCCM

AL23

VCCM

AL26

VCCM

AN21

VCCM

AN23

VCCM

AN25

VCCM

AN27

VCCM

AN29

VCCM

AP3

VCC1.8

AB12

VCC1.8

AB13

VCC1.8

AC12

VCC1.8

AC13

VCC1.8

AC14

VCC1.8

AC15

VCC1.8

AH6

VCC1.8

AH7

VCC1.8

AJ4

VCC1.8

AJ5

VCC1.8

AJ6

VCC1.8

AJ7

VCC1.8

AN2

VCC1.8

AK4

VCC1.8

AK5

VCC1.8

AL1

VCC1.8

AL2

VCC1.8

AL3

VCC1.8

AL4

VCC1.8

AM1

VCC1.8

AM2

VCC1.8

AM3

VCC1.8

AN3

VCC1.8

AN5

VCC1.8

AN7

VCC1.8

AN9

VCC1.8

E8

VDDVB1.8

F9

VDDVB1.8

F8

VDDVB1.8

E10

VDD1.8

F10

VDD1.8

N19

PVDDH

N21

PVDDH

P20

PVDDH

P22

PVDDH

R21

PVDDH

T22

PVDDH

U21

PVDDH

V22

PVDDH

M11

VDDPEX

N11

VDDPEX

P11

VDDPEX

R11

VDDPEX

T11

VDDPEX

U11

VDDPEX

V11

VDDPEX

W11

VDDPEX

Y11

VDDPEX

AA11

VDDPEX

AB11

VDDPEX

B5

AUX_IVDD

C5

AUX_IVDD

D6

AUX_IVDD

G8

AUX1.8

SISM672MX-A1_TEBGA_847P

MX@

M13

IVDD

M14

IVDD

M15

IVDD

M16

IVDD

M17

IVDD

M18

IVDD

M19

IVDD

N16

IVDD

N17

IVDD

N18

IVDD

N20

IVDD

R22

IVDD

N22

IVDD

N13

IVDD

P13

IVDD

Y13

IVDD

Y22

IVDD

T13

IVDD

U13

IVDD

U22

IVDD

V13

IVDD

W13

IVDD

PWR

IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD

VTTP
VTTP
VTTP
VTTP
VTTP
VTTP
VTTP
VTTP
VTTP
VTTP

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

W22
AA13
AA22
AB14
AB15
AB16
AB18
AB20
AB22
AF6
AF7
AK3
AG4
AG5
AG6
AG7
R13
AH3
AH4
AH5
AJ1
AJ2
AJ3
AK1
AK2
AC22
AC21
AC19
AC17

A19
A20
B19
B20
C19
C20
D19
D20
E19
E20
F19
F20
G19
G20
L18
L19
L20
M20
M21
M22
M23
N23
P23
R23
T23
U23
V23
M12
N12
P12
R12
T12
U12
V12
W12
Y12
AA12

4

+1.2VS

+1.05VS

+1.8VS

+1.8V +1.2VS +1.8VALW +1.2VALW

C244 1U_0603_10V4Z

C245 1U_0603_10V4Z

C246 10U_0805_10V4Z

PVDDH/VCC1.8/VTTP/VDD1.8

+1.8VS +1.2VS

/VDDVB1.8:392mA

C232 0.1U_0402_16V4Z

C239 1U_0603_10V4Z

C247 10U_0805_10V4Z

1 2

1 2

1 2

1 2

1 2

1 2

VCCM:644mA

IVDD:2024mA

C225 1U_0603_10V4Z

1 2

C227 1U_0603_10V4Z

1 2

C243 10U_0805_10V4Z

1 2

VDDPEX:876mA

C202 0.1U_0402_16V4Z

1 2

C195 1U_0603_10V4Z

1 2

C229 10U_0805_10V4Z

1 2

Place these Cap under M672MX solder side.

+1.8V +1.2VS

C230 0.1U_0402_16V4Z

1 2

C231 0.1U_0402_16V4Z

1 2

C235 1U_0603_10V4Z

1 2

C223 1U_0603_10V4Z

1 2

C237 4.7U_0805_10V4Z

1 2

C236 4.7U_0805_10V4Z

1 2

+1.8VS +1.2VS +1.05VS

C198 0.1U_0402_16V4Z

1 2

C221 1U_0603_10V4Z

1 2

C193 1U_0603_10V4Z

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

C226 0.1U_0402_16V4Z

1 2

C209 0.1U_0402_16V4Z

1 2

C213 1U_0603_10V4Z

1 2

C220 1U_0603_10V4Z

1 2

C196 4.7U_0805_10V4Z

1 2

C242 4.7U_0805_10V4Z

1 2

C197 0.1U_0402_16V4Z

1 2

C240 1U_0603_10V4Z

1 2

C234 1U_0603_10V4Z

1 2

2

AUX1.8:1mA AUX_IVDD:92mA

1

C187
1U_0603_10V4Z

2

+1.05VS

C204 0.1U_0402_16V4Z

1 2

C192 1U_0603_10V4Z

1 2

C176 10U_0805_10V4Z

1 2

+1.8VALW +1.2VALW

1

C190
1U_0603_10V4Z

2

C188 0.1U_0402_16V4Z

1 2

C179 1U_0603_10V4Z

1 2

C184 1U_0603_10V4Z

1 2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

M672MX (4/5)-POWER

KSWXX M/B LA-4611P Schematic

1

C183
1U_0603_10V4Z

2

VTT:80mA

1

C182
1U_0603_10V4Z

2

10 47Friday, August 01, 2008

1

of

0.1

5

D D

B21
B23
B25
B27
B29
B31

C10
C11
C16
C18

G10

C32
C33

D10
D12
D21
D23
D25
D27
D29

E11
E13
E14
E18
E29
E30
E33

F14
F22
F24
F26
F28

P21
T21
V21

C C

B B

4

AA16

AA17

AA18

AA19

AA20

AA21

AA31

AA33

AB3

AB4

AB5

AB7

AB29

AC2

AC3

AC31

AC33

AD2

AD3

AD4

AD5

AD7

AD29

AE3

AE31

AE33

AF2

VSS

VSS

VSS

VSSM2VSSM3VSS

M29

AF3

VSS

VSS

VSS

GND

VSSN3VSSN4VSSN5VSSN6VSSN7VSS

U30F

A3

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

B2

VSS

B3

VSS

B4

VSS
VSS

VSS
VSS
VSS
VSS
VSS

C1

VSS

C2

VSS

C3

VSS

C4

VSS

C9

VSS
VSS
VSS
VSS
VSS
VSS
VSS

D1

VSS

D2

VSS

D3

VSS

D4

VSS

D5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E1

VSS

E2

VSS

E3

VSS

E6

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

F2

VSS

F3

VSS

F4

VSS

F5

VSS

F6

VSS
VSS
VSS
VSS
VSS
VSS

G2

VSS

G3

VSS

G7

VSS
VSS
VSS
VSS
VSS

VSSH5VSS

VSSJ2VSSJ3VSSJ7VSS

VSS

VSSK3VSSK4VSSK5VSS

VSSL2VSSL3VSSL4VSSL5VSSL7VSS

J33

K29

G31

VSS

G33

VSS

VSS

H4

H29

J31

VSS

VSS

L31

L33

VSS

AF4

VSS

AF5

N14

VSS

AF29

N15

VSS

VSS

AG2

N31

VSS

VSS

AG31

VSS

VSS

N33

3

AG33

AH1

VSS

VSS

VSSP2VSSP3VSS

2

AH29

AJ8

AJ10

AJ12

AJ14

AJ16

AJ18

AJ20

AJ26

AJ28

AJ33

AK31

AL6

AL8

AL10

AL12

AL14

AL16

AL18

AL20

AL28

AL30

AL33

AN11

AN13

AN15

AN17

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

T29

VSS

U2

VSS

U3

VSS

U4

VSS

U5

VSS

U6

VSS

U14

VSS

U15

VSS

U16

VSS

U17

VSS

U18

VSS

U19

VSS

U20

VSS

U31

VSS

U33

VSS

V2

VSS

V3

VSS

V4

VSS

V5

VSS

V14

VSS

V15

VSS

V16

VSS

V17

VSS

V18

VSS

V19

VSS

V20

VSS

V29

VSS

AN33

VSS

AN31

VSS

AN19

VSS

W3

VSS

W14

VSS

W15

VSS

W16

VSS

W17

VSS

W18

VSS

W19

VSS

W20

VSS

W21

VSS

W31

VSS

W33

VSS

Y2

VSS

Y3

VSS

Y4

VSS

Y5

VSS

Y7

VSS

Y14

VSS

Y15

VSS

Y16

VSS

Y17

VSS

Y18

VSS

Y19

VSS

Y20

VSS

Y21

VSS

Y29

VSS

AA2

VSS

AA3

VSS

AA14

VSS

AA15

VSS

AB17

VSS

AB19

VSS

AB21

VSS

P19

VSS

VSS

VSS

VSS

VSS

VSS

VSSR2VSSR3VSSR4VSSR5VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSST3VSST6VSS

VSS

VSS

VSS

VSS

VSS

VSS

T14

P14

P15

P16

P17

P18

P29

R14

R15

R16

R17

R18

R19

R20

R31

R33

T15

SISM672MX-A1_TEBGA_847P

T16

T17

T18

T19

T20

1

MX@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

M672MX (5/5)-GND

KSWXX M/B LA-4611P Schematic

11 47Friday, August 01, 2008

1

0.1

of

5

+1.8V +1.8V

JDIMM1

+DIMM_VREF

DDRA_SDQ0
DDRA_SDQ1

DDRA_SDQS0#<8,13>
DDRA_SDQS0<8,13>

D D

DDRA_SDQS1#<8,13>
DDRA_SDQS1<8,13>

DDRA_SDQS2#<8,13>
DDRA_SDQS2<8,13>

EC_TX_P80_DATA<13,31>

C C

EC_RX_P80_CLK<13,31>

B B

EC_RX_P80_CLK

A A

DDRA_CKE0<8>

DDRA_SBS2<8,13>

DDRA_SBS0<8,13>
DDRA_SWE#<8,13>

DDRA_SCAS#<8,13>
DDRA_SCS1#<8>

DDRA_ODT1<8>

DDRA_SDQS4#<8,13>
DDRA_SDQS4<8,13>

R237 0_0402_5%

1 2

EC_RX_P80_CLK_R<13>

DDRA_SDQS6#<8,13>
DDRA_SDQS6<8,13>

SDATA<13,14,15,20>
SCLK<13,14,15,20>

+3VS

C786

2.2U_0603_6.3V6K

5

DDRA_SDQS0#
DDRA_SDQS0

DDRA_SDQ2
DDRA_SDQ3

DDRA_SDQ8
DDRA_SDQ9

DDRA_SDQS1#
DDRA_SDQS1

DDRA_SDQ10
DDRA_SDQ11

DDRA_SDQ16
DDRA_SDQ17

DDRA_SDQS2#
DDRA_SDQS2

DDRA_SDQ18
DDRA_SDQ19

DDRA_SDQ24
DDRA_SDQ25

DDRA_SDM3
EC_TX_P80_DATA

DDRA_SDQ26
DDRA_SDQ27

DDRA_CKE0
EC_RX_P80_CLK

DDRA_SBS2
DDRA_SMA12

DDRA_SMA9
DDRA_SMA8

DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

DDRA_SMA10
DDRA_SBS0
DDRA_SWE#

DDRA_SCAS#
DDRA_SCS1#

DDRA_ODT1
DDRA_SDQ32

DDRA_SDQ33
DDRA_SDQS4#

DDRA_SDQS4
DDRA_SDQ34

DDRA_SDQ35
DDRA_SDQ40

DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42

DDRA_SDQ43
DDRA_SDQ48

DDRA_SDQ49

EC_RX_P80_CLK_R

EC_RX_P80_CLK_R

DDRA_SDQS6#
DDRA_SDQS6

DDRA_SDQ50
DDRA_SDQ51

DDRA_SDQ56
DDRA_SDQ57

DDRA_SDM7
DDRA_SDQ58

DDRA_SDQ59
SDATA

SCLK

+3VS

1

C787

0.1U_0402_16V4Z

2

DIMM0 STD H:5.2mm (BOT)

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_ASOA426-M2RN-7F

CONN@

VSS
DQ4
DQ5
VSS

DM0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106

BA1

108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198

SA0

200

SA1

DDRA_SDQ4
DDRA_SDQ5

DDRA_SDM0
DDRA_SDQ6

DDRA_SDQ7
DDRA_SDQ12

DDRA_SDQ13
DDRA_SDM1
DDR_CLK0

DDR_CLK0#
DDRA_SDQ14

DDRA_SDQ15

DDRA_SDQ20
DDRA_SDQ21

DDRA_SDM2
DDRA_SDQ22

DDRA_SDQ23
DDRA_SDQ28

DDRA_SDQ29
DDRA_SDQS3#

DDRA_SDQS3
DDRA_SDQ30

DDRA_SDQ31
DDRA_CKE1

DDRA_SMA14
DDRA_SMA11

DDRA_SMA7
DDRA_SMA6

DDRA_SMA4
DDRA_SMA2
DDRA_SMA0

DDRA_SBS1
DDRA_SRAS#
DDRA_SCS0#

DDRA_ODT0
DDRA_SMA13

DDRA_SDQ36
DDRA_SDQ37

DDRA_SDM4
DDRA_SDQ38

DDRA_SDQ39
DDRA_SDQ44

DDRA_SDQ45
DDRA_SDQS5#

DDRA_SDQS5
DDRA_SDQ46

DDRA_SDQ47
DDRA_SDQ52

DDRA_SDQ53
DDR_CLK1

DDR_CLK1#
DDRA_SDM6
DDRA_SDQ54

DDRA_SDQ55
DDRA_SDQ60

DDRA_SDQ61
DDRA_SDQS7#

DDRA_SDQS7
DDRA_SDQ62

DDRA_SDQ63

R238 10K_0402_5%

1 2

R239 10K_0402_5%

1 2

DDR_CLK0 <15>
DDR_CLK0# <15>

DDRA_SDQS3# <8,13>
DDRA_SDQS3 <8,13>

DDRA_CKE1 <8>

Swap RP6 Pin2 & RP7 Pin 1

DDRA_SBS1 <8,13>
DDRA_SRAS# <8,13>
DDRA_SCS0# <8>

DDRA_ODT0 <8>

DDRA_SDQS5# <8,13>
DDRA_SDQS5 <8,13>

DDR_CLK1 <15>
DDR_CLK1# <15>

DDRA_SDQS7# <8,13>
DDRA_SDQS7 <8,13>

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+DIMM_VREF

20mils

1

C771

0.1U_0402_16V4Z

2

DDRA_SMA[0..14]<8,13>

DDRA_SDQ[0..63]<8,13>

DDRA_SDM[0..7]<8,13>

Swap RP11,RP12 Pin 1 & 2

DDRA_SBS2
DDRA_CKE0

DDRA_SMA9
DDRA_SMA12

DDRA_SMA8
DDRA_SMA5

DDRA_SMA3
DDRA_SMA1

DDRA_SMA10
DDRA_SBS0

DDRA_SWE#
DDRA_SCAS#

DDRA_SCS1#
DDRA_ODT1

DDRA_SMA11
DDRA_SMA14

DDRA_SMA6
DDRA_SMA7

DDRA_SMA2
DDRA_SMA4

DDRA_SBS1
DDRA_SMA0

DDRA_SCS0#
DDRA_SRAS#

DDRA_SMA13
DDRA_ODT0

DDRA_CKE1

2006/08/18 2007/8/18

3

C277

2.2U_0603_6.3V6K

DDRA_SMA[0..14]
DDRA_SDQ[0..63]
DDRA_SDM[0..7]

1 4
2 3

RP11 56_0404_4P2R_5%

1 4
2 3

RP12 56_0404_4P2R_5%

1 4
2 3

RP6 56_0404_4P2R_5%

1 4
2 3

RP7 56_0404_4P2R_5%

1 4
2 3

RP8 56_0404_4P2R_5%

1 4
2 3

RP9 56_0404_4P2R_5%

1 4
2 3

RP10 56_0404_4P2R_5%

1 4
2 3

RP13 56_0404_4P2R_5%

1 4
2 3

RP14 56_0404_4P2R_5%

1 4
2 3

RP15 56_0404_4P2R_5%

1 4
2 3

RP16 56_0404_4P2R_5%

1 4
2 3

RP17 56_0404_4P2R_5%

1 4
2 3

RP18 56_0404_4P2R_5%

1 2

R241 56_0402_5%

Layout Note:
Place these resistor
closely JP35,all
trace length Max=1.5"

Compal Secret Data

Deciphered Date

R236

1K_0402_1%

R235

1K_0402_1%

+0.9VS

2

+1.8V

12

0.1U_0402_16V4Z

12

0.1U_0402_16V4Z

2

1

New Add For SiS New Add For SiS

1

C770

2

1

C772

2

+1.8V

C296

2.2U_0603_6.3V6K

+1.8V

1

C778

0.1U_0402_16V4Z

2

+0.9VS

1

C780

0.1U_0402_16V4Z

2

+0.9VS

1

C784

0.1U_0402_16V4Z

2

+0.9VS

1

C306

0.1U_0402_16V4Z

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+DIMM_VREF

1

C773
220P_0402_50V7K

2

@

C774

2.2U_0603_6.3V6K

1

C297

0.1U_0402_16V4Z

2

1

C781

0.1U_0402_16V4Z

2

1

C785

0.1U_0402_16V4Z

2

1

C305

0.1U_0402_16V4Z

2

Title

Size Document Number Rev

Date: Sheet

+1.8V

1

+

C303

@

330U_D2E_2.5VM

2

Layout Note:
Place near JP35

1

C779

0.1U_0402_16V4Z

2

1

C782

0.1U_0402_16V4Z

2

1

C299

0.1U_0402_16V4Z

2

1

C298

0.1U_0402_16V4Z

2

C776

2.2U_0603_6.3V6K

1

C295

0.1U_0402_16V4Z

2

1

C744

0.1U_0402_16V4Z

2

1

C308

0.1U_0402_16V4Z

2

C775

2.2U_0603_6.3V6K

Compal Electronics, Inc.

DDRII-SODIMM0

B

KSWXX M/B LA-4611P Schematic

1

1

+

C304

@

330U_D2E_2.5VM

2

C777

2.2U_0603_6.3V6K

1

C783

0.1U_0402_16V4Z

2

1

C307

0.1U_0402_16V4Z

2

of

12 47Friday, August 01, 2008

0.1

A

+1.8V +1.8V

JDIMM2

+DIMM_VREF

DDRA_SDQ0
DDRA_SDQ1

DDRA_SDQS0#<8,12>
DDRA_SDQS0<8,12>

1 1

DDRA_SDQS1#<8,12>
DDRA_SDQS1<8,12>

DDRA_SDQS2#<8,12>
DDRA_SDQS2<8,12>

EC_TX_P80_DATA<12,31>

2 2

3 3

4 4

EC_RX_P80_CLK<12,31>

DDRA_CKE2<8>

DDRA_SBS2<8,12>

DDRA_SBS0<8,12>
DDRA_SWE#<8,12>

DDRA_SCAS#<8,12>
DDRA_SCS3#<8>

DDRA_ODT3<8>

DDRA_SDQS4#<8,12>
DDRA_SDQS4<8,12>

EC_RX_P80_CLK_R<12>

DDRA_SDQS6#<8,12>
DDRA_SDQS6<8,12>

SDATA<12,14,15,20>
SCLK<12,14,15,20>

C259

2.2U_0603_6.3V6K

A

+3VS

DDRA_SDQS0#
DDRA_SDQS0

DDRA_SDQ2
DDRA_SDQ3

DDRA_SDQ8
DDRA_SDQ9

DDRA_SDQS1#
DDRA_SDQS1

DDRA_SDQ10
DDRA_SDQ11

DDRA_SDQ16
DDRA_SDQ17

DDRA_SDQS2#
DDRA_SDQS2

DDRA_SDQ18
DDRA_SDQ19

DDRA_SDQ24

DDRA_SDM3
EC_TX_P80_DATA

DDRA_SDQ26
DDRA_SDQ27

DDRA_CKE2
EC_RX_P80_CLK

DDRA_SBS2
DDRA_SMA12

DDRA_SMA9
DDRA_SMA8

DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

DDRA_SMA10
DDRA_SBS0
DDRA_SWE#

DDRA_SCAS#
DDRA_SCS3#

DDRA_ODT3
DDRA_SDQ32

DDRA_SDQ33
DDRA_SDQS4#

DDRA_SDQS4
DDRA_SDQ34

DDRA_SDQ35
DDRA_SDQ40

DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42

DDRA_SDQ43
DDRA_SDQ48

DDRA_SDQ49

EC_RX_P80_CLK_R

DDRA_SDQS6#
DDRA_SDQS6

DDRA_SDQ50
DDRA_SDQ51

DDRA_SDQ56
DDRA_SDQ57

DDRA_SDM7
DDRA_SDQ58

DDRA_SDQ59
SDATA

SCLK

+3VS

1

C260

0.1U_0402_16V4Z

2

DIMM1 STD H:9.2mm (BOT)

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692B-A0G16-P

CONN@

DQ12
DQ13

CK0#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS
DM2

VSS

VSS

VSS

VSS

VSS
VDD

VDD

VDD

VDD
BA1

VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO
SA1

B

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDRA_SDQ4
DDRA_SDQ5

DDRA_SDM0
DDRA_SDQ6

DDRA_SDQ7
DDRA_SDQ12

DDRA_SDQ13
DDRA_SDM1
DDR_CLK2

DDR_CLK2#
DDRA_SDQ14

DDRA_SDQ15

DDRA_SDQ20
DDRA_SDQ21

DDRA_SDM2
DDRA_SDQ22

DDRA_SDQ23
DDRA_SDQ28

DDRA_SDQ29DDRA_SDQ25
DDRA_SDQS3#

DDRA_SDQS3
DDRA_SDQ30

DDRA_SDQ31
DDRA_CKE3

DDRA_SMA14
DDRA_SMA11

DDRA_SMA7
DDRA_SMA6

DDRA_SMA4
DDRA_SMA2
DDRA_SMA0

DDRA_SBS1
DDRA_SRAS#
DDRA_SCS2#

DDRA_ODT2
DDRA_SMA13

DDRA_SDQ36
DDRA_SDQ37

DDRA_SDM4
DDRA_SDQ38

DDRA_SDQ39
DDRA_SDQ44

DDRA_SDQ45
DDRA_SDQS5#

DDRA_SDQS5
DDRA_SDQ46

DDRA_SDQ47
DDRA_SDQ52

DDRA_SDQ53
DDR_CLK3

DDR_CLK3#
DDRA_SDM6
DDRA_SDQ54

DDRA_SDQ55
DDRA_SDQ60

DDRA_SDQ61
DDRA_SDQS7#

DDRA_SDQS7
DDRA_SDQ62

DDRA_SDQ63

R233 10K_0402_5%

1 2

R234 10K_0402_5%

1 2

DDRA_CLK2 <15>
DDRA_CLK2# <15>

DDRA_SDQS3# <8,12>
DDRA_SDQS3 <8,12>

DDRA_CKE3 <8>

DDRA_SBS1 <8,12>
DDRA_SRAS# <8,12>
DDRA_SCS2# <8>

DDRA_ODT2 <8>

DDRA_SDQS5# <8,12>
DDRA_SDQS5 <8,12>

DDRA_CLK3 <15>
DDRA_CLK3# <15>

DDRA_SDQS7# <8,12>
DDRA_SDQS7 <8,12>

+3VS

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+DIMM_VREF

20mils

1

C258

0.1U_0402_16V4Z

2

DDRA_SCS3#
DDRA_ODT3

DDRA_CKE3
DDRA_CKE2

DDRA_SCS2#
DDRA_ODT2

2006/08/18 2007/8/18

C

C255

2.2U_0603_6.3V6K

DDRA_SMA[0..14]<8,12>
DDRA_SDQ[0..63]<8,12>
DDRA_SDM[0..7]<8,12>

1 4
2 3

RP3 56_0404_4P2R_5%

1 4
2 3

RP5 56_0404_4P2R_5%

1 4
2 3

RP4 56_0404_4P2R_5%

Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.5"

Compal Secret Data

DDRA_SMA[0..14]
DDRA_SDQ[0..63]
DDRA_SDM[0..7]

Deciphered Date

D

+0.9VS

4.7U_0805_10V4Z

D

+1.8V

C253

2.2U_0603_6.3V6K

+1.8V

+0.9VS

C262

C256

2.2U_0603_6.3V6K

1

C266

0.1U_0402_16V4Z

2

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

1

C267

0.1U_0402_16V4Z

2

1

C261

4.7U_0805_10V4Z

2

Title

Size Document Number Rev

B

Date: Sheet

E

Layout Note:
Place near JP34

1

C265

0.1U_0402_16V4Z

2

C264

2.2U_0603_6.3V6K

1

C257

0.1U_0402_16V4Z

2

C263

2.2U_0603_6.3V6K

C254

2.2U_0603_6.3V6K

Compal Electronics, Inc.

DDRII-SODIMM1

JSWXX M/B LA-4611P Schematic

13 47Friday, August 01, 2008

E

0.1

of

5

+3VS

L3

1 2

KC FBM-L11-201209-221LMAT_0805

10U_0805_10V4Z

D D

+3VS

RP39

10K_1206_8P4R_5%

Remove R43 R66 R529 R527 and use PR39
Michael 2008/5/30

+3VS

R80 2.7K_0402_5%@
R55 2.7K_0402_5%@
R78 2.7K_0402_5%@

C C

R54 2.7K_0402_5%@
R76 2.7K_0402_5%@
R53 2.7K_0402_5%@
R52 2.7K_0402_5%
R74 2.7K_0402_5%@
R73 2.7K_0402_5%@
R56 2.7K_0402_5%

C100

45
36
27
18

1

10U_0805_10V4Z

2

MODE

CLK_RESET#

STOP#

48M

C664

1

C69

0.1U_0402_16V4Z

2

1

2

SB

EC

C70

0.1U_0402_16V4Z

1

2

FSL0

FSL1

FSL2

FSL3

FSL4

1

1

C71

0.1U_0402_16V4Z

2

2

10U_0805_10V4Z

Reference schematic use 1206

CLK_14M_SIO<33>
REF_CLK0<9>
REF_CLK1<20>
VBRCLK<18>

CLK_PCI_SB<19>

CLK_PCI_EC<31>

DB

EXP_CLKREQ#<30>

R39 4.7K_0402_5%

CPU_BSEL0<5>
CPU_BSEL1<5>
CPU_BSEL2<5>

B B

A A

C82 18P_0402_50V8J

C86 18P_0402_50V8J

DDATA<29,30>

DCLK<29,30>

1 2

R40 4.7K_0402_5%

1 2

R38 4.7K_0402_5%

1 2

XTAL_IN

12

Y1

14.31818MHZ_16PF_DSX840GA

XTAL_OUT

R352

2.2K_0402_5%

DDATA

+3VS

DCLK

5

FSL0
FSL1
FSL2

R355

2.2K_0402_5%

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

WLAN_CLKREQ#<29>

CLK_PCI_DB<33>
CLK_EN#<46>

VGATE<46>
CPUSTP#<25>

SDATA<12,13,15,20>

SCLK<12,13,15,20>

R344

1K_0402_5%

Q3A

6 1

2
5

3

4

Q3B

Replace Package from SOT23 to SOT363-6
Michael 2008/5/30

1

C98

C72

0.1U_0402_16V4Z

2

+3VS

1

C420

@

2

+3VS+3VALW

4

12

R32

@

10K_0402_5%

1

C79

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C99

0.1U_0402_16V4Z

2

CLKGEN_VDD

1

C405

0.1U_0402_16V4Z

2

Use SB03904008L & SB000006A00 FootPrint

L30

1 2

0.1U_0402_16V4Z

CLK_14M_SIO
REF_CLK0
REF_CLK1
VBRCLK

CLK_PCI_SB

CLK_PCI_DB PCICLK7

CLK_EN#

VTTPWRGD

SDATA
SCLK

R343
1K_0402_5%

SDATA

SCLK

4

KC FBM-L11-201209-221LMAT_0805

1

C403

1

C404

2

R35 22_0402_5%@
R79 33_0402_5%
R77 22_0402_5%
R818 22_0402_5%

R75 33_0402_5%

R72 33_0402_5%

R50 33_0402_5%
R71 33_0402_5%
R51 33_0402_5%@
R62 0_0402_5%@

R81 0_0402_5%@
R82 0_0402_5%

R67 0_0402_5%

R338 0_0402_5%
R337 0_0402_5%

10U_0805_10V4Z

2

1 2
1 2
1 2
1 2

1 2

1 2

1 2
1 2
1 2
1 2

1 2
1 2

1 2

1 2
1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS +3VS+CPU_CORE

2

B

E

VDDA

XTAL_IN
XTAL_OUT

FSL0
FSL1

FSL2
FSL3
FSL4CLK_PCI_EC
STOP#
MODE
CLKREQ0#EXP_CLKREQ#
CLKREQ1#WLAN_CLKREQ#

CK_PWRGDVGATE
CLK_RESET#CPUSTP#

SMDATA
SMCLK

3

12

R58

@

10K_0402_5%

C

Q10
MMBT3904_SOT23

@

3 1

CLKGEN_VDD

U4

50

VDDA

47

GNDA

5

X1

6

X2

3

*FSL0/REF0_2x

4

**FSL1/REF1_2x

9

**FSL2/PCICLK0_2x

10

**FS3/PCICLK1_2x

11

**FS4/PCICLK2

12

*(PCI_STOP#)/PCICLK3

15

**MODE/PCICLK4

16

(PECLKREQ0#)/PCICLK5

17

(PECLKREQ1#)/PCICLK6

18

PCICLK7

1

VTTPWRGD/PD#/(CLK_STOP#)

28

*(CPU_STOP#)/RESET#

45

SDATA

46

SCLK

2005/03/01

3

12

R57

@

10K_0402_5%

C

Q9

2

B

MMBT3904_SOT23

E

@

3 1

23

14

19

2

VDDREF

VDDPCI_0

VDDPCI_1

ICS9LPR600

GNDREF7GNDPCI_0

8

13

Compal Secret Data

VTTPWRGD

56

24

39

29

VDDZ

VDD48

VDDCPU

VDDPCIEX_0

VDDPCIEX_1

**SEL24_48#/24_48MHz

GNDPCI_1

GNDZ

GND48

GNDCPU

GNDPCIEX_0

20

27

53

42

Deciphered Date

0

0

55

CPUT_L0

54

CPUC_L0

52

CPUT_L1

51

CPUC_L1

44

PCIET_L0

43

PCIEC_L0

41

PCIET_L1

40

PCIEC_L1

38

PCIET_L2

37

PCIEC_L2

36

PCIET_L3

35

PCIEC_L3

34

PCIET_L4F

33

PCIEC_L4F

31

PCIET_L5F

30

PCIEC_L5F

ZCLK0
ZCLK1

12MHz

48
49

21
22

26

25

SATACLKC_L
SATACLKT_L

GNDPCIEX_1

ICS9LPR600BGLF-T_TSSOP56

32

2

CPU

FSL21FSL1FSL3FSL4 ZCLK

FSL0

MHz

1

1

1

0

1

0 1 0 200 100 33.30 1 133

CPUT_L0
CPUC_L0
CPUT_L1
CPUC_L1

PCIET_L0
PCIEC_L0

PCIET_L2
PCIEC_L2

PCIET_L3
PCIEC_L3

PCIET_L4F
PCIEC_L4F

PCIET_L5F
PCIEC_L5F

SATACLKC_L
SATACLKT_L

ZCLK0
ZCLK1

48M CLK_48M_CR

12M USB_CLK_12M

R95 33_0402_5%

1 2

R102 33_0402_5%

1 2

R94 33_0402_5%

1 2

R101 33_0402_5%

1 2

R91 33_0402_5%

1 2

R90 33_0402_5%

1 2

R89 33_0402_5%

1 2

R88 33_0402_5%

1 2

R106 33_0402_5%

1 2

R105 33_0402_5%

1 2

R87 33_0402_5%

1 2

R86 33_0402_5%

1 2

R104 33_0402_5%

1 2

R103 33_0402_5%

1 2

R92 33_0402_5%

1 2

R93 33_0402_5%

1 2

R49 22_0402_5%

1 2

R70 22_0402_5%

1 2

R65 33_0402_5%

1 2

R68 33_0402_5%

1 2

Pin 26 need BIOS to set disable,

for saving power & good EMI

2006/03/01

2

Title

Size Document Number Rev

Custom
Date: Sheet

133

166

H_CLK_DP0
H_CLK_DN0
H_CLK_DP1
H_CLK_DN1

PCIE_CLK_NB
PCIE_CLK_NB#

PCIE_CLK_SB
PCIE_CLK_SB#

PCIE_CLK_307
PCIE_CLK_307#

PCIE_CLK_EXP
PCIE_CLK_EXP#

PCIE_CLK_WLAN
PCIE_CLK_WLAN#

SATA_CLK_DN
SATA_CLK_DP

Z_CLK0
Z_CLK1

Z_CLK0
Z_CLK1
CLK_PCI_SB

CLK_PCI_EC
CLK_PCI_DB
REF_CLK0
REF_CLK1

Clock Generator ICS9LPR600C

KSWXX M/B LA-4611P Schematic

Friday, August 01, 2008

1

PCI

PCIE

MHz

MHz

1000

33.30

100

33.3

H_CLK_DP0 <4>
H_CLK_DN0 <4>
H_CLK_DP1 <7>
H_CLK_DN1 <7>

PCIE_CLK_NB <7>
PCIE_CLK_NB# <7>

PCIE_CLK_SB <20>
PCIE_CLK_SB# <20>

PCIE_CLK_307 <18>
PCIE_CLK_307# <18>

PCIE_CLK_EXP <30>
PCIE_CLK_EXP# <30>

PCIE_CLK_WLAN <29>
PCIE_CLK_WLAN# <29>

SATA_CLK_DN <21>
SATA_CLK_DP <21>

Z_CLK0 <9>
Z_CLK1 <19>

CLK_48M_CR <26>

USB_CLK_12M <21>

C62 10P_0402_50V8J@

1 2

C61 10P_0402_50V8J@

1 2

C63 10P_0402_50V8J@

1 2

C66 10P_0402_50V8J@

1 2

C59 10P_0402_50V8J@

1 2

C65 10P_0402_50V8J@

1 2

C64 10P_0402_50V8J@

1 2

1

MHz

133

133

NB

SB

NewCard

14 47

of

307LV

WLAN

0.1

5

+1.8V

L25

1 2

D D

KC FBM-L11-201209-221LMAT_0805

1

C274

10U_0805_10V4Z

2

1

C665
10U_0805_10V4Z

2

C301

1

2

4

0.1U_0402_16V4Z

1

C302

C273

2

0.1U_0402_16V4Z

1

C788

2

3

CLKBUF_VDD

1

1

C275

2

2

2

1

0.1U_0402_16V4Z

+1.8V

L26

1 2

1

C789

@

10U_0805_10V4Z

2

C C

KC FBM-L11-201209-221LMAT_0805

1

C790

0.1U_0402_16V4Z

2

1

C276
10U_0805_10V4Z

2

CLKBUF_AVDD

Reference schematic use 1206

B B

0.1U_0402_16V4Z

CLK_INC<8>
CLK_INT<8>

SDATA<12,13,14,20>
SCLK<12,13,14,20>

10P_0402_50V8J

0.1U_0402_16V4Z

CLKBUF_VDD

CLK_INC

CLK_INT

SDATA
SCLK

R243 0_0402_5%

1

C300

2

R245 0_0402_5%
R244 0_0402_5%

12

R242 22_0402_5%

12
12

FB_INAFB_OUTA

12

Horizontal rotate

U12

3

VDD1.8_0

11

VDD1.8_1

25

VDD1.8_2

21

VDD1.8_3

10

CLK_INC

9

CLK_INT

20

SDATA

19

SCLK

18

FB_IN

17

FB_OUT

8

GND_0

6

GND_1

28

GND_2

24

GND_3

14

GND_4

ICS9P935AFLF-T_SSOP28

VDDA1.8

DDRC0
DDRT0

DDRC1
DDRT1

DDRC2
DDRT2

DDRC3
DDRT3

DDRC4
DDRT4

DDRC5
DDRT5

CLKBUF_AVDD

7

DDRC0

1
2

5
4

13
12

15
16

23
22

27
26

R819 0_0402_5%

DDRT0
DDRC1

DDRT1
DDRC2

DDRT2
DDRC3

DDRT3 DDR_CLK3

1 2

R820 0_0402_5%

1 2

R821 0_0402_5%

1 2

R822 0_0402_5%

1 2

R823 0_0402_5%

1 2

R824 0_0402_5%

1 2

R825 0_0402_5%

1 2

R826 0_0402_5%

1 2

DDR_CLK0#
DDR_CLK0

DDR_CLK2#
DDR_CLK2

DDR_CLK1#

DDR_CLK1

DDR_CLK3#

DDR_CLK0# <12>
DDR_CLK0 <12>

DDRA_CLK2# <13>
DDRA_CLK2 <13>

DDR_CLK1# <12>
DDR_CLK1 <12>

DDRA_CLK3# <13>
DDRA_CLK3 <13>

C300 close to R242

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01

3

Compal Secret Data

Deciphered Date

2006/03/01

2

Title

Size Document Number Rev

Custom
Date: Sheet of

Clock Buffer ICS9P935

KSWXX M/B LA-4611P Schematic

Friday, August 01, 2008

1

15 47

0.1

5

LCD POWER CIRCUIT

4

3

2

1

G

2

C29

+3VS

1 3

1

@

2

W=60mils

S

Q5
SI2301BDS_SOT23

D

1

2

+LCDVDD

1

2

C36

@

4.7U_0805_10V4Z

W=60mils

C32

0.1U_0402_16V4Z

+LCDVDD

D D

+3VALW +3VS

12

R827

2

B

E

10K_0402_5%

C

Q37
MMBT3904_SOT23

3 1

Level Shift Circuit

R829

GMCH_ENVDD<18>

C C

12

R22
100K_0402_5%

1 2

47K_0402_5%

12

SSM3K7002FU_SC70-3

R828
15K_0402_5%

C

Q38

2

B

MMBT3904_SOT23

E

3 1

12

13

D

Q8

S

GMCH_ENVDD_Q

Change Q7 Q8 package from SOT23 to SC70-3
Michael 2008/5/30

R16
300_0603_5%

2

G

+3VALW

12

R17
100K_0402_5%

R15 10K_0402_5%

13

D

Q7

2

G

SSM3K7002FU_SC70-3

S

2

1

12

C35

0.1U_0402_16V4Z

4.7U_0805_10V4Z

LCD/PANEL BD. Conn.
(IFTXX)

TZOUT0+<18>

+3VS

1

C268

0.1U_0402_16V4Z

2

+LCDVDD

B B

+LCDVDD_L

1

C271
10U_0805_10V4Z

2

1

C272

0.1U_0402_16V4Z

2

FBMA-L11-201209-221LMA30T_0805

TZOUT0-<18>
TZOUT1+<18>

TZOUT1-<18>
TZOUT2+<18> TXOUT2+ <18>

TZOUT2-<18>
TZCLK+<18>

TZCLK-<18>

L10

TZOUT0+
TZOUT0-

TZOUT1+
TZOUT1-

TZOUT2­TZCLK+ TXCLK+

TZCLK­+LCDVDD_L

12

(60 MIL)

1

C269
220P_0402_50V7K

2

<EMI>

Follow HEL80's pin definition
Except pin 29

JLVDS1

112

3

3

5

5

7

7
9910
111112

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

GND1

32

GND2

ACES_88242-3001
CONN@

2
4

4

6

6

8

8

10
12
14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

TXOUT0+
TXOUT0-

TXOUT1+
TXOUT1-

TXOUT2+TZOUT2+
TXOUT2-

TXCLK­I2CC_SDA

I2CC_SCL

1

C270
220P_0402_50V7K

2

<EMI>

+3VS+3VS

TXOUT0+ <18>
TXOUT0- <18>

TXOUT1+ <18>
TXOUT1- <18>

TXOUT2- <18>
TXCLK+ <18>

TXCLK- <18>
I2CC_SDA <18>

I2CC_SCL <18>

0208 Add C796 , C797 for EMI

INVERTER Conn.

INV_PWN_R

DAC_BRIG<31>

+INVPWR_B+

BKOFF#<31>

DISPOFF#

INVT_PWM<31>

JP37

1
2
3
4
5
6
7

MOLEX_53780-0790

ME@

BKOFF# DISPOFF#

INVT_PWM INV_PWN_R

D11 RB751V_SOD323

R25 0_0402_5%

21

1 2

DAC_BRIG
INVT_PWM
DISPOFF#

+3VS

12

R28

4.7K_0402_5%

1 2

C44 470P_0402_50V7K

1 2

C48 470P_0402_50V7K

1 2

C45 470P_0402_50V7K

copy jhtxx by ivan

+INVPWR_B+

L12

KC FBM-L11-201209-221LMAT_0805

L11

KC FBM-L11-201209-221LMAT_0805

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

Compal Secret Data

C49

0.1U_0603_50V4Z

Deciphered Date

1

C43
68P_0402_50V8K

2

@

2

12

12

B+

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

LVDS & DVI Connector

KSWXX M/B LA-4611P Schematic

16 47Friday, August 01, 2008

1

0.1

A

B

C

D

E

D7

@

DAN217_SC59

1

2

3

CRT_R_2

CRT_G_2CRT_G_1

CRT_B_2

1

C287

10P_0402_50V8J

2

CRT_HSYNC_2

CRT_VSYNC_2

1

C291

2

<EMI>

DAN217_SC59

+5VS

L13

KC FBM-L11-201209-221LMAT_0805

<EMI>

D9

@

1 2

+L_CRT_VCC

1

2

2 1

C292
10P_0402_50V8J

<EMI>

1

2

3

D8

RB491D_SC59-3

2

1

C288

2

<EMI>

100P_0402_50V8J

1

D10

<EMI>

DAN217_SC59

@

3

W=40mils

F1

21

1.1A_6VDC_FUSE

1

C278

0.1U_0402_16V4Z

2

1

C290

<EMI>

68P_0402_50V8K

2

1

C293
68P_0402_50V8K

2

<EMI>

12/22 Change to SE071680J80
(IFTXX)

+CRT_VCC+R_CRT_VCC

W=40mils

JCRT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070546FR015S233CR

DSUB_12

DSUB_15

Add IFTXX
Andy_1102

16
17

CRT Connector

Checklist recommend: 2-pole filter on R/G/B signals
C - L - C - L - C
10p - 47 Ohm/100MHz - 22p - 47 Ohm/100MHz - 10p

1 1

Place closed to chipset

VGA_CRT_R<9>

VGA_CRT_G<9>

VGA_CRT_B<9>

2 2

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

75_0402_5%

R212

12

75_0402_5%

R213

12

75_0402_5%

VGA_CRT_HSYNC<9>

R214

12

C279

10P_0402_50V8J

Place closed to chipset

VGA_CRT_VSYNC<9>

12/15 Modified. Note L26~L30 are 0 Ohm resisters
(IFTXX)

1

1

2

C281

C280

2

10P_0402_50V8J

10P_0402_50V8J

1 2

C289 0.1U_0402_16V4Z

VGA_CRT_HSYNC

L14 0_0603_5%

L16 0_0603_5%

L18 0_0603_5%

1

2

+CRT_VCC

1

5

P

OE#

A2Y

G

TC7SET125FUF_SC70

3

1 2

C294 0.1U_0402_16V4Z

VGA_CRT_ VSYNC

U5

4

+CRT_VCC

1

C283

C282

2

22P_0402_50V8J

22P_0402_50V8J

CRT_HSYNC_0

1

5

U6

P

OE#

A2Y

G

TC7SET125FUF_SC70

3

CRT_R_1

CRT_B_1

4

1

1

C285

2

2

22P_0402_50V8J

R215 10K_0402_5%

1 2

R216 39_0402_1%

CRT_VSYNC_0

L15

1 2

FBMA-L10-160808-800LMT_0603
L17

1 2

FBMA-L10-160808-800LMT_0603
L19

1 2

FBMA-L10-160808-800LMT_0603

12

CRT_HSYNC_1

1 2

R218 39_0402_1%

+3VS

C284

10P_0402_50V8J

CRT_VSYNC_1

D5

@

DAN217_SC59

1

2

D6

@

DAN217_SC59

2

3

1

C286
10P_0402_50V8J

2

<EMI>

<EMI>

1

3

10P_0402_50V8J

1

2

1 2

L20 FCM1608C-121T_0603

1 2

L21 FCM1608C-121T_0603

+5VS

+CRT_VCC

3 3

12

R221

2.2K_0402_5%

DSUB_12

DSUB_15

12

R222

2.2K_0402_5%

2N7002DW-T/R7_SOT363-6

+3VS

6 1

Q44A

2N7002DW-T/R7_SOT363-6

10/5 Change to SB00000AR00

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

D

+3VS

12

R220

2.2K_0402_5%

2

5

3

4

Q44B

12

R225

2.2K_0402_5%

+3VS

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

CRT & TV-OUT Connector

KSWXX M/B LA-4611P Schematic

GMCH_CRT_DATA <9>

GMCH_CRT_CLK <9>

E

17 47Friday, August 01, 2008

0.1

of

5

+1.8VS +1.8VS

L2 MBK1608121YZF_0603

1 2

1

C436

2

10U_0805_10V4Z

Modify 10U_1206 to

D D

10U_0805

1

0.1U_0402_16V4Z

2

For 307LV/ELV only

GMCH_ENVDD<16>
ENBKL<31>

C C

VB_LAVDD

307LV/ELV:
Stuff R107, R96, C110
Un-stuff R108
307DV/CP: Stuff R108
Un-stuff R107, R96, C110

B B

R108 1.65K_0402_1%@

1 2

R107 6.04K_0402_1%

1 2

R96 24K_0402_1%

1 2

C110
1U_0603_10V4Z

VBRCLK<14>

1 2

+3VS

General I/O Power

1 2

R358 0_0402_5%

VBRCLK

1

C425

C444

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

R130

100K_0402_5%

TZOUT2+<16>
TZOUT2-<16>
TZOUT1+<16>
TZOUT1-<16>
TZOUT0+<16>
TZOUT0-<16>
TZCLK+<16>
TZCLK-< 16>
TXCLK+<16>
TXCLK-<16>
TXOUT0+<16>
TXOUT0-<16>
TXOUT1+<16>
TXOUT1-<16>
TXOUT2+<16>
TXOUT2-<16>

I2CC_SDA<16>
I2CC_SCL<16>

R830 0_0402_5%

1 2

NB_RST#<9,19>

VB_VDD3V

1

C434

0.1U_0402_16V4Z

2

1

C424

2

0.1U_0402_16V4Z

T17
T20
T21
T18
T7
T8

12

T10
T12
T16
T13
T14
T19
T22

T15
T11
T9

PAD
PAD
PAD
PAD
PAD
PAD

PAD
PAD
PAD
PAD
PAD
PAD
PAD

PAD
PAD
PAD

1

2

C423

EXTSWING

VBOSCO
VBRCLK_R

VB_PCIEVDD VB_PCIEAVDD

254mA 35mA

1

C422

0.1U_0402_16V4Z

2

Modify 10U_1206 to
10U_0805

U7

G2

H2
H1

G1
E12
E11

G13
G12

F11

F3

G3

F2
F1
H3

J3

C13
A12
A13
C11
C12
A10
A11

C9

C10

A8
A9
C7
C8
A6
A7
C5
C6
A4
A5
C3
C4

E13
F12

J1
J2

G11

F10
E10
F13

NOTE: all stuffed(default)

+1.8VS

A A

1

C441

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

2

1

C437

0.1U_0402_16V4Z

2

1

C440

2

0.1U_0402_16V4Z

C433

Internal Core Power

5

Modify before using!

I2CC_SCL
I2CC_SDA

4

L37 MBK1608121YZF_0603

1

C439
10U_0805_10V4Z

2

R365 0_0402_5%

VB_VDD3V VB_ DA CVDD

GPIOA
GPIOB
GPIOC
GPIOD
LCDSENSE/GPIOE
INTN/GPIOF
GPIOG
GPIOH
GPIOI
GPIOJ
GPIOK
V2HSYNC/GPIOL
V2VSYNC/GPIOM
TSCLKI/GPION
TVCLKO/GPIOO

EXTSWING
LX3P
LX3N
LX2P
LX2N
LX1P
LX1N
LX0P
LX0N
LXC1P
LXC1N
LXC2P
LXC2N
LX4P
LX4N
LX5P
LX5N
LX6P
LX6N
LX7P
LX7N

LDDCDATA
LDDCCLK
VBOSCO
VBRCLK
PFTEST2
PFTEST1
PFTESTO
EXTRSTN

8/28 Change U6 from SIS307LV SA00000O920 to SIS307ELV SA00000O930

VSSF5VSSF6VSSF7VSSF8VSSF9VSSG5VSSG6VSSG7VSSG8VSSG9VSSH5VSSH6VSSH7VSSH8VSS

DDC pull-up

R124 2.2K_0402_5%

1 2
1 2

R118 2.2K_0402_5%

4

1 2

1 2

+1.8VS

392mA

G10

H13

IVDD

VDD3V

+5VS

3

1

C443

0.1U_0402_16V4Z

2

H10

J4

H11

H12

IVDD

IVDD

IVDD

VSS

H9

J10

IVDDH4IVDD

PCIEVSS

K12

G4

IVDD

K10

1

C442

0.01U_0402_16V7K

2

VB_PCIEAVSS

VB_PCIEVDD

K3

J6

K4

PCIEVDDJ5PCIEVDD

PCIEVDD

PCIEVDD

J7

J8

L1

PCIEVDD

PCIEVDD

PCIEVDDJ9PCIEVDD

VB_PCIEAVDD

VB_LVDSPLLVDD

VB_PLL1VDD

L6

C2

B3

L2

PCIEVDD

K2

L3

M1

DACVDD

PCIEVDD

PCIEVDD

PLL1VDD

PCIEAVDD

LVDSPLLVDD

SiS307ELV

PCIEVSS

PCIEVSS

PCIEVSS

PCIEVSS

PCIEVSSM5PCIEVSS

PCIEVSS

PCIEVSSK5PCIEVSSK6PCIEVSSK7PCIEVSSK8PCIEVSSK9PCIEVSS

M4

M2

M3

L11

L10

PCIEVSS

PCIEVSS

PCIEVSSM7PCIEVSS

PCIEVSS

PCIEVSS

M8

M9

M6

M11

M10

VB_LAVDD

E9

D10

D11

D12

D13

LAVDDE5LAVDDE6LAVDDE7LAVDDE8LAVDD

LAVDD

LAVDD

LAVDD

LAVDD

LAVSSA3LAVSSB4LAVSSB5LAVSSB6LAVSSB7LAVSSB8LAVSSB9LAVSS

PCIEVSS

PCIEVSS

N1

M12

M13

R334 0_0603_5%

B10

B11

LAVSS

B12

LAVSS

B13

PERN5/SVB_Bn
PERP5/SVB_Bp
PERN4/SVB_Gn
PERP4/SVB_Gp
PERN3/SVB_Rn
PERP3/SVB_Rp

PERN2/SVA_Bn
PERP2/SVA_Bp
PERN1/SVA_Gn
PERP1/SVA_Gp
PERN0/SVA_Rn
PERP0/SVA_Rp

LVDSPLLVSS

LAVSS

LAVSSD4LAVSSD5LAVSSD6LAVSSD7LAVSSD8LAVSS

REFCLKN

REFCLKP
PCIERSET0
PCIERSET1

VACLK
VBCLK

VBHSYNC

VBVSYNC

VBHCAD

VBHCLK

V2RSET
V2COMP
TVDACR
TVDACG

TVDACB

TVCSYNC

PCIEAVSS

PLL1VSS

DACVSS
DACVSS
DACVSS
DACVSS
DACVSS

SIS307LV-B0_BGA_167P

D9

AGND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01

3

Compal Secret Data

Deciphered Date

2

96mA

0.1U_0402_16V4Z

N12
N13
N10
N11
N8
N9

N6
N7
N4
N5
N2
N3

L7
L8

VB_PCIERSET0

L4

VB_PCIERSET1

L5
K13

VBCLK_R

J12
K11
J11
L13
L12

V2RSET

B2

V2COMP

B1
D2
D1
E2
E1

VB_PCIEAVSS

L9

VB_LVDSPLLVSS

A2

VB_PLL1VSS

K1
C1

D3
E3
E4
F4

AGND

0.1U_0402_16V4Z

2006/03/01

2

1

VB_LAVDD

1

C430

1

C429

0.1U_0402_16V4Z

2

2

VB_LVDSPLLVDD

30mA

0.1U_0402_16V4Z

VB_LVDSPLLVSS

HDVBN2_C <7>
HDVBP2_C <7>
HDVBN1_C <7>
HDVBP1_C <7>
HDVBN0_C <7>
HDVBP0_C <7>

HDVAN2_C <7>
HDVAP2_C <7>
HDVAN1_C <7>
HDVAP1_C <7>
HDVAN0_C <7>
HDVAP0_C <7>

R370 499_0402_1%

1 2

R369 124_0402_1%

R132 33_0402_5%

1 2

R345 0_0402_5%

1 2

R346 115_0402_1%

@

PAD

307ELV:NC these 4 pins!

T6

V2COMP

VB_DACVDD +3VS

99mA

1

1

C92

2

2

0.01U_0402_16V7K

AGND

VBOSCO

11mA

VB_PLL1VDD

VB_PLL1VSS

Title

Size Document Number Rev

Custom

Date: Sheet

1

C431

0.1U_0402_16V4Z

2

1

C421

2

307ELV:stuff R345, un-stuff R346
307LV/DV/CP:stuff R346, un-stuff R345

5/20 Change R345 from @ to stuff

C109 0.1U_0402_16V4Z

1 2

307ELV:change C94 to 0 ohm
307LV/DV/CP:C94=0.1uF

C94 0_0402_5%

1 2

8/28 Change C94 from 0.1U to 0 Ohm

1

C91

C93

10U_0805_10V4Z

2

4.7U_0805_10V4Z

Y2 14.31818MHZ_16PF_DSX840GA@

1 2

2

C116

@

27P_0402_50V8J

1

1

C118

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

LVDS Encoder SiS307LV

KSWXX M/B LA-4611P Schematic

Friday, August 01, 2008

MBK1608121YZF_0603
L35

1 2

1

C427

0.1U_0402_16V4Z

2

Modify 10U_1206 to
10U_0805

L32

1 2

MBK1608121YZF_0603

1

C402

0.01U_0402_16V7K

2

1 2

R336 0_0402_5%

Modify 10U_1206 to
10U_0805

PCIE_CLK_307# <14>
PCIE_CLK_307 <14>

VACLK <9>
VBCLK <9>
VBHSYNC <9>

Side-Band

VBVSYNC <9>
VBCAD <9>

Signals

VBHCLK <9>

VB_DACVDD

AGND

AGND

1

1

2

2

C670
10U_0805_10V4Z

C669

7/30 change L 14 t o 1_0603
Add C669 and C670

R125 10_0402_5%@

1 2

2

C113

@

27P_0402_50V8J

1

L7

1 2

MBK1608121YZF_0603

1

C119

0.01U_0402_16V7K

2

1 2

R139 0_0402_5%

1

L4

1_0603_5%

+3VS

1

C428

10U_0805_10V4Z

2

+3VS

1

C399

10U_0805_10V4Z

2

VBRCLK_R

+3VS

1

C154
10U_0805_10V4Z

2

of

18 47

0.1

5

D D

C C

ZAD[0..16]<9>

+1.8VS

12

R198
150_0402_1%

SZVREF

12

B B

A A

10U_0805_10V4Z

R200

49.9_0402_1%

+1.8VS

+1.8VS

C541

1

C194

0.1U_0402_16V4Z

2

1 2

R206 56_0402_5%

1 2

R204 56_0402_5%

L67

1 2

MBK1608121YZF_0603

1

0.1U_0402_16V4Z

2

1 2

R446 0_0402_5%

5

C549

1

2

SZCMP_N

SZCMP_P

AVDD_SZ4X

1

C550

0.01U_0402_16V7K

2

AVSS_SZ4X

16mA

ZAD[0..16]

ZSTB_DP0<9>
ZSTB_DN0<9>
ZSTB_DP1<9>
ZSTB_DN1<9>

ZUREQ<9>
ZDREQ<9>

Z_CLK1<14>

4

4

ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16

ZSTB_DP0
ZSTB_DN0
ZSTB_DP1
ZSTB_DN1

ZUREQ
ZDREQ

SZCMP_N
SZCMP_P

AVDD_SZ4X
AVSS_SZ4X

SZVREF

3

U11A

H5

AD31

J4

AD30

J3

AD29

K1

AD28

K2

AD27

J5

AD26

K4

AD25

K3

AD24

L2

AD23

K5

AD22

L4

AD21

L3

AD20

M1

AD19

M2

AD18

L5

AD17

M4

AD16

P3

AD15

R1

AD14

R2

AD13

P5

AD12

R4

AD11

R3

AD10

T1

AD9

T2

AD8

T4

AD7

T3

AD6

U1

AD5

U2

AD4

T5

AD3

U4

AD2

U3

AD1

V1

AD0

Y22

ZAD0

Y25

ZAD1

Y23

ZAD2

W21

ZAD3

Y26

ZAD4

W22

ZAD5

W24

ZAD6

W25

ZAD7

U21

ZAD8

U24

ZAD9

U22

ZAD10

T22

ZAD11

U25

ZAD12

T23

ZAD13

T25

ZAD14

T26

ZAD15

AA26

ZAD16

V22

ZSTB0

V23

ZSTB0#

V25

ZSTB1

V26

ZSTB1#

AA23

ZUREQ

AA24

ZDREQ

AB24

ZCMP_N

AB25

ZCMP_P

AA22

AVDD_Z4X

AB23

AVSS_Z4X

AB26

ZVREF

AC26

ZCLK

AE22

SPI_DI

AD22

SPI_DO

AF21

SPI_CS1N

AE21

SPI_CS0N

SIS968-B0_TEBGA_570P

PCI

MuTIOL

SPI

SPI_HARDWARE_TRAP

PREQ4#
PREQ3#
PREQ2#
PREQ1#
PREQ0#

PGNT4#
PGNT3#
PGNT2#
PGNT1#
PGNT0#

C/BE3#
C/BE2#
C/BE1#
C/BE0#

FRAME#

TRDY#
STOP#
SERR#

DEVSEL#

PLOCK#

PCICLK

PCIRST#

IDSAA2
IDSAA1
IDSAA0

IDE

IDECSA1#
IDECSA0#

IIORA#

IIOWA#

IDACKA#

ICHRDYA

IDREQA

CBLIDA

AVDD_IDE
AVSS_IDE

SPI_CLK

INTA#
INTB#
INTC#
INTD#

IRDY#

PAR

IDA0
IDA1
IDA2
IDA3
IDA4
IDA5
IDA6
IDA7
IDA8

IDA9
IDA10
IDA11
IDA12
IDA13
IDA14
IDA15

IIRQA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/05/15

3

PCI_REQ#4

H2

PCI_REQ#3

H1

PCI_REQ#2

G3

PCI_REQ#1

G4

PCI_REQ#0

G2

PCI_GNT#4

J2

PCI_GNT#3

J1

PCI_GNT#2

H3

PCI_GNT#1

H4
G5

L1
M3
N5
R5

INT_N_A

F5

PCI_PIRQB#

F4

PCI_PIRQC#

F3

PCI_PIRQD#

G1

PCI_FRAME#

N1

PCI_IRDY#

N2

PCI_TRDY#

M5

PCI_STOP#

N3

PCI_SERR#

P2
P4

PCI_DEVSEL#

N4

PCI_PLOCK#

P1

CLK_PCI_SB

V2

PCI_RST#_R

D5

AE19
AD18
AC17
AF18
AB16
AE17
AD16

IDE_DD7

AF16
AE16
AF17
AC16
AD17
AE18
AB17
AF19
AC18

AD21
AD20
AB20

AC21
AB21

AF20
AD19
AC19

IDE_DIORDY

AE20

IDE_DDREQ

AB18

IDE_IRQ

AB19
AC20

V3

IDEAVSS

V4

AF22
AF23

1 2

R257 4.7K_0402_5%

SPI_Hardware Trap

0:LPC (Default)
1:SPI

Compal Secret Data

Deciphered Date

PAD

T28

PAD

T29

PAD

T27

PAD

T26

INT_N_A <7,9>

CLK_PCI_SB <14>

2

R384 33_0402_5%

1 2

R831 33_0402_5%

1 2

2009/05/15

2

1

+3VS

PCI_REQ#4
PCI_REQ#3
PCI_REQ#2
PCI_REQ#1

PCI_REQ#0
INT_N_A
PCI_PIRQB#
PCI_PIRQC#

PCI_PIRQD#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#

PCI_STOP#
PCI_SERR#
PCI_DEVSEL#
PCI_PLOCK#

PCI_RST# <28,29,30,31,33>
NB_RST# <9,18>

IDE_DIORDY
IDE_IRQ

IDE_DDREQ
IDE_IRQ
IDE_DD7

R450 4.7K_0402_5%@
R434 8.2K_0402_5%

R441 4.7K_0402_5%@
R437 4.7K_0402_5%@
R259 5.6K_0402_5%

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 2
1 2

1 2
1 2
1 2

RP44

8.2K_1206_8P4R_5%
RP45

8.2K_1206_8P4R_5%
RP46

8.2K_1206_8P4R_5%
RP47

8.2K_1206_8P4R_5%

+3VS

R450 => Intel :Pull-up 4.7K ohm (Mount) SiS : Pull-up ? ohm (Un-Mount)
R434 => Int e l :Pull-up 8.2K ohm (Mount) SiS :Not Pull-up
R441 => Intel :Don't Pull-down SiS : Pull-down ? ohm (Un-Mount)
R437 => Intel :Don't Pull-down SiS : Pull-down ? ohm (Un-Mount)
R218 => Intel :Don't Pull-down SiS : Pull-down 5.6K ohm (Mount)

1

+1.8VS

1

C521

0.1U_0402_16V4Z

2

19 47

0.1

8mA

IDEAVDDIDEAVDD

1

C536

0.1U_0402_16V4Z

Title

Size Document Number Rev

Custom

Date: Sheet of

2

IDEAVSS

Compal Electronics, Inc.

SIS968(1/5)-PCI_IDE _MuTIO L
KSWXX M/B LA-4611P Schematic

Friday, August 01, 2008

L66

1 2

MBK1608121YZF_0603

1

C535

0.01U_0402_16V7K

2

1 2

R428 0_0402_5%

5

C175 15P_0402_50V8J

X1

3

NC

2

32.768KHZ_12.5P_1TJS125BJ2A251

D D

NC

C172 15P_0402_50V8J

4

OUT

1

IN

8/07 modified from 12P to 15P

+3VS

R430 4.7K_0402_5%

1 2

R429 10K_0402_5%

1 2

R173

10M_0402_5%

LPC_DRQ0#
SERIRQ

12

SB_PWRGD<9,31>

0.1U_0402_16V4Z

LPC_AD0<31,33>
LPC_AD1<31,33>
LPC_AD2<31,33>
LPC_AD3<31,33>

LPC_FRAME#<31,33>
LPC_DRQ0#<33>

SERIRQ<31,33>

R430 => Intel :Not Pull-up SiS : Pull-up 4.7K ohm (Mount)
R429 => Intel :Pull-up 10K ohm (Mount) SiS :Not Pull-up

HDA_BITCLK_AUDIO<35>
HDA_BITCLK_MDC<37>
HDA_SDOUT_AUDIO<35>

C C

HDA_SDOUT_MDC<37>
HDA_SYNC_AUDIO<35>
HDA_SYNC_MDC<37>
HDA_RST_AUDIO#<35>
HDA_RST_MDC#<37>

8/29 change net from BAT_PWRGD to net +RTCVCC

SMT1-05_4P
SW1

@

1
2

5

6

+3VALW

B B

+3VS

A A

RP40

45
36
27

10K_1206_8P4R_5%

10K_1206_8P4R_5%

BATT1

-+

ML1220T13RE

@

18

RP41

45

CPUSTP_N_OLD

36
27
18

R381 10K_0402_5%

1 2

R397 10K_0402_5%

1 2

R393 10K_0402_5%

1 2

R390 10K_0402_5%@

1 2

R403 10K_0402_5%@

1 2

R398 10K_0402_5%@

1 2

12

1 2

R192 33_0402_5%

1 2

R194 33_0402_5%

1 2

R201 33_0402_5%

1 2

R203 33_0402_5%

1 2

R197 33_0402_5%

1 2

R199 33_0402_5%

1 2

R166 33_0402_5%

1 2

R167 33_0402_5%

+RTCVCC

3
4

7/30 add for debug

EC_SMI#

EC_LID_OUT#

EC_SCI#

PM_SLP_S5#

Remove R163 R162 R164 R388 R382
R425 R387 R381; Add RP40 RP41

AGPSTOP#

Michael 2008/5/30

GPIO14

PM_SLP_S3#

GATEA20
KB_RST#

+RTC_BATT

R291

+RTCBATT

1 2

511_0603_1%

Decoupling Capacitor

5

HDA_SDOUT_SB

HDA_SYNC_SB

HDA_RST_SB#

CPU IU

1 2

0_0402_5%

AUX_PWRGD<9,31>

GPIO16
GATEA20
KB_RST#
EC_THERM#

D20

1

BAS40-04_SOT23

1U_0603_10V4Z

Please close to SB

R176

2

3

1

C326

C346

2

10U_0805_10V4Z

HDA_SDIN0<35>
HDA_SDIN1<37>

H_INIT#<4>
H_A20M#<4>
H_SMI#<4>
H_INTR<4>

H_NMI<4>
H_IGNNE#<4>
H_FERR#<4>
H_STPCLK#<4>
H_CPUSLP#<5>

H_PROCHOT#<4,46>
H_THERMTRIP#<4>
AGPBUSY#<9>

REF_CLK1<14>

SB_SPKR<35>

PBTN_OUT#<31>

PCI_PME#<31>

PSON#<31>

C168 0.1U_0402_16V4Z

PM_SLP_S5#<31>
PM_SLP_S3#<31>

EC_SMI#<31>

EC_LID_OUT#<31>

EC_SCI#<31>

AGPSTOP#<9>
CPUSTP_N_OLD<25>
SB_DPRSLPVR<25>

GATEA20<31>
KB_RST#<31>

+CHGRTC

1

1

C333

0.01U_0402_16V7K

2

2

0.1U_0402_16V4Z

@

1

C332

2

C473

12

+RTCVCC

4

U11B

OSC32KHO
OSC32KHI

BAT_PWRGD
SB_PWRGD

1

+RTCVCC

2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ0#
SERIRQ

HDA_SDIN0
HDA_SDIN1

HDA_SDOUT_SB
HDA_SYNC_SB

HDA_RST_SB#
HDA_BITCLK_SB

H_INIT#
H_A20M#
H_SMI#
H_INTR
H_NMI
H_IGNNE#
H_FERR#
H_STPCLK#
H_CPUSLP#

AA4
AB2
AB3

AB1
AB4
AA5

AC23
AE26
AD23
AC22
AE25
AE24
AF24
AF25
AD24

E2
E1

F1

E4

D1
D2

Y5

E5
C4

Y3
Y2

B3
Y1

OSC32KHO
OSC32KHI

BATOK
PWROK

RTCVDD
RTCVSS

LAD0
LAD1
LAD2
LAD3

LFRAME#
LDRQ#
SIRQ

HDA_SDIN0
HDA_SDIN1

HDA_SDOUT
HDA_SYNC

HDA_RESET#
HDA_BIT_CLK

INIT#
A20M#
SMI#
INTR
NMI
IGNNE#
FERR#
STPCLK#
CPUSLP#

LPCRTC HD Audio ACPI

CPU_S

APIC

H_PROCHOT#
H_THERMTRIP#
AGPBUSY#

REF_CLK1
SB_SPKR
PBTN_OUT#

PCI_PME#
PSON#

PM_SLP_S5#
PM_SLP_S3#

EC_SMI#
EC_LID_OUT#
EC_SCI#

AGPSTOP#
CPUSTP_N_OLD
SB_DPRSLPVR
GPIO14

GPIO16
GATEA20
KB_RST#

D19 RLS4148_LL34-2

1 2

R279 10K_0402_5%

1 2

12

J1

@

JOPEN

4

AC24

PROCHOT#

AD25

THERMTRIP#

AE23

BMBUSY#

AA2

OSCI

F2

ENTEST

AA1

SPK

E6

PWRBTN#

A6

PME#

E7

PSON#

C3

AUXOK

A5

ACPILED

C2

GPIO10/SLP_S5#

C7

GPIO15/SLP_S3#

D6

GPIO7/GPWAK#

A4

GPIO8/RING

C6

GPIO9/HDA_SDIN2

F6

GPIO11/STP_PCI#/AGPSTOP#

D4

GPIO12/CPUSTP#/DPSLP#

D3

GPIO13/DPRSLPVR

B5

GPIO14/AGPSTOP#/S3AUXSW#

B7

GPIO16/DPRSTP#

D7

GPIO17/GA20#

B4

GPIO18/KBDRST#

Change D19 footprint from RLS4148_LL34-2 to LL34

SIS968-B0_TEBGA_570P

@

J2 JOPEN

1 2

BAT_PWRGD

GPIO

8/29 change J1,J4 from net BAT_PWRGD to net +RTCVCC

C328

10U_0805_10V4Z

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

AVSS_GMACCMP18

AVDD_GMACCMP18

OSC25MHO

OSC25MHI

GTXCLK
EXTCLK

TXCLK

TXEN
TXER

TXD0
TXD1
TXD2
TXD3

RGMCMP_N

GMACPCI Express

GPIO1/LDRQ1#/PCIE_HOTPLUG

GPIO14

RGMCMP_P

RGMVREF

RXCLK

RXDV
RXER

RXD0
RXD1
RXD2
RXD3

COL
CRS

MDC

MDIO

GPIO21
GPIO22
GPIO23
GPIO24

PRX0+

PRX0­PTX0+

PTX0-

PRX1+

PRX1­PTX1+

PTX1-

NC11
NC10

NC9
NC8
NC7
NC6
NC5
NC4

PCLK100P
PCLK100N

AVDD_PEXTRX

AVSS_PEXTRX

RSET0
RSET1

PCIEPRSNT1
PCIEPRSNT0

GPIO0/STPCPU#

GPIO2/THERM#
GPIO3/EXTSMI#

GPIO4/CLKRUN#

GPIO5/PREQ5#
GPIO6/PGNT5#

GPIO19
GPIO20

R431 0_0402_5%

1 2

R394 0_0402_5%@

1 2

Compal Secret Data

2008/05/15

3

Deciphered Date

AVSS_GMACCMP

C8

AVDD_GMACCMP

D9

MOSC25MHO

B8

MOSC25MHI

A8

GTXCLK

A12
F14

B11
C12

C11
D12

A13
B13
C13

A14
B14
C14

A11
C10

E12
A10

C9
B9
A9

E10
E11
E14
E13

D8
F8
E8
A7

M26
M25
N24
N23
K26
K25
L24
L23

F26
F25
G24
G23
H26
H25
J24
J23

P26
P25
R25
R26
P22
P21

R21
R23

U5
AB5
V5
W4
W3
W2
W1

Y4
W5

PAD

EXTCLK

PAD

TXCLK
TX_EN

R389 33_0402_5%

TXER
TXD_0

TXD_1
TXD_2
TXD_3

RGMCMP_N
RGMCMP_P
RGMVREF

RXCLK
RXDV

RXER
RXD0

RXD1
RXD2
RXD3

COL
CRS

MDIO
GPIO21

GPIO22
GPIO23
GPIO24

PCIE_PTX_C_IRX_P0
PCIE_PTX_C_IRX_N0

PCIE_ITX_PRX_N0
PCIE_PTX_C_IRX_P1
PCIE_PTX_C_IRX_N1
PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1

PCIE_CLK_SB
PCIE_CLK_SB#
AVDD_PEXTRX
AVSS_PEXTRX

PCIEPRSNT1
PCIEPRSNT0

PROJECT_ID
GPIO1
GPIO2
GPIO3
PM_CLKRUN#
GPIO5
IDE_HRESET#

SCLK
SDATA

1 2

PAD

R146 33_0402_5%

1 2

R159 33_0402_5%

1 2

R158 33_0402_5%

1 2

R145 33_0402_5%

1 2

R420 499_0402_1%

1 2

R426 124_0402_1%

1 2

7/20 modified

R187 4.7K_0402_5%

2 1

D14 RB751V_SOD323

2

T4
T25

TXCLK <28>

T24

R161 56_0402_5%

1 2

R160 56_0402_5%

1 2

R147 150_0402_1%

1 2

RXCLK <28>
RXDV <28>

RXER <28>
RXD0 <28>

RXD1 <28>
RXD2 <28>
RXD3 <28>

COL <28>

R260 33_0402_5%

CRS <28>

1 2

MDIO <28>

GPIO23
GPIO22
GPIO21
GPIO24

C515 0.1U_0402_10V7K

1 2

C511 0.1U_0402_10V7K

1 2

C512 0.1U_0402_10V7K

1 2

C506 0.1U_0402_10V7K

1 2

PCIE_CLK_SB <14>
PCIE_CLK_SB# <14>

R427 0_0402_5%

1 2

7/20 modified

PM_CLKRUN# <31>

SCLK <12,13,14,15>
SDATA <12,13,14,15>

12

CP_PE#PCIEPRSNT1

EC_THERM#GPIO2

2009/05/15

2

+1.8VS

1

8mA

AVDD_GMACCMP

1

C459

TXEN <28>

TXD0 <28>
TXD1 <28>
TXD2 <28>
TXD3 <28>

R142

150_0402_1%

MDCH_MDC

0.1U_0402_16V4Z

AVSS_GMACCMP

12

1

2

U9

4

DO

3

DI

2

SK

1

CS

AT93C46-10SI-2.7_SO8

@

PCIE_ITX_C_PRX_P0PCIE_ITX_PRX_P0
PCIE_ITX_C_PRX_N0

PCIE_ITX_C_PRX_P1
PCIE_ITX_C_PRX_N1

PCI-Express

30mA

AVDD_PEXTRX

0.1U_0402_16V4Z

AVSS_PEXTRX

2

+3VALW
+3VALW

C120

0.01U_0402_16V7K

MDC <28>

5

GND

6

NC

7

NC

8

VCC

C185

GPIO23
PBTN_OUT#
PCI_PME#
PSON#

1

2

10/26 modified

GPIO1
PM_CLKRUN#

GPIO3
GPIO5
IDE_HRESET#
GPIO2

Remove R433 R435 R438 R439
Add RP42 Michael 2008/5/30

SB_DPRSLPVR

CP_PE# <30>

EC_THERM# <31>

Title

Size Document Number Rev

Custom

Date: Sheet of

PROJECT_ID

Compal Electronics, Inc.

SIS968(2/5)-PCIE_LAN_RTC

KSWXX M/B LA-4611P Schematic

Friday, August 01, 2008

L38

1 2

MBK1608121YZF_0603

1

C457

0.01U_0402_16V7K

2

1 2

R832 0_0402_5%

Put closed to 968

MOSC25MHO

R151 0_0402_5%

MOSC25MHI

33P_0402_50V8J

the same with "180"

7/30 modified from 27P to 33P

PCIE_PTX_C_IRX_P0 <29>
PCIE_PTX_C_IRX_N0 <29>
PCIE_ITX_C_PRX_P0 <29>
PCIE_ITX_C_PRX_N0 <29>
PCIE_PTX_C_IRX_P1 <30>
PCIE_PTX_C_IRX_N1 <30>
PCIE_ITX_C_PRX_P1 <30>
PCIE_ITX_C_PRX_N1 <30>

1

2

R386 4.7K_0402_5%

1 2

R833 100K_0402_5%

1 2

R385 4.7K_0402_5%

1 2

R834 100K_0402_5%

1 2

1 2

R611 1K_0402_5%
R443 10K_0402_5%@

1 2

R444 10K_0402_5%@

1 2

10K_1206_8P4R_5%

R404 4.7K_0402_5%

1 2

R436 10K_0402_5%@

1 2
1 2

R424 1K_0402_5%14W@

1 2

Y4

1 2

25MHZ_20PF_6X25000017
C152

33P_0402_50V8J

+3VALW

L9

1 2

MBK1608121YZF_0603

C186

0.01U_0402_16V7K

1 2

R190 0_0402_5%

RP42

45
36
27
18

20 47

1

@

+1.8VALW

R150

0_0402_5%

C151

WLAN

NEW Card

+1.8VS

+3VALW

12

+3VS

+3VS

0.1

5

4

3

2

1

+1.8VALW

L8

1 2

MBK1608121YZF_0603

D D

+3VALW

L43

1 2

MBK1608121YZF_0603

C C

B B

A A

0.1U_0402_16V4Z
R168 0_0402_5%

R392 0_0402_5%

+1.8VALW

L46

1 2

MBK1608121YZF_0603

R407 0_0402_5%

+1.8VALW

L44

1 2

MBK1608121YZF_0603

+3VALW

R836 4.7K_0402_5%

+1.8VS

L23

1 2

MBK1608121YZF_0603

0.1U_0402_16V4Z

1 2

R217 0_0402_5%

+3VS

L51

1 2

MBK1608121YZF_0603

0.1U_0402_16V4Z

1 2

R440 0_0402_5%

C170

1 2

C489

0.1U_0402_16V4Z

C465

0.1U_0402_16V4Z

1 2

C476

0.1U_0402_16V4Z

1 2

C475

0.1U_0402_16V4Z

1 2

C222

C545

5

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

C215

0.01U_0402_16V7K

2

1

C548

0.01U_0402_16V7K

2

7mA

USBPVDD18

C171

0.01U_0402_16V7K

USBPVSS18

8mA

Place C478,C489 close to

C478

U11 Pin F17,F19,F22

0.01U_0402_16V7K

8mA

USBCMPAVDD33

Place C465,C466

C466

close to U11 Pin D21

0.01U_0402_16V7K

USBCMPAVSS33

9mA

USBCMPAVDD18

C477

0.01U_0402_16V7K

USBCMPAVSS18

284mA

UVDD18

C474

0.01U_0402_16V7K

SB_PCIE_WAKE#

6mA

AVDD_SATARX

AVSS_SATARX

41mA

AVDD_SATAPLL33

AVSS_SATAPLL33

Card Reader

+3VALW

USB20_P0
USB20_N0
USB20_P1
USB20_N1
USB20_P2
USB20_N2
USB20_P3
USB20_N3
USB20_P4
USB20_N4
USB20_P5
USB20_N5
USB20_P6
USB20_N6
USB20_P7
USB20_N7

USB_OC#06
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#45

USB_OC#6
USB_OC#7

AVDD_SATARX
AVSS_SATARX

AVDD_SATAPLL33

AVSS_SATAPLL33

SATA_CLK_DP
SATA_CLK_DN

SB_PCIE_WAKE#
ATRAP
TRAP0

1 2

USB20_P0<30>
USB20_N0<30>
USB20_P1<33>
USB20_N1<33>
USB20_P2<30>
USB20_N2<30>
USB20_P3<37>
USB20_N3<37>
USB20_P4<30>
USB20_N4<30>
USB20_P5<30>
USB20_N5<30>
USB20_P6<26>
USB20_N6<26>
USB20_P7<37>
USB20_N7<37>

USB_OC#06<30>

USB_OC#45<30>

SATA_CLK_DP<14>
SATA_CLK_DN<14>

SB_PCIE_WAKE#<7,29,30>

USB
BT

New Card

WLAN

USB
USB

CAMERA

R211 12K_0402_1%

1 2

C216 22P_0402_50V8J

1 2

R405 1K_0402_5%

1 2

R155 1K_0402_5%@

133MHz:Internal pull-down
66MHz:External pull-up

Remove R838 R839 R840 R552
Add RP43 Michael 2008/5/30

+3VALW

4

RP43

45
36
27

10K_1206_8P4R_5%

R841 10K_0402_5%

18

1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SATA_REXT

USB_OC#2
USB_OC#1
USB_OC#3
USB_OC#7

USB_OC#6

Issued Date

U11C

D26

UV0+

D25

UV0-

E24

UV1+

E23

UV1-

A20

UV2+

B20

UV2-

C19

UV3+

D19

UV3-

A18

UV4+

B18

UV4-

C17

UV5+

D17

UV5-

A16

UV6+

B16

UV6-

C15

UV7+

D15

UV7-

A23

OC0#

F21

OC1#

A24

OC2#

B24

OC3#

C23

OC4#

C24

OC5#

A25

OC6#

B23

OC7#

AF14

AVDD_SATARX

AF15

AVSS_SATARX

AC9

AVDD_SATAPLL33

AD9

AVDD_SATAPLL33

AC8

AVSS_SATAPLL33

AD8

AVSS_SATAPLL33

AF7

REXT

AE15

CLK100P

AD15

CLK100N

E9

PCIEWAKE

D10

ATRAP

E22

TRAP0

SIS968-B0_TEBGA_570P

2008/05/15

3

AVDD_USBCMP18
AVSS_USBCMP18

AVDD_USBCMP33
AVSS_USBCMP33

USB

SATA

Compal Secret Data

OSC12MHI

OSC12MHO

USBREF

AVDD_USBPLL18
AVSS_USBPLL18

UVDD33
UVDD33
UVDD33

UVDD18
UVDD18
UVDD18
UVDD18
UVDD18
UVDD18
UVDD18
UVDD18
UVDD18
UVDD18

STX0+

STX0-

SRX0+

SRX0-

STX1+

STX1-

SRX1+

SRX1-

XOUT

HDACT

ISWITCHOPEN1
ISWITCHOPEN0

IPB_OUT0
IPB_OUT1

Deciphered Date

USB_CLK_12M

A22
B22

USBREF

F20

USBPVDD18

B26

USBPVSS18

B25

USBCMPAVDD18

E21

USBCMPAVSS18

E20

USBCMPAVDD33

D21

USBCMPAVSS33

C21

USBCMPAVDD33

F17
F19
F22

UVDD18

J15
H15
H16
H17
H18
J19
F16
F15
E18
E16

SATA_ITX_DRX_P0

AC13

SATA_ITX_DRX_N0

AD13

SATA_DTX_C_IRX_P0

AF12

SATA_DTX_C_IRX_N0

AE12

SATA_ITX_DRX_P1

AC6

SATA_ITX_DRX_N1

AD6

SATA_DTX_C_IRX_P1

AF5

SATA_DTX_C_IRX_N1

AE5

SOSC25MHI

AE8

XIN

AF8

H_SATA_LED#

AA3

ISWITCHOPEN1

AC1

ISWITCHOPEN0

AD1

D22
C22

H_SATA_LED# SATA_LED#

2009/05/15

2

USB_CLK_12M <14>

R402 127_0402_1%

1 2

C560 0.01U_0402_16V7K

1 2

C559 0.01U_0402_16V7K

1 2

SATA_DTX_C_IRX_P0 <24>
SATA_DTX_C_IRX_N0 <24>

C791 0.01U_0402_16V7K

1 2

C792 0.01U_0402_16V7K

1 2

SATA_DTX_C_IRX_P1 <24>
SATA_DTX_C_IRX_N1 <24>

1 2

R219 0_0402_5%

R207 1K_0402_5%

1 2

R209 1K_0402_5%

1 2

+5VS+3VS

12

R205

@

10K_0402_5%

R837 0_0402_5%

1 2

Title

Size Document Number Rev

Custom

KSWXX M/B LA-3961P Schematic

Friday, August 01, 2008

Date: Sheet of

SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0

SATA_ITX_C_DRX_P1
SATA_ITX_C_DRX_N1

C663 0.1U_0402_16V4Z@
R576 10K_0402_5%@

1

5

U39

P

4

OE#

A2Y

G

TC7SET125FUF_SC70@

3

1 2
1 2

SATA_ITX_C_DRX_P0 <24>
SATA_ITX_C_DRX_N0 <24>

SATA_ITX_C_DRX_P1 <24>
SATA_ITX_C_DRX_N1 <24>

Compal Electronics, Inc.

SIS968(3/5)-USB_SATA

21 47

1

SATA_LED# <37>

0.1

5

D D

+1.05VS

22mA

+3VS

29mA

C C

+3VALW

4mA

+3VALW

8mA

+1.8VS

153mA

B B

U11D

AA21

VTT

AB22

VTT

V16

PVDD

V15

PVDD

V14

PVDD

T8

PVDD

N8

PVDD

L9

PVDD

W17

OVDD

W16

OVDD

W15

OVDD

W14

OVDD

W13

OVDD

W12

OVDD

K8

OVDD

L8

OVDD

M8

OVDD

P8

OVDD

R8

OVDD

U8

OVDD

V8

OVDD

H19

OVDD_AUX

H9

OVDD_AUX

H8

OVDD_AUX

F7

OVDD_AUX

J11

OVDD_AUX

J12

OVDD_AUX

H10

GMIIVDD_AUX

H11

GMIIVDD_AUX

H12

GMIIVDD_AUX

H13

GMIIVDD_AUX

J13

GMIIVDD_AUX

K18

AVDDPEX

L18

AVDDPEX

L19

AVDDPEX

M18

AVDDPEX

M19

AVDDPEX

N19

AVDDPEX

H21

AVDDPEX

J21

AVDDPEX

K21

AVDDPEX

L21

AVDDPEX

M21

AVDDPEX

N21

AVDDPEX

M22

AVDDPEX

H22

AVDDPEX

SIS968-B0_TEBGA_570P

Power

IVDD_AUX
IVDD_AUX
IVDD_AUX
IVDD_AUX
IVDD_AUX
IVDD_AUX

AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA

IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD

VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ

4

T18
J14
U9
T9
R9
P9
N9
M9
K9
V10
V11
V12
V13
V17
R17
R18

N18
W19
V19
V18
U18
W18
P18
Y24
V24
T24
R24
AA25
W26
U26

J9
J8
J10
J16
J17
J18

W11
W10
W9
W8
V9
AF10
AE10
AD11
AD10
AC11
AC10
AB11
AB10
AB9
AB8

413mA

413mA

19mA

+1.8VS

190mA

+1.8VS

+1.8VS

+1.8VALW

Put under 968 solder side

C537

0.1U_0402_16V4Z

3

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.01U_0402_16V7K

0.01U_0402_16V7K

+1.8VS

0.1U_0402_16V4Z

1

C530

2

+3VS

1

C502

2

+1.8VS

1

C514

2

+1.8VS

1

C533

2

+1.8VS

1

C504

2

1

C520

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C507

2

0.1U_0402_16V4Z

1

C525

2

0.1U_0402_16V4Z

C557,C555,C217,C228,C551,C554
close to U30 Pin AVDD_SATA

1

C555

2

0.1U_0402_16V4Z

C504,C509,C494,C495,C513,C503
close to U30 Pin AVDDPEX

1

C509

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C517

2

1

C522

2

0.1U_0402_16V4Z

1

C526

2

1U_0603_10V4Z

1

C217

2

1U_0603_10V4Z

1

C494

2

1

C794

2

0.1U_0402_16V4Z

1

C534

2

0.1U_0402_16V4Z

1

C527

2

0.1U_0402_16V4Z

1

C228

2

10U_0805_10V4Z

1

C495

2

10U_0805_10V4Z

1

0.1U_0402_16V4Z

2

2

1U_0603_10V4Z

1

C542

2

1U_0603_10V4Z

1

C539

2

0.1U_0402_16V4Z

+3VS

1

C531

2

10U_0805_10V4Z

1

2

1

2

+1.8VALW

C501

C519

C543

10U_0805_10V4Z

C524

1

C497

0.1U_0402_16V4Z

2

+3VALW

1

2

1

2

C538

1U_0603_10V4Z

C540

1U_0603_10V4Z

0.1U_0402_16V4Z

1

C556

2

10U_0805_10V4Z

1

C523

2

10U_0805_10V4Z

1

2

1U_0603_10V4Z

1

C148

C500

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C516

C532

2

0.1U_0402_16V4Z

1

2

1

2

C488
1U_0603_10V4Z

1

C510

2

1U_0603_10V4Z

1

2

+1.05VS

1

C547

0.1U_0402_16V4Z

2

1

2

+1.05VS

1

2

1

C546

0.1U_0402_16V4Z

1

C793
1U_0603_10V4Z

2

+3VALW

1

C493

0.1U_0402_16V4Z

2

A A

1

C499

0.1U_0402_16V4Z

2

+3VALW

1

C482

0.1U_0402_16V4Z

2

1

C486

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/05/15

3

+1.8VALW

1

C492

0.1U_0402_16V4Z

2

Compal Secret Data

Deciphered Date

1

C498

0.1U_0402_16V4Z

2

2009/05/15

+1.8VS +1.8VS

1

C513

0.1U_0402_16V4Z

2

2

1

C503

0.01U_0402_16V7K

2

Title

Size Document Number Rev

Custom

KSWXX M/B LA-4611P Schematic

Friday, August 01, 2008

Date: Sheet of

1

C551

0.1U_0402_16V4Z

2

1

C544

0.01U_0402_16V7K

2

Compal Electronics, Inc.

SIS968(4/5)-POWER

22 47

1

0.1

5

D D

C C

B B

4

U11E

K10

VSS

K11

VSS

K12

VSS

L10

VSS

L11

VSS

L12

VSS

L14

VSS

L15

VSS

L16

VSS

M10

VSS

M11

VSS

M12

VSS

M13

VSS

Gound

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX

AD26
AC25

M14
M15
N10

B10
B12
D11
D13
U15
U14
U13
U12
U11
U10
T14
T13
T12
T11
T10
R14
R13
R12
R11
R10
P14
P13
P12
P11
P10
N14
N13
N12
N11

P24
P23
N22
N26
N25
M24
M23

K22
G22

K24
K23

H24
H23
G26
G25
F24
F23
E26
E25
P16
M17
N17
P17
M16
N16
N15

L22
J22
L26

L25

J26
J25

3

VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ

USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS

AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA

U17
U16
T16
R16
R15
T17
P15
T15
Y21
V21
T21
R22
W23
U23

D14
E15
A15
B15
C16
D16
A17
B17
E17
C18
D18
A19
B19
E19
C20
D20
A21
B21
D23
D24
C25
C26
K13
K14
K15
K16
K17
L13
L17

AB6
AB7
AB12
AB13
AB14
AB15
AC2
AC3
AC4
AC5
AC7
AC12
AC14
AC15
AD2
AD3
AD4
AD5
AD7
AD12
AD14
AE1
AE2
AE3
AE4
AE6
AE7
AE9
AE11
AE13
AE14
AF2
AF3
AF4
AF6
AF9
AF11
AF13

2

1

SIS968-B0_TEBGA_570P

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/05/15

3

Compal Secret Data

Deciphered Date

2009/05/15

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SIS968(5/5)-GND

KSWXX M/B LA-4611P Schematic

Friday, August 01, 2008

1

23 47

of

0.1

A

B

C

D

E

F

G

H

14W SATA ODD Conn.

1 1

+5VS

0.1U_0402_16V4Z

1

2

1000P_0402_50V7K

2 2

SATA_DTX_C_IRX_N1<21>

SATA_DTX_C_IRX_P1<21>

C369

14W@

1

2

1

C370

14W@

C371

14W@

2

10U_0805_10V4Z

SATA_DTX_C_IRX_N1

SATA_DTX_C_IRX_P1

SATA_ITX_C_DRX_P1<21>
SATA_ITX_C_DRX_N1<21>

1 2

C372 0.01U_0402_16V7K

1 2

C373 0.01U_0402_16V7K

SATA_DTX_IRX_N1

SATA_DTX_IRX_P1

SATA_ITX_C_DRX_P1
SATA_ITX_C_DRX_N1

SATA_DTX_IRX_N1
SATA_DTX_IRX_P1

R373 1K_0402_1%@

1 2

+5VS

SATA ODD Conn.

Copy JIWA2 Symbol

JSATA1

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

DP

9

+5V

10

+5V

11

MD

12

GND

13

GND

OCTEK_SLS-13SB1G

Update FootPrint from
OCTEK_SLS-13SB1G_13P-T to
OCTEK_SLS-13SB1G_13P_RV-T

SATA HDD Conn.

+5VS +3VS

0.1U_0402_16V4Z

1

C366

2

1000P_0402_50V7K

1

C365

2

1U_0603_10V4Z

1

C367

2

10U_0805_10V4Z

1

C353

2

1

C354

2

10U_0805_10V4Z

1

C68

0.1U_0402_16V4Z

2

@

15W SATA ODD Conn.

+5VS_ODD

3 3

SATA_ITX_C_DRX_P1
SATA_ITX_C_DRX_N1
SATA_DTX_IRX_N1
SATA_DTX_IRX_P1

4 4

A

0.1U_0402_16V4Z

1

2

1000P_0402_50V7K

R374 0_0402_5%
R375 0_0402_5%
R376 0_0402_5%
R377 0_0402_5%

1

C381

15W@

C382

15W@

2

12

15W@

12

15W@

12

15W@

12

15W@

+5VS +5VS_ODD

1

C380

15W@

2

10U_0805_10V4Z

SATA_ITX_C_DRX_P1_R
SATA_ITX_C_DRX_N1_R
SATA_DTX_IRX_N1_R
SATA_DTX_IRX_P1_R

1 2

R778 0_1206_5%15W@

1 2

R779 0_1206_5%15W@

B

SATA_ITX_C_DRX_P1_R
SATA_ITX_C_DRX_N1_R

SATA_DTX_IRX_N1_R
SATA_DTX_IRX_P1_R

R378 1K_0402_1%@

1 2
+5VS_ODD

C

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0

SATA ODD Conn.

SATA_DTX_C_IRX_N0<21>
SATA_DTX_C_IRX_P0<21>

Copy JIWA2 Symbol

JSATA2

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

DP

9

+5V

10

+5V

11

MD

12

GND

13

GND

OCTEK_SLS-13SB1G

Update FootPrint from
OCTEK_SLS-13SB1G_13P-T to
OCTEK_SLS-13SB1G_13P_RV-T

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2008/05/15 2009/05/15

E

Compal Secret Data

Deciphered Date

SATA_ITX_C_DRX_P0<21>
SATA_ITX_C_DRX_N0<21>

1 2

C400 0.01U_0402_16V7K

1 2

C395 0.01U_0402_16V7K

6/18 Change symbol from JHTXX by Ivan

F

SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0

SATA_DTX_IRX_N0
SATA_DTX_IRX_P0

+3VS

+5VS

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

HDD & ODD Connector

KSWXX M/B LA-4611P Schematic

G

JSATA3

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21
22

FOX_LD2122H-S43_NR

CONN@

(NEW)

Change Library

Update Symbol
SP01000G800
FOX_LD2122H-S43_NR

25

V12

GND

26

V12

GND

Manually update pin number

of

24 47Friday, August 01, 2008

H

0.1

5

+3VS

C496 0.1U_0402_16V4Z

5

U32

R401 33_0402_5%

D D

SB_DPRSLPVR<20>

1 2

C464

0.01U_0402_16V7K

1

@

2

4

Vcc

A2Y

1

NC

G

NL17SZ17DFT2G_SOT353-5

3

4

1 2

R414 33_0402_5%

1 2

Connecte to CPU

PM_DPRSLPVR_D <46> SB_DPRSLPVR<20>

3

R391 33_0402_5%

1 2

C460

0.01U_0402_16V7K

@

2

+3VS

C448 0.1U_0402_16V4Z

1 2

1

5

U24

P

NC

A2Y

G

1

2

NL17SZ14DFT2G_SOT353-5

3

R842 33_0402_5%

4

1 2

1

DPRSTP_N_INV

Use SA00001N400 FootPrint

R553 0_0402_5%@

1 2

8/1 Rotate

R170

1.05K_0402_1%

+3VS

R171

1.05K_0402_1%

R172

@

200K_0402_5%

8/1 Rotate

+1.05VS

12

R157

300_0402_5%

12

R165

300_0402_5%

7/20 Reserved

C C

DPRSTP_N_INV

H_DPSLP_N_LS

U40

1

A1

2

GND

3

A2

NC7WZ07P6X_NL_SC70-6

VCC

Y1

5

+3VALW

H_DPSLP#

4

Y2

DPRSTP_N_INV

H_DPSLP_N_LS

C173

0.01U_0402_16V7K

1

@

2

H_DPRSTP#

6

8

U10

EN

7

VREF2

6

SCL2

5

SDA2

2

VREF1

3

SCL1

4

SDA1

GND

PCA9306DCUR_VSSOP8

1

@

H_DPRSTP# <5,46>
H_DPSLP# <5>

+3VS +3VS

C450 0.1U_0402_16V4Z

1 2

B B

CPUSTP_N_OLD<20>

A A

R372 499_0402_1%

1 2

R380 33_0402_5%

C447

100P_0402_50V8J

1

2

1

C451

@

0.01U_0402_16V7K

2

5

Vcc

A2Y

NC

G

U23

NL17SZ17DFT2G_SOT353-5

3

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C458 0.1U_0402_16V4Z

1 2

Use SA00001N400 FootPrint

4
1

5

4

Vcc

A2Y

1

NC

G

U31

NL17SZ17DFT2G_SOT353-5

3

Use SA00001N400 FootPrint

Issued Date

1 2

R371 33_0402_5%

1 2

R379 33_0402_5%

2008/05/15

3

Compal Secret Data

Deciphered Date

+3VS

5

U33

2

P

B

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

+3VS

5

U22

2

B

Vcc

Y

1

A

G

NC7SZ32P5X_NL_SC70-5

3

1 2

C446 0.1U_0402_16V4Z

H_DPSLP_N_LS

4

1 2

C452 0.1U_0402_16V4Z

CPUSTP#

4

2009/05/15

2

CPUSTP# <14>

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Other

Custom

KSWXX M/B LA-4611P Schematic

Friday, August 01, 2008

1

25 47

0.1

5

4

3

2

1

SD,MMC,MS muti-function pin define

CS

SK

DI

DO

SD Card
PIN Name

SDWP#
SDCD#
SDCDAT1

SDCDAT1
SDCDAT0
SDCDAT7

SDCDAT6
SDCCLKSP11
SDCDAT5
SDCDAT4

SDCDAT3
SDCDAT2

CARD_EECS

1

CARD_EESK

2

CARD_EEDO

3

CARD_EEDI

4

MDIO

1

2

+VCC_3IN1

PIN Name
SP1

SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10

SP12
SP13
SP14
SP15
SP16
SP17
SP18
SP19

U42

8

VCC

7

NC

6

NC

5

GND

AT93C46-10SI-2.7_SO8

@

SDDAT0_MSD0
XDD4_SDDAT1
SDDAT2_XDRE#
SDDAT3_XDWE#
SD_CLK
SD_WP
SD_CMD
SD_CD#

SP6
MS_CLK

MS_INS#
SDDAT0_MSD0
MS_BS
SDDAT6_MSD3
SDDAT7_MSD2

Change BOM control C796 R843
for 5158 and 5158E co-layout
Michael 2008/6/18

D D

+3VS

C C

B B

Add C823 C824 for 5158 and 5158E co-layout
Michael 2008/6/18

0.1U_0402_16V4Z

1

C799
1U_0603_10V4Z

2

1U_0603_10V4Z

CLK_48M_CR<14>

Add R852 for 5158 and
5158E co-layout
Michael 2008/6/18

100K_0402_5%

1

2

0.1U_0402_16V4Z

+3VS

12

C804

+VCC_OUT

12

R859

5158@

C800

+3VS

+3VALW

R846
100K_0402_5%

12

@

499K_0402_1%

0_0402_5%

1 2

0.1U_0402_16V4Z

1

2

R850

R852

5158E@

0.1U_0402_16V4Z

1

C823

C801

2

5158@

0.1U_0402_16V4Z

R845 0_0603_5%

R849

1 2

0_0402_5%

Change C804 package from 0402 to 0603
Change R850 part number
Michael 2008/5/30

5158@

R844 0_0603_5%

1 2

@

1 2

4.7U_0805_10V4Z

CARD_RST#

CARD_XTLI

1

2

+3VS

1

C810

2

@

2

1

C824

2

C802

Change C802 package from 0603 to 0805
Michael 2008/5/30

5158@

Y5

CARD_XTLO

1 2

12MHZ_16P_6X12000012

R854

5158@

270K_0402_5%

C806
6P_0402_50V8J

5158@

U43

3

VIN

VOUT

4

VIN/CE

VOUT

2

GND

RT9701-PB_SOT23-5

5158@

1

AV_PLL

C803

1

0.1U_0402_16V4Z

2

1

2

1
5

C797
1U_0603_10V4Z

USB20_N6<21>
USB20_P6<21>

6.19K_0402_1%

C807
6P_0402_50V8J

5158@

1

C811

2

1U_0603_10V4Z

@

+VCC_OUT

12

R853

+VCC_3IN1

12

2

C798

0.1U_0402_16V4Z

1

+3V3_IN
CARD_RST#
MODE_SEL
CARD_XTLO
CARD_XTLI

USB20_N6
USB20_P6

R860
100K_0402_5%

@

12

R855
0_0402_5%

1
3
7

9
11
33

8
44
45
47
48

4

5
14

2
12

32

6
46

C796

47P_0402_50V8J

5158@

U41

AV_PLL
NC
NC
CARD_3V3
D3V3
D3V3

3V3_IN
RST#
MODE_SEL
XTLO
XTLI

DM
DP
GPIO0

RREF
DGND

DGND
AGND

AGND

RTS5158E-GR_LQFP48_7X7

5158E@

U41

S IC RTS5158-GR LQFP 48P CARD READER

5158@

+VCC_OUT

MODE_SEL

12

1

R843
10K_0402_5%

2

5158@

XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17

SD_DAT2/XD_RE#_SP16

SD_DAT3/XD_WE#_SP15

SD_DAT4/XD_WP#/MS_D7_SP13

SD_DAT5/XD_D0/MS_D6_SP12
SD_CLK/XD_D1/MS_CLK_SP11
SD_DAT6/XD_D7/MS_D3_SP10

SD_DAT7/XD_D2/MS_D2_SP8
SD_DAT0/XD_D6/MS_D0_SP7
SD_DAT1/XD_D3/MS_D1_SP6

XD_RDY_SP14

MS_INS#_SP9

XD_D4/SD_DAT1_SP4

R856

1 2

0_0603_5%5158E@

4.7U_0805_10V4Z

XD_D5_SP5

SD_CD#_SP3

SD_WP_SP2

XD_CD#_SP1

XTAL_CTR

C822

VREG

MS_D4

EEDI

MS_D5

EEDO
EECS
EESK

SD_CMD

NC

10
22
30

43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18

13
24

15
16
17
36

+VCC_3IN1

C808

10U_0805_10V4Z

MS_CLK SD_CLK

12

R857

10_0402_5%

10P_0402_50V8J

AV_PLL

SDDAT2_XDRE#
SDDAT3_XDWE#

SDCLK_MSCLK
SDDAT6_MSD3
MS_INS#
SDDAT7_MSD2
SDDAT0_MSD0
SP6
MS_BS
SP4
SD_CD#
SD_WP

CARD_EEDI

5158E@

1 2

R851 0_0402_5%

CARD_EEDO
CARD_EECS
CARD_EESK
SD_CMD

@

1

C812

@

2

5158@

R873 0_0402_5%

1 2

5158E@

R874 0_0402_5%

SP4 XDD4_SDDAT1

1 2

Add R873 R874 for 5158 and
5158E co-layout
Michael 2008/6/18

40mil

@

1

C809

2

0.1U_0402_16V4Z

1

2

10P_0402_50V8J

R847 0_0402_5%

1 2

R848 0_0402_5%

1 2

+3VS

XDD4_SDDAT1SP6

R858

10_0402_5%

C813

SD_CLK
MS_CLK

0.1U_0402_16V4Z

12

@

1

@

2

+3VS

C805

@

MMC Card
PIN Name

JREAD1

6

VDD_SD

9

DAT0_SD

10

DAT1_SD

2

DAT2_SD

3

CD/DAT3_SD

7

CLK_SD

11

WP_SD

4

CMD_SD

1

CD_SD

5

VSS_SD

8

VSS_SD

19

VCC_MS

13

VCC_MS

14

SCLK_MS

16

INS_MS

18

SDIO_MS

20

BS_MS

15

RESERVED_MS

17

RESERVED_MS

21

VSS_MS

12

VSS_MS

22

GND

23

GND

PROCO_MDR019-C0-1202

CONN@

MS Card
PIN Name

MSWR
MSBS
MSCDAT1
MSCDAT0
MSCDAT2
MS_INS#
MSCDAT3
MSCCLK
MSCDAT6
MSCDAT7

Add C822 4.7u and reserve C808 10u

A A

5

4

for cost down Michael 2008/5/30

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/05/15 2009/05/15

3

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom
Date: Sheet

Compal Electronics, Inc.

RTS5158E Cardreader

KSWXX M/B LA-4611P Schematic

26 47Friday, August 01, 2008

1

of

0.1

5

D D

C C

4

3

2

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/05/15 2009/05/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

None

KSWXX M/B LA-4611P Schematic

1

of

27 47Friday, August 01, 2008

0.1

5

4

3

2

1

+3VALW

T1

TPRX+
TPRX-

PWFBOUT

R33 0_0603_5%

1

C56

0.1U_0402_16V4Z

R30 0_0603_5%

2

1

C50

0.1U_0402_16V4Z

2

Other CG use 1206

PWFBOUT

1

C95

10U_0805_10V4Z

2

Place C464, C465, L48 close to PWFBOUT and place C466 close to PWFBIN.

LED2

D3 RLS4148_LL34-2

LED3

D4 RLS4148_LL34-2

1

12

C31 680P_0402_50V7K

R12 150_0402_1%

1 2

8/1 Change R12 from 300ohm to 150ohm

For EMI => Change C31,C38 from SE071680J80
(68pF) to SE074681K80 (680pF)

L61

1 2
12

R34 75_0402_5%

1 2

R29 75_0402_5%

1 2

D33

1

PSOT24C_SOT23

@

change T1 from SP050001210(BOTHHAND)to
SP050001310(Lankcom)

12

12

D34

PSOT24C_SOT23

@

R863 75_0402_5%
R864 75_0402_5%

R865 75_0402_5%
R575 75_0402_5%

+3V_LAN

1

2

RTSET
ISOLATE

RPTR
SPEED
DUPLEX
ANE
LDPS
RESETB

+3V_LAN

FBM-L11-160808-601LMT_0603

1

1

C149

C147

0.1U_0402_16V4Z

2

2

+3V_LAN

1

C122

0.1U_0402_16V4Z

2

+3V_LAN_AVDD

PWFBOUT
PWFBIN

TPRX­TPRX+

TPTX­TPTX+

R351 2K_0402_1%

1 2

R361 4.7K_0402_5%

1 2

R356 4.7K_0402_5%

1 2

R353 4.7K_0402_5%

1 2

R123 4.7K_0402_5%

1 2

R116 4.7K_0402_5%

1 2

R357 4.7K_0402_5%

1 2

R363 0_0402_5%

1 2

R359 0_0402_5%@

1 2

L6

1 2

LED0 LINKLED#

Other CG use 1210

+3V_LAN

D D

R350 1.5K_0402_1%

1 2

R366 4.7K_0402_5%@

1 2

R152 4.7K_0402_5%@

1 2

R368 4.7K_0402_5%

1 2

R367 4.7K_0402_5%

1 2

R153 4.7K_0402_5%

1 2

R154 4.7K_0402_5%

1 2

R364 4.7K_0402_5%

1 2

R97 4.7K_0402_5%

1 2

R354 4.7K_0402_5%

1 2

C C

MDC<20>
MDIO<20>
TXD0<20>
TXD1<20>
TXD2<20>
TXD3<20>

TXEN<20>
TXCLK<20>
RXDV<20>
RXD0<20>
RXD1<20>
RXD2<20>
RXD3<20>
RXCLK<20>
COL<20>
CRS<20>
RXER<20>

+3V_LAN

B B

1 2

25MHZ_20PF_6X25000017

C115
33P_0402_50V8J

MDC
MDIO
TXD0
TXD1
TXD2
TXD3
TXEN

R156 33_0402_5%

1 2

R109 33_0402_5%

1 2

R117 33_0402_5%

1 2

R122 33_0402_5%

1 2

R129 33_0402_5%

1 2

R135 33_0402_5%

1 2

R138 33_0402_5%

1 2

R861 33_0402_5%

1 2

R862 33_0402_5%

1 2

R872 33_0402_5%

1 2

R360 4.7K_0402_5%

1 2

Y3

C117
33P_0402_50V8J

MDIO
ISOLATE
COL
LED0
LED1
LED2
LED3
LED4
RXER

CRS

TXC
RXD_V
RXD_0
RXD_1
RXD_2
RXD_3
RXC
COL_R
CRS_R
RXER_R

MII_SNIB

LAN_XTAL_IN
LAN_XTAL_OUT

LED0
LED1
LED2
LED3
LED4

R149
0_0603_5%

1

C150
10U_0805_10V4Z

2

U8

25

MDC

26

MDIO

6

TXD0

5

TXD1

4

TXD2

3

TXD3

2

TXEN

7

TXC

22

RXDV

21

RXD0

20

RXD1

19

RXD2

18

RXD3

16

RXC

1

COL

23

CRS

24

RXER/FXEN

44

MII/SNIB

46

X1

47

X2

9

PHYAD0/LED0

10

PHYAD1/LED1

12

PHYAD2/LED2

13

PHYAD3/LED3

15

PHYAD4/LED4

RTL8201CL-VD-LF

+3V_LAN

MII I/F

CLK

Other CG use

4.7U_0805_10V4Z

Place L47, C460, C462, C463 as close to each power pin
as possible.

DVDD33
DVDD33

AVDD33

PWFBOUT

PWFBIN

PWRGND

TPRX-

TPRX+

TPTX-

TPTX+

RTSET

ISOLATE

RPTR

SPEED

DUPLEX

ANE

LDPS

RESETB

Network I/F

DGND
DGND
DGND

AGND
AGND

C121

14
48

36

32
8

30
31

33
34

28
43

40
39
38
37
41
42

27

NC

11
17
45
29
35

0.1U_0402_16V4Z

PHY/LED

7/30 modified from 27P to 33P

TPRX-

R23 49.9_0402_1%

TPRX+

TPTX-

A A

TPTX+

1 2

R26 49.9_0402_1%

1 2

R36 49.9_0402_1%

1 2

R41 49.9_0402_1%

1 2

C41

1 2

C60

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3V_LAN_AVDD

1

C102

0.1U_0402_16V4Z

2

+3V_LAN

12

R362

4.7K_0402_5%

1

C435

0.1U_0402_16V4Z

2

+3V_LAN

PCI_RST# <19,29,30,31,33>

8/30 Add L61 FBMA-L10-160808-800LMT_0603 for EMI

R14 300_0402_5%

1 2

C38 680P_0402_50V7K

FBMA-L10-160808-800LMT_0603

RXCT
TXCT

RCT

TCT
TPTX+
TPTX-

7/20 Swap p in 1,2 to 7,8 and 16,15 to 10,9

L5

FBM-L11-160808-601LMT_0603

1

C101

0.1U_0402_16V4Z

2

8/27 Change D7,D8 footprint from RLS4148_LL34-2 to LL34

8/1 Change D7,D8 from SC1B751V010 to SC11N414880

2
3

1 2
1 2

1 2
1 2

2

+3V_LAN

3

1

RD+

2

RD-

3

CT

4

NC

5

NC

6

CT

7

TD+
TD-8TX-

350uH_NS0013LF

12

12
11

RX-

RX+
TX­TX+

10

C42

1 2

1000P_1206_2KV7K

C26

0.1U_0402_16V4Z

RX+

RX-

CT
NC
NC

CT

TX+

PWFBIN

1

C153

0.1U_0402_16V4Z

2

Lan Conn.

JP23

Amber LED+
Amber LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+
Green LED-

9

Green LED+

TYCO_3-440470-4

<BOM Structu re>

1

2

16
15
14
13
12
11

TX+

10

TX-

9

SHLD2
SHLD1

SHLD2
SHLD1

1

C27

4.7U_0805_10V4Z

2

RX+
RX­RXCT

TXCT

ACTIVITY LED

16
15

14
13

LINKLED

LANGND

LED0 LED1 LED2 LED3 LED4
Link Dupx 10Act 100Act COL

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/05/15 2009/05/15

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

LAN RTL8201CL

KSWXX M/B LA-4611P Schematic

28 47Friday, August 01, 2008

1

0.1

A

1 1

B

C

D

E

Kill SWITCH

+3VALW

2

3

D21

DAN217_SC59

@

1

3

11223

SW2

2 2

1BS003-1211L_3P

01/22 change sw2 P/N DE100000300
11/23 Chan ge SW2 to corre ct symbol (by Andy)

KILL_SW#

+3VALW

R461
100K_0402_5%

1 2

KILL_SW# <31>

Mini-Express Card for WLAN

8/31Add R593 connect net WLAN_ACTIVE to JP22 pin3

SB_PCIE_WAKE#<7,21,30>

8/31Add R594 connect net BT_ACTIVE to JP22 pin5

C206

WLAN_ACTIVE
BT_ACTIVE

WLAN_CLKREQ#<14>

PCIE_CLK_WLAN#<14>
PCIE_CLK_WLAN<14>

PCIE_PTX_C_IRX_N0<20>
PCIE_PTX_C_IRX_P0<20>

PCIE_ITX_C_PRX_N0<20>
PCIE_ITX_C_PRX_P0<20>

1

0.1U_0402_16V4Z

2

A

WLAN_ACTIVE<33>
BT_ACTIVE<33>

3 3

4 4

0.01U_0402_16V7K

C205

R866 0_0402_5%
R867 0_0402_5%

1

4.7U_0805_10V4Z

2

1 2
1 2

WLAN_CLKREQ#
CLK_PCIE_WLAN#

CLK_PCIE_WLAN

MINI_VCC

+3VS +1.5VS

1

C199

2

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

0.01U_0402_16V7K

***

JMIN2

1

1

3

3

5

5

7

7

9

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

GND1

GND2

FOX_AS0B226-S56N-7F

ME@

1

C241

0.1U_0402_16V4Z

2

2

2

4

4

6

6

8

8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

B

C207

MINI_RF_OFF#
PCI_RST#
MINI_VCC

DCLK
DDATA

WLAN_LED#

1

4.7U_0805_10V4Z

2

R223

1 2

100K_0402_5%

@

C203

PCI_RST# <19,28,30,31,33>

DCLK <14,30>
DDATA <14,30>

WLAN_LED# <37>

+3VS

1

2

+1.5VS +3VS

MINI_VCCSB_PCIE_WAKE#

L68

1 2

KC FBM-L11-201209-221LMAT_0805

12/13 Add

+3VS

12

R462

10K_0402_5%

13

D

S

RF_ON#

2

G

Deciphered Date

RF_ON# <31>

SSM3K7002FU_SC70-3

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/05/15 2009/05/15

Q45

Compal Secret Data

Please place these caps between JMIN1 and JMIN2

DCLK

C757 100P_0402_50V8J@

DDATAMINI_RF_OFF#

Title

Size Document Number Rev

D

Date: Sheet of

1 2

C758 100P_0402_50V8J@

1 2

Compal Electronics, Inc.

Mini-Card/Kill SW

KSWXX M/B LA-4611P Schematic

29 47Friday, August 01, 2008

E

0.1

A

B

C

D

E

New Card Socket (Left/TOP)

USB20_N2<21>
USB20_P2<21>

DCLK<14,29>

DDATA<14,29>

+1.5VS_CARD1

+3VALW_CARD1
+3VS_CARD1

CP_PE#<20>

USB20_N2
USB20_P2

CP_USB#

DCLK
DDATA

SB_PCIE_WAKE#

PERST1#

EXP_CLKREQ#
CP_PE#
PCIE_CLK_EXP#
PCIE_CLK_EXP

PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P1

PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P1

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

27
28

JAQ60

JEXP1

GND
USB_D­USB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLK­REFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND

GND1

GND3

GND2

GND4

SANTA_130810-1

CONN@

29
30

C695

0.1U_0402_16V4Z

C697

0.1U_0402_16V4Z

C699

0.1U_0402_16V4Z

+3VS_CARD1

1

2

+1.5VS_CARD1

1

2

+3VALW_CARD1

1

2

1

C696

@

4.7U_0805_10V4Z

2

1

C698

@

4.7U_0805_10V4Z

2

1

C700

@

4.7U_0805_10V4Z

2

SB_PCIE_WAKE#<7,21,29>

EXP_CLKREQ#<14>
PCIE_CLK_EXP#<14>

PCIE_CLK_EXP<14>

PCIE_PTX_C_IRX_N1<20>
PCIE_PTX_C_IRX_P1<20>

PCIE_ITX_C_PRX_N1<20>
PCIE_ITX_C_PRX_P1<20>

New Card Power Switch

New Card

C694

0.1U_0402_16V4Z

1 1

+3VALW

+3VALW

12

C689

0.1U_0402_16V4Z

12

12

C693

PCI_RST#<19,28,29,31,33>
SYSON<31,39>
SUSP#<31,39,45>

12

R635 100K_0402_5%

12

R636 100K_0402_5%

+1.5VS

+3VS

0.1U_0402_16V4Z

PCI_RST#
SYSON
SUSP#
CP_PE#
CP_USB#

internal pull high to 3.3Vaux-in
EC need setting at Hi-Z & output Low

U18

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

R5538D001-TR-F_QFN20_4X4~D

1.5Vout

1.5Vout

3.3Vout

3.3Vout

OC#

PERST#

GND

+3VALW_CARD1

PERST1#

40 mils

+1.5VS_CARD1

+3VS_CARD1

60 mils

40 mils

11
13

3
5

15
19
8
16

NC

7

Change to GMT PartNumber

Update FootPrint from

2 2

SANTA _13181060-5_26P-T to
SANTA_130810-1_26P

USB IO Conn.

+USB_VCCC

80 mils

OUT
OUT

NC

OC

USB20_N0
USB20_P0

USB20_N4
USB20_P4

USB20_N5
USB20_P5

1

C768
10U_0805_10V4Z

2

+USB_VCCC

8
7
6
5

R468
10K_0402_5%

1 2

1

C568

0.1U_0402_16V4Z

2

@

USB20_N0<21>
USB20_P0<21>

USB20_N4<21>
USB20_P4<21>

150u
ESR 0.9 ohm

3 3

4 4

Package(L*W*H)7.3*4.3*2.9
Rating 6.3V

+USB_VCCC

+USB_VCCC

1

+

C564

@

150U_D_6.3VM

2

+5VALW +3VALW

1

C566

4.7U_0805_10V4Z

2

USB2_ON#<31>

USB20_N5<21>
USB20_P5<21>

W=80mils

1

C563
470P_0402_50V7K

2

copy LM75CIMMX-3_MSOP8
footprint

U26

1

GND

2

IN

3

IN

4

EN#

G545A2P8U MSOP 8P

JP52

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

ACES_85201-20051

11/29 change this symbol's footprint as
ADT7421ARMZ-REEL_MSOP8

R691 0_0402_5%

12

USB_OC#45 <21>
USB_OC#06 <21>

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

NewCard & USB Connector

KSWXX M/B LA-4611P Schematic

30 47Friday, August 01, 2008

E

0.1

of

5

L29 FBM-11-160808-601-T_0603

+3VALW +EC_AVCC

1 2

0.1U_0402_16V4Z

1 2

L27 FBM-11-160808-601-T_0603

C355

2

1

ECAGND

1

C363
1000P_0402_50V7K

2

+3VALW +EC_DVCC

C417

0.1U_0402_16V4Z

C396

0.1U_0402_16V4Z

1

1

2

2

20 mils

D D

22P_0402_50V8J@

R331

+3VALW

EC_SMB_CK1
EC_SMB_DA1

KB_RST#

C426

1 2

47K_0402_5%

0.1U_0402_16V4Z

R347 10K_0402_5%

1 2

R349 0_0402_5%

KB_RST#<20>

CLK_PCI_EC<14>

+3VALW

PCI_PME#<20>

+5VALW

C C

1 2

R317 4.7K_0402_5%

1 2

R310 4.7K_0402_5%

1 2

R711 10K_0402_5%

1 2

R712 10K_0402_5%

1 2

R713 10K_0402_5%

ISP MODE SUPPORT

@

1 2
1 2

@

1 2

@

1 2

1 2

SPI_CS#<33>
SPI_CLK_R<33>
SPI_SI<33>

EC_TX_P80_DATA
EC_RX_P80_CLK

12

EC_SMB_CK2
EC_SMB_DA2

C357

100P_0402_50V8J

FRD#SPI_SO

FSEL#SPICS#

SUSP#

ACK_GUEST ACK_GUEST_R

SPI_CLK_R
SPI_SI

5

R327 4.7K_0402_5%

+3VS

R309 4.7K_0402_5%
R308 4.7K_0402_5%

+3VALW

B B

R325 100K_0402_1%

R335 100K_0402_1%

C413 100P_0402_50V8J@

ACK_GUEST<34>

A A

EC DEBUG PORT

+3VALW

1 2

R342 0_0402_5%
D22

@

2 1

RB751V_SOD323

@

12

L57 0_0402_5%<EMI>
L58 0_0402_5%<EMI>

CLK_GUEST_R
DATA_GUEST_R
ACK_GUEST_R

KSO3

1

@

2

R814 0_0402_5%

R341 0_0402_5%
R332 0_0402_5%
R326 0_0402_5%

JP61

1

1

2

2

3

3

4

4

ACES_85205-0400

ME@

12

R340 10_0402_5%

1

C391

2

12

CYPRESS@

1 2

CYPRESS@

1 2

KSO[0..15]<32>
KSI[0..7]<32>

1

C358

@

100P_0402_50V8J

2

DATA_GUEST ESB_DAT

CYPRESS@

1 2

1 2
1 2
1 2

GATEA20<20>

SERIRQ<20,33>
LPC_FRAME#<20,33>
LPC_AD3<20,33>
LPC_AD2<20,33>
LPC_AD1<20,33>
LPC_AD0<20,33>

PCI_RST#<19,28,29,30,33>
EC_SCI#<20>

PM_CLKRUN#<20>

EC_PME#

CLK_GUEST
DATA_GUEST

KSO[0..15]
KSI[0..7]

EC_SMB_CK1<33,41>
EC_SMB_DA1<33,41>
EC_SMB_CK2<4>
EC_SMB_DA2<4>

PM_SLP_S3#<20>
PM_SLP_S5#<20>
EC_SMI#<20>

ENE@

LID_SW#<34>

L55 0_0402_5%<EMI>

1 2

L56 0_0402_5%<EMI>

1 2

ENE@

P_USB#<34>
USB2_ON#<30>
FAN_SPEED1<4>

EC_TX_P80_DATA<12,13>
EC_RX_P80_CLK<12,13>
ON/OFF#<34>
SM_KEY_LED#<34>
NUM_LED#<34>

FSEL#SPICS#SPI_CS#
SPI_CLK
FWR#SPI_SI

12P_0402_50V8J

Modify X2 part number from SJ132P7KW10
to SJ132P7K220 for cost down; Michael 2008/5/30

XCLKI XCLKO

C820

4

L28

1 2

FBM-11-160808-601-T_0603

C386

0.1U_0402_16V4Z

C406

0.1U_0402_16V4Z

GATEA20
SERIRQ

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_EC
PCI_RST#
EC_RST#
EC_SCI#

@

1 2

R329 0_0402_5%

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PM_SLP_S5#
EC_SMI#
LID_SW#

P_USB#
USB2_ON#
FAN_SPEED1

ACK_GUEST_R

EC_TX_P80_DATA
EC_RX_P80_CLK
ON/OFF#
SM_KEY_LED#
NUM_LED#

XCLKI
XCLKO

4

1

IN

OUT

NC3NC

X2

2

32.768KHZ_12.5P_1TJS125BJ2A251

1

2

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

ESB_CLKCLK_GUEST

4

1

2

122
123

C821
12P_0402_50V8J

20 mils

C815

1000P_0402_50V7K

10
12

13
37
20
38

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

77
78
79
80

14
15
16
17
18
19
25
28
29
30
31
32
34
36

C359

1000P_0402_50V7K

1

1

2

2

U21

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

LPC & MISC

LAD0
PCICLK

PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

6

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

XCLK1
XCLK0

KB926QFA1 LQFP 128P

Int. K/B
Matrix

Use KB926C0

3

+EC_AVCC

2

20 mils

9

22

33

96

111

125

67

VCC

VCC

VCC

VCC

VCC

VCC

PWM Output

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

SM Bus

GPIO

GND

GND

11

24

35

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

ACOFF/FANPWM2/GPIO13

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

AD Input

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO54

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

ICH_PWROK/GPXO06

GPO

PM_SLP_S4#/GPXID1

GPI

GND

AGND

GND

GND

69

94

113

ECAGND

FANPWM1/GPIO12

ADP_I/AD2/GPIO3A

AD3/GPIO3B

AD4/GPIO42

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CAPS_LED#/GPIO53
SUSP_LED#/GPIO55

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXO05

EC_SWI#/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

INVT_PWM

21

BEEP#

23
26

ACOFF

27

BATT_TEMP

63

BATT_OVP

64

ADP_I

65
66
75

MB_ID

76

DAC_BRIG

68

EN_FAN1

70

IREF

71

CHGVADJ

72

CLK_GUEST_R

83

DATA_GUEST_R

84

POWER_USB_LED#

85
86

TP_CLK

87

TP_DATA

88

R320 10K_0402_5%@

97
98

GPXOA02 ACK_GUEST

99

SM_KEY#

109

FRD#SPI_SO

119

FWR#SPI_SI

120

SPI_CLK

126

FSEL#SPICS#

128

S3AUXSW#

73

PSON#

74

FSTCHG

89

CHARGE_LED0#

90

CAPS_LED#

91

CHARGE_LED1#

92

PWR_LED#

93

SYSON

95

VR_ON

121

ACIN

127

AUX_PWRGDPM_SLP_S3#

100

EC_LID_OUT#

101

EC_ON

102
103

SB_PWRGD

104

BKOFF#

105

RF_ON#

106

BT_ON#

107
108

KILL_SW#

110

ENBKL_Q

112

EAPD

114

EC_THERM#

115

SUSP#

116

PBTN_OUT#

117

EC_PME#

118
124

2

1

ENBKL<18>

L54 0_0402_5%

1 2

R812 0_0402_5%TONTEK@

+3VS

C518

4.7U_0805_10V4Z
R869 10K_0402_5%

+3VALW

INVT_PWM <16>
BEEP# <35>

ACOFF <42>

ECAGND

1 2

C816 0.01U_0402_16V7K

BATT_OVP <42>
ADP_I <42>

DAC_BRIG <16>
EN_FAN1 <4>
IREF <42>
CHGVADJ <42>

TONTEK@

L53 0_0402_5%<EMI>

1 2

TONTEK@

1 2

<EMI>

POWER_USB_LED# <34>
TP_CLK <33>

1 2

R868 15K_0402_5%

1 2

1 2

R546

1 2

47K_0402_5%

TP_DATA <33>

SM_KEY# <34>

FRD#SPI_SO <33>

S3AUXSW# <8>
PSON# <20>
FSTCHG <42>
CHARGE_LED0# <37>
CAPS_LED# <34>
CHARGE_LED1# <37>
PWR_LED# <34,37>
SYSON <30,39>
VR_ON <46>
ACIN <40,42>

AUX_PWRGD <9,20>
EC_LID_OUT# <20>
EC_ON <34>

SB_PWRGD <9,20>
BKOFF# <16>
RF_ON# <29>
BT_ON# <33>

KILL_SW# <29>
EAPD <35,36>

EC_THERM# <20>
SUSP# <30,39,45>
PBTN_OUT# <20>

No stuff when use KB926C0

KB926 SPI STRAP PIN

C

2

B

E

3 1

CLK_GUEST

DATA_GUEST

Q39
MMBT3904_SOT23

Level Shift Circuit

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/05/15

3

Compal Secret Data

Deciphered Date

2009/05/15

2

2

B

E

1

+3VALW

12

R312

RA@

Ra

100K_0402_5%

MB_ID

1

C356

0.1U_0402_16V4Z

BATT_TEMP <41>

CLK_GUEST <34>
DATA_GUEST <34>

ENBKL_Q

C

Q40
MMBT3904_SOT23

3 1

Custom

Date: Sheet

TP_CLK
TP_DATA

PCI_RST#

P_USB#
SM_KEY#

GPXOA02

AUX_PWRGD
BEEP#
SYSON
EC_SCI#
EC_THERM#
SERIRQ

SB_PWRGD
PBTN_OUT#
EN_FAN1

ACIN
VR_ON
ENBKL_Q

Title

Size Document Number Rev

Compal Electronics, Inc.

EC_KB926

KSWXX M/B LA-4611P Schematic

Friday, August 01, 2008

2

R316 4.7K_0402_5%
R315 4.7K_0402_5%

R256 100K_0402_5%

1 2

R64 10K_0402_5%
R60 10K_0402_5%

R813 10K_0402_5%

CLK_GUEST
DATA_GUEST

22P_0402_50V8J

1

1

2

2

100P_0402_50V8J

100P_0402_50V8J

C401

C419

C389 100P_0402_50V8J
C819 100P_0402_50V8J
C374 100P_0402_50V8J

Rb

1 2
1 2

TONTEK@

1 2

C719

@
<EMI>

1

2

100P_0402_50V8J

C416

1 2
1 2
1 2

1

12

R311

14_A@

0_0402_5%

1

2

1

2

100P_0402_50V8J

C418

C360

1

2

100P_0402_50V8J

C415

C361

31 47

12
12

1

C720

@

22P_0402_50V8J

2

<EMI>

1

2

100P_0402_50V8J

100P_0402_50V8J

C817

1

2

100P_0402_50V8J

100P_0402_50V8J

C818

of

+5VS

+3VALW

+5VALW

1

2

1

2

0.1

5

INT_KBD Conn.

4

3

2

1

D D

C C

For KSW91 For KSW01

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

JP43

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25
GND
GND

ACES_88502-2501

CONN@

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

27
26

JP44

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25
GND
GND

ACES_88502-2501

CONN@

27
26

KSI[0..7]
KSO[0..15]

Delete C525~C548 SE071101J80 (100pF)
Add SI102101K80 (CP : 100pF)
(EMI Recommend)

KSI4
KSI5
KSO0
KSI2

KSI1
KSI7
KSI6
KSO9

KSO2
KSO4
KSO7
KSO8

KSI[0..7] <31>
KSO[0..15] <31>

CP1

<EMI>

81

2

7

3

6

4 5

100P_1206_8P4C_50V8
CP2

<EMI>

81

2

7

3

6

4 5

100P_1206_8P4C_50V8
CP3

<EMI>

81

2

7

3

6

4 5

100P_1206_8P4C_50V8

KSO6
KSO3
KSO12
KSO13

KSI3
KSO5
KSO1
KSI0

KSO14
KSO11
KSO10
KSO15

CP4

<EMI>

81

2

7

3

6

4 5

100P_1206_8P4C_50V8

CP5

<EMI>

2
3
4 5

100P_1206_8P4C_50V8
CP6

<EMI>

2
3
4 5

100P_1206_8P4C_50V8

81
7
6

81
7
6

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/05/15 2009/05/15

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

2

Date: Sheet of

Compal Electronics, Inc.

KB /SW Conn.

KSWXX M/B LA-4611P Schematic

32 47Friday, August 01, 2008

1

0.1

+5VALW+3VALW

EEPROM_VCC

1 2

R298 4.7K_0402_5%

1 2

R299 4.7K_0402_5%

EEPROM_VCC

@

R301 0_0603_5%

R302 0_0603_5%

@
@

12

@

12

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK1 <31,41>
EC_SMB_DA1 <31,41>

+3VALW

SPI_CS#
SPI_SO

JP6

2

112

4

334

6

556

8

778

E&T_2941-G08N-00E~D

ME@

C108

0.1U_0402_16V4Z

SPI_CS#< 31>
SPI_CLK_R<31>
SPI_SI<31>

SPI_CLK_R
SPI_SI

8M SPI ROM

+3VALW

20mils

1

2

SPI_CS#
SPI_CLK_R
SPI_SI SPI_SO

+3VALW

U3

8

VCC

VSS

3

W

7

HOLD

1

S

6

C

5

Q

D

SST25LF080A_SO8-200mil

4

2

R110 0_0402_5%

12

FRD#SPI_SO <31>

TP_DATA<31>
TP_CLK<31>

+5VS

SWR#
SWL#

2

3

1

Update Footprint

To TP/B Conn.

SWR#
SWL#
TP_DATA
TP_CLK

D25

@

PSOT24C_SOT23

JP12

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_85201-06051

+5VS

C552

0.1U_0402_16V4Z

14W Use 15W Use

Bluetooth Conn.

Need to check BT pin definition again!
9/20 modified this block

R529

10K_0402_5%

BT_LED#<37>

BT_ON#<31>

BT_LED#

SSM3K7002FU_SC70-3

Q18

0.1U_0402_16V4Z

R531 100K_0402_5%

1 2

+5VS

D

S

12

13

C553

2

G

12

R530
10K_0402_5%

4.7U_0805_10V4Z

2

BT_ACTIVE<29>
USB20_P1<21>
USB20_N1<21>

C557

+3VALW

G

@

S

Q19
SI2301BDS_SOT23

D

W=40mils

1 3

1

2

BT_ACTIVE
USB20_P1
USB20_N1
BTON_LED

1

C554
1U_0603_10V4Z

2

C558

0.1U_0402_16V4Z

WCM2012F2SF-121T04_0805

WLAN_ACTIVE<29>

+BT_VCC

L39

<EMI>

1

1

4

4

@

R638 0_0402_5%
R639

<EMI>

1 2
1 2

<EMI>

2

3

2

3

0_0402_5%

+BT_VCC

USB20_R_P1
USB20_R_N1

WLAN_ACTIVE

10

FOR LPC DEBUG PORT

+3VS

JP57

1

1
2
3
4
5
6
7
8
9

10
GND
GND

ACES_85201-1005N

ME@

CLK_PCI_DB

2
3

LPC_AD0

4

LPC_AD1

5

LPC_AD2

6

LPC_AD3

7

LPC_FRAME#

8
9

PCI_RST#

10
11
12

JP42

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND1

GND2

MOLEX_53780-0870

CONN@

1

2

C576

@

0.1U_0402_16V7K

CLK_PCI_DB <14>

LPC_AD0 <20,31>
LPC_AD1 <20,31>
LPC_AD2 <20,31>
LPC_AD3 <20,31>

LPC_FRAME# <20,31>
PCI_RST# <19,28,29,30,31>

SW4

5

6

2

Left Switch Left Switch

Right Switch

1

SMT1-05_4P

14W@

2
1

SMT1-05_4P

14W@

SW6

5

6

SWL#SWL#

4
3

4
3

SWR#SWR#

Right Switch

FOR LPC SIO DEBUG PORT

JP54

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

+5VS

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
PCI_RST#

CLK_PCI_DB
SERIRQ

+3VS

CLK_14M_SIO <14>

LPC_DRQ0# <20>

SERIRQ <20,31>

R467 10K_0402_5%

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

ACES_85201-2005

ME@

SW5

5

6

2
1

2
1

@

12

SMT1-05_4P

15W@

5

6

SMT1-05_4P

15W@

4
3

SW7

4
3

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/05/15 2009/05/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

BIOS, I/O Port & K/B Connector

KSWXX M/B LA-4611P Schematic

of

33 47Friday, August 01, 2008

0.1

A

ON/OFF switch

1 1

TOP Side

12

J3 JOPEN@

12

J4 JOPEN@

Bottom Side

ON/OFFBTN#

D26

1

DAN202UT106_SC70-3

+3VALW

2
3

Power Button

SMT1-05_4P
SW3

A@

ON/OFFBTN#

1
2

2 2

3
4

5

6

10/09 add for debug

EC_ON<31>

EC_ON

R535

10K_0402_5%

2

G

1 2

Function Board Conn.

R817 0_0603_5%@

+3VS

R816 0_0603_5%@

+3VALW

R805 0_0603_5%@

+5VS

R806 0_0603_5%

+5VALW

D12

CLK_GUEST

1

PJSOT24C_SOT23-3

@

2

DATA_GUEST

3

3 3

12
12
12
12

CLK_GUEST<31>
DATA_GUEST<31>
ACK_GUEST<31>
SM_KEY#<31>
SM_KEY_LED#<31>

CAPS_LED#<31>
NUM_LED#<31>

ACK_GUEST

+5V_SW

@

0.1U_0402_16V4Z

CLK_GUEST
DATA_GUEST
ACK_GUEST
SM_KEY#
SM_KEY_LED#

CAPS_LED#
NUM_LED#

C759 100P_0402_50V8J@

1 2

For EMC command

C8

Michael Hsiao 2008/6/18

12

1
2
3
4
5
6
7
8

9
10
11
12

JP48

1
2
3
4
5
6
7
8
9
10
GND
GND

ACES_85201-1005N

CONN@

Lid Switch

B

12/4 Change D14 to correct symbols

R533
100K_0402_5%

1 2

ON/OFF#

51_ON#

2

C561
1000P_0402_50V7K

1

13

D

S

Q21
SSM3K7002FU_SC70-3

ON/OFF# <31>
51_ON# <40>

12

D27
RLZ20A_LL34

SINGLE INT MIC

+MIC2_VREFO

C

05/29 close to codec

R610

12

0_0402_5%

D41

@

2 1

RB751V_SOD323

1 2

R870 2.2K_0402_5%

D

Power USB Board Conn.

+5VALW

C7

12

ON/OFFBTN#
D_P_USB#
PWR_LED#
POWER_USB_LED#

+3VALW

D67

2

1

3

DAN202UT106_SC70-3

12

R659
10K_0402_5%

PWR_LED#<31,37>
POWER_USB_LED#<31>

D_P_USB#

0.1U_0402_16V4Z @

For EMC command
Michael Hsiao 2008/6/18

JP62

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_85201-06051

P_USB#
51_ON#

P_USB# <31>
51_ON# <40>

E

JMIC2

1

1

2

2

3

GND

4

GND

ACES_88231-02001

MIC@

Security Classification

C675 220P_0402_50V7K

MIC_GND

C565

+VCC_LID

1

2

+3VALW

4 4

1 2

R536 0_0402_5%

0.1U_0402_16V4Z

R537 100K_0402_5%

1 2

2

VDD

3

OUTPUT

GND

U25

1

A3212ELHLT-T_SOT23W-3

2

C567
10P_0402_50V8J

1

LID_SW# <31>

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

MIC2 MIC2_R

12

@

2008/05/15 2009/05/15

2

3

D42
PSOT05C-LF-T7 SOT-23-3

@

1

Compal Secret Data

12

R871 0_0402_5%

Deciphered Date

1

C677
15P_0402_50V8J

2

@

D

MIC2_R <35>

@

L64

1 2

MBK1608121YZF_0603

R608 0_0603_5%

GNDA

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

PWROK/LID/Front/IO Board

KSWXX M/B LA-4611P Schematic

MIC_GND

of

34 47Friday, August 01, 2008

E

0.1

5

HD Audio Codec

1 2

R716 1K_0402_5%

1 2

R717 1K_0402_5%

1 2

R718 1K_0402_5%

EAPD<31,36>

L34

0_0603_5%

10U_0805_10V4Z

R547
10_0402_5%

@

1 2
1

C598
15P_0402_50V8J

2

@

D D

+VDDA

MIC2_R<34>

C C

MIC1_L<36>
MIC1_R<36>

B B

0.1U_0402_16V4Z

1

C573

MIC2_R_R

1

C574

2

2

0.1U_0402_16V4Z

C589 2.2U_0603_6.3V6K
C585 2.2U_0603_6.3V6K

2/01 Let the m floa tin g

MIC1_R_L

C591 2.2U_0603_6.3V6K

MIC1_R_R

C592 2.2U_0603_6.3V6K

C594 100P_0402_50V8J

1 2

@

HDA_RST_AUDIO#<20>
HDA_SYNC_AUDIO<20>
HDA_SDOUT_AUDIO<20>

1

1

C575

C577

@

2

100P_0402_50V8J

2

MIC2_C_L
MIC2_C_R

MIC1_C_L
MIC1_C_R

MONO_IN

SENSE_A
SENSE_B

5/29 Realtek suggest change P/N:SA00001GD10

DGND

4

+AVDD_AC97

40mil

U27

AVDD125AVDD2

14

NC

15

NC

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1_L

22

MIC1_R

12

PCBEEP

11

RESET#

10

SYNC

5

SDATA_OUT

2

GPIO0

3

GPIO3

13

SENSE A

34

SENSE B

47

EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

ALC268-GR_LQFP48

38

+3VS_DVDD

10mil

1

DVDD

LINE_OUT_L
LINE_OUT_R

HP_OUT_L
HP_OUT_R

DMIC_CLK

BIT_CLK

SDATA_IN

MONO_OUT

LINE1_VREFO

GPIO1

MIC1_VREFO_L

MIC1_VREFO_R

MIC2_VREFO

VREF

JDREF

AVSS1
AVSS2

10mil

9

DVDD_IO

NC

NC
NC

NC

AMP_LEFT

35

AMP_RIGHT

36

AMP_LEFT_HP

39

AMP_RIGHT_HP

41
45
46
43
44

HDA_BITCLK_AUDIO

6

SDIN0

8
37
29
31
28

10mil

32

10mil

30

10mil

ACZ_VREF

27

ACZ_JDREF

40
33
26

42

AGND

1

C570

2

0.1U_0402_16V4Z

1

C580

2

0.1U_0402_16V4Z

1 2

R545 33_0402_5%

+MIC1_VREFO_L
+MIC1_VREFO_R
+MIC2_VREFO

12

R548

20K_0402_1%

3

1

C571

@

4.7U_0805_10V4Z

2

1

C581

@

4.7U_0805_10V4Z

2

10mil

L33

1 2

FBMA-L11-160808-800LMT_0603

R539 0_0603_5%@

AMP_LEFT <36>
AMP_RIGHT <36>
AMP_LEFT_HP <36>
AMP_RIGHT_HP <36>

HDA_BITCLK_AUDIO <20>

HDA_SDIN0 <20>

1

C596
10U_0805_10V4Z

2

+3VS

+3VS

1

C597
100P_0402_50V8J

2

2

EC Beep

R541

BEEP#<31>

SB_SPKR<20>

1 2

10K_0402_5%

R543

1 2

10K_0402_5%

PCI Beep

R544

10K_0402_5%

Sense Pin Impedance Codec Signals

39.2K

SENSE A / B

SENSE B

20K
10K

5.1K

39.2K
20K
10K

5.1K

R804

1 2

0_0402_5%

12

2 1

PORT-A (PIN 39, 41)
PORT-B (PIN 21, 22)
PORT-C (PIN 23, 24)
PORT-D (PIN 35, 36)
PORT-E (PIN 14, 15)
PORT-F (PIN 16, 17)
PORT-G (PIN 43, 44)
PORT-H (PIN 45, 46)

1

+VDDA

12

R538

@

10K_0402_5%

C572 0.1U_0402_16V4Z

1 2

12

R540
0_0402_5%

1 2

C582 0.1U_0402_16V4Z

1

C

R542

2

B

Q22

@

E

2SC2411K_SOT23

3

1 2

2.4K_0402_5%

Need Update Footprint

D28

@

CH751H-40PT_SOD323-2

9/19 Realtek suggest
Add bypass schematic.

Funnction
HP
MIC
LINE IN
LINE OUT
HP
MIC
LINE IN
LINE OUT

MONO_INMONO_IN_1

@

SENSE FOR Ext. Mic.

MIC_SENSE<36>

1 2

R550 20K_0402_1%

SENSE_A

SENSE FOR Solo Int. Mic.

1 2

A A

R551 20K_0402_1%

SENSE_B

Moat Bridge

SENSE FOR HP

SENSE_A

HP_SENSE<36>

R554 39.2K_0402_1%

5

12

1 2

R555 0_0805_5%

1 2

R556 0_0805_5%

4

HDA_BITCLK_AUDIO

R549
10_0402_5%

@

1 2
1

C599
10P_0402_50V8J

2

@

Regulator for CODEC

+5VS

L36

0_0603_5%

60mil

10U_0805_10V4Z

C600

@

+5VS_VDDA

1

2

1

2

10/2 change circuit

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/05/15

3

Compal Secret Data

Deciphered Date

2009/05/15

2

C601

0.1U_0402_16V4Z

U28

1

IN

OUT

2

GND

3

SHDN

BYP

G9191-475T1U_SOT23-5

0.01U_0402_16V7K

(Max outpu t = 300 mA)

5

4

C603

1

1

2

2

40mil

C602

4.7U_0805_10V4Z

@

+VDDA

4.75V

U8 change footprint

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

<Title>

Custom

HD Audio Codec ALC268

KSWXX M/B LA-4611P Schematic

Friday, August 01, 2008

1

35 47

of

0.1

A

APA2057 SPK/HP Amplifier

1 1

fo=1/(2*3.14*R*C)=106Hz
R=1.5K / C= 1uF

AMP_RIGHT<35>
AMP_LEFT<35>

AMP_RIGHT_HP<35>
AMP_LEFT_HP<35>

1 2

R569 0_0402_5%

9/5 If implement AMP BEEP, Swap C641 and R524.

2 2

R524 change from 0 Ohm to 47K

C609 1U_0603_10V4Z
C608 1U_0603_10V4Z

C612 4.7U_0805_10V4Z
C613 4.7U_0805_10V4Z

C614 0.47U_0603_16V4Z

1 2
1 2

1 2
1 2

1 2

R560 1.5K_0402_1%@

1 2

R562 1.5K_0402_1%@

1 2

R563 100K_0402_5%
R564 100K_0402_5%@

+5VS

AMP_RHPIN
AMP_LHPIN
AMP_SD#

1 2
1 2

1 2

R565 39K_0402_5%

1 2

R566 39K_0402_5%

1 2

R567 0_0402_5%

1 2

C617 1U_0603_10V6K
C618 2.2U_0603_6.3V6K
C620 0.1U_0402_16V4Z

IN_A Gain = 10dB (Internal Speaker)
IN_H Gain = 0dB (Headphone)

W=40mil

C604

12

B

10/2 U6 APA2057A P/N:SA00001QD00

+5VALW

1

1

C606

C605

680P_0402_50V7K

AMPR
AMPL
AMP_EN#
HP_EN
INR_H
INL_H

AMP_BEEP
AMP_CP+

AMP_CP­AMP_BIAS

2

0.1U_0402_16V4Z

3

5
27
24

4

6
26
28
12

14
25

U29

INR_A
INL_A

/AMP EN
HP EN
INR_H

INL_H
/SD
BEEP
CP+

CP­BIAS

APA2057A_TSSOP28

+3VALW

2

10U_0805_10V4Z

19

11

20

10

PVDD

PVDD

HVDD

CVDD

ROUT+

LOUT+

11/28 Modified to X5R
11/28 Change to SE080105K80

1

VDD

ROUT-

LOUT-

HP_R

HP_L

CVSS

GND
PGND
PGND
CGND

GND

VSS

2

C607
1U_0603_10V4Z

1

22
21

8
9

17
18

15
16
2

23
7
13
29

SPKR+
SPKR-

SPKL+
SPKL-

HP_R
HP_L

CVSS

C

12

C619
1U_0603_10V6K

D

+MIC1_VREFO_R

+MIC1_VREFO_L

12

1

2

12

R558

2.2K_0402_5%

KC FBM-L11-160808-121LMT 0603
KC FBM-L11-160808-121LMT 0603

1

C611

<EMI>

220P_0402_50V7K

2

10mil 10mil

R557

2.2K_0402_5%

MIC_SENSE<35>

MIC1_R<35>
MIC1_L<35>

MIC_SENSE

MIC1_R
MIC1_L

220P_0402_50V7K

<EMI>

C610

Trace width/spacing/other=8/6/50

R570

@

12

HP_SENSE

HP_R
HP_L

12

R568

@

0_0402_5%

10P_0402_50V8J

C615

<EMI>

KC FBM-L11-160808-121LMT 0603
KC FBM-L11-160808-121LMT 0603

1

1

C616

<EMI>

2

2

10P_0402_50V8J

HP_SENSE<35>

0_0402_5%

Trace width/spacing=15/9

L47

1 2

L48

1 2

10mil

L49

1 2

L50

1 2

<EMI>
<EMI>

<EMI>
<EMI>

MIC1_R_1
MIC1_L_1

2

@

D29
PSOT05C-LF-T7 SOT-23-3

<EMI>

HPR
HPL

2

@

D30
PSOT05C-LF-T7 SOT-23-3

<EMI>

E

MICROPHONE
IN JACK

JP63

5
4
3

6 7
2

3

1

1

FOX_JA6333L-B3S0-7F~N

CONN@

RED

10
9
8

HEADPHONE
OUT JACK

JP64

5
4
3

6 7
2

3

1

1

FOX_JA6333L-B3S0-7F~N

CONN@

GREEN

10
9
8

Add below circuit for APA2057 gain tunning use

+3VALW

3 3

EAPD<31,35>

EAPD

12

R577 0_0402_5%

SSM3K7002FU_SC70-3

R573

10K_0402_5%

2

G

Q24

13

1 2

13

D

S

D

2

G

S

Q23
SSM3K7002FU_SC70-3

C621

0.01U_0402_16V7K

Gain= 10dB

Gain (dB) Low (V) High (V) Recommended (V)
10
11

4 4

12
13

3.45

3.56

3.68

3.80

3.51

3.62

3.73

3.85

A

3.48

3.59

3.70

3.82
+5VALW assume equal 5.1V

10 dB ---> 5.1 x 220 / 320 = 3.5

B

+5VALW

12

R571
10K_0402_1%

AMP_SD# HP_EN

R572 10K_0402_5%

1 2

12

1

R574
22K_0402_1%

2

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1

C622

0.1U_0402_16V4Z

2

Compal Secret Data

Deciphered Date

SPKL-

R580 0_0603_5%<EMI>

1 2

SPKL+ SPK_L1+

R578 0_0603_5%<EMI>

SPKR­SPKR+

20mil

1 2

R581 0_0603_5%<EMI>

1 2

R579 0_0603_5%<EMI>

1 2

Speaker Conn.

2008/8/182007/08/18

D

PSOT24C_SOT23

Title

Size Document Number Rev

Custom

Date: Sheet

1/8 change JSPK1 following JAW91

SPK_L1­SPK_R1-

SPK_R1+

2

3

2

3

<EMI>

D31

@

1

D32

@

PSOT24C_SOT23

<EMI>

1

Compal Electronics, Inc.

AMP/VR/Audio Jack

KSWXX M/B LA-4611P Schematic

E

JSPK1

4

4

G2

3

3

G1

2

2

1

1

ACES_88266-04001

CONN@

of

36 47Friday, August 01, 2008

6
5

0.1

MDC Conn.

HDA_SDOUT_MDC<20>
HDA_SYNC_MDC<20>
HDA_RST_MDC#<20>

HDA_SDIN1<20>

Please add these caps close to JMDC1 as close as possible,

HDA_SDOUT_MDC
HDA_SYNC_MDC

SDIN1_MDC
HDA_RST_MDC#

HDA_SDIN1

1 2

JMDC1

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

Connector for MDC Rev1.5

ACES_88018-124G

CONN@

R593

SDIN1_MDC

33_0402_5%

IAC_BITCLK

GND13GND14GND15GND16GND17GND

18

RES0
RES1

3.3V
GND3
GND4

2
4
6
8
10
12

Mount R710; Michael 2008/5/30

20mil

+VCC_MDC
+3V_MDC

HDA_BITCLK_MDC

1

2

0.1U_0402_16V4Z

R710 0_0402_5%

1 2

R697 0_0402_5%

1 2

C629
22P_0402_50V8J

@

+VCC_MDC +3V_MDC

C746

@

1

2

+3VS

HDA_BITCLK_MDC <20>

1

C745

0.1U_0402_16V4Z

2

@

Camera Conn

USB20_N7<21>
USB20_P7<21>

USB20_N7
USB20_P7

1 2
1 2

4

1

R590 0_0603_5%
R591 0_0603_5%@

4.7U_0805_10V4Z

3

3

2

2

+5VS+3VS

+5VALW

R594 0_0402_5%
R595 0_0402_5%

@

WCM2012F2SF-121T04_0805

4

1

L42

C627

12
12

1

2

1

C628

0.1U_0402_16V4Z

2

USB20_R_N7
USB20_R_P7

+5V_CAMERA

JP3

1

1

2

2

3

3

4

4

5

5

6

GND1

7

GND2

ACES_88266-05001

CAMCONN@

LED

HDA_SDOUT_MDC
HDA_SYNC_MDC
HDA_RST_MDC#
SDIN1_MDC

C752 100P_0402_50V8J@

1 2

C753 100P_0402_50V8J@

1 2

C754 100P_0402_50V8J@

1 2

C756 100P_0402_50V8J@

1 2

05/30 Change R660,R596,R597,R598,R599,R600 to 820ohm for 15W@
05/30 Add R660,R596,R597,R598,R599,R600 to 2kohm for 14W@; follow JHXXX

R660

2K_0402_5%

14W@

+5VALW

+5VALW

+3VS

+5VS

+5VS

+5VALW

R596

2K_0402_5%

14W@

R660
820_0402_5%

1 2

R596
820_0402_5%

1 2

R597
820_0402_5%

1 2

R598

1 2

820_0402_5%

R599
820_0402_5%

1 2

R600

1 2

820_0402_5%

15W@

15W@

15W@

15W@

15W@

15W@

R597

2K_0402_5%

14W@

2 1

HT-191NB_BLUE_0603

2 1

HT-191NB_BLUE_0603

HT-191UD_AMBER_0603

2 1

2 1

2 1

2 1

LED6

LED7

HT-191NB_BLUE_0603

HT-191UD_AMBER_0603

LED5

LED3

HT-191NB_BLUE_0603

R598

2K_0402_5%

14W@

LED4

LED1

Amber
Blue

Amber
Blue

R599

2K_0402_5%

14W@

R600

2K_0402_5%

14W@

SATA_LED# <21>

PWR_LED# <31,34>

CHARGE_LED0# <31>

CHARGE_LED1# <31>

WLAN_LED# <29>

BT_LED# <33>

12/7 Modified LE D f o ot p r i nt to LED_HT-297UD-CB_4P

12/15 Modified to correct LED symbol!

Finger Print board

1/05 Modified D3 to SCA00000A00
0208 Remove D3 , Add D55 (SC300000G00)

D36

05/26 Change D36 from SC300000X00 to SC300000K00;
Michael 2008/5/30

USB20_P3<21>
USB20_N3<21>

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/05/15 2009/05/15

USB20_P3
USB20_N3

+3VS

Compal Secret Data

4.7U_0805_10V4Z

Deciphered Date

FP@

3

I/O

4

VCC

PJLCR05 SOT143

1

C630

2

@

2

I/O

1

GND

1

C631

0.1U_0402_16V4Z

2

FP@

For EMI

2/1 change JP4 pin 6 to +5VS for LTT FP use

+5VS

@

WCM2012F2SF-121T04_0805

4

4

1

1

L60

FP@

R640 0_0402_5%

1 2
1 2

R641

0_0402_5% FP@

Title

LED/MDC/CAMERA

Size Document Number Rev

B

Date: Sheet

3

3

2

2

USB20_R_P3
USB20_R_N3

Compal Electronics, Inc.

KSWXX M/B LA-4611P Schematic

C9

1 2

0.1U_0402_16V4Z

@

JP4

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_85201-06051

FPCONN@

37 47Friday, August 01, 2008

0.1

of

11/27 Add screw for layout request

H_3P0

H_3P7

H_4P2

H1
HOLEA

1

H22
HOLEA

1

H28
HOLEA

1

H2
HOLEA

1

H23
HOLEA

1

H29
HOLEA

1

H3
HOLEA

1

H26
HOLEA

1

H30
HOLEA

1

2/22 change these from H_3P7 to H_3P8

H21

H9

HOLEA

HOLEA

1

1

2/22 change these from H_3P2 to H_3P3

H15

H16

HOLEA

HOLEA

1

1

H4
HOLEA

1

H31
HOLEA

1

H5
HOLEA

1

H27
HOLEA

1

H19
HOLEA

1

H6
HOLEA

1

H32
HOLEA

1

H20
HOLEA

1

H7
HOLEA

1

H8
HOLEA

1

H10
HOLEA

1

H11
HOLEA

1

H12
HOLEA

1

H13
HOLEA

1

H14
HOLEA

1

FD1

FD5

FD3

FD2

@

1

1

FD4

@

@

1

1

FD6

@

@

@

1

1

M1
HOLEA

1

H_5P0X3P2N

M3
HOLEA

1

H_5P2X3P2N

M2
HOLEA

1

H_5P0X3P2N

M4
HOLEA

1

-*

H_3P1N

M5
HOLEA

1

H_5P0X3P2N

11/27 Add screw for layout request

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/05/15 2009/05/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

FAN & Screw Hole

JFWXX M/B LA-3961P Schematic

38 47Friday, August 01, 2008

of

0.1

A

B

C

D

E

1 1

1

C335

@

10U_0805_10V4Z

2 2

10U_0805_10V4Z

3 3

2

+VSB

R288
33K_0402_5%

SSM3K7002FU_SC70-3

Change Q48 package from SOT23
to SC70-3; Michael 2008/5/30

1

C339

@

2

+VSB

R287
47K_0402_5%

SSM3K7002FU_SC70-3

Change Q17 package from SOT23
to SC70-3; Michael 2008/5/30

+5VALW TO +5VS +1.8VALW to +1.8VS

C345

@

10U_0805_10V4Z

SUSP

C325

@

10U_0805_10V4Z

1 2

SUSP

+5VALW

U13

8

S

D

7

S

D

6

S

D

5

1

2

2

G

Q48

D

AO4468_SO8

5VS_GATE

13

D

S

G

+3VALW TO +3VS

+3VALW

U16

8

S

D

7

S

D

6

S

D

5

1

2

2

G

Q17

+1.5VS +1.05VS +0.9VS

D

S

G

D

AO4468_SO8

3VS_GATE

13

D

S

R289
470_0603_5%

@

1 2

Q20

13

SSM3K7002FU_SC70-3

SUSP SUSP SUSP

2

G

@

1
2
3
4

1
2
3
4

+5VS

1

C344

@

10U_0805_10V4Z

1

C323

0.1U_0603_25V7K

2

+3VS

C331

@

10U_0805_10V4Z

1

C320

0.1U_0603_25V7K

2

1

C334

2

2

1U_0603_10V4Z

Change Q25 Q50 package from SOT23
to Q52A Q52B SOT363-6; Michael 2008/5/30

1

1

C343

2

2

1U_0603_10V4Z

R280
470_0603_5%

@

1 2

Q12

13

D

SSM3K7002FU_SC70-3

2

G

@

S

R295

@

470_0603_5%

1 2
61

Q52A

@

SUSP

2

2N7002DW-T/R7_SOT363-6

R292

@

470_0603_5%

1 2
3

Q52B

@

SUSP

5

2N7002DW-T/R7_SOT363-6

4

R296
470_0603_5%

@

1 2

Q26

13

D

SSM3K7002FU_SC70-3

2

G

@

S

1

C324

@

10U_0805_10V4Z

10U_0805_10V4Z

2

1 2

+VSB

R286
47K_0402_5%

SYSON#

SSM3K7002FU_SC70-3

Change Q49 package from SOT23
to SC70-3; Michael 2008/5/30

1

C336

@

2

1 2

+VSB

R283
47K_0402_5%

SUSP

SSM3K7002FU_SC70-3

Change Q16 package from SOT23
to SC70-3; Michael 2008/5/30

+1.8VALW TO +1.8V

+1.8VALW +1.8V

U17

8

S

D

7

S

D

6

S

D

5

1

C341

@

10U_0805_10V4Z

2

2

G

Q49

D

AO4468_SO8

1.8V_GATE

13

D

S

G

+1.2VALW TO +1.2VS

+1.2VALW +1.2VS

U14

8

S

D

7

S

D

6

S

D

5

1

C321

@

10U_0805_10V4Z

2

2

G

Q16

D

AO4468_SO8

1.2VS_GATE

13

D

S

G

1
2
3
4

1
2
3
4

1

C340

@

10U_0805_10V4Z

2

1

C318

0.1U_0603_25V7K

2

1

C327

@

10U_0805_10V4Z

2

1

C317

0.1U_0603_25V7K

2

1

C329

2

1U_0603_10V4Z

Change Q46 package from SOT23
to SC70-3; Michael 2008/5/30

1

C338

2

1U_0603_10V4Z

R294

@

470_0603_5%

1 2
13

D

SYSON#

2

G

Q46

S

SSM3K7002FU_SC70-3

Change Q47 Q51 package from SOT23
to Q53A Q53B SOT363-6; Michael 2008/5/30

R290

@

470_0603_5%

1 2
3

Q53B

@

SUSP

5

2N7002DW-T/R7_SOT363-6

4

+1.8VALW

1

1

C337

C322

10U_0805_10V4Z

+VSB

Change Q15 package from SOT23
to SC70-3; Michael 2008/5/30

@

@

10U_0805_10V4Z

2

2

R284
47K_0402_5%

SUSP

SSM3K7002FU_SC70-3

Q15

SYSON<30,31>

12

2

G

7/24 Change R281 from 100K to 10K

SUSP#<30,31,45>

U15

8

D

7

D

6

D

5

D

AO4468_SO8

1.8VS_GATE

13

D

S

10K_0402_5%

10K_0402_5%

S
S
S
G

SYSON

R281

R282

+1.8VS

1
2
3
4

1

C330

@

10U_0805_10V4Z

2N7002DW-T/R7_SOT363-6

1

C319

0.1U_0603_25V7K

2

+5VALW

SYSON#

2

G

12

Change Q13 Q14 package from
SOT23 to SC70-3; Michael 2008/5/30

+5VALW

2

G

12

1

C342

2

2

1U_0603_10V4Z

R285
100K_0402_5%

1 2

13

D

SSM3K7002FU_SC70-3

Q14

S

R278
100K_0402_5%

1 2

SUSP

13

D

SSM3K7002FU_SC70-3

Q13

S

R293

@

470_0603_5%

1 2
61

1

C316
100P_0402_50V8J

2

Q53A

@

SUSP

2

SUSP <45>

Change Q20 Q12 Q26 package from SOT23 to SC70-3; Michael 2008/5/30

4 4

3/14 Change R16 from 100K to 10K

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/05/15 2009/05/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

DC Interface

KSWXX M/B LA-4611P Schematic

E

of

39 47Friday, August 01, 2008

0.1

A

B

C

D

DC301001Y00

SINGA_2DW-0268-B16

@

1

1

2

2

3

3

4

4

PJP1

1 1

VIN

12

PR4

PR7

84.5K_0402_1%

22K_0402_1%

1 2

12

2 2

12

3.3V

PR13

560_0603_5%

1 2

+CHGRTC

3 3

PR14
560_0603_5%

1 2

PR8

PC6

1000P_0603_50V7K

RTCVREF

12

PC8

4.7U_0805_10V4Z

20K_0402_1%

G920AT24U_SOT89-3
PU3

3

OUT

GND

1

ADPIN

12

PC1

0.01U_0402_50V7K

PR2
10K_0402_1% @

1 2

PR3
1M_0402_1%

1 2

VS

8

3

P

+

12

PC7

0.1U_0402_16V7K

2

IN

2

-

4

PR10
10K_0402_1%

PR15
200_0805_5%

12

PC9

O

G

PU2A
LM393DG_SO8

12

1U_0805_25V4Z

51_ON#<34>

PL1

HCB4532KF-800T90_1812

1 2

12

PC2

0.01U_0402_50V7K

PC5

0.01U_0402_25V7K@

1 2

1

RTCVREF

3.3V

BATT+

RLS4148_LL34-2

CHGRTCP

12

PR17
22K_0402_1%

1 2

12

PC142

2200P_0402_50V7K

VS

12

PR5

10K_0402_1%

12

PD2

PD4

12

12

RLZ4.3B_LL34

12

PR16

100K_0402_1%

PC3

0.022U_0603_50V7K

12

12

VIN

12

PR9

10K_0402_1%

PC10

PC4

0.022U_0603_50V7K

PR6
10K_0402_1%

1 2

ACIN <31,42>

Vin Detector

High 18.764 17.901 17.063
Low 17.745 16.9 16.03

VIN

PD3
RLS4148_LL34-2

1 2
12

12

PR12

PR11

68_1206_5%

68_1206_5%

13

12

PC11

2

0.22U_1206_25V7K

PQ1

TP0610K-T1-E3_SOT23-3

8

5

P

+

7

O

6

-

G

PU2B

LM393DG_SO8

VS

0.1U_0603_25V7K

4

PJ2

+5VALWP

PAD-OPEN 3x3m

1 2

+5VALW

+1.8VALWP

(8.5A,340mils ,Via NO.= 17)

(7A,280mils ,Via NO.= 14)

PJ5
PAD-OPEN 3x3m

+3VALWP

4 4

1 2

(5A,200mils ,Via NO.=10)

PJ6
PAD-OPEN 3x3m

1 2

+3VALW

+0.9VSP

(2A,80mils ,Via NO.= 4)

+VSBP +VSB+1.2VALWP +1.2VALW

(4A,160mils ,Via NO.=8)

A

PJ1 PAD-OPEN 3x3m

1 2

PJ3
PAD-OPEN 3x3m

1 2

PJ7
PAD-OPEN 3x3m

1 2

+1.8VALW

+0.9VS

(0.3A,40mils ,Via NO.= 2)

PJ14 PAD-OPEN 3x3m

+1.05VSP_LDO

+1.05VSP

1 2

PJ4 PAD-OPEN 3x3m

1 2

(3A,120mils ,Via NO.= 6)

B

+1.5VSP

+1.05VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/10/17 2006/10/17

Compal Secret Data

PJ17 PAD-OPEN 3x3m

1 2

(2A,80mils ,Via NO.= 4)

Deciphered Date

C

+1.5VS

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

DCIN/DECTOR

D

40 47Friday, August 01, 2008

0.2

A

B

C

D

DC040003600

PJP2

1
2
3

1 1

4
5
6
7
8

9
G1
G2

SUYIN_200275MR009G180ZR

<BOM Structu re>

BATT++

1
2

CNT1

3

CNT2

4

EC_SMCA

5

EC_SMDA

6

TS_A

7

GND

8
9
10
11

12

12

PR25

100_0402_1%

PR20

1 2

PR26

100_0402_1%

PR19

1 2

100K_0402_5%@

1K_0402_1%

+3VALWP

PR21

1 2

1K_0402_1%

1 2

PR18

@

100K_0402_5%

+3VALWP

BATT++

12

PC12

1000P_0402_50V7K

12

EC_SMB_CK1 <31,33>
EC_SMB_DA1 <31,33>

2 2

12

PR30

1K_0402_1%

1 2

PR29

6.49K_0402_1%

+3VALWP

PJ8
PAD-OPEN 3x3m

1 2

PC13

1000P_0402_50V7K

BATT+

PH1 under CPU botten side :

CPU thermal protection at 89 degree C
Recovery at 70 degree C

12

PC14

0.01U_0402_50V7K

12

VL

12

12

PC16

1000P_0402_50V7K

PR22

10K_0402_1%

PR27

78.7K_0603_1%

1 2

PH1

100K_0603_1%_TH11-4H104FT

12

TM_REF1

LM358ADR_SO8

12

PC17

1U_0603_6.3V6M

PC15

12

0.1U_0603_25V7K

PU4A

3

+

2

-

PR28
150K_0402_1%

PR31

150K_0402_1%

VS

PR24
442K_0603_1%

1 2

8

P

1

0

G

4

<BOM Structu re>

12

VL

PD5

1 2

1SS355TE-17_SOD323-2

<BOM Structu re>

VL

PR23

1 2

150K_0402_1%

MAINPWON <43>

BATT_TEMP <31>

PQ2

TP0610K-T1-E3_SOT23-3

B+

12

12

PC18

PR32

100K_0402_1%

0.22U_1206_25V7K

PR33

3 3

VL

22K_0402_1%

1 2

13

2

+VSBP

12

PC19

0.1U_0603_25V7K

PR34

PR35

10K_0402_1%

1 2

0_0402_5%

SPOK<43,44>

1 2

13

D

2

G

12

PQ3
SSM3K7002F_SC59-3

S

PC20

0.1U_0402_16V7K

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

BATTERY CONN. / OTP

D

41 47Friday, August 01, 2008

0.1

A

B

65W, Iadapter=0~3.42A, Current sense=0.015ohm, PR45=110K, CP=3.175A
90W, Iadapter=0~4.74A, Current Sense=0.015ohm, PR45=54.9K, CP=4.303A

C

B+

D

AO4407_SO8

PR41
340K_0402_1%

ACDET

PR42

54.9K_0402_1%

PQ4

4

VIN

1 1

12

PR37

3.3_1210_5%

12

PR43

3.3_1210_5%

12

PD6

@

RLZ24B_LL34

2 2

12

PC31

2.2U_0805_25V6K

PC22

0.01U_0603_50V7K

1 2

Icharge=(Vsrset/Vvdac)*(0.1/PR44)
Iadapter=(Vacset/Vvdac)*(0.1/PR36)

8
7

5

1 2

1 2

PR48
340K_0402_1%

1 2

OVPSET

Input OVP : 22.3V
Input UVP : 17.26V
Fsw : 300KHz

VREF VREF

12

PR179
100K_0402_1%

PC141

ACOFF

1 2

0.1U_0402_16V7K

3 3

12

PR180
340K_0402_1%

2

G

PR178

12

200K_0402_1%

13

D

PQ31
RHU002N06_SOT323-3

S

13

D

2

G

S

PQ30
RHU002N06_SOT323-3

OVP voltage :

LI-3S :13.50V--BATT-OVP=1.5V
BATT-OVP=0.111*BATT+

4 4

BATT_OVP<31>

PR63

10K_0402_1%

1 2

12

PC48

@

0.01U_0402_25V7K

7

0

A

1 2

VS

12

8

PU4B

5

P

+

6

-

G

LM358ADR_SO8

4

<BOM Structure>

PR49

54.9K_0402_1%

0.1U_0603_25V7K

ACGOOD#

BATT+

PC47

0.01U_0402_25V7K

1 2

PC43

12

PR59

340K_0402_1%

12

PR62

499K_0402_1%

12

PR64

105K_0402_1%

PR51
100K_0402_1%

1

1

2

2

3 6

36

12

PC26

1 2

0.01U_0402_25V7K

VREF

CP setting

2

12

ACSET

12

PC49

0.01U_0402_25V7K

PQ5
AO4407_SO8

4

PR39

100K_0402_1%

ACDRV

PR45

110K_0402_1%

1 2

PC35

0.01U_0402_25V7K@

VREF=3.3V

1U_0603_10V6K

PQ9

SI2301BDS-T1-E3_SOT23-3

1 3

CHGVADJ<31>

0V 4V

8
7

1

5

2

0.1U_0402_16V7K

1 2

12

PC29

0.1U_0603_25V7K

12

PC42

Per CellCHGVADJ

4.35V3.3V

B

PC27

ACP

12

PR47
100K_0402_1%

1 2

VREF

12

BATDRV#

REGN

PR57

1 2

4.3K_0402_5%@

PR36

0.015_2512_1%

4
3

CHGEN#

12

PC30

0.1U_0603_25V7K

@

ACN

ACSET

PC38

0.47U_0603_16V7K

10

11

VADJ

12

13

14

12

12

PR60
10K_0402_5%@

PU5

1

CHGEN

2

ACN

3

ACP

4

ACDRV

5

ACDET

6

ACSET

7

ACOP

8

OVPSET

9

AGND

VREF

VDAC

VADJ

ACGOOD

BATDRV

BQ24751ARHDR_QFN28_5X5

PR56
0_0402_5%

LODRV

IADAPT

VADJ

12

PC140
1000P_0402_50V7K

@

PVCC

BTST

HIDRV

PH

REGN

PGND

LEARN

CELLS

SRP
SRN

BAT

TP

SRSET

100K_0402_1%

ACGOOD#

CHG_PVCC

28

PR40

2.2_0603_5%

1 2

27

1 2

26

0_0603_5%

25

REGN

24

12

PC36
1U_0603_10V6K

23

22

21

20

19
18
17

12

29

16

1 2

15

PR54

10_0603_5%

100P_0402_50V8J

RTCVREF

PR52

2200P_0402_50V7K

PC28

0.1U_0805_25V7K

PR181

PD7

12

RLS4148_LL34-2

1 2

SE_CHG+
SE_CHG-

PC44

0.1U_0603_25V7K

PC46

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PC23

10U_1206_25V6M

12

PC145

1 2

1 2

1 2

PC32

0.1U_0603_25V7K

PQ8

AO4466_SO8

ACOFF <31>

PR50

0_0402_5%

12

ADP_I<31>

VREF

1 2

13

D

2

G

S

Compal Secret Data

Deciphered Date

C

PL11

FBMA-L11-453215-121LMA90T_2

1 2

1 2

PC24

578

10U_1206_25V6M

3 6

578

3 6

241

ICHG setting

12

PR55
100K_0402_1%

PR61

100K_0402_1%@

PQ11
SSM3K7002F_SC59-3@

PQ6
AO4466_SO8

241

PL2

10UH_SIL1045RA-100PF_4.5A_30%

1 2

12

PR46

4.7_1206_5%

12

PC37
680P_0603_50V7K

12

PC40

0.1U_0603_25V7K

PR53

12

49.9K_0402_1%

12

PC45

0.01U_0402_25V7K

@

CurrentIREF

3A2.968V

ACIN <31,40> FSTCHG<31>

2007/05/182006/05/18

12

PR38

PC21

0.01U_0402_25V7K

BATDRV#

PR44

0.02_2512_1%

1
2

<BOM Structure>

PC39

0.1U_0402_16V7K

1 2

IREF <31>

Title

Size Document Number Rev

Date: Sheet

100K_0402_1%

1 2

4
3

12

578

PC41

0.1U_0603_25V7K

@

VREF

1 2

13

2

G

36

241

PQ7
AO4407_SO8

12

PC33

<BOM Structure>

10U_1206_25V6M

PR58
100K_0402_1%

CHGEN#

D

PQ10
RHU002N06_SOT323-3

S

Compal Electronics, Inc.

CHARGER

CHARGER

D

42 47Friday, August 01, 2008

BATT+

12

PC34

10U_1206_25V6M

of

1.0

A

B+

PJ10 PAD-OPEN 3x3m

1 2

PC50

4.7U_1206_25V6K

PL3

1 2

12

PC51

2200P_0402_50V7K

PR67

@

PC62

@

2.2_1206_5%

680P_0603_50V8J

1 1

+3VALWP

1

+

220U_6.3V_M

PC59

2

2 2

12

PC150

2200P_0402_50V7K

4.7UH_SIL104R-4R7PF_5.7A_30%

PR70

0_0402_5%

1 2

PR74

10K_0402_1%

1 2

@

ISL6237_B+

12

12

12

Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)

3.3VALWP
Imax=5.59A
Ipeak=7.85A

PZD1

VS

RLZ5.1B_LL34

1 2

PR77

100K_0402_1%

1 2

Iocp=10.133A

3 3

MAINPW O N<41>

2

1 3

PQ29
TP0610K-T1-E3_SOT23-3

PD8

1 2

4 4

1SS355TE-17_SOD323-2

PR85

0_0402_5%

3 6

241

3 6

241

12

B

PQ12

578

AO4466_SO8

578

PQ15
AO4712_SO8

PR78

1 2

200K_0402_5%

PC60

0.1U_0603_25V7K

1 2

Rds=18mOHM

PC66

0.22U_0603_25V7K

1 2

12

PC67

0.047U_0603_16V7K

PR65

1 2

0_0603_5%

0.1U_0603_25V7K

DH3

PR66

BST3A

12

0_0603_5%

LX3

FB3

VL

2VREF_ISL6237

1 2

PC65 0.22U_0603_10V7K

PR81

0_0402_5%@

1 2

1 2

PR86

@

47K_0402_1%

12

PC68

@

0.047U_0402_16V7K

PC55

1 2

PU6

33

TP

26

UGATE2

24

BOOT2

25

PHASE2

23

LGATE2

30

OUT2

32

REFIN2

1

REF

8

LDOREFIN

20

NC

4

EN_LDO

14

EN1

27

EN2

PR82

0_0402_5%

1 2

2VREF_ISL6237

PC139

1U_0603_10V6K

C

D

ISL6237_B+

12

12

PC54

PC53

4.7U_1206_25V6K

4.7U_1206_25V6K

PL4

4.7UH_SIL104R-4R7PF_5.7A_30%

2.2_1206_5%

680P_0603_50V8J

12

2200P_0402_50V7K

12

PR71

61.9K_0402_1%

@

1 2

PR72

1 2

0_0402_5%

+5VALWP

1

+

2

220U_6.3V_M

PC64

PQ14

578

3 6

578

3 6

241

241

PC52

12

PR69

@

12

PC63

@

Rds=18mOHM

PQ13

PC61

AO4466_SO8

12

1 2

AO4712_SO8

VL

1 2

PC56

3

6

VIN

VCC

1U_0603_10V6K

7

UGATE1

PHASE1

LGATE1

LDO

PVCC

BOOT1

PGND

OUT1

FB1

12

PC57

PC58

4.7U_0805_6.3V6K
1U_0603_10V6K

19

1 2

DH5

15
17

16

18

22

10

11

BST5A

0_0603_5%

0.1U_0603_25V7K

LX5

DL5DL3

FB5

PR68

VFB=0.7V

9

BYP

29

SKIP

28

POK2

13

POK1

12

ILIM1

31

ILIM2

TON

2

12

PR84
0_0402_5%

GND

ISL6237IRZ-T_QFN32_5X5

21

NC

5

12

PR75 0_0402_5%@

PR76 0_0402_5%

1 2

ILM1

ILIM2

12

PR79

301K_0402_1%

PR80

301K_0402_1%

12

12

VL

SPOK <41,44>

Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)

5VALWP
Imax=4.9A
Ipeak=7A
Iocp=10.146A

2VREF_ISL6237

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. T HIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

+5VALWP/+3VALWP

D

43 47Friday, August 01, 2008

0.1

5

4

3

2

1

PR83

12

PR94

PR88

2.2_0603_5%

PR101

0_0603_5%

12

PC82

44.2K_0402_1%

1 2

12

12

12

BST_1.2V
UG_1.2V

LX_1.2V

LG_1.2V

1U_0603_10V6K

+1.2VALWP

D D

+1.2VALWP

C C

51124_B+

12

PC83

4.7U_1206_25V6K

1.8U_D104C-919AS-1R8N_9.5A_30%

1

12

+

PC84

2

220U_6.3V_M

12

PC75

4.7U_1206_25V6K

PL5

1 2

PC79

4.7U_0805_6.3V6K

2200P_0402_50V7K

12

PC77

PR90

PC87

12

4.7_1206_5%

12

680P_0603_50V7K

241

241

578

3 6

578

3 6

PQ16

AO4466_SO8

PC69

0.1U_0402_16V7K

UG_1.2V-1 UG_1.8V

PQ18
AO4712_SO8

0_0402_5%

0.1U_0402_16V7K@

75K_0402_1%

1 2

PU7

25

P PAD

7

PGOOD2

8

EN2

9

VBST2

10

DR VH2

11

LL2

12

DR VL2

PR93

6.49K_0402_1%

1 2

PC78

PR87

PR89

0_0402_5%

1 2

3.3_0402_5%

12

6

VO2

PGND2

13

PR98

1 2

4

5

VFB2

TRIP2

15

14

3

GND

TONSEL

V5FILT

V5IN

16

12

PC88

4.7U_0805_10V6K

2

VFB1

TRIP1

17

12

PR92

14.7K_0402_1%

PR99

75K_0402_1%

1

VO1

PGOOD1

EN1

VBST1

DR VH1

LL1

DR VL1

PGND1

TPS51124RGER_QFN24_4x4

18

+5VALWP

12

24
23
22
21
20
19

PR97

107K_0402_1%

BST_1.8V

LX_1.8V

LG_1.8V

12

1 2

12

2.2_0603_5%

PR96

0_0402_5%

PC80

0.1U_0402_16V7K@

+1.8VALWP

PR95

0.1U_0402_16V7K

12

PR100

0_0603_5%

PC81

1 2

12

UG_1.8V-1

SPOK <41,43>SPOK<41,43>

PQ17

AO4466_SO8

PQ19

AO4712_SO8

51124_B+

578

578

PC85

4.7U_1206_25V6K

3 6

241

1.8U_D104C-919AS-1R8N_9.5A_30%

3 6

241

PJ11

112

JUMP_43X118@

12

1 2

12

PR91

4.7_1206_5%

12

PC76

680P_0603_50V7K

2

B+

12

PC70

PL6

12

4.7U_1206_25V6K

PC71

2200P_0402_50V7K

+1.8VALWP

1

+

PC86
220U_6.3V_M

1 2

PC74

2

4.7U_0805_6.3V6K

B B

A A

5

4

VFB=0.764V

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

1.5VP/1.8VP

Friday, August 01, 2008

0.1

of

1

44 47

5

PJ12

B+

D D

SUSP#<30,31,39>

ZZZ

C C

ISL6268CAZ

2

12

PC149
3300P_0402_50V7K

+1.8VS

JUMP_43X118@

PR118

1 2

0_0402_5%

1

PJ15

1

JUMP_43X118

2

2

12

PC168

4.7U_0805_6.3V6K

112

4.7U_1206_25V6K

6268_B+

PC91

2.2U_0603_6.3V6K

12

12

12

1 2

0.1U_0603_25V7K@

PC96

PC99

0.1U_0402_16V7K

@

+5VS

12

PC92

4.7U_1206_25V6K

PC94

6268_1.05V

12

22P_0402_50V8J

PC167

1U_0603_6.3V6M

12

PC100

PR114
0_0603_5%

4

12

49.9K_0402_1%

6268_1.05V

PR112

10K_0402_1%

PU500

3

VIN

4

VCC

5

EN

12

PR121

12

PC102

6800P_0402_25V7K

12

2

8

GND

PGOOD

COMP6FB7FSET

FB_1.05V

57.6K_0402_1%

1

PR122

PHASE

PHASE_1.05V

DH_1.05-1

16

UG

9

12

PR111

1 2

PR113

1 2

2.2_0603_5%

BOOT_1.05V

15

BOOT

14

PVCC

PC95 2.2U_0603_6.3V6K

13

LG

12

PGND

11

ISEN

VO

10

12

PC500

@

0.01U_0402_25V7K

3

0_0603_5%

1 2

+5VS

PR115

12

0_0603_5%

PR116

4.7_0603_5%

1 2

1 2

LG_1.05V

ISEN_1.05V

1 2

PR119

3.65K_0402_1%

@

ISL6268CAZ-T_SSOP16

VFB=0.6V

DH_1.05-2

PC93

0.1U_0402_16V7K

6268_1.05V

AO4712_SO8

Rds=18mOHM

PQ21

578

3 6

578

3 6

241

241

PQ20
AO4466_SO8

PL7

1.8UH_SIL104R-1R8PF_9.5A_30%

1 2

12

PR117

4.7_1206_5%

12

PC98
680P_0603_50V7K

2

1

+1.05VSP

+1.05VSP

1

+

PC97
220U_D2_4VY_R15M

2

12

PR120

2.37K_0402_1%

12

PR123

3.01K_0402_1%

PU8

6

PR124

VCNTL

5

VIN

9

VIN

8

EN

7

POK

VFB=0.8V

12

12

PR126
1K_0402_1%

3

VOUT

4

VOUT

2

FB

GND

APL5913-KAC-TRL_SO8

1

12

12

PC106
10U_0805_6.3V6M

PC105

0.1U_0402_16V7K

PU9

VIN1VCNTL

2

GND

3

VREF

4

VOUT

APL5331KAC-TRL_SO8

+0.9VSP

4

3K_0402_1%

6
5

NC

7

NC

8

NC

9

TP

PR269

12

12

PR270

3.4K_0402_1%

12

12

PC170

0.01U_0402_25V7K

+3VALWP

PC104
1U_0603_6.3V6M

12

PC169

22U_0805_6.3V6M

+1.5VSP

12

6

PU11

7

POK

PR315

SUSP#<30,31,39>

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR DISCLO SED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

0_0402_5%

2005/10/17 2006/10/17

8

EN

12

PC269

0.1U_0402_16V7K

@

Compal Secret Data

Deciphered Date

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

VIN

GND

1

APL5912-KAC-TRL_SO8

+1.2VS+5VS

PJ16

2

JUMP_43X118@

2

PC263

1U_0603_6.3V6M

2

1

1
12

PC264

4.7U_0805_6.3V6K

12

PR316

1.1K_0402_1%

0.01U_0402_25V7K

12

PR319

3.4K_0402_1%

Size Document Number Rev

Date: Sheet

12

12

PC265

Compal Electronics, Inc.

Title

Custom

Friday, August 01, 2008

12

PC266

PC267

22U_0805_6.3V6M

1.05VSP/0.9VSP

12

PC268

@

22U_0805_6.3V6M

22U_0805_6.3V6M

1

1

+

PC270
220U_6.3V_M

@

2

+1.05VSP_LDO

of

45 47

0.1

PR268

0_0402_5%

0.1U_0402_16V7K@

4.7U_0805_6.3V6K

PR125

0_0402_5%

1 2

PC107

5

1 2

PC171

PC103

12

SSM3K7002F_SC59-3

+1.8V

PQ22

2

G

12

1

1

2

2

12

PJ13

JUMP_43X118

1K_0402_1%

13

D

S

SUSP#<30,31,39>

B B

A A

SUSP<39>

0.1U_0402_16V7K@

5

4

3

2

1

+5VS

1 2

12

12

PC109

2.2U_0603_6.3V6K

0.22U_0603_10V7K
PC115

1 2

1 2

0_0603_5%

PR143

1 2

PC123

AO4456-T1-E3_SO8

PR127
1_0603_5%

UGATE_CPU1-2

PQ24
AO4456-T1-E3_SO8

UGATE_CPU2-2

PQ27

+CPU_B+

12

12

3 5

241

PC110

PQ23
SI7686DP-T1-E3_SO8

10U_1206_25V6M

PC112

PC111

10U_1206_25V6M

12

5

4

5

D8D7D6D

S1S2S3G

4

D8D7D6D

PQ25

S1S2S3G

AO4456-T1-E3_SO8

PQ26
SI7686DP-T1-E3_SO8

4.7_1206_5%

12

PC116

680P_0603_50V8J

PR144

PR145

12

PC119

1

12

+

2

PC113

220U_25V_M

10U_1206_25V6M

.36UH +-20% ETQP4LR36WFC 24A

12

12

PR146

10K_0402_1%

3.65K_0805_1%

VSUM

ISEN1

0.22U_0603_10V7K

12

PC120

10U_1206_25V6M

3 5

241

5

5

D8D7D6D

S1S2S3G

4

4

12

PR157

D8D7D6D

S1S2S3G

4.7_1206_5%

12

PC125
680P_0603_50V8J

.36UH +-20% ETQP4LR36WFC 24A

12

PR159

PR158

10K_0402_1%

3.65K_0805_1%

VSUM

PQ28

AO4456-T1-E3_SO8

PL8

HCB4532KF-800T90_1812

1 2

12

PC143
2200P_0402_50V7K

12

12

PL9

PR148 0_0603_5%@

1 2

PC117

1 2

+CPU_B+

VCC_PRM

10U_1206_25V6M

12

PL10

12

PR164 0_0603_5%@

1 2

PC128

1 2

0.22U_0603_10V7K

ISEN2

PR147

1_0402_5%

12

PR160

1_0402_5%

VCC_PRM

B+

+CPU_CORE

D D

PR128 0_0402_5%

PM_DPRSLPVR_D<25>

H_DPRSTP#<5,25>

CLK_EN#<14>

PR131 0_0402_5%

12

PR140

PR142

499_0402_1%

+3VS

+3VS

1 2

VGATE<14>

H_PSI#<5>

PR152 4.22K_0402_1%@

PC118

@

0.015U_0402_16V7K

PMON

1 2

PR151 0_0402_5%@

1 2

100K_0603_1%_TH11-4H104FT@

1 2

PH2

1 2

C C

H_PROCHOT#<4,20>

PR153 13K_0402_1%

PC124 1000P_0402_50V7K

PR161 97.6K_0402_1%

1 2

1 2

B B

PC129 220P_0402_50V7K
255_0402_1%

1 2

PR166

PR168 1K_0402_1%

VCCSENSE<5>

+CPU_CORE

1 2

PR170 20_0402_5%

VSSSENSE<5>

1 2

PR149 0_0402_5%@

1 2

PR150 147K_0402_1%

VR_TT#

PC1210.022U_0603_50V7K

1 2

1 2
1 2

PC1221000P_0402_50V7K

PR156 6.81K_0402_1%

1 2

1 2

PC126 470P_0402_50V7K

12

PC130 1000P_0402_50V7K

1 2

1 2

1 2

PR169 0_0402_5%

PR173

12

12

PC134

0.018U_0603_50V7J

PC1320.018U_0603_50V7J

20_0402_5%

PR175 1K_0402_1%

VCC_PRM

0.22U_0603_10V7K

A A

PR129 0_0402_5%

PR130 0_0402_5%@

1 2

1 2

12

PC114

1U_0603_6.3V6M

1.91K_0402_1%

1

PGOOD

2

PSI#

3

PMON

4

RBIAS

5

VR_TT#

6

NTC

7

SOFT

8

OCSET

9

VW

10

COMP

11

FB

12

FB2

PR162

@

0_0402_5%

1 2

1 2

1 2

PR172 0_0402_5%

PC135180P_0402_50V8J

1 2

1 2

PC137

1 2

1 2

48

49

46

47

3V3

GND

CLK_EN#

DPRSTP#

ISL6262ACRZ-T_QFN48_7X7

VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1

12

PR165
1K_0402_1%

12

PC133

0.018U_0603_50V7J

1 2

PR176 3.92K_0402_1%

12

<31>

VR_ON

CPU_VID4

CPU_VID5

CPU_VID6

PR133

PR134

PR135

PR132

12

12

12

12

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

45

44

43

VR_ON

DPRSLPVR

12

PR174

PC1360.1U_0402_16V7K

1 2

PC1380.22U_0402_6.3V6K

12

CPU_VID2

CPU_VID3

PR136

PR138

PR137

12

12

12

0_0402_5%

0_0402_5%

12

PC127

1U_0402_6.3V6K

PR167

10_0603_5%

1 2

PC131

0.1U_0603_25V7K

12

PR171

12

PH3

11K_0402_1%

1 2

CPU_VID0

CPU_VID1

PR139

12

0_0402_5%

0_0402_5%

BOOT_CPU1

VID037VID138VID239VID340VID441VID542VID6

36

BOOT1
UGATE1
PHASE1

PGND1

LGATE1

PVCC

LGATE2

PGND2
PHASE2
UGATE2

BOOT2

24

1 2

35
34
33
32
31
30
29
28
27
26
25

NC

PU10

<BOM Structure>

ISEN1
ISEN2

UGATE_CPU1-1

PHASE_CPU1

UGATE_CPU2-1

BOOT_CPU2

PR163 1_0603_5%

+CPU_B+

VSUM

2.61K_0402_1%

10KB_0603_5%_ERTJ1VR103J

LGATE_CPU1

PHASE_CPU2

1 2

PR155

2.2_0603_5%

+5VS

PC108

0.022U_0402_16V7K

2.2_0603_5%
PR141

1 2

LGATE_CPU2

PR154

1 2

0_0603_5%

0.22U_0603_10V7K

<5>

<5>

<5>

<5>

<5>

<5>

<5>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2005/10/17 2006/10/17

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

+CPU_CORE

46 47Friday, August 01, 2008

1

0.1

of

5

4

3

2

1

page Reason for change Modify list

PVT Add PR46 & PC37 for EMI request

Add bead at charger B+ for EMI request

D D

Add PR141,PR144,PC116,PR155,PR157,PC125 for EMI power board band noise.

Add PC87,PR90,PR88,PR95,PR91,PC76 for EMI power board band noise.

Add PR113,PR117,PC98 for EMI power board band niose.

Change 1.8V from 1.836 to 1.853. SO PR97 to 107K for HW request

Change PR176 to 3.92K for adjust Loadline

Change PC97 to 220UF form EVT SMT MEMO

C C

B B

A A

Title

<Title>

Size Document Number Rev

<Doc> <RevCode>

Custom

5

4

3

2

Date: Sheet

1

of

47 47Friday, August 01, 2008