INTELBRAS I30, LA-3961P Schematics

A

[e-mail]

B

C

D

E

PJP1

14W_DCIN

14W_45@

1 1

ZZZ1

PCB

<BOM Structure>

PJP1

15W_DCIN

15W_45@

Compal Confidential

2 2

Intel Merom Processor with SiSM672MX + DDRII + SiS968 + SiS307LV

JFWXX Schematics Document

2007-09-06
REV: 0.3

3 3

4 4

A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

JFWXX M/B LA-3961P Schematic

149Thursday, September 06, 2007

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Compal Confidential

Model Name : JFWXX

Fan Control

page 4

File Name : LA-3961P

1 1

CRT & TV-out

page 17

Intel Merom Processor

uPGA-478 Package

H_A#(3..35)

FSB

667/800MHz

page 4,5,6

H_D#(0..63)

SiS M672MX

LCD Conn.

page 17

SiS 307LV

page 18

PCI-Express

TEBGA-847

page 7,8,9,10,11

Thermal Sensor

ADM1032

page 4

Memory BUS(DDRII)

Single Channel

1.8V DDRII 533/667

Clock Generator

ICS9LPRS600C+
ICS9P935

page 14,15

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

page 12,13

1GB/s MuTIOL IO Link

2 2

PCI-Express

SiS968

MII

TEBGA-570

page 19,20,21,22,23

New Card
Socket

page 30

MINI Card x1

WLAN

page 29

LAN

page 28

PCI BUS

3.3V 33 MHz

IDSEL:AD22
(PIRQG#,PIRQH#,
GNT#0, REQ#0)

Card Reader

R5C833

page 26

USB conn x2
TO M/B

page 33

3.3V 48MHz

3.3V 24.576MHz/48Mhz

3.3V ATA-100
S-ATA

port 0

S-ATA HDD
Conn.

RJ45

3 3

RTC CKT.

page 20

Power On/Off CKT.

page 34

Switch/B Conn.

page 32

page 28

1394
Conn.

page 26

3 in 1
socket

page 27

Touch Pad

page 33

ENE KB926

LPC BUS

page 31

Int.KBD

page 32

USB conn x2
TO I/O/B

USB

IDE

page 24

Bluetooth

page 37 page 33 page 37

Conn

Web Camera

HD Audio

CDROM
Conn.

page 24

MDC 1.5
Conn

page 37

HDA Codec

ALC268

Audio AMP

page 36

page 35

DC/DC Int erface CKT.

page 40

I/O Conn.

BIOS

page 33

FRONT LCD /B.

Power Circuit DC/DC

4 4

page 41,42,44,458
46,47,48

LID SW

page 34

CHARGER

page 43

A

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

Block Diagrams

JFWXX M/B LA-3961P Schematic

249Thursday, September 06, 2007

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Voltage Rails

DescriptionPower Plane

1 1

2 2

VIN
B+
+CPU_CORE

+1.05VS

+1.5VS
+1.8V

+2.5VS
+3VALW
+3VS
+5VALW
+5VS

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

0.9V switched power rail for DDR terminator+0.9VS ( Actual +0.9V )

1.05V switched power rail

1.5V switched power rail

1.8V power rail for DDR

1.8V switched power rail+1.8VS

2.5V switched power rail

3.3V always on power rail

3.3V switched power rail
5V always on power rail
5V switched power rail

RTC power+RTCVCC

SIGNAL

SLP_S3#SLP_S1#

HIGH HIGH HIGH

LOW

LOW

LOW

LOW LOW LOW

SLP_S4#

HIGH

LOWLOWLOW

SLP_S5#

HIGHHIGHHIGHHIGH

HIGH

HIGH

LOW

S3S1

N/A N/A N/A

OFFON

ON

ON

ON1.25V switched power rail+1.25VS

ON

ON

OFF

ON
ON

OFF

ON

OFF

ON
ON

ON
OFF

ON OFF

ONONON

+VALW

+V +VS Clock

ON

ON

ON

ON

ON

ON

ON

OFF

ON

OFF

S5

N/AN/AN/A

OFF
OFF
OFFOFFON
OFFOFF
OFFOFFON
OFF
OFF
OFF
ON*ON
OFF
ON*

ON*ONVSB always on power rail+VSB
ON

ON

OFF

OFF

OFF

ONON

LOW

OFF

OFF

OFF

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

External PCI Devices

DEVICE

1394+Cardreader G,H

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

IDSEL #

AD20
AD22

Address

1010 000X b

REQ/GNT #

2

PIRQ

C,DCARD BUS CB1410

0

EC SM Bus2 address

Device

ADI ADM1032
NVIDIA NB8X

Address

1001 100X b0001 011X b

ICH8M SM Bus address

Device

Clock Generator
(ICS9LPRS325AKLFT_MLF72)

DDR DIMM0
DDR DIMM1

Address

1101 001Xb

1010 000Xb
1010 010Xb

PROJECT ID Table

3 3

14W
15W

PROJECT_ID
R424 (Pull low)
NA (Internal Pull High)

SKU ID Table

Vcc 3.3V +/- 5%

100K +/- 5%Ra

Ra~ R312

R311

8.2K_0402_5%

14_B@

R311

18K_0402_5%

14_C@

R311

33K_0402_5%

14_MP@

R311

56K_0402_5%

15_A@

R311

100K_0402_5%

15_B@

Rb~ R311

Board ID

0
1
2
3
4
5

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

6
7

2006/08/18 2007/8/18

Rb

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

NC

Compal Secret Data

Vmin

AD_BID

0 V

Vtyp

AD_BID

0 V 0 V

0.217 V 0.250 V 0.288 V

0.439 V

0.721 V

1.054 V

0.503 V

0.819 V

1.185 V 1.325 V

1.489 V 1.650 V 1.819 V

2.019 V

3.135V

Deciphered Date

2.200 V

3.300 V

D

V

max

AD_BID

Rb BOM Structure

0.575 V

0.926 V

2.386 V

3.465 V

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

JFWXX M/B LA-3961P Schematic

14_A@
14_B@
14_C@
14_MP@
15_A@
15_B@
15_C@
15_MP@

Notes List

R311

200K_0402_5%

15_C@

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1

Trace length must short

H_PREQ#
H_IERR#
ITP_TMS
ITP_TDI
H_PROCHOT#
ITP_TCK
ITP_TRST#

Checklist recommend 39 Ohm

ADM1032

1

C111

2200P_0402_50V7K

+VCC_FAN1
EN_FAN1

+5VS

FAN_SPEED1<31>

2

THERMDA

2

THERMDC

C58 10U_0805_10V4Z

U3

1

VEN

2

VIN

3

VO

4

VSET

G993P1UF_SOP8

Place close to CPU within 500mil

+1.05VS

R85 56_0402_5%@

1 2

R115 56_0402_5%

1 2

R84 56_0402_5%

1 2

R83 150_0402_1%

1 2

R113 56_0402_5%

1 2

R69 27.4_0402_1%

1 2

R61 680_0402_5%

1 2

CRB pull 75 Ohm

+3VS

C112 0.1U_0402_16V4Z

1 2

U7

1

VDD

2

D+

3

D­THERM#4GND

ADM1032ARMZ_MSOP8

F75383M_MSOP8

1 2

8

GND

7

GND

6

GND

5

GND

+3VS

12

R31
10K_0402_5%

+VCC_FAN1

1

C54
1000P_0402_50V7K

2

Title

Size Document Number Rev

B

JFWXX M/B LA-3961P Schematic

Date: Sheet

SDATA

ALERT#

40mil

SCLK

8
7
6
5

+5VS

12

D12
1SS355_SOD323

1000P_0402_50V7K

C52 10U_0805_10V4Z

D11

1 2

BAS16_SOT23-3

1 2

C55

1 2

1
2
3

4
5

EC_SMB_CK2 <31>
EC_SMB_DA2 <31>

JP6

1
2
3

GND
GND

ACES_85205-03001

ME@

Compal Electronics, Inc.

Merom (1/3)

449Thursday, Sept em be r 06, 2007

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of

0.1

H_A#[3..35]
H_REQ#[0..4]
H_RS#[0..2]

5

H_ADSTB#0<7>

H_ADSTB#1<7>

H_A20M#<20>

H_FERR#<20>

H_IGNNE#<20>

H_STPCLK#<20>

H_INTR<20>

H_NMI<20>

H_SMI#<20>

H_STPCLK#
H_INIT#
H_IGNNE#
H_SMI#
H_A20M#
H_NMI
H_INTR
H_THERMTRIP#
H_FERR#

H_BR0#
H_RESET#
ITP_DBRESET#

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

JP36A

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Merom Ball-out Rev 1a

conn@

ADDR GROUP 0 ADDR GROUP 1

ICH

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

XDP/ITP SIGNALS

DBR#

THERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

H CLK

BCLK[0]
BCLK[1]

RESERVED

H1
E2
G5

H5
F21
E1

F1

H_IERR#

D20

H_INIT#

B3
H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2

H_PREQ#

AC1

ITP_TCK

AC5

ITP_TDI

AA6

TDI

AB3

ITP_TMS

AB5

ITP_TRST#

AB6

ITP_DBRESET#

C20

H_PROCHOT#

D21

THERMDA

A24

THERMDC

B25

H_THERMTRIP#

H_THERMTRIP#

C7

C114 0.1U_0402_16V4Z

1 2

A22
A21

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel : Pull-up 56ohm (Mount) SiS : Pull-up 56ohm (Mount)
Intel : Pull-up 56ohm (Mount) SiS : Pull-up 56ohm (Mount)

Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Un-Mount)
Intel :Don't Pull-up SiS : Pull-up 150ohm (Mount)

4

H_ADS# <7>
H_BNR# <7>
H_BPRI# <7>

H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>

H_BR0# <7>

H_INIT# <20>
H_LOCK# <7>
H_RESET# <7>

H_TRDY# <7>
H_HIT# <7>

H_HITM# <7>

ITP_DBRESET#

H_PROCHOT# <20>

H_CLK_DP0 <14>
H_CLK_DN0 <14>

Connect SB SYS_RESET# or just left NC

Intel :Pull-up 56ohm (Un-Mount) SiS : Pull-up 56ohm (Mount)

Intel :Pull-up 56ohm (Mount) SiS : Pull-up 54.9ohm (Mount)

Intel :Pull-up 56ohm (Mount) SiS : Pull-up 75ohm (Mount)

H_THERMTRIP# <20>

FAN1 Conn

EN_FAN1<31>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

H_A#[3..35]<7>

H_REQ#[0..4]<7>

H_RS#[0..2]<7>

D D

C C

B B

+1.05VS

CPU to SB interface

R120 56_0402_5%

1 2

R141 56_0402_5%

1 2

R128 56_0402_5%

1 2

R144 56_0402_5%

1 2

R148 56_0402_5%

1 2

R137 56_0402_5%

1 2

R140 56_0402_5%

1 2

R127 56_0402_5%

A A

1 2

R214 56_0402_5%

1 2

+1.05VS

R114 51_0402_1%

1 2

R136 56_0402_5%@

1 2

R112 150_0402_1%

1 2

5

[e-mail]

GTL_REF

1

C368
1U_0603_10V4Z

2

D D

SiS Recommend

Close to CPU pin AD26
within 500mils.

C C

Width=20 mil

B B

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

1

2

R321

1K_0402_1%

R319

2K_0402_1%

C369
220P_0402_50V7K

+1.05VS

1 2

R111 1K_0402_5%@
R98 1K_0402_5%@

1 2

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14

PAD
PAD

PAD

H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

GTL_REF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

H_DSTBN#0<7> H_DSTBN#2 <7>
H_DSTBP#0<7> H_DSTBP#2 <7>

H_DINV#0<7>

H_DSTBN#1<7> H_DSTBN#3 <7>
H_DSTBP#1<7> H_DSTBP#3 <7>

H_DINV#1<7>

12
12

1 2

T3
T2

T23

H_BSEL0<14>
H_BSEL1<14>
H_BSEL2<14>

C364 0.1U_0402_16V4Z@

CPU_BSEL CPU_BSEL2 CPU_BSEL1

001133

166

200

01

0

1

4

JP36B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

conn@

CPU_BSEL0

1

0

DATA GRP 0

DATA GRP 1

MISC

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#

DATA GRP 2DATA GRP 3

D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP0
COMP1
COMP2
COMP3

H_DPSLP#
H_DPWR#_R
H_PWRGOOD
H_CPUSLP#

3

H_D#[0..63]

H_DINV#2 <7>

R324 27.4_0402_1%
R323 54.9_0402_1%
R42 27.4_0402_1%
R44 54.9_0402_1%

H_DPWR#_R H_DPWR#

R131
10_0402_5%

H_DINV#3 <7>

1 2
1 2
1 2
1 2

H_DPRSTP# <25,48>
H_DPSLP# <25>

H_PWRGOOD <7>
H_CPUSLP# <20>
H_PSI# <48>

H_D#[0..63] <7>

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

@

1 2

R126 0_0402_5%

+CPU_CORE

H_DPWR# <7>

2

JP36C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

conn@

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

+CPU_CORE

VCCSENSE

VSSSENSE

CPU_VID0 <48>
CPU_VID1 <48>
CPU_VID2 <48>
CPU_VID3 <48>
CPU_VID4 <48>
CPU_VID5 <48>
CPU_VID6 <48>

R27

R24 100_0402_1%

Length match within 25 mils.

1

Place this cap more close to
B26/C26 rather than 10UF

1

+

C80
330U_D2E_2.5VM_R9

2

20mils

1

C438

0.01U_0402_16V7K

2

1 2

1 2

100_0402_1%

+CPU_CORE

VCCSENSE <48>

VSSSENSE <48>

+1.05VS

+1.5VS

1

C432
10U_0805_10V4Z

2

The trace width/space/other is

+1.05VS

R121 56_0402_5%

A A

1 2

R143 56_0402_5%

1 2

R133 56_0402_5%@

1 2

R119 56_0402_5%@

1 2

C650 0.1U_0402_16V4Z@

1 2

5

H_CPUSLP#
H_DPSLP#
H_PWRGOOD
H_DPWR#

H_PWRGOOD

Intel :Don't Pull-up SiS : Pull-up 56ohm (Mount)

SiS Recommend
Intel :Pull-up 56ohm (Un-Mount) SiS : Pull-up 56ohm (Mount)
Intel :Don't Pull-up (Connecte to ICH) SiS : Pull-up 56ohm (Un-Mount)
Intel :Don't Pull-up SiS : Pull-up 56ohm (Un-Mount)

Intel :Don't Pull-down SiS :Pull-down Cap (Un-Mount)

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

2

20/7/25.

Close to CPU pin
within 500mils.

Title

Size Document Number Rev

B

JFWXX M/B LA-3961P Schematic

Date: Sheet

Compal Electronics, Inc.

Merom (2/3)

549Thursday, Sept em be r 06, 2007

1

0.1

of

5

4

3

2

1

+CPU_CORE

JP36D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

D D

C C

B B

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

conn@

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

1

+

C47
330U_D2E_2.5VM_R9

2

+CPU_CORE

1

C394

2

10U_0805_6.3V6M

+CPU_CORE

1

C379

2

10U_0805_6.3V6M

+CPU_CORE

1

C107

2

10U_0805_6.3V6M

+CPU_CORE

1

C77

2

10U_0805_6.3V6M

+CPU-CORE
Decoupling
SPCAP,Polymer

MLCC 0805 X5R

3 x 330uF(9mOhm/3) 3 x 330uF(9mOhm/3)

1

+

C350

2

330U_D2E_2.5VM_R9

South Side Seco ndary North Side Sec ondary

1

C383

10U_0805_6.3V6M

2

10U_0805_6.3V6M

1

+

C390

@

330U_D2E_2.5VM_R9

2

1

C408

10U_0805_6.3V6M

2

(Place these capacitors on South side,Secondary Layer)

1

C378

10U_0805_6.3V6M

2

1

C377

2

10U_0805_6.3V6M

10U_0805_6.3V6M

(Place these capacitors on North side,Secondary Layer)

1

C106

10U_0805_6.3V6M

2

1

C105

2

10U_0805_6.3V6M

10U_0805_6.3V6M

(Place these capacitors on South side,Primary Layer)

1

C76

10U_0805_6.3V6M

2

1

C75

2

10U_0805_6.3V6M

10U_0805_6.3V6M

(Place these capacitors on North side,Primary Layer)

C,uF ESR, mohm ESL,nH
6X330uF 9m ohm/6 1.8nH/6

32X22uF 3m ohm/32 0.6nH/32
32X10uF 3m ohm/32 0.6nH/32

+1.05VS

1

2

0.1U_0402_16V4Z

1

C97

0.1U_0402_16V4Z

2

C87

0.1U_0402_16V4Z

1

2

1

2

1

2

1

2

1

C81

0.1U_0402_16V4Z

2

+CPU_CORE

1

+

C347

330U_D2E_2.5VM_R9

2

330U_D2E_2.5VM_R9

C409

C376

C104

C74

1

C410

2

10U_0805_6.3V6M

1

C375

2

10U_0805_6.3V6M

1

C103

2

10U_0805_6.3V6M

1

C84

2

10U_0805_6.3V6M

1

C96

2

0.1U_0402_16V4Z

1

+

C155

2

1

10U_0805_6.3V6M

2

1

10U_0805_6.3V6M

2

1

10U_0805_6.3V6M

2

1

10U_0805_6.3V6M

2

1

C83

0.1U_0402_16V4Z

2

C169

@

330U_D2E_2.5VM_R9

C411

10U_0805_6.3V6M

C385

10U_0805_6.3V6M

C89

10U_0805_6.3V6M

C78

10U_0805_6.3V6M

1

C73

2

1

+

2

1

C412

10U_0805_6.3V6M

2

1

C393

10U_0805_6.3V6M

2

1

C46

10U_0805_6.3V6M

2

1

C88

10U_0805_6.3V6M

2

1

CRB no stuff. Reserved!

C392

2

1

C384

2

1

C90

2

1

C85

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

2

Date: Sheet

Compal Electronics, Inc.

Merom (3/3)

JFWXX M/B LA-3961P Schematic

649Thursday, Sept em be r 06, 2007

1

0.1

of

5

+1.05VS

12

R210

75_0402_1%

D D

12

R202

150_0402_1%

C C

B B

+1.8VS +1.8VS

A A

L40

1 2

MBK1608121YZF_0603

1

C454
10U_0805_10V4Z

2

1 2

R399 0_0402_5%

1

C191

0.01U_0402_16V7K

2

1

C212

2

0.01U_0402_16V7K

1

C472

0.1U_0402_16V4Z

2

5

1

C200

0.1U_0402_16V4Z

2

PAD

T30

PAD

T5

H_DPWR#<5>

H_CLK_DP1<14>

H_CLK_DN1<14>

H_LOCK#<4>
H_DEFER#<4>
H_TRDY#<4>

H_RESET#<4>

H_PWRGOOD<5>

H_BPRI#<4>
H_BR0#<4>
H_RS#[0..2]<4>

H_ADS#<4>

H_HITM#<4>

H_HIT#<4>

H_DRDY#<4>
H_DBSY#<4>
H_BNR#<4>

H_REQ#[0..4]<4>

H_ADSTB#0<4>
H_ADSTB#1<4>
H_A#[3..35]<4>

C1XAVDD:10mA C4XAVDD:12mA

C1XAVDD

1

C481

0.01U_0402_16V7K

2

C1XAVSS

C1XAVDD
C1XAVSS

C4XAVDD
C4XAVSS

NB_GTLREF

PCREQ#
EDRDY#

H_DPWR#

H_CLK_DP1
H_CLK_DN1

H_LOCK#
H_DEFER#
H_TRDY#
H_RESET#
H_PWRGOOD
H_BPRI#
H_BR0#

H_RS#0
H_RS#1
H_RS#2

H_ADS#
H_HITM#
H_HIT#
H_DRDY#
H_DBSY#
H_BNR#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0
H_ADSTB#1

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

1 2

MBK1608121YZF_0603

1

C455
10U_0805_10V4Z

2

R400 0_0402_5%

L39

1 2

B16
C17

A17
B18

W24

U24
R24
N24

R34
P32

E21

F18

G18

P30
P31
F21
P28
N30
P33

K34

M31

K33

M34

N34
N32

M33
M32

T34
R30
R29
R32
P34

U34

AA34

T32
T28
T31
T33
T30
U32
U30
V34
U29
V33
V32
V28
V31

W34

Y33

W32

V30

W30

Y34
Y28

W29

Y32
Y30

Y31
AA32
AA30
AA29
AB33
AB34
AB32
AC34
AB30
AB31

L21

L32

L34

4

U30C

C1XAVDD
C1XAVSS

C4XAVDD
C4XAVSS

HVREF
HVREF
HVREF
HVREF
HVREF

PCREQ#
EDRDY#

DPWR#

CPUCLK
CPUCLK#

HLOCK#
DEFER#
HTRDY#
CPURST#
CPUPWRGD
BPRI#
BREQ0#

RS0#
RS1#
RS2#

ADS#
HITM#
HIT#
DRDY#
DBSY#
BNR#

HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#

HASTB0#
HASTB1#

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HA32#
HA33#
HA34#
HA35#

SISM672MX-A1_TEBGA_847P

1

C470

0.1U_0402_16V4Z

2

Host

1

2

4

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

DBI0#
DBI1#
DBI2#
DBI3#

HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#

HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#

HPCOMP
HNCOMP

C4XAVDD

C479

0.01U_0402_16V7K

C4XAVSS

3

H_D#0

N29

H_D#1

M30

H_D#2

M28

H_D#3

L30

H_D#4

L29

H_D#5

K28

H_D#6

K31

H_D#7

K30

H_D#8

H31

H_D#9

G34

H_D#10

H32

H_D#11

G32

H_D#12

K32

H_D#13

F34

H_D#14

F33

H_D#15

F32

H_D#16

H28

H_D#17

J30

H_D#18

H30

H_D#19

G29

H_D#20

J29

H_D#21

G30

H_D#22

F30

H_D#23

D33

H_D#24

D34

H_D#25

B32

H_D#26

B33

H_D#27

C34

H_D#28

D31

H_D#29

A32

H_D#30

A31

H_D#31

C31

H_D#32

B30

H_D#33

C30

H_D#34

A30

H_D#35

D28

H_D#36

G28

H_D#37

C29

H_D#38

C28

H_D#39

E28

H_D#40

E27

H_D#41

C27

H_D#42

G26

H_D#43

E26

H_D#44

D26

H_D#45

B26

H_D#46

A26

H_D#47

C26

H_D#48

G22

H_D#49

C24

H_D#50

A25

H_D#51

B24

H_D#52

C25

H_D#53

A24

H_D#54

E23

H_D#55

E25

H_D#56

G24

H_D#57

D22

H_D#58

C22

H_D#59

E22

H_D#60

C23

H_D#61

A23

H_D#62

A22

H_D#63

B22

H_DINV#0

J32

H_DINV#1

E32

H_DINV#2

F27

H_DINV#3

F23

H_DSTBN#0

H33

H_DSTBN#1

E31

H_DSTBN#2

B28

H_DSTBN#3

D24

H_DSTBP#0

H34

H_DSTBP#1

D32

H_DSTBP#2

A28

H_DSTBP#3

E24

H_PCOMP

A21
C21

R175 10_0402_5%

H_NCOMP

R188 110_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

H_D#[0..63] <5>

V_AVDD_PCIE_1.2V

SB_PCIE_WAKE#<21,29,30>

INT_N_A<9,19>

H_DINV#0 <5>
H_DINV#1 <5>
H_DINV#2 <5>
H_DINV#3 <5>

H_DSTBN#0 <5>
H_DSTBN#1 <5>
H_DSTBN#2 <5>
H_DSTBN#3 <5>

H_DSTBP#0 <5>
H_DSTBP#1 <5>
H_DSTBP#2 <5>
H_DSTBP#3 <5>

+1.05VS

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

+1.2VS V_AVDD_PCIE_1.2V

SB_PCIE_WAKE#
INT_N_A

2

L22

1 2

MBK1608121YZF_0603

U30D

P7

PCIEAVDD

R7

PCIEAVDD

T7

PCIEAVDD

U7

PCIEAVDD

V7

PCIEAVDD

D7

PME#

G16

INTX#

E4

PERP0

E5

PERN0

F1

PERP1

G1

PERN1

H3

PERP2

H2

PERN2

H1

PERP3

J1

PERN3

K1

PERP4

PCIE

PERN4
PERP5
PERN5
PERP6
PERN6
PERP7
PERN7
PERP8
PERN8
PERP9
PERN9
PERP10
PERN10

PETN10(HDVBN1)
PERP11
PERN11

PETN11(HDVBN0)
PERP12
PERN12
PERP13
PERN13

PETN13(HDVAN2)
PERP14
PERN14

PETN14(HDVAN1)
PERP15
PERN15

PETN15(HDVAN0)

SISM672MX-A1_TEBGA_847P

HDVBP2
HDVBN2
HDVBP1
HDVBN1
HDVBP0
HDVBN0

HDVAP2
HDVAN2
HDVAP1
HDVAN1
HDVAP0
HDVAN0

AA1
AB1
AB2
AC1
AD1
AE1
AE2

AF1

AG1

K2
L1

M1

N1
N2
P1
R1
T1
T2
U1

V1
W1
W2

Y1

2

1

PCIEAVDD:77mA

1

C201

0.1U_0402_16V4Z

2

REFCLK+

REFCLK-

PETP0
PETN0
PETP1
PETN1
PETP2
PETN2
PETP3
PETN3
PETP4
PETN4
PETP5
PETN5
PETP6
PETN6
PETP7
PETN7
PETP8
PETN8

PETP9(HDVBP2)

PETN9(HDVBN2)

PETP10(HDVBP1)
PETP11(HDVBP0)

PETP12
PETN12

PETP13(HDVAP2)
PETP14(HDVAP1)
PETP15(HDVAP0)

C653 0.1U_0402_10V7K

12

C660 0.1U_0402_10V7K

12

C662 0.1U_0402_10V7K

12

C654 0.1U_0402_10V7K

12

C655 0.1U_0402_10V7K

12

C656 0.1U_0402_10V7K

12

C658 0.1U_0402_10V7K

12

C657 0.1U_0402_10V7K

12

C652 0.1U_0402_10V7K

12

C651 0.1U_0402_10V7K

12

C659 0.1U_0402_10V7K

12

C661 0.1U_0402_10V7K

12

Title

Size Document Number Rev

Custom

Date: Sheet

1

C218

0.01U_0402_16V7K

2

PCIE_CLK_NB

T5
T4

G6
H6
G4
G5
J6
K6
J4
J5
L6
M6
M4
M5
P6
R6
P4
P5
V6
W6
W4
W5
Y6
AA6
AA4
AA5
AB6
AC6
AC4
AC5
AD6
AE6
AE4
AE5

PCIE_CLK_NB#

HDVBP2
HDVBN2
HDVBP1
HDVBN1
HDVBP0
HDVBN0

HDVAP2
HDVAN2
HDVAP1
HDVAN1
HDVAP0
HDVAN0

HDVBP2_C
HDVBN2_C
HDVBP1_C
HDVBN1_C
HDVBP0_C
HDVBN0_C

HDVAP2_C
HDVAN2_C
HDVAP1_C
HDVAN1_C
HDVAP0_C
HDVAN0_C

PCIE_CLK_NB <14>
PCIE_CLK_NB# <14>

HDVBP2_C <18>
HDVBN2_C <18>
HDVBP1_C <18>
HDVBN1_C <18>
HDVBP0_C <18>
HDVBN0_C <18>

HDVAP2_C <18>
HDVAN2_C <18>
HDVAP1_C <18>
HDVAN1_C <18>
HDVAP0_C <18>
HDVAN0_C <18>

Compal Electronics, Inc.

M672MX (1/5)-HOST/PCIE

JFWXX M/B LA-3961P Schematic

1

0.1

749Thursday, Sept em be r 06, 2007

of

5

4

3

2

1

DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..14]

D D

C C

B B

A A

DDRA_SDQ[0..63] <12,13>

DDRA_SDM[0..7] <12,13>

DDRA_SMA[0..14] <12,13>

DDRA_SDQS0<12,13>
DDRA_SDQS0#<12,13>

DDRA_SDQS1<12,13>
DDRA_SDQS1#<12,13>

DDRA_SDQS2<12,13>
DDRA_SDQS2#<12,13>

DDRA_SDQS3<12,13>

DDRA_SDQS3#<12,13>

DDRA_SDQS4<12,13>
DDRA_SDQS4#<12,13>

DDRA_SDQS5<12,13>

DDRA_SDQS5#<12,13>

DDRA_SDQS6<12,13>
DDRA_SDQS6#<12,13>

DDRA_SDQS7<12,13>

DDRA_SDQS7#<12,13>

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDM0
DDRA_SDQS0
DDRA_SDQS0#

DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDM1
DDRA_SDQS1
DDRA_SDQS1#

DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDM2
DDRA_SDQS2
DDRA_SDQS2#

DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDM3
DDRA_SDQS3
DDRA_SDQS3#

DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDM4
DDRA_SDQS4
DDRA_SDQS4#

DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDM5
DDRA_SDQS5
DDRA_SDQS5#

DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDM6
DDRA_SDQS6
DDRA_SDQS6#

DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDM7
DDRA_SDQS7
DDRA_SDQS7#

U30B

AD31

MD0A

AD30

MD1A

AG34

MD2A

AE29

MD3A

AE32

MD4A

AF34

MD5A

AF31

MD6A

AE30

MD7A

AD28

DQM0A

AF32

DQS0A

AF33

DQS0A#

AF28

MD8A

AJ34

MD9A

AH31

MD10A

AG30

MD11A

AF30

MD12A

AG32

MD13A

AJ32

MD14A

AJ31

MD15A

AH34

DQM1A

AH32

DQS1A

AH33

DQS1A#

AK34

MD16A

AH30

MD17A

AL32

MD18A

AM33

MD19A

AK32

MD20A

AG29

MD21A

AM34

MD22A

AL31

MD23A

AJ30

DQM2A

AK33

DQS2A

AL34

DQS2A#

AM32

MD24A

AP32

MD25A

AP31

MD26A

AM29

MD27A

AK30

MD28A

AK29

MD29A

AJ27

MD30A

AK28

MD31A

AN32

DQM3A

AM30

DQS3A

AM31

DQS3A#

AK20

MD32A

AM20

MD33A

AM19

MD34A

AJ19

MD35A

AN20

MD36A

AJ21

MD37A

AP19

MD38A

AH20

MD39A

AK21

DQM4A

AK19

DQS4A

AL19

DQS4A#

AK18

MD40A

AJ17

MD41A

AK17

MD42A

AP16

MD43A

AH18

MD44A

AP18

MD45A

AN18

MD46A

AP17

MD47A

AM18

DQM5A

AL17

DQS5A

AM17

DQS5A#

AN16

MD48A

AK16

MD49A

AN14

MD50A

AJ15

MD51A

AP15

MD52A

AM16

MD53A

AK15

MD54A

AP14

MD55A

AH16

DQM6A

AL15

DQS6A

AM15

DQS6A#

AL13

MD56A

AM13

MD57A

AM12

MD58A

AJ13

MD59A

AM14

MD60A

AK14

MD61A

AN12

MD62A

AH14

MD63A

AK13

DQM7A

AP12

DQS7A

AP13

DQS7A#

SISM672MX-A1_TEBGA_847P

DRAM

D1XAVDD
D1XAVSS

D4XAVDD
D4XAVSS

MA0A
MA1A
MA2A
MA3A
MA4A
MA5A
MA6A
MA7A
MA8A

MA9A
MA10A
MA11A
MA12A
MA13A
MA14A
MA15A
MA16A
MA17A

RASA#
CASA#

WEA#

FWDSDCLKOA

FWDSDCLKOA#

CS0A#
CS1A#
CS2A#
CS3A#

ODT0A
ODT1A
ODT2A
ODT3A

CKEA0
CKEA1
CKEA2
CKEA3

DDRVREF0
DDRVREF1

DDRCOMP
DDRCOMN

OCDVREFP
OCDVREFN

S3AUXSW#

A15
B15

AP11
AP10

AH24
AP25
AM25
AL25
AP26
AM26
AN26
AK25
AP27
AP28
AK24
AN24
AP24
AM28
AM27
AN28
AP21
AP29

AM23
AP22
AJ23

AK12
AH12

AP23
AH22
AM22
AM21

AK22
AP20
AN22
AL21

AN30
AP30
AH26
AK27

AD18
AD23

AJ25
AK26

AH28
AJ29

B6

D1XAVDD
D1XAVSS

D4XAVDD
D4XAVSS

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SBS0
DDRA_SBS1
DDRA_SBS2
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13

DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#

CLK_INT
CLK_INC

DDRA_SCS0#
DDRA_SCS1#
DDRA_SCS2#
DDRA_SCS3#

DDRA_ODT0
DDRA_ODT1
DDRA_ODT2
DDRA_ODT3

DDRA_CKE0
DDRA_CKE1
DDRA_CKE2
DDRA_CKE3

DDRVREF

DDRCOMP
DDRCOMN

OCDVREFP
OCDVREFN

S3AUXSW#

DDRA_SBS0 <12,13>
DDRA_SBS1 <12,13>
DDRA_SBS2 <12,13>

DDRA_SRAS# <12,13>
DDRA_SCAS# <12,13>
DDRA_SWE# <12,13>

CLK_INT <15>
CLK_INC <15>

DDRA_SCS0# <12>
DDRA_SCS1# <12>
DDRA_SCS2# <13>
DDRA_SCS3# <13>

DDRA_ODT0 <12>
DDRA_ODT1 <12>
DDRA_ODT2 <13>
DDRA_ODT3 <13>

DDRA_CKE0 <12>
DDRA_CKE1 <12>
DDRA_CKE2 <13>
DDRA_CKE3 <13>

R225 36_0402_1%
R227 36_0402_1%

S3AUXSW# <31>

+1.8V

+1.8VS

1 2

MBK1608121YZF_0603

1

C456
10U_0805_10V4Z

2

R409 0_0402_5%

+1.8VS

1 2

MBK1608121YZF_0603

1

C583
10U_0805_10V4Z

2

R473 0_0402_5%

+1.8V

12

R276

1K_0402_1%

12

R501

1K_0402_1%

+1.8V +1.8V

12

R277

40.2_0402_1%

12

R224
36_0402_1%

L41

1

C480

0.1U_0402_16V4Z

1 2

L52

1 2

OCDVREFP OCDVREFN

2

1

C582

0.1U_0402_16V4Z

2

1

C251

0.1U_0402_16V4Z

2

1

C238

2

0.1U_0402_16V4Z

1

2

12

R511
36_0402_1%

12

R228

40.2_0402_1%

C233
1U_0603_10V4Z

D1XAVDD:7mA

D1XAVDD

1

C471

0.01U_0402_16V7K

2

D1XAVSS

D4XAVDD:10mA

D4XAVDD

1

C581

0.01U_0402_16V7K

2

D4XAVSSDDRA_SMA14

DDRVREF

Place C233
under M672MX
solder side.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

M672MX (2/5)-DDR

JFWXX M/B LA-3961P Schematic

849Thursday, Sept em be r 06, 2007

1

0.1

of

5

4

3

2

1

+1.8VS

L24

1 2

MBK1608121YZF_0603

1

C252
10U_0805_10V4Z

2

D D

C C

B B

A A

1 2

R231 0_0402_5%

+1.8VS

12

R232
150_0402_1%

12

R229

49.9_0402_1%

+1.8VS

1 2

MBK1608121YZF_0603

1

C467
10U_0805_10V4Z

2

1 2

R396 0_0402_5%

+1.8VS

1 2

MBK1608121YZF_0603

1

C491
10U_0805_10V4Z

2

1 2

R415 0_0402_5%

+1.8VS

1

C453

@

10U_0805_10V4Z

2

1 2

R383 0_0402_5%

L42

L45

R395

3.3_0402_5%

1

C250

0.1U_0402_16V4Z

2

1

C67

0.1U_0402_16V4Z

2

1

C249

0.1U_0402_16V4Z

2

1

2

1

2

1

2

7/24 modified

5

Z4XAVDD:10mA

1

C248

0.01U_0402_16V7K

2

Z_VREF

VGA_CRT_HSYNC<17>
VGA_CRT_VSYNC<17>

GMCH_CRT_CLK<17>

GMCH_CRT_DATA<17>

DCLKAVDD:5mA

C468

0.1U_0402_16V4Z

1

2

ECLKAVDD:5mA

C484

0.1U_0402_16V4Z

1

2

DACAVDD1:73mA

C461

@

1U_0603_10V4Z

1

2

7/30 modified to @

Z4XAVDD

Z4XAVSS

DCLKAVDD

C469

0.01U_0402_16V7K

DCLKAVSS

ECLKAVDD

C485

0.01U_0402_16V7K

ECLKAVSS

DACAVDD1

C463

@

0.1U_0402_16V4Z

DACAVSS1

VGA_CRT_HSYNC
VGA_CRT_VSYNC

GMCH_CRT_CLK
GMCH_CRT_DATA

+1.8VS

1 2

1

C174
10U_0805_10V4Z

2

1 2

R406 0_0402_5%

DACAVDD1 Spec.
Voltage : 1.5V +/- 5%
Current : 100mA

4

ZAD[0..16]<19>

+3VS

12

R178
390_0402_5%

R177

0_0402_5%

ZAD[0..16]

+1.8VS

12

R179
390_0402_5%

INT_N_A<7,19>

REF_CLK0<14>

1 2

C178 0.1U_0402_16V4Z

1 2

C177 0.1U_0402_16V4Z

DACAVDD2:73mA

1

C490
1U_0603_10V4Z

2

1 2

R174 130_0402_5%

Z_CLK0<14>

ZDREQ<19>
ZUREQ<19>

ZSTB_DP0<19>
ZSTB_DN0<19>
ZSTB_DP1<19>

ZSTB_DN1<19>

R472 56_0402_5%

1 2

R230 56_0402_5%

1 2

VGA_CRT_R<17>
VGA_CRT_G< 17>
VGA_CRT_B<17>

R184 0_0402_5%

1 2

R185 0_0402_5%

1 2

R183 0_0402_5%

1 2

R182 0_0402_5%

1 2

R196 0_0402_5%

1 2

R195 0_0402_5%

1 2

VCOMP
VVBWN

DACAVDD2

1

C483

0.1U_0402_16V4Z

2

DACAVSS2

VRSET

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Z_CLK0
ZDREQ

ZUREQ
ZSTB_DP0

ZSTB_DN0
ZSTB_DP1
ZSTB_DN1

ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16

Z_VREF
Z_COMP_P
Z_COMP_N

Z4XAVDD
Z4XAVSS

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

A_HSYNC
A_VSYNC

A_DDC1CLK
A_DDC1DAT

VCOMP
VVBWN
VRSET

INTA#
VOSCI
DACAVDD1

DACAVSS1
DACAVDD2

DACAVSS2
DCLKAVDD

DCLKAVSS

ECLKAVDD
ECLKAVSS

2006/08/18 2007/8/18

3

Compal Secret Data

U30A

AH10

ZCLK

AP8

ZDREQ

AN8

ZUREQ

AM7

ZSTB0

AL7

ZSTB0#

AP4

ZSTB1

AP5

ZSTB1#

AK10

ZAD0

AM6

ZAD1

AK11

ZAD2

AJ11

ZAD3

AP7

ZAD4

AJ9

ZAD5

AP6

ZAD6

AN6

ZAD7

AK9

ZAD8

AM4

ZAD9

AK6

ZAD10

AK8

ZAD11

AN4

ZAD12

AK7

ZAD13

AL5

ZAD14

AM5

ZAD15

AM8

ZAD16

AL9

ZVREF

AP9

ZCMP_P

AM9

ZCMP_N

AM10

Z4XAVDD

AN10

Z4XAVSS

D13

ROUT

C12

GOUT

C13

BOUT

F12

HSYNC

G12

VSYNC

D11

VGPIO0

E12

VGPIO1

D15

VCOMP

C15

VVBWN

C14

VRSET

F13

INTA#

F11

VOSCI

A12

DACAVDD1

B12

DACAVSS1

A13

DACAVDD2

B13

DACAVSS2

B10

DCLKAVDD

A11

DCLKAVSS

A9

ECLKAVDD

B8

ECLKAVSS

SISM672MX-A1_TEBGA_847P

Deciphered Date

ASL

ENTEST

TESTMODE0
TESTMODE1
TESTMODE2

TRAP0
TRAP1
TRAP2

TRAP3
TRAP4
TRAP5
TRAP6
TRAP7
TRAP8
TRAP9

TRAP10

AUXOK

PWROK

PCIRST#

AGPSTOP#
AGPBUSY#

VBVSYNC
VBHSYNC

VBHCLK

VBCLK

VBCAD

VACLK

NC0
NC1

F15
D16

E16
F16
D17
E17
F17

AC32
AD34
AB28
AD32
AD33
AE34
AC30
AC29

A5
C6
A7

G14
A6

D8
F7

E7
C8

E9
D9

AH2
AG3

2

NB_ENTEST

AUX_PWRGD
SB_PWRGD
NB_RST#

AGPSTOP#
AGPBUSY#

VBVSYNC
VBHSYNC

VBHCLK
VBCLK

VBCAD

R193 4.7K_0402_5%

1 2

AUX_PWRGD <20,31>
SB_PWRGD <20,31>
NB_RST# <18,19>

AGPSTOP# <20>
AGPBUSY# <20>

VBVSYNC <18>
VBHSYNC <18>

VBHCLK <18>
VBCLK <18>

R559 33_0402_5%

VBCAD <18>

1 2

VACLKH_VACLK

For SiS VB 307 use only

AGPBUSY#
AUX_PWRGD
SB_PWRGD

R216 4.7K_0402_5%

1 2

C180 0.1U_0402_16V4Z

1 2

C181 0.1U_0402_16V4Z

1 2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

M672MX (3/5)-ASL

JFWXX M/B LA-3961P Schematic

VACLK <18>

+3VS

1

0.1

of

949Thursday, September 06, 2007

5

U30E

4

3

2

1

+1.8V

D D

+1.8VS

C C

+1.8VS

B B

A A

+1.8VS

+1.2VS

+1.2VALW

+1.8VALW

W23

VCCM

Y23

VCCM

AA23

VCCM

AB23

VCCM

AC23

VCCM

AC18

VCCM

AC20

VCCM

AC16

VCCM

AD16

VCCM

AD17

VCCM

AD19

VCCM

AD20

VCCM

AD21

VCCM

AD22

VCCM

AJ22

VCCM

AJ24

VCCM

AL23

VCCM

AL26

VCCM

AN21

VCCM

AN23

VCCM

AN25

VCCM

AN27

VCCM

AN29

VCCM

AP3

VCC1.8

AB12

VCC1.8

AB13

VCC1.8

AC12

VCC1.8

AC13

VCC1.8

AC14

VCC1.8

AC15

VCC1.8

AH6

VCC1.8

AH7

VCC1.8

AJ4

VCC1.8

AJ5

VCC1.8

AJ6

VCC1.8

AJ7

VCC1.8

AN2

VCC1.8

AK4

VCC1.8

AK5

VCC1.8

AL1

VCC1.8

AL2

VCC1.8

AL3

VCC1.8

AL4

VCC1.8

AM1

VCC1.8

AM2

VCC1.8

AM3

VCC1.8

AN3

VCC1.8

AN5

VCC1.8

AN7

VCC1.8

AN9

VCC1.8

E8

VDDVB1.8

F9

VDDVB1.8

F8

VDDVB1.8

E10

VDD1.8

F10

VDD1.8

N19

PVDDH

N21

PVDDH

P20

PVDDH

P22

PVDDH

R21

PVDDH

T22

PVDDH

U21

PVDDH

V22

PVDDH

M11

VDDPEX

N11

VDDPEX

P11

VDDPEX

R11

VDDPEX

T11

VDDPEX

U11

VDDPEX

V11

VDDPEX

W11

VDDPEX

Y11

VDDPEX

AA11

VDDPEX

AB11

VDDPEX

B5

AUX_IVDD

C5

AUX_IVDD

D6

AUX_IVDD

G8

AUX1.8

SISM672MX-A1_TEBGA_847P

M13

IVDD

M14

IVDD

M15

IVDD

M16

IVDD

M17

IVDD

M18

IVDD

M19

IVDD

N16

IVDD

N17

IVDD

N18

IVDD

N20

IVDD

R22

IVDD

N22

IVDD

N13

IVDD

P13

IVDD

Y13

IVDD

Y22

IVDD

T13

IVDD

U13

IVDD

U22

IVDD

V13

IVDD

W13

IVDD

PWR

IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD

VTTP
VTTP
VTTP
VTTP
VTTP
VTTP
VTTP
VTTP
VTTP
VTTP

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

W22
AA13
AA22
AB14
AB15
AB16
AB18
AB20
AB22
AF6
AF7
AK3
AG4
AG5
AG6
AG7
R13
AH3
AH4
AH5
AJ1
AJ2
AJ3
AK1
AK2
AC22
AC21
AC19
AC17

A19
A20
B19
B20
C19
C20
D19
D20
E19
E20
F19
F20
G19
G20
L18
L19
L20
M20
M21
M22
M23
N23
P23
R23
T23
U23
V23
M12
N12
P12
R12
T12
U12
V12
W12
Y12
AA12

+1.2VS

+1.05VS

+1.8VS

+1.8V +1.2VS +1.8VALW +1.2VALW

C244 1U_0603_10V4Z

C245 1U_0603_10V4Z

C246 10U_0805_10V4Z

PVDDH/VCC1.8/VTTP/VDD1.8

+1.8VS +1.2VS

/VDDVB1.8:392mA

C232 0.1U_0402_16V4Z

C239 1U_0603_10V4Z

C247 10U_0805_10V4Z

VCCM:644mA

1 2

1 2

1 2

1 2

1 2

1 2

IVDD:2024mA

C225 1U_0603_10V4Z

1 2

C227 1U_0603_10V4Z

1 2

C243 10U_0805_10V4Z

1 2

VDDPEX:876mA

C202 0.1U_0402_16V4Z

1 2

C195 1U_0603_10V4Z

1 2

C229 10U_0805_10V4Z

1 2

Place these Cap under M672MX solder side.

+1.8V +1.2VS

C230 0.1U_0402_16V4Z

1 2

C231 0.1U_0402_16V4Z

1 2

C235 1U_0603_10V4Z

1 2

C223 1U_0603_10V4Z

1 2

C237 4.7U_0805_10V4Z

1 2

C236 4.7U_0805_10V4Z

1 2

+1.8VS +1.2VS +1.05VS

C198 0.1U_0402_16V4Z

1 2

C221 1U_0603_10V4Z

1 2

C193 1U_0603_10V4Z

1 2

C226 0.1U_0402_16V4Z

1 2

C209 0.1U_0402_16V4Z

1 2

C213 1U_0603_10V4Z

1 2

C220 1U_0603_10V4Z

1 2

C196 4.7U_0805_10V4Z

1 2

C242 4.7U_0805_10V4Z

1 2

C197 0.1U_0402_16V4Z

1 2

C240 1U_0603_10V4Z

1 2

C234 1U_0603_10V4Z

1 2

AUX1.8:1mA AUX_IVDD:92mA

1

C187
1U_0603_10V4Z

2

+1.05VS

C204 0.1U_0402_16V4Z

1 2

C192 1U_0603_10V4Z

1 2

C176 10U_0805_10V4Z

1 2

+1.8VALW +1.2VALW

1

C190
1U_0603_10V4Z

2

C188 0.1U_0402_16V4Z

1 2

C179 1U_0603_10V4Z

1 2

C184 1U_0603_10V4Z

1 2

1

C183
1U_0603_10V4Z

2

VTT:80mA

1

C182
1U_0603_10V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

M672MX (4/5)-POWER

JFWXX M/B LA-3961P Schematic

10 49Thursday, Sept em be r 06, 2007

1

0.1

of

5

D D

B21
B23
B25
B27
B29
B31

C10
C11
C16
C18

G10

C32
C33

D10
D12
D21
D23
D25
D27
D29

E11
E13
E14
E18
E29
E30
E33

F14
F22
F24
F26
F28

P21
T21
V21

C C

B B

4

AA16

AA17

AA18

AA19

AA20

AA21

AA31

AA33

AB3

AB4

AB5

AB7

AB29

AC2

AC3

AC31

AC33

AD2

AD3

AD4

AD5

AD7

AD29

AE3

AE31

AE33

AF2

VSS

VSS

VSS

VSSM2VSSM3VSS

M29

AF3

VSS

VSS

VSS

GND

VSSN3VSSN4VSSN5VSSN6VSSN7VSS

U30F

A3

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

B2

VSS

B3

VSS

B4

VSS
VSS

VSS
VSS
VSS
VSS
VSS

C1

VSS

C2

VSS

C3

VSS

C4

VSS

C9

VSS
VSS
VSS
VSS
VSS
VSS
VSS

D1

VSS

D2

VSS

D3

VSS

D4

VSS

D5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E1

VSS

E2

VSS

E3

VSS

E6

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

F2

VSS

F3

VSS

F4

VSS

F5

VSS

F6

VSS
VSS
VSS
VSS
VSS
VSS

G2

VSS

G3

VSS

G7

VSS
VSS
VSS
VSS
VSS

VSSH5VSS

VSSJ2VSSJ3VSSJ7VSS

VSS

VSSK3VSSK4VSSK5VSS

VSSL2VSSL3VSSL4VSSL5VSSL7VSS

J33

K29

G31

VSS

G33

VSS

VSS

H4

H29

J31

VSS

VSS

L31

L33

VSS

AF4

VSS

AF5

N14

VSS

AF29

N15

VSS

VSS

AG2

N31

VSS

VSS

AG31

VSS

VSS

N33

3

AG33

AH1

VSS

VSS

VSSP2VSSP3VSS

2

AH29

AJ8

AJ10

AJ12

AJ14

AJ16

AJ18

AJ20

AJ26

AJ28

AJ33

AK31

AL6

AL8

AL10

AL12

AL14

AL16

AL18

AL20

AL28

AL30

AL33

AN11

AN13

AN15

AN17

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

T29

VSS

U2

VSS

U3

VSS

U4

VSS

U5

VSS

U6

VSS

U14

VSS

U15

VSS

U16

VSS

U17

VSS

U18

VSS

U19

VSS

U20

VSS

U31

VSS

U33

VSS

V2

VSS

V3

VSS

V4

VSS

V5

VSS

V14

VSS

V15

VSS

V16

VSS

V17

VSS

V18

VSS

V19

VSS

V20

VSS

V29

VSS

AN33

VSS

AN31

VSS

AN19

VSS

W3

VSS

W14

VSS

W15

VSS

W16

VSS

W17

VSS

W18

VSS

W19

VSS

W20

VSS

W21

VSS

W31

VSS

W33

VSS

Y2

VSS

Y3

VSS

Y4

VSS

Y5

VSS

Y7

VSS

Y14

VSS

Y15

VSS

Y16

VSS

Y17

VSS

Y18

VSS

Y19

VSS

Y20

VSS

Y21

VSS

Y29

VSS

AA2

VSS

AA3

VSS

AA14

VSS

AA15

VSS

AB17

VSS

AB19

VSS

AB21

VSS

P19

VSS

VSS

VSS

VSS

VSS

VSS

VSSR2VSSR3VSSR4VSSR5VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSST3VSST6VSS

VSS

VSS

VSS

VSS

VSS

VSS

T14

P14

P15

P16

P17

P18

P29

R14

R15

R16

R17

R18

R19

R20

R31

R33

T15

SISM672MX-A1_TEBGA_847P

T16

T17

T18

T19

T20

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

M672MX (5/5)-GND

JFWXX M/B LA-3961P Schematic

11 49Thursday, Sept em be r 06, 2007

1

0.1

of

5

+1.8V +1.8V

JP35

+DIMM_VREF

DDRA_SDQ0
DDRA_SDQ1

DDRA_SDQS0#<8,13>
DDRA_SDQS0<8,13>

D D

DDRA_SDQS1#<8,13>
DDRA_SDQS1<8,13>

DDRA_SDQS2#<8,13>
DDRA_SDQS2<8,13>

EC_TX_P80_DATA<13,31>

C C

EC_RX_P80_CLK<13,31>

B B

EC_RX_P80_CLK

A A

DDRA_CKE0<8>

DDRA_SBS2<8,13>

DDRA_SBS0<8,13>
DDRA_SWE#<8,13>

DDRA_SCAS#<8,13>
DDRA_SCS1#<8>

DDRA_ODT1<8>

DDRA_SDQS4#<8,13>
DDRA_SDQS4<8,13>

R237 0_0402_5%

1 2

EC_RX_P80_CLK_R<13>

DDRA_SDQS6#<8,13>
DDRA_SDQS6<8,13>

SDATA<13,14,15,20>
SCLK<13,14,15,20>

+3VS

C285

2.2U_0603_6.3V6K

5

DDRA_SDQS0#
DDRA_SDQS0

DDRA_SDQ2
DDRA_SDQ3

DDRA_SDQ8
DDRA_SDQ9

DDRA_SDQS1#
DDRA_SDQS1

DDRA_SDQ10
DDRA_SDQ11

DDRA_SDQ16
DDRA_SDQ17

DDRA_SDQS2#
DDRA_SDQS2

DDRA_SDQ18
DDRA_SDQ19

DDRA_SDQ24
DDRA_SDQ25

DDRA_SDM3
EC_TX_P80_DATA

DDRA_SDQ26
DDRA_SDQ27

DDRA_CKE0
EC_RX_P80_CLK

DDRA_SBS2
DDRA_SMA12

DDRA_SMA9
DDRA_SMA8

DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

DDRA_SMA10
DDRA_SBS0
DDRA_SWE#

DDRA_SCAS#
DDRA_SCS1#

DDRA_ODT1
DDRA_SDQ32

DDRA_SDQ33
DDRA_SDQS4#

DDRA_SDQS4
DDRA_SDQ34

DDRA_SDQ35
DDRA_SDQ40

DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42

DDRA_SDQ43
DDRA_SDQ48

DDRA_SDQ49

EC_RX_P80_CLK_R

EC_RX_P80_CLK_R

DDRA_SDQS6#
DDRA_SDQS6

DDRA_SDQ50
DDRA_SDQ51

DDRA_SDQ56
DDRA_SDQ57

DDRA_SDM7
DDRA_SDQ58

DDRA_SDQ59
SDATA

SCLK

+3VS

1

C284

0.1U_0402_16V4Z

2

DIMM0 STD H:5.2mm (BOT)

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5652C-A0G16

VSS
DQ4
DQ5
VSS

DM0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106

BA1

108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

SA1

DDRA_SDQ4
DDRA_SDQ5

DDRA_SDM0
DDRA_SDQ6

DDRA_SDQ7
DDRA_SDQ12

DDRA_SDQ13
DDRA_SDM1
DDR_CLK0

DDR_CLK0#
DDRA_SDQ14

DDRA_SDQ15

DDRA_SDQ20
DDRA_SDQ21

DDRA_SDM2
DDRA_SDQ22

DDRA_SDQ23
DDRA_SDQ28

DDRA_SDQ29
DDRA_SDQS3#

DDRA_SDQS3
DDRA_SDQ30

DDRA_SDQ31
DDRA_CKE1

DDRA_SMA14
DDRA_SMA11

DDRA_SMA7
DDRA_SMA6

DDRA_SMA4
DDRA_SMA2
DDRA_SMA0

DDRA_SBS1
DDRA_SRAS#
DDRA_SCS0#

DDRA_ODT0
DDRA_SMA13

DDRA_SDQ36
DDRA_SDQ37

DDRA_SDM4
DDRA_SDQ38

DDRA_SDQ39
DDRA_SDQ44

DDRA_SDQ45
DDRA_SDQS5#

DDRA_SDQS5
DDRA_SDQ46

DDRA_SDQ47
DDRA_SDQ52

DDRA_SDQ53
DDR_CLK1

DDR_CLK1#
DDRA_SDM6
DDRA_SDQ54

DDRA_SDQ55
DDRA_SDQ60

DDRA_SDQ61
DDRA_SDQS7#

DDRA_SDQS7
DDRA_SDQ62

DDRA_SDQ63

R238 10K_0402_5%

1 2

R239 10K_0402_5%

1 2

DDR_CLK0 <15>
DDR_CLK0# <15>

DDRA_SDQS3# <8,13>
DDRA_SDQS3 <8,13>

DDRA_CKE1 <8>

Swap RP6 Pin2 & RP7 Pin 1

DDRA_SBS1 <8,13>
DDRA_SRAS# <8,13>
DDRA_SCS0# <8>

DDRA_ODT0 <8>

DDRA_SDQS5# <8,13>
DDRA_SDQS5 <8,13>

DDR_CLK1 <15>
DDR_CLK1# <15>

DDRA_SDQS7# <8,13>
DDRA_SDQS7 <8,13>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+DIMM_VREF

20mils

1

C278

0.1U_0402_16V4Z

2

DDRA_SMA[0..14]<8,13>

DDRA_SDQ[0..63]<8,13>

DDRA_SDM[0..7]<8,13>

Swap RP11,RP12 Pin 1 & 2

DDRA_SBS2
DDRA_CKE0

DDRA_SMA9
DDRA_SMA12

DDRA_SMA8
DDRA_SMA3

DDRA_SMA5
DDRA_SMA1

DDRA_SMA10
DDRA_SBS0

DDRA_SWE#
DDRA_SCAS#

DDRA_SCS1#
DDRA_ODT1

DDRA_SMA11
DDRA_SMA14

DDRA_SMA6
DDRA_SMA7

DDRA_SMA2
DDRA_SMA4

DDRA_SBS1
DDRA_SMA0

DDRA_SCS0#
DDRA_SRAS#

DDRA_SMA13
DDRA_ODT0

DDRA_CKE1

2006/08/18 2007/8/18

3

C277

2.2U_0603_6.3V6K

DDRA_SMA[0..14]
DDRA_SDQ[0..63]
DDRA_SDM[0..7]

1 4
2 3

RP11 56_0404_4P2R_5%

1 4
2 3

RP12 56_0404_4P2R_5%

1 4
2 3

RP6 56_0404_4P2R_5%

1 4
2 3

RP7 56_0404_4P2R_5%

1 4
2 3

RP8 56_0404_4P2R_5%

1 4
2 3

RP9 56_0404_4P2R_5%

1 4
2 3

RP10 56_0404_4P2R_5%

1 4
2 3

RP13 56_0404_4P2R_5%

1 4
2 3

RP14 56_0404_4P2R_5%

1 4
2 3

RP15 56_0404_4P2R_5%

1 4
2 3

RP16 56_0404_4P2R_5%

1 4
2 3

RP17 56_0404_4P2R_5%

1 4
2 3

RP18 56_0404_4P2R_5%

1 2

R241 56_0402_5%

Layout Note:
Place these resistor
closely JP35,all
trace length Max=1.5"

Compal Secret Data

Deciphered Date

R236

1K_0402_1%

R235

1K_0402_1%

+0.9VS

2

+1.8V

12

0.1U_0402_16V4Z

12

0.1U_0402_16V4Z

2

1

New Add For SiS New Add For SiS

1

C271

2

1

C269

2

+1.8V

C296

2.2U_0603_6.3V6K

+1.8V

1

C281

0.1U_0402_16V4Z

2

+0.9VS

1

C289

0.1U_0402_16V4Z

2

+0.9VS

1

C288

0.1U_0402_16V4Z

2

+0.9VS

1

C306

0.1U_0402_16V4Z

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+DIMM_VREF

1

C270
220P_0402_50V7K

2

@

C282

2.2U_0603_6.3V6K

1

C297

0.1U_0402_16V4Z

2

1

C290

0.1U_0402_16V4Z

2

1

C292

0.1U_0402_16V4Z

2

1

C305

0.1U_0402_16V4Z

2

Title

Size Document Number Rev

Date: Sheet

+1.8V

1

+

C303

@

330U_D2E_2.5VM

2

Layout Note:
Place near JP35

1

C294

0.1U_0402_16V4Z

2

1

C291

0.1U_0402_16V4Z

2

1

C299

0.1U_0402_16V4Z

2

1

C298

0.1U_0402_16V4Z

2

C280

2.2U_0603_6.3V6K

1

C295

0.1U_0402_16V4Z

2

1

C287

0.1U_0402_16V4Z

2

1

C308

0.1U_0402_16V4Z

2

C283

2.2U_0603_6.3V6K

Compal Electronics, Inc.

DDRII-SODIMM0

B

JFWXX M/B LA-3961P Schematic

1

1

+

C304

@

330U_D2E_2.5VM

2

C293

2.2U_0603_6.3V6K

1

C286

0.1U_0402_16V4Z

2

1

C307

0.1U_0402_16V4Z

2

12 49Thursday, September 06, 2007

of

0.1

A

+1.8V +1.8V

JP34

+DIMM_VREF

DDRA_SDQ0
DDRA_SDQ1

DDRA_SDQS0#<8,12>
DDRA_SDQS0<8,12>

1 1

DDRA_SDQS1#<8,12>
DDRA_SDQS1<8,12>

DDRA_SDQS2#<8,12>
DDRA_SDQS2<8,12>

EC_TX_P80_DATA<12,31>

2 2

3 3

4 4

EC_RX_P80_CLK<12,31>

DDRA_CKE2<8>

DDRA_SBS2<8,12>

DDRA_SBS0<8,12>
DDRA_SWE#<8,12>

DDRA_SCAS#<8,12>
DDRA_SCS3#<8>

DDRA_ODT3<8>

DDRA_SDQS4#<8,12>
DDRA_SDQS4<8,12>

EC_RX_P80_CLK_R<12>

DDRA_SDQS6#<8,12>
DDRA_SDQS6<8,12>

C259

2.2U_0603_6.3V6K

A

SDATA<12,14,15,20>
SCLK<12,14,15,20>

+3VS

DDRA_SDQS0#
DDRA_SDQS0

DDRA_SDQ2
DDRA_SDQ3

DDRA_SDQ8
DDRA_SDQ9

DDRA_SDQS1#
DDRA_SDQS1

DDRA_SDQ10
DDRA_SDQ11

DDRA_SDQ16
DDRA_SDQ17

DDRA_SDQS2#
DDRA_SDQS2

DDRA_SDQ18
DDRA_SDQ19

DDRA_SDQ24

DDRA_SDM3
EC_TX_P80_DATA

DDRA_SDQ26
DDRA_SDQ27

DDRA_CKE2
EC_RX_P80_CLK

DDRA_SBS2
DDRA_SMA12

DDRA_SMA9
DDRA_SMA8

DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

DDRA_SMA10
DDRA_SBS0
DDRA_SWE#

DDRA_SCAS#
DDRA_SCS3#

DDRA_ODT3
DDRA_SDQ32

DDRA_SDQ33
DDRA_SDQS4#

DDRA_SDQS4
DDRA_SDQ34

DDRA_SDQ35
DDRA_SDQ40

DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42

DDRA_SDQ43
DDRA_SDQ48

DDRA_SDQ49

EC_RX_P80_CLK_R

DDRA_SDQS6#
DDRA_SDQS6

DDRA_SDQ50
DDRA_SDQ51

DDRA_SDQ56
DDRA_SDQ57

DDRA_SDM7
DDRA_SDQ58

DDRA_SDQ59
SDATA

SCLK

+3VS

1

C260

0.1U_0402_16V4Z

2

DIMM1 STD H:9.2mm (BOT)

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692A-A0G16-N

DQ4
DQ5

DM0
DQ6

DQ7

DQ12
DQ13

DM1

CK0#

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36
DQ37

DM4

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DM6

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

SAO

VSS

VSS
VSS

VSS

VSS
VSS

CK0
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

BA1

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
VSS

VSS

VSS

VSS

VSS
SA1

B

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDRA_SDQ4
DDRA_SDQ5

DDRA_SDM0
DDRA_SDQ6

DDRA_SDQ7
DDRA_SDQ12

DDRA_SDQ13
DDRA_SDM1
DDR_CLK2

DDR_CLK2#
DDRA_SDQ14

DDRA_SDQ15

DDRA_SDQ20
DDRA_SDQ21

DDRA_SDM2
DDRA_SDQ22

DDRA_SDQ23
DDRA_SDQ28

DDRA_SDQ29DDRA_SDQ25
DDRA_SDQS3#

DDRA_SDQS3
DDRA_SDQ30

DDRA_SDQ31
DDRA_CKE3

DDRA_SMA14
DDRA_SMA11

DDRA_SMA7
DDRA_SMA6

DDRA_SMA4
DDRA_SMA2
DDRA_SMA0

DDRA_SBS1
DDRA_SRAS#
DDRA_SCS2#

DDRA_ODT2
DDRA_SMA13

DDRA_SDQ36
DDRA_SDQ37

DDRA_SDM4
DDRA_SDQ38

DDRA_SDQ39
DDRA_SDQ44

DDRA_SDQ45
DDRA_SDQS5#

DDRA_SDQS5
DDRA_SDQ46

DDRA_SDQ47
DDRA_SDQ52

DDRA_SDQ53
DDR_CLK3

DDR_CLK3#
DDRA_SDM6
DDRA_SDQ54

DDRA_SDQ55
DDRA_SDQ60

DDRA_SDQ61
DDRA_SDQS7#

DDRA_SDQS7
DDRA_SDQ62

DDRA_SDQ63

R233 10K_0402_5%

1 2

R234 10K_0402_5%

1 2

DDR_CLK2 <15>
DDR_CLK2# <15>

DDRA_SDQS3# <8,12>
DDRA_SDQS3 <8,12>

DDRA_CKE3 <8>

DDRA_SBS1 <8,12>
DDRA_SRAS# <8,12>
DDRA_SCS2# <8>

DDRA_ODT2 <8>

DDRA_SDQS5# <8,12>
DDRA_SDQS5 <8,12>

DDR_CLK3 <15>
DDR_CLK3# <15>

DDRA_SDQS7# <8,12>
DDRA_SDQS7 <8,12>

+3VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+DIMM_VREF

20mils

1

C258

0.1U_0402_16V4Z

2

DDRA_SMA[0..14]<8,12>

DDRA_SDQ[0..63]<8,12>

DDRA_SDM[0..7]<8,12>

DDRA_ODT3
DDRA_SCS3#

DDRA_CKE3
DDRA_CKE2

DDRA_SCS2#
DDRA_ODT2

2006/08/18 2007/8/18

C

C255

2.2U_0603_6.3V6K

1 4
2 3

RP3 56_0404_4P2R_5%

1 4
2 3

RP5 56_0404_4P2R_5%

1 4
2 3

RP4 56_0404_4P2R_5%

Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.5"

Compal Secret Data

Deciphered Date

DDRA_SMA[0..14]
DDRA_SDQ[0..63]
DDRA_SDM[0..7]

D

+0.9VS

4.7U_0805_10V4Z

D

+1.8V

C253

2.2U_0603_6.3V6K

+1.8V

+0.9VS

C262

C256

2.2U_0603_6.3V6K

1

C266

0.1U_0402_16V4Z

2

1

2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

1

C267

0.1U_0402_16V4Z

2

1

C261

4.7U_0805_10V4Z

2

Title

Size Document Number Rev

B

Date: Sheet

E

Layout Note:
Place near JP34

1

C265

0.1U_0402_16V4Z

2

C264

2.2U_0603_6.3V6K

1

C257

0.1U_0402_16V4Z

2

C263

2.2U_0603_6.3V6K

C254

2.2U_0603_6.3V6K

Compal Electronics, Inc.

DDRII-SODIMM1

JFWXX M/B LA-3961P Schematic

13 49Thursday, September 06, 2007

E

0.1

of

5

+3VS

L13

1 2

KC FBM-L11-201209-221LMAT_0805

10U_0805_10V4Z

D D

+3VS

R43 10K_0402_5%

1 2

R66 10K_0402_5%

1 2

R528 10K_0402_5%

1 2

C100

1

10U_0805_10V4Z

2

C664

MODE
CLK_RESET#
STOP#

1

C69

0.1U_0402_16V4Z

2

1

C70

0.1U_0402_16V4Z

2

1

2

1

C71

0.1U_0402_16V4Z

2

1

2

Part no.SD028270180

+3VS

R80 2.7K_0402_5%@
R55 2.7K_0402_5%@
R78 2.7K_0402_5%@

C C

R54 2.7K_0402_5%@
R76 2.7K_0402_5%@
R53 2.7K_0402_5%@
R52 2.7K_0402_5%
R74 2.7K_0402_5%@
R73 2.7K_0402_5%@
R56 2.7K_0402_5%

FSL0

FSL1

FSL2

FSL3

FSL4

1394

10U_0805_10V4Z

Reference schematic use 1206

CLK_14M_SIO<33>

REF_CLK0<9>
REF_CLK1<20>

SB

EC

VBRCLK<18>
CLK_PCI_SB<19>
CLK_PCI_1394<26>
CLK_PCI_EC<31>

DB

EXP_CLKREQ#<30>

1K_0402_5%

D

1 3

2
2

1 3

D

WLAN_CLKREQ#< 29>

CLK_PCI_DB<33>

R344

S

Q30
2N7002_SOT23

G

G

S

Q31
2N7002_SOT23

VGATE<48>

CPUSTP#<25>

SDATA<12,13,15,20>
SCLK<12,13,15,20>

+3VS+3VALW

R39 4.7K_0402_5%

H_BSEL0<5>
H_BSEL1<5>
H_BSEL2<5>

B B

A A

C82 18P_0402_50V8J

C86 18P_0402_50V8J

DDATA<29,30>

1 2

R40 4.7K_0402_5%

1 2

R38 4.7K_0402_5%

1 2

XTAL_IN

12

Y1

14.31818MHZ_16PF_DSX840GA

XTAL_OUT

R352

2.2K_0402_5%

DDATA

+3VS

DCLK<29,30>

DCLK

5

FSL0
FSL1
FSL2

R355

2.2K_0402_5%

1

C98

C72

0.1U_0402_16V4Z

2

4

1

C79

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

C99

0.1U_0402_16V4Z

2

CLKGEN_VDD

1

C405

0.1U_0402_16V4Z

2

12

R32
10K_0402_5%

+3VS +3VS+CPU_CORE

2

B

E

3

12

R58
10K_0402_5%

C

Q10
MMBT3904_SOT23

3 1

2

B

E

12

R57
10K_0402_5%

VTTPWRGD

C

Q9
MMBT3904_SOT23

3 1

2

CPU

FSL21FSL1FSL3F SL4 ZCLK

FSL0

MHz

0

1

0

1

0

1

0 1 0 200 100 33.30 1 133

133

1

166

Use SB03904008L & SB000006A00 FootPrint

CLKGEN_VDD

+3VS

L34

1 2

1

C420

@

0.1U_0402_16V4Z

2

CLK_14M_SIO
REF_CLK0
REF_CLK1
VBRCLK

CLK_PCI_SB

CLK_PCI_DB PCICLK7

VTTPWRGD

SDATA
SCLK

R343
1K_0402_5% C59 10P_0402_50V8J@

SDATA

SCLK

KC FBM-L11-201209-221LMAT_0805

1

1

C403

2

R35 22_0402_5%@
R79 33_0402_5%
R77 22_0402_5%
R541 22_0402_5%

R75 33_0402_5%
R37 33_0402_5%
R72 33_0402_5%

R50 33_0402_5%
R71 33_0402_5%
R51 33_0402_5%@

R81 0_0402_5%@
R82 0_0402_5%

R67 0_0402_5%

R338 0_0402_5%
R337 0_0402_5%

C404
10U_0805_10V4Z

2

1 2
1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2

1 2

1 2
1 2

Security Classification

VDDA

XTAL_IN
XTAL_OUT

FSL0
FSL1

FSL2
FSL3CLK_PCI_1394
FSL4CLK_PCI_EC
STOP#
MODE
CLKREQ0#EXP_CLKREQ#
CLKREQ1#WLAN_CLKREQ#

CK_PWRGDVGATE
CLK_RESET#CPUSTP#

SMDATA
SMCLK

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U4

50

VDDA

47

GNDA

5

X1

6

X2

3

*FSL0/REF0_2x

4

**FSL1/REF1_2x

9

**FSL2/PCICLK0_2x

10

**FS3/PCICLK1_2x

11

**FS4/PCICLK2

12

*(PCI_STOP#)/PCICLK3

15

**MODE/PCICLK4

16

(PECLKREQ0#)/PCICLK5

17

(PECLKREQ1#)/PCICLK6

18

PCICLK7

1

VTTPWRGD/PD#/(CLK_STOP#)

28

*(CPU_STOP#)/RESET#

45

SDATA

46

SCLK

2005/03/01

3

23

56

24

14

2

VDDREF

39

19

VDDZ

VDD48

VDDCPU

VDDPCI_0

VDDPCI_1

VDDPCIEX_0

ICS9LPR600

**SEL24_48#/24_48MHz

GNDREF7GNDPCI_0

GNDPCI_1

GNDZ

GND48

GNDCPU

8

13

20

27

53

Compal Secret Data

Deciphered Date

29

55

CPUT_L0
CPUC_L0
CPUT_L1
CPUC_L1

PCIET_L0

PCIEC_L0
PCIET_L1

PCIEC_L1
PCIET_L2

PCIEC_L2
PCIET_L3

PCIEC_L3

PCIET_L4F
PCIEC_L4F

PCIET_L5F
PCIEC_L5F

ZCLK0
ZCLK1

12MHz

54
52
51

44
43

41
40

38
37

36
35

34
33

31
30

48
49

21
22

26

25

VDDPCIEX_1

SATACLKC_L
SATACLKT_L

GNDPCIEX_0

GNDPCIEX_1

ICS9LPR600BGLF-T_TSSOP56

42

32

CPUT_L0
CPUC_L0
CPUT_L1
CPUC_L1

PCIET_L0
PCIEC_L0

PCIET_L2
PCIEC_L2

PCIET_L3
PCIEC_L3

PCIET_L4F
PCIEC_L4F

PCIET_L5F
PCIEC_L5F

SATACLKC_L
SATACLKT_L

ZCLK0
ZCLK1

12M USB_CLK_12M

R95 33_0402_5%

1 2

R102 33_0402_5%

1 2

R94 33_0402_5%

1 2

R101 33_0402_5%

1 2

R91 33_0402_5%

1 2

R90 33_0402_5%

1 2

R89 33_0402_5%

1 2

R88 33_0402_5%

1 2

R106 33_0402_5%

1 2

R105 33_0402_5%

1 2

R87 33_0402_5%

1 2

R86 33_0402_5%

1 2

R104 33_0402_5%

1 2

R103 33_0402_5%

1 2

R92 33_0402_5%

1 2

R93 33_0402_5%

1 2

R49 22_0402_5%

1 2

R70 22_0402_5%

1 2

R68 33_0402_5%

1 2

H_CLK_DP0
H_CLK_DN0
H_CLK_DP1
H_CLK_DN1

PCIE_CLK_NB
PCIE_CLK_NB#

PCIE_CLK_SB
PCIE_CLK_SB#

PCIE_CLK_307
PCIE_CLK_307#

PCIE_CLK_EXP
PCIE_CLK_EXP#

PCIE_CLK_WLAN
PCIE_CLK_WLAN#

SATA_CLK_DN
SATA_CLK_DP

Z_CLK0
Z_CLK1

Pin 26 need BIOS to set disable,

for saving power & good EMI

Z_CLK0
Z_CLK1
CLK_PCI_SB
CLK_PCI_1394
CLK_PCI_EC
CLK_PCI_DB
REF_CLK0
REF_CLK1

2006/03/01

2

Title

Clock Generator ICS9LPR600C

Size Document Number Rev

Custom

JFWXX M/B LA-3961P Schematic

Thursday, September 06, 2007

Date: Sheet

C62 10P_0402_50V8J@
C61 10P_0402_50V8J@
C63 10P_0402_50V8J@
C57 10P_0402_50V8J@
C66 10P_0402_50V8J@

C65 10P_0402_50V8J@
C64 10P_0402_50V8J@

1

PCIE
MHz

1000

100

H_CLK_DP0 <4>
H_CLK_DN0 <4>
H_CLK_DP1 <7>
H_CLK_DN1 <7>

PCIE_CLK_NB <7>
PCIE_CLK_NB# <7>

PCIE_CLK_SB <20>
PCIE_CLK_SB# <20>

PCIE_CLK_307 <18>
PCIE_CLK_307# <18>

PCIE_CLK_EXP <30>
PCIE_CLK_EXP# <30>

PCIE_CLK_WLAN <29>
PCIE_CLK_WLAN# <29>

SATA_CLK_DN <21>
SATA_CLK_DP <21>

Z_CLK0 <9>
Z_CLK1 <19>

USB_CLK_12M <21>

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1

PCI
MHz

33.30

33.3

MHz

133

133

NB

SB

NewCard

14 49

of

307LV

WLAN

0.1

5

+1.8V

L25

1 2

D D

KC FBM-L11-201209-221LMAT_0805

1

C274

10U_0805_10V4Z

2

1

C665
10U_0805_10V4Z

2

C301

1

2

4

0.1U_0402_16V4Z

1

C302

C273

2

0.1U_0402_16V4Z

1

C279

2

3

CLKBUF_VDD

1

1

C275

2

2

2

1

0.1U_0402_16V4Z

+1.8V

L26

1 2

1

C268

@

10U_0805_10V4Z

2

C C

KC FBM-L11-201209-221LMAT_0805

1

C272

0.1U_0402_16V4Z

2

1

C276
10U_0805_10V4Z

2

CLKBUF_AVDD

Reference schematic use 1206

B B

0.1U_0402_16V4Z

CLK_INC<8>

CLK_INT<8>

SDATA<12,13,14,20>
SCLK<12,13,14,20>

10P_0402_50V8J

0.1U_0402_16V4Z

CLKBUF_VDD

CLK_INC

CLK_INT

SDATA
SCLK

R243 0_0402_5%

1

C300

2

R245 0_0402_5%
R244 0_0402_5%

12

R242 22_0402_5%

12
12

FB_INAFB_OUTA

12

Horizontal rotate

U12

3

VDD1.8_0

11

VDD1.8_1

25

VDD1.8_2

21

VDD1.8_3

10

CLK_INC

9

CLK_INT

20

SDATA

19

SCLK

18

FB_IN

17

FB_OUT

8

GND_0

6

GND_1

28

GND_2

24

GND_3

14

GND_4

ICS9P935AFLF-T_SSOP28

VDDA1.8

DDRC0
DDRT0

DDRC1
DDRT1

DDRC2
DDRT2

DDRC3
DDRT3

DDRC4
DDRT4

DDRC5
DDRT5

CLKBUF_AVDD

7

DDRC0

R560 0_0402_5%

1

DDRT0

2

DDRC1

5

DDRT1

4

DDRC2

13

DDRT2

12

DDRC3

15

DDRT3 DDR_CLK3

16
23

22
27

26

1 2

R561 0_0402_5%

1 2

R562 0_0402_5%

1 2

R563 0_0402_5%

1 2

R564 0_0402_5%

1 2

R565 0_0402_5%

1 2

R566 0_0402_5%

1 2

R567 0_0402_5%

1 2

DDR_CLK0#
DDR_CLK0

DDR_CLK2#
DDR_CLK2

DDR_CLK1#
DDR_CLK1

DDR_CLK3#

DDR_CLK0# <12>

DDR_CLK0 <12>

DDR_CLK2# <13>

DDR_CLK2 <13>

DDR_CLK1# <12>

DDR_CLK1 <12>

DDR_CLK3# <13>

DDR_CLK3 <13>

C300 close to R242

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01

3

Compal Secret Data

Deciphered Date

2006/03/01

2

Title

Size Document Number Rev

Custom
Date: Sheet

Clock Buffer ICS9P935

JFWXX M/B LA-3961P Schematic

Thursday, September 06, 2007

1

15 49

of

0.1

5

LCD POWER CIRCUIT

4

3

2

1

G

2

C29

+3VS

1 3

1

@

2

W=60mils

S

Q5
SI2301BDS_SOT23

D

1

2

+LCDVDD

1

2

C36

@

4.7U_0805_10V4Z

W=60mils

C32

0.1U_0402_16V4Z

R544
15K_0402_5%

GMCH_ENVDD_Q

Q38
MMBT3904_SOT23

+LCDVDD

12

13

D

S

D D

GMCH_ENVDD<18>

12

C C

Level Shift Circuit

R542

1 2

47K_0402_5%
R22
100K_0402_5%

+3VALW +3VS

12

R543
10K_0402_5%

C

Q37

2

B

MMBT3904_SOT23

E

3 1

12

C

2

B

E

3 1

R16
300_0603_5%

2

G

Q8
2N7002_SOT23

+3VALW

12

R17
100K_0402_5%

R15 10K_0402_5%

13

D

Q7

2

G

2N7002_SOT23

S

2

1

12

C35

0.1U_0402_16V4Z

4.7U_0805_10V4Z

LCD/PANEL BD. Conn.

+3VS

1

C18

0.1U_0402_16V4Z

2

B B

1

2

C28
10U_0805_10V4Z

+LCDVDD_L

1

C25

0.1U_0402_16V4Z

2

+LCDVDD

FBMA-L11-201209-221LMA30T_0805

TXOUT0-<18>
TXOUT0+<18>

TXOUT1-<18>

TXOUT1+<18>
TXOUT2-<18>

TXOUT2+<18>

TXCLK-<18>
TXCLK+<18>

L10

+3VS

12

(60 MIL)

TXOUT0­TXOUT0+

TXOUT1+
TXOUT2-

TXOUT2+
TXCLK-

TXCLK+
+LCDVDD_L

1

C22
220P_0402_50V7K

2

@

Follow HEL80's pin definition

JP31

112

3

3

5

5

7

7
9910
111112

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

GND1

32

GND2

ACES_88242-3001
ME@

2
4

4

6

6

8

8

10
12
14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

TZOUT0­TZOUT0+

TZOUT1-TXOUT1­TZOUT1+

TZOUT2­TZOUT2+

TZCLK­TZCLK+

I2CC_SDA
I2CC_SCL

1

2

+3VS

C20
220P_0402_50V7K

@

TZOUT0- <18>

TZOUT0+ <18>

TZOUT1- <18>

TZOUT1+ <18>

TZOUT2- <18>

TZOUT2+ <18>

TZCLK- <18>

TZCLK+ <18>
I2CC_SDA <18>

I2CC_SCL <18>

Except pin 29

INVERTER Conn.

INV_PWN_R

DAC_BRIG<31>

+INVPWR_B+

DISPOFF#

BKOFF#<31>

INVT_PWM<31>

JP37

1
2
3
4
5
6
7

MOLEX_53780-0790

ME@

BKOFF# DISPOFF#

INVT_PWM INV_PWN_R

D10 RB751V_SOD323

R25 0_0402_5%

21

1 2

DAC_BRIG
INVT_PWM
DISPOFF#

+3VS

12

R28

4.7K_0402_5%

1 2

C44 470P_0402_50V7K@

1 2

C48 470P_0402_50V7K@

1 2

C45 470P_0402_50V7K@

+INVPWR_B+

L12

KC FBM-L11-201209-221LMAT_0805

L11

KC FBM-L11-201209-221LMAT_0805

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/18 2007/8/18

Compal Secret Data

C49

0.1U_0603_50V4Z

Deciphered Date

1

C43
68P_0402_50V8K

2

@

2

12

12

B+

Title

Size Document Number Rev

B

JFWXX M/B LA-3961P Schematic

Date: Sheet

Compal Electronics, Inc.

LVDS & DVI Connector

16 49Thursday, September 06, 2007

1

0.1

of

A

CRT Connector

1 1

VGA_CRT_R<9>

VGA_CRT_G<9>

VGA_CRT_B<9>

2 2

Place closed to chipset

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

R10

75_0402_5%

12

75_0402_5%

R9

9/5 change C8,C12,C15 from 10P @to mount

VGA_CRT_HSYNC<9>

12

VGA_CRT_VSYNC<9>

TV-OUT Conn.

3 3

TVDACG_Y<18>

TVDACB_C<18>

TVDACR_CVBS<18>

R339

75_0402_5%

8/29 change R330,R333,R339 from 75Ohm to @

8/29 change L30,L31,L33 from BEAD to @

TVDACG_Y

TVDACB_C

TVDACR_CVBS

12

@

75_0402_5%

R330

12

R333

@

75_0402_5%

12

C397

@

6P_0402_50V8D

B

12/15 Modified. Note L26~L30 are 0 Ohm resisters

L9 0_0603_5%

L7 0_0603_5%

12

R8

75_0402_5%

C15

10P_0402_50V8J

Place closed to chipset

1

1

1

2

C388

@

2

6P_0402_50V8D

C414

@

6P_0402_50V8D

2

1

1

C12

2

2

10P_0402_50V8J

1 2

C11 0.1U_0402_16V4Z

VGA_CRT_HSYNC

+3VS

1 2

L33 FCM1608C-121T_0603@

1 2

L30 FCM1608C-121T_0603@

1 2

L31 FCM1608C-121T_0603@

@

L5 0_0603_5%

1

C8

2

10P_0402_50V8J

+CRT_VCC

1 2

C5 0.1U_0402_16V4Z

VGA_CRT_ VSYNC

D24

@

DAN217_SC59

1

C398

6P_0402_50V8D

2

1

2

18P_0402_50V8J

8/29 changeC9,C14,C17 from 22P @ to 18p

1

5

U2

P

A2Y

G

TC7SET125FUF_SC70

3

1

2

@

6P_0402_50V8D

OE#

3

C387

4

+CRT_VCC

A2Y

D23

@

DAN217_SC59

2

1

@

2

CRT_HSYNC_0

5

P

G

TC7SET125FUF_SC70

3

1

3

C407

8/29 change C397,C388,C414,C398,C387,C407 from 6P to @

C

D6

@

DAN217_SC59

2

+3VS

8/29 changeL4,L6,L8 from 0 Ohm to bead

CRT_R_1

CRT_G_1

CRT_B_1

1

C17

2

18P_0402_50V8J

1

U1

CRT_VSYNC_0

4

OE#

D25

@

DAN217_SC59

2

TV_C
TV_CVBS

TV_Y

1

@

6P_0402_50V8D

2

L8
FBMA-L10-160808-800LMT_0603

L6
FBMA-L10-160808-800LMT_0603

L4
FBMA-L10-160808-800LMT_0603

1

C9

C14

2

18P_0402_50V8J

R6 10K_0402_5%

1 2

R7 39_0402_1%

1 2

R5 39_0402_1%

1

3

1 2

1 2

1 2

12

CRT_HSYNC_1

CRT_VSYNC_1

1

C16

10P_0402_50V8J

2

JP30

3
6
7
5
2
4
1
8
9

SUYIN_030107FR007SX08FU

ME@

D

D5

@

DAN217_SC59

2

3

1

C13
10P_0402_50V8J

2

1

3

10P_0402_50V8J

+5VS

2.2K_0402_5%

DSUB_12

DSUB_15

1

1 2

L3 FCM1608C-121T_0603

1 2

L2 FCM1608C-121T_0603

D4

@

DAN217_SC59

1

2

3

CRT_R_2

CRT_G_2

CRT_B_2

1

C10
10P_0402_50V8J

2

CRT_HSYNC_2

CRT_VSYNC_2

1

C6

2

DAN217_SC59

+CRT_VCC

R2

+5VS

0208 Add L64 for EMI

L1
KC FBM-L11-201209-221LMAT_0805

1 2

+L_CRT_VCC

2 1

RB411DT146_SOT23-3

1

C4
10P_0402_50V8J

2

1

D3

@

2

3

2

12

R3

2.2K_0402_5%

1 3

D

Q1
2N7002_SOT23

+3VS

2

Q2
2N7002_SOT23

12

D1

1

C3

2

100P_0402_50V8J

1

D2
DAN217_SC59

@

3

G

S

2

G

1 3

D

E

W=40mils

F1

1.1A_6VDC_FUSE

0.1U_0402_16V4Z

21

1

C1

2

1

C7
68P_0402_50V8K

2

1

2

W=40mils

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

DSUB_12

DSUB_15

C2
68P_0402_50V8K

12/22 Change to SE071680J80

+3VS

12

R1

2.2K_0402_5%

S

R4

2.2K_0402_5%

1 2

+3VS

+CRT_VCC+R_CRT_VCC

JP29

16
17

SUYIN_7846S-15G2T-HI

ME@

GMCH_CRT_DATA <9>

GMCH_CRT_CLK <9>

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

CRT & TV-OUT Connector

JFWXX M/B LA-3961P Schematic

E

of

17 49Thursday, September 06, 2007

0.1

5

+1.8VS +1.8VS

L36 MBK1608121YZF_0603

1 2

1

C436

2

10U_0805_10V4Z

Modify 10U_1206 to

D D

10U_0805

1

0.1U_0402_16V4Z

2

For 307LV/ELV only

GMCH_ENVDD<16>
ENBKL<31>

C C

VB_LAVDD

307LV/ELV:
Stuff R107, R96, C110
Un-stuff R108
307DV/CP: Stuff R108
Un-stuff R107, R96, C110

B B

R108 1.65K_0402_1%@

1 2

R107 6.04K_0402_1%

1 2

R96 24K_0402_1%

1 2

C110
1U_0603_10V4Z

VBRCLK<14>

1 2

+3VS

General I/O Power

1 2

R358 0_0402_5%

VBRCLK

1

C444

C425

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

R130

100K_0402_5%

TZOUT2+<16>
TZOUT2-<16>
TZOUT1+<16>
TZOUT1-<16>
TZOUT0+<16>
TZOUT0-<16>
TZCLK+<16>
TZCLK-<16>
TXCLK+<16>
TXCLK-<16>
TXOUT0+<16>
TXOUT0-<16>
TXOUT1+<16>
TXOUT1-<16>
TXOUT2+<16>
TXOUT2-<16>

I2CC_SDA<16>
I2CC_SCL<16>

R540 0_0402_5%

1 2

NB_RST#<9,19>

VB_VDD3V

1

C434

0.1U_0402_16V4Z

2

1

C424

2

T17
T20
T21
T18
T7
T8

12

T10
T12
T16
T13
T14
T19
T22

T15
T11
T9

1

C423

2

0.1U_0402_16V4Z

PAD
PAD
PAD
PAD
PAD
PAD

PAD
PAD
PAD
PAD
PAD
PAD
PAD

EXTSWING

VBOSCO
VBRCLK_R

PAD
PAD
PAD

VB_PCIEVDD VB_PCIEAVDD

254mA 35mA

1

C422

0.1U_0402_16V4Z

2

Modify 10U_1206 to
10U_0805

U6

G2

H2
H1

G1
E12
E11

G13
G12

F11

F3

G3

F2
F1
H3

J3

C13

A12
A13

C11
C12

A10
A11

C9

C10

A8
A9
C7
C8
A6
A7
C5
C6
A4
A5
C3
C4

E13
F12

J1
J2

G11

F10
E10
F13

NOTE: all stuffed(default)

+1.8VS

A A

1

C441

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

2

1

C437

0.1U_0402_16V4Z

2

1

C440

2

0.1U_0402_16V4Z

C433

Internal Core Power

5

Modify before using!

I2CC_SCL
I2CC_SDA

4

L37 MBK1608121YZF_0603

1

C439
10U_0805_10V4Z

2

R365 0_0402_5%

VB_VDD3V VB_ DA CVDD

GPIOA
GPIOB
GPIOC
GPIOD
LCDSENSE/GPIOE
INTN/GPIOF
GPIOG
GPIOH
GPIOI
GPIOJ
GPIOK
V2HSYNC/GPIOL
V2VSYNC/GPIOM
TSCLKI/GPION
TVCLKO/GPIOO

EXTSWING
LX3P
LX3N
LX2P
LX2N
LX1P
LX1N
LX0P
LX0N
LXC1P
LXC1N
LXC2P
LXC2N
LX4P
LX4N
LX5P
LX5N
LX6P
LX6N
LX7P
LX7N

LDDCDATA
LDDCCLK
VBOSCO
VBRCLK
PFTEST2
PFTEST1
PFTESTO
EXTRSTN

8/28 Change U6 from SIS307LV SA00000O920 to SIS307ELV SA00000O930

VSSF5VSSF6VSSF7VSSF8VSSF9VSSG5VSSG6VSSG7VSSG8VSSG9VSSH5VSSH6VSSH7VSSH8VSS

DDC pull-up

R124 2.2K_0402_5%

1 2
1 2

R118 2.2K_0402_5%

4

1 2

1 2

+1.8VS

392mA

G10

H13

IVDD

VDD3V

+5VS

3

H12

1

2

H10

H11

IVDD

IVDD

IVDD

VSS

H9

J10

C443

0.1U_0402_16V4Z

J4

G4

IVDDH4IVDD

IVDD

PCIEVSS

K10

K12

1

C442

0.01U_0402_16V7K

2

VB_PCIEAVSS

VB_PCIEVDD

K3

J6

K4

PCIEVDDJ5PCIEVDD

PCIEVDD

PCIEVDD

J7

J8

L1

PCIEVDD

PCIEVDD

PCIEVDDJ9PCIEVDD

VB_PCIEAVDD

VB_LVDSPLLVDD

VB_PLL1VDD

L6

C2

L2

PCIEVDD

K2

L3

M1

B3

DACVDD

PCIEVDD

PCIEVDD

PLL1VDD

PCIEAVDD

LVDSPLLVDD

SiS307ELV

PCIEVSS

PCIEVSS

PCIEVSS

PCIEVSS

PCIEVSS

PCIEVSSK5PCIEVSSK6PCIEVSSK7PCIEVSSK8PCIEVSSK9PCIEVSS

M4

M2

M3

L11

L10

PCIEVSS

PCIEVSSM5PCIEVSS

PCIEVSSM7PCIEVSS

PCIEVSS

PCIEVSS

M8

M9

M6

M10

PCIEVSS

M11

VB_LAVDD

E9

D10

D11

D12

D13

LAVDDE5LAVDDE6LAVDDE7LAVDDE8LAVDD

LAVDD

LAVDD

LAVDD

LAVDD

LAVSSA3LAVSSB4LAVSSB5LAVSSB6LAVSSB7LAVSSB8LAVSSB9LAVSS

PCIEVSS

PCIEVSS

N1

M12

M13

R334 0_0603_5%

B10

LAVSS

B11

B12

LAVSS

B13

PERN5/SVB_Bn

PERP5/SVB_Bp
PERN4/SVB_Gn
PERP4/SVB_Gp
PERN3/SVB_Rn

PERP3/SVB_Rp

PERN2/SVA_Bn

PERP2/SVA_Bp
PERN1/SVA_Gn
PERP1/SVA_Gp
PERN0/SVA_Rn

PERP0/SVA_Rp

LVDSPLLVSS

LAVSS

LAVSSD4LAVSSD5LAVSSD6LAVSSD7LAVSSD8LAVSS

REFCLKN

REFCLKP
PCIERSET0
PCIERSET1

VACLK
VBCLK

VBHSYNC

VBVSYNC

VBHCAD

VBHCLK

V2RSET
V2COMP
TVDACR
TVDACG
TVDACB

TVCSYNC

PCIEAVSS

PLL1VSS

DACVSS
DACVSS
DACVSS
DACVSS
DACVSS

SIS307LV-B0_BGA_167P

D9

AGND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01

3

Compal Secret Data

Deciphered Date

2

96mA

0.1U_0402_16V4Z

N12
N13
N10
N11
N8
N9

N6
N7
N4
N5
N2
N3

L7
L8

VB_PCIERSET0

L4

VB_PCIERSET1

L5
K13

VBCLK_R

J12
K11
J11
L13
L12

V2RSET

B2

V2COMP

B1
D2
D1
E2
E1

VB_PCIEAVSS

L9

VB_LVDSPLLVSS

A2

VB_PLL1VSS

K1
C1

D3
E3
E4
F4

AGND

0.1U_0402_16V4Z

2006/03/01

2

1

VB_LAVDD

1

C430

PAD

1

C429

0.1U_0402_16V4Z

2

2

VB_LVDSPLLVDD

30mA

0.1U_0402_16V4Z

VB_LVDSPLLVSS

HDVBN2_C <7>
HDVBP2_C <7>
HDVBN1_C <7>
HDVBP1_C <7>
HDVBN0_C <7>
HDVBP0_C <7>

HDVAN2_C <7>
HDVAP2_C <7>
HDVAN1_C <7>
HDVAP1_C <7>
HDVAN0_C <7>
HDVAP0_C <7>

R370 499_0402_1%

1 2

R369 124_0402_1%

R132 33_0402_5%

1 2

R345 0_0402_5%@

1 2

R346 115_0402_1%

T6

V2COMP

VB_DACVDD +3VS

99mA

1

1

C92

2

2

0.01U_0402_16V7K

AGND

VBOSCO

11mA

VB_PLL1VDD

VB_PLL1VSS

Title

Size Document Number Rev

Custom

Date: Sheet

1

C431

0.1U_0402_16V4Z

2

1

C421

2

C109 0.1U_0402_16V4Z

1 2

307ELV:change C94 to 0 ohm
307LV/DV/CP:C94=0.1uF

C94 0_0402_5%

1 2

8/28 Change C94 from 0.1U to 0 Ohm

1

C91

C93

10U_0805_10V4Z

2

4.7U_0805_10V4Z

Y2 14.31818MHZ_16PF_DSX840GA@

1 2

2

C116

@

27P_0402_50V8J

1

1

C118

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

LVDS Encoder SiS307LV

JFWXX M/B LA-3961P Schematic

Thursday, September 06, 2007

MBK1608121YZF_0603
L35

1 2

1

C427

0.1U_0402_16V4Z

2

Modify 10U_1206 to
10U_0805

L32

1 2

MBK1608121YZF_0603

1

C402

0.01U_0402_16V7K

2

1 2

R336 0_0402_5%

Modify 10U_1206 to
10U_0805

PCIE_CLK_307# <14>
PCIE_CLK_307 <14>

VACLK <9>
VBCLK <9>
VBHSYNC <9>
VBVSYNC <9>
VBCAD <9>
VBHCLK <9>

TVDACR_CVBS <17>
TVDACG_Y <17>
TVDACB_C <17>

Side-Band
Signals

VB_DACVDD

AGND

307ELV:NC these 4 pins!

AGND

L14

1

1

C670
10U_0805_10V4Z

2

1_0603_5%

C669

2

7/30 change L14 to 1_0603
Add C669 and C670

R125 10_0402_5%@

1 2

2

C113

@

27P_0402_50V8J

1

L17

1 2

MBK1608121YZF_0603

1

C119

0.01U_0402_16V7K

2

1 2

R139 0_0402_5%

1

+3VS

1

C428

10U_0805_10V4Z

2

+3VS

1

C399

10U_0805_10V4Z

2

VBRCLK_R

+3VS

1

C154
10U_0805_10V4Z

2

of

18 49

0.1

5

D D

C C

+1.8VS

12

R198
150_0402_1%

SZVREF

12

B B

A A

10U_0805_10V4Z

R200

49.9_0402_1%

+1.8VS

+1.8VS

C552

1

C194

0.1U_0402_16V4Z

2

1 2

R206 56_0402_5%

1 2

R204 56_0402_5%

L49

1 2

MBK1608121YZF_0603

1

0.1U_0402_16V4Z

2

1 2

R446 0_0402_5%

5

C549

1

1

2

2

PCI_AD[0..31]< 26>

ZAD[0..16]<9>

SZCMP_N

SZCMP_P

16mA

AVDD_SZ4X

C550

0.01U_0402_16V7K

AVSS_SZ4X

ZAD[0..16]

ZSTB_DP0<9>
ZSTB_DN0<9>
ZSTB_DP1<9>
ZSTB_DN1<9>

ZUREQ<9>
ZDREQ<9>

Z_CLK1<14>

4

4

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16

SZCMP_N
SZCMP_P

AVDD_SZ4X
AVSS_SZ4X

SZVREF

3

U11A

H5

AD31

J4

AD30

J3

AD29

K1

AD28

K2

AD27

J5

AD26

K4

AD25

K3

AD24

L2

AD23

K5

AD22

L4

AD21

L3

AD20

M1

AD19

M2

AD18

L5

AD17

M4

AD16

P3

AD15

R1

AD14

R2

AD13

P5

AD12

R4

AD11

R3

AD10

T1

AD9

T2

AD8

T4

AD7

T3

AD6

U1

AD5

U2

AD4

T5

AD3

U4

AD2

U3

AD1

V1

AD0

Y22

ZAD0

Y25

ZAD1

Y23

ZAD2

W21

ZAD3

Y26

ZAD4

W22

ZAD5

W24

ZAD6

W25

ZAD7

U21

ZAD8

U24

ZAD9

U22

ZAD10

T22

ZAD11

U25

ZAD12

T23

ZAD13

T25

ZAD14

T26

ZAD15

AA26

ZAD16

V22

ZSTB0

V23

ZSTB0#

V25

ZSTB1

V26

ZSTB1#

AA23

ZUREQ

AA24

ZDREQ

AB24

ZCMP_N

AB25

ZCMP_P

AA22

AVDD_Z4X

AB23

AVSS_Z4X

AB26

ZVREF

AC26

ZCLK

AE22

SPI_DI

AD22

SPI_DO

AF21

SPI_CS1N

AE21

SPI_CS0N

SIS968-B0_TEBGA_570P

PCI

MuTIOL

SPI

SPI_HARDWARE_TRAP

PREQ4#
PREQ3#
PREQ2#
PREQ1#
PREQ0#

PGNT4#
PGNT3#
PGNT2#
PGNT1#
PGNT0#

C/BE3#
C/BE2#
C/BE1#
C/BE0#

FRAME#

TRDY#
STOP#
SERR#

DEVSEL#

PLOCK#

PCICLK

PCIRST#

IDSAA2
IDSAA1
IDSAA0

IDE

IDECSA1#
IDECSA0#

IIORA#

IIOWA#

IDACKA#

ICHRDYA

IDREQA

CBLIDA

AVDD_IDE
AVSS_IDE

SPI_CLK

INTA#
INTB#
INTC#
INTD#

IRDY#

PAR

IDA0
IDA1
IDA2
IDA3
IDA4
IDA5
IDA6
IDA7
IDA8

IDA9
IDA10
IDA11
IDA12
IDA13
IDA14
IDA15

IIRQA

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01

3

PCI_REQ#4

H2

PCI_REQ#3

H1

PCI_REQ#2

G3

PCI_REQ#1

G4

PCI_REQ#0

G2

PCI_GNT#4

J2

PCI_GNT#3

J1

PCI_GNT#2

H3

PCI_GNT#1

H4

PCI_GNT#0

G5

PCI_CBE#3

L1

PCI_CBE#2

M3

PCI_CBE#1

N5

PCI_CBE#0

R5

INT_N_A

F5

PCI_PIRQB#

F4

PCI_PIRQC#

F3

PCI_PIRQD#

G1

PCI_FRAME#

N1

PCI_IRDY#

N2

PCI_TRDY#

M5

PCI_STOP#

N3

PCI_SERR#

P2

PCI_PAR

P4

PCI_DEVSEL#

N4

PCI_PLOCK#

P1

CLK_PCI_SB

V2

PCI_RST#_R

D5

IDE_DD0

AE19

IDE_DD1

AD18

IDE_DD2

AC17

IDE_DD3

AF18

IDE_DD4

AB16

IDE_DD5

AE17

IDE_DD6

AD16

IDE_DD7

AF16

IDE_DD8

AE16

IDE_DD9

AF17

IDE_DD10

AC16

IDE_DD11

AD17

IDE_DD12

AE18

IDE_DD13

AB17

IDE_DD14

AF19

IDE_DD15

AC18

IDE_DA2

AD21

IDE_DA1

AD20

IDE_DA0

AB20

IDE_DCS3#

AC21

IDE_DCS1#

AB21

IDE_DIOR#

AF20

IDE_DIOW#

AD19

IDE_DDACK#

AC19

IDE_DIORDY

AE20

IDE_DDREQ

AB18

IDE_IRQ

AB19
AC20

V3

IDEAVSS

V4

AF22
AF23

1 2

R215 4.7K_0402_5%

SPI_Hardware Trap

0:LPC (Default)
1:SPI

Compal Secret Data

Deciphered Date

2

R432 need to close to R5C833

PCI_REQ#0 <26>

PAD

T28

PAD

T29

PAD

T27

PAD

T26

PCI_GNT#0 <26>
PCI_CBE#3 <26>

PCI_CBE#2 <26>
PCI_CBE#1 <26>
PCI_CBE#0 <26>

INT_N_A <7,9>

PCI_PIRQC# <26>
PCI_PIRQD# <26>

PCI_FRAME# <26>
PCI_IRDY# <26>
PCI_TRDY# <26>
PCI_STOP# <26>
PCI_SERR# <26>
PCI_PAR <26>
PCI_DEVSEL# <26>

CLK_PCI_SB <14>

IDE_DD[0..15] <24>

IDE_DA[0..2] <24>

IDE_DCS3# <24>
IDE_DCS1# <24>

IDE_DIOR# <24>

IDE_DIOW# <24>

IDE_DDACK# <24>

IDE_DIORDY <24>

IDE_DDREQ <24>

IDE_IRQ <24>

R384 33_0402_5%
R373 33_0402_5%

2006/03/01

2

1

+3VS

1 2
1 2

PCI_REQ#4
PCI_REQ#3
PCI_REQ#2
PCI_REQ#1

PCI_PERR#<26>

PCI_PERR#
INT_N_A
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_SERR#
PCI_DEVSEL#
PCI_PLOCK#

IDE_DIORDY
IDE_IRQ

IDE_DDREQ
IDE_IRQ
IDE_DD7

R189 8.2K_0402_5%

1 2

R186 8.2K_0402_5%

1 2

R180 8.2K_0402_5%

1 2

R181 8.2K_0402_5%

1 2

R432 8.2K_0402_5%

1 2

R408 8.2K_0402_5%

1 2

R412 8.2K_0402_5%

1 2

R410 8.2K_0402_5%

1 2

R413 8.2K_0402_5%

1 2

R419 8.2K_0402_5%

1 2

R421 8.2K_0402_5%

1 2

R416 8.2K_0402_5%

1 2

R418 8.2K_0402_5%

1 2

R422 8.2K_0402_5%

1 2

R417 8.2K_0402_5%

1 2

R191 8.2K_0402_5%

1 2

PCI_RST# <24,26,28,29,30,31,33>
NB_RST# <9,18>

R450 4.7K_0402_5%@

1 2

R434 8.2K_0402_5%

1 2

R441 4.7K_0402_5%@

1 2

R437 4.7K_0402_5%@

1 2

R218 5.6K_0402_5%

1 2

+3VS

R450 => Intel :Pull-up 4.7K ohm (Mount) SiS : Pull-up ? ohm (Un-Mount)
R434 => Intel :Pull-up 8. 2K ohm (Mount) SiS :Not Pull-up
R441 => Intel :Don't Pull-down SiS : Pull-down ? ohm (Un-Mount)
R437 => Intel :Don't Pull-down SiS : Pull-down ? ohm (Un-Mount)
R218 => Intel :Don't Pull-down SiS : Pull-down 5.6K ohm (Mount)

1

+1.8VS

1

C521

0.1U_0402_16V4Z

2

19 49

of

8mA

IDEAVDDIDEAVDD

1

C536

0.1U_0402_16V4Z

Title

Size Document Number Rev

Custom

Date: Sheet

2

IDEAVSS

Compal Electronics, Inc.

SIS968(1/5)-PCI_IDE _MuTIO L
JFWXX M/B LA-3961P Schematic

Thursday, September 06, 2007

L47

1 2

MBK1608121YZF_0603

1

C535

0.01U_0402_16V7K

2

1 2

R428 0_0402_5%

0.1

5

C175 15P_0402_50V8J

X1

3

NC

2

32.768KHZ_12.5P_1TJS125BJ2A251

D D

NC

C172 15P_0402_50V8J

4

OUT

1

IN

8/07 modified from 12P to 15P

+3VS

R430 4.7K_0402_5%

1 2

R429 10K_0402_5%

1 2

R173

10M_0402_5%

LPC_DRQ0#
SERIRQ

12

SB_PWRGD<9,31>

0.1U_0402_16V4Z

LPC_AD0<31,33>
LPC_AD1<31,33>
LPC_AD2<31,33>
LPC_AD3<31,33>

LPC_FRAME#<31,33>

LPC_DRQ0#<33>

SERIRQ<26,31,33>

R430 => Intel :Not Pull-up SiS : Pull-up 4.7K ohm (Mount)
R429 => Intel :Pull-up 10K ohm (Mount) SiS :Not Pull-up

+RTCVCC

3
4

+RTCBATT

5

1 2

R192 33_0402_5%

1 2

R194 33_0402_5%

1 2

R201 33_0402_5%

1 2

R203 33_0402_5%

1 2

R197 33_0402_5%

1 2

R199 33_0402_5%

1 2

R166 33_0402_5%

1 2

R167 33_0402_5%

EC_SMI#
EC_LID_OUT#
EC_SCI#
PM_SLP_S5#
AGPSTOP#
CPUSTP_N_OLD
EC_THERM#
PM_SLP_S3#
GPIO16 PSON#
GATEA20
KB_RST#
GPIO14

GATEA20
KB_RST#

+RTC_BATT

R291

1 2

511_0603_1%

1

BAS40-04_SOT23

1U_0603_10V4Z

Decoupling Capacitor

Please close to SB

HDA_SDOUT_SB

HDA_SYNC_SB

HDA_RST_SB#

CPU IU

R176

1 2

0_0402_5%

AUX_PWRGD<9,31>

D20

C346

HDA_BITCLK_AUDIO<35>
HDA_BITCLK_MDC<37>
HDA_SDOUT_AUDIO<35>

C C

HDA_SDOUT_MDC<37>
HDA_SYNC_AUDIO<35>

HDA_SYNC_MDC<37>
HDA_RST_AUDIO#<35>
HDA_RST_MDC#<37>

8/29 change net from BAT_PWRGD to net +RTCVCC

SMT1-05_4P
SW2

@

1
2

5

6

B B

+3VALW

+3VS

-+

A A

7/30 add for debug

R163 10K_0402_5%

1 2

R162 10K_0402_5%

1 2

R164 10K_0402_5%

1 2

R388 10K_0402_5%

1 2

R382 10K_0402_5%

1 2

R425 10K_0402_5%

1 2

R390 10K_0402_5%@

1 2

R387 10K_0402_5%

1 2

R381 10K_0402_5%

1 2

R397 10K_0402_5%

1 2

R393 10K_0402_5%

1 2

R548 10K_0402_5%

1 2

R403 10K_0402_5%@

1 2

R398 10K_0402_5%@

1 2

BATT1

12

ML1220T13RE

@

H_THERMTRIP#<4>

2

3

1

C326

2

10U_0805_10V4Z

HDA_SDIN0<35>
HDA_SDIN1<37>

H_INIT#<4>

H_A20M#<4>

H_SMI#<4>
H_INTR<4>

H_NMI<4>

H_IGNNE#<4>

H_FERR#<4>
H_STPCLK#<4>
H_CPUSLP#<5>

H_PROCHOT#<4>

AGPBUSY#<9>

REF_CLK1<14>

SB_SPKR< 35>

PBTN_OUT#<31>

PCI_PME#<31>

PSON#<31>

C168 0.1U_0402_16V4Z

PM_SLP_S5#<31>

PM_SLP_S3#<31>

EC_SMI#<31>
EC_LID_OUT#<31>

EC_SCI#<31>

AGPSTOP#<9>
CPUSTP_N_OLD<25>
SB_DPRSLPVR<25>

GATEA20<31>
KB_RST#<31>

+CHGRTC

1

1

C333

0.01U_0402_16V7K

2

2

0.1U_0402_16V4Z

@

1

C332

2

C473

12

+RTCVCC

4

U11B

OSC32KHO
OSC32KHI

BAT_PWRGD
SB_PWRGD

1

+RTCVCC

2

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#
LPC_DRQ0#
SERIRQ

HDA_SDOUT_SB
HDA_SYNC_SB

HDA_RST_SB#
HDA_BITCLK_SB

H_INIT#
H_A20M#
H_SMI#
H_INTR
H_NMI
H_IGNNE#
H_FERR#
H_STPCLK#
H_CPUSLP#

AA4
AB2
AB3

AB1
AB4
AA5

AC23
AE26
AD23
AC22
AE25
AE24
AF24
AF25
AD24

E2
E1

F1

E4

D1
D2

Y5

E5
C4

Y3
Y2

B3
Y1

OSC32KHO
OSC32KHI

BATOK
PWROK

RTCVDD
RTCVSS

LAD0
LAD1
LAD2
LAD3

LFRAME#
LDRQ#
SIRQ

HDA_SDIN0
HDA_SDIN1

HDA_SDOUT
HDA_SYNC

HDA_RESET#
HDA_BIT_CLK

INIT#
A20M#
SMI#
INTR
NMI
IGNNE#
FERR#
STPCLK#
CPUSLP#

LPCRTC HD Audio ACPI

CPU_S

APIC

AC24

H_THERMTRIP#
AGPBUSY#

SB_SPKR
PBTN_OUT#

PCI_PME#
PSON#

PM_SLP_S5#
PM_SLP_S3#

EC_SMI#
EC_LID_OUT#
EC_SCI#

AGPSTOP#
CPUSTP_N_OLD
SB_DPRSLPVR
GPIO14

GPIO16
GATEA20
KB_RST#

Change D19 footprint from RLS4148_LL34-2 to LL34

D19 RLS4148_LL34-2

1 2

R279 10K_0402_5%

1 2

12

J1

@

JOPEN

10U_0805_10V4Z

4

PROCHOT#

AD25

THERMTRIP#

AE23

BMBUSY#

AA2

OSCI

F2

ENTEST

AA1

SPK

E6

PWRBTN#

A6

PME#

E7

PSON#

C3

AUXOK

A5

ACPILED

C2

GPIO10/SLP_S5#

C7

GPIO15/SLP_S3#

D6

GPIO7/GPWAK#

A4

GPIO8/RING

C6

GPIO9/HDA_SDIN2

F6

GPIO11/STP_PCI#/AGPSTOP#

D4

GPIO12/CPUSTP#/DPSLP#

D3

GPIO13/DPRSLPVR

B5

GPIO14/AGPSTOP#/S3AUXSW#

B7

GPIO16/DPRSTP#

D7

GPIO17/GA20#

B4

GPIO18/KBDRST#

SIS968-B0_TEBGA_570P

@

J4 JOPEN

1 2

BAT_PWRGD

GPIO

8/29 change J1,J4 from net BAT_PWRGD to net +RTCVCC

C328

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

AVSS_GMACCMP18

AVDD_GMACCMP18

OSC25MHO

OSC25MHI

GTXCLK
EXTCLK

TXCLK

TXEN
TXER

TXD0
TXD1
TXD2
TXD3

RGMCMP_N

GMACPCI Express

GPIO1/LDRQ1#/PCIE_HOTPLUG

GPIO14

RGMCMP_P

RGMVREF

RXCLK

RXDV
RXER

RXD0
RXD1
RXD2
RXD3

COL
CRS
MDC

MDIO

GPIO21
GPIO22
GPIO23
GPIO24

PRX0+

PRX0­PTX0+

PTX0-

PRX1+

PRX1­PTX1+

PTX1-

NC11
NC10

NC9

NC8

NC7

NC6

NC5

NC4

PCLK100P
PCLK100N

AVDD_PEXTRX

AVSS_PEXTRX

RSET0
RSET1

PCIEPRSNT1
PCIEPRSNT0

GPIO0/STPCPU#

GPIO2/THERM#
GPIO3/EXTSMI#

GPIO4/CLKRUN#

GPIO5/PREQ5#
GPIO6/PGNT5#

GPIO19
GPIO20

R431 0_0402_5%

1 2

R394 0_0402_5%@

1 2

Compal Secret Data

2005/03/01

3

Deciphered Date

AVSS_GMACCMP

C8

AVDD_GMACCMP

D9

MOSC25MHO

B8

MOSC25MHI

A8

GTXCLK

A12
F14

B11
C12

C11
D12

A13
B13
C13

A14
B14
C14

A11
C10

E12
A10

C9
B9
A9

E10
E11
E14
E13

D8
F8
E8
A7

M26
M25
N24
N23
K26
K25
L24
L23

F26
F25
G24
G23
H26
H25
J24
J23

P26
P25
R25
R26
P22
P21

R21
R23

U5
AB5
V5
W4
W3
W2
W1

Y4
W5

PAD

EXTCLK

PAD

TX_EN

R389 33_0402_5%

TXER
TXD_0

TXD_1
TXD_2
TXD_3

RGMCMP_N
RGMCMP_P
RGMVREF

RXCLK
RXDV

RXER
RXD0

RXD1
RXD2
RXD3

COL
CRS

MDIO
GPIO21

GPIO22
GPIO23
GPIO24

PCIE_PTX_C_IRX_P0
PCIE_PTX_C_IRX_N0

PCIE_ITX_PRX_N0
PCIE_PTX_C_IRX_P1
PCIE_PTX_C_IRX_N1
PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1

PCIE_CLK_SB
PCIE_CLK_SB#
AVDD_PEXTRX
AVSS_PEXTRX

PCIEPRSNT1
PCIEPRSNT0

PROJECT_ID
GPIO1
GPIO2
GPIO3
PM_CLKRUN#
GPIO5
IDE_HRESET#

SCLK
SDATA

1 2

PAD

R146 33_0402_5%

1 2

R159 33_0402_5%

1 2

R158 33_0402_5%

1 2

R145 33_0402_5%

1 2

R420 499_0402_1%

1 2

R426 124_0402_1%

1 2

7/20 modified

R187 4.7K_0402_5%

2 1

D14 RB751V_SOD323

2

T4
T25

TXCLK <28>

T24

R161 56_0402_5%

1 2

R160 56_0402_5%

1 2

R147 150_0402_1%

1 2

RXCLK <28>
RXDV <28>

RXER <28>
RXD0 <28>

RXD1 <28>
RXD2 <28>
RXD3 <28>

COL <28>

R568 33_0402_5%

CRS <28>

1 2

MDIO <28>

GPIO23
GPIO22
GPIO21
GPIO24

C515 0.1U_0402_10V7K

1 2

C511 0.1U_0402_10V7K

1 2

C512 0.1U_0402_10V7K

1 2

C506 0.1U_0402_10V7K

1 2

PCIE_CLK_SB <14>
PCIE_CLK_SB# <14>

R427 0_0402_5%

1 2

7/20 modified

PM_CLKRUN# <26,31>

IDE_HRESET# <24>

SCLK <12,13,14,15>

SDATA <12,13,14,15>

12

CP_PE#PCIEPRSNT1

EC_THERM#GPIO2

2006/03/01

2

+1.8VS

EC_THERM# <31>

1

8mA

AVDD_GMACCMP

1

C459

0.1U_0402_16V4Z

AVSS_GMACCMP

TXEN <28>

TXD0 <28>
TXD1 <28>
TXD2 <28>
TXD3 <28>

R142

150_0402_1%

MDCH_MDC

CP_PE# <30>

Title

Size Document Number Rev

Custom

Date: Sheet

+3VALW
+3VALW

12

1

C120

0.01U_0402_16V7K

2

U9

4

DO

3

DI

2

SK

1

CS

AT93C46-10SI-2.7_SO8

@

PCIE_ITX_C_PRX_P0PCIE_ITX_PRX_P0
PCIE_ITX_C_PRX_N0

PCIE_ITX_C_PRX_P1
PCIE_ITX_C_PRX_N1

PCI-Express

30mA

AVDD_PEXTRX

0.1U_0402_16V4Z

AVSS_PEXTRX

Compal Electronics, Inc.

SIS968(2/5)-PCIE_LAN_RTC

JFWXX M/B LA-3961P Schematic

Thursday, September 06, 2007

MDC <28>

5

GND

6

NC

7

NC

8

VCC

C185

GPIO23
PBTN_OUT#
PCI_PME#

GPIO1
GPIO2
GPIO3
GPIO5
IDE_HRESET#
PM_CLKRUN#

SB_DPRSLPVR

PROJECT_ID

2

PCIE_ITX_C_PRX_N0 <29>
PCIE_PTX_C_IRX_P1 <30>

PCIE_PTX_C_IRX_N1 <30>
PCIE_ITX_C_PRX_N1 <30>

1

2

R386 4.7K_0402_5%
R376 100K_0402_5%
R385 4.7K_0402_5%
R375 100K_0402_5%

R443 10K_0402_5%
R433 10K_0402_5%
R435 10K_0402_5%
R438 10K_0402_5%
R439 10K_0402_5%
R444 10K_0402_5%@

R404 4.7K_0402_5%

R436 10K_0402_5%@

L38

1 2

MBK1608121YZF_0603

1

C457

0.01U_0402_16V7K

2

1 2

R378 0_0402_5%

Put closed to 968

MOSC25MHO

R151 0_0402_5%

MOSC25MHI

33P_0402_50V8J

the same with "180"

7/30 modified from 27P to 33P

PCIE_PTX_C_IRX_P0 <29>
PCIE_PTX_C_IRX_N0 <29>
PCIE_ITX_C_PRX_P0 <29>

PCIE_ITX_C_PRX_P1 <30>

1

2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2

1 2

1 2
1 2

R424 1K_0402_5%14W@

1 2

Y4

1 2

25MHZ_20PF_6X25000017
C152

33P_0402_50V8J

+3VALW

L19

1 2

MBK1608121YZF_0603

C186

0.01U_0402_16V7K

1 2

R190 0_0402_5%

20 49

1

@

of

+1.8VALW

R150

0_0402_5%

C151

WLAN

NEW Card

+1.8VS

+3VALW

+3VS

12

+3VS

0.1

5

4

3

2

1

+1.8VALW

L18

1 2

MBK1608121YZF_0603

D D

+3VALW

L43

1 2

MBK1608121YZF_0603

C C

B B

A A

0.1U_0402_16V4Z
R168 0_0402_5%

R392 0_0402_5%

+1.8VALW

L46

1 2

MBK1608121YZF_0603

R407 0_0402_5%

+1.8VALW

L44

1 2

MBK1608121YZF_0603

+3VALW

R374 4.7K_0402_5%

+1.8VS

L23

1 2

MBK1608121YZF_0603

0.1U_0402_16V4Z

1 2

R217 0_0402_5%

+3VS

L48

1 2

MBK1608121YZF_0603

0.1U_0402_16V4Z

1 2

R440 0_0402_5%

C170

1 2

C489

0.1U_0402_16V4Z

C465

0.1U_0402_16V4Z

1 2

C476

0.1U_0402_16V4Z

1 2

C475

0.1U_0402_16V4Z

1 2

C222

C545

5

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

C215

0.01U_0402_16V7K

2

1

C548

0.01U_0402_16V7K

2

7mA

USBPVDD18

C171

0.01U_0402_16V7K

USBPVSS18

8mA

Place C478,C489 close to

C478

U11 Pin F17,F19,F22

0.01U_0402_16V7K

8mA

USBCMPAVDD33

Place C465,C466

C466

close to U11 Pin D21

0.01U_0402_16V7K

USBCMPAVSS33

9mA

USBCMPAVDD18

C477

0.01U_0402_16V7K

USBCMPAVSS18

284mA

UVDD18

C474

0.01U_0402_16V7K

SB_PCIE_WAKE#

6mA

AVDD_SATARX

AVSS_SATARX

41mA

AVDD_SATAPLL33

AVSS_SATAPLL33

+3VALW

1 2

1 2

SB_PCIE_WAKE#<7,29,30>

1 2
1 2

USB20_P0<30>
USB20_N0<30>

USB20_P2<30>
USB20_N2<30>
USB20_P3<29>
USB20_N3<29>
USB20_P4<34>
USB20_N4<34>
USB20_P5<34>
USB20_N5<34>
USB20_P6<30>
USB20_N6<30>
USB20_P7<37>
USB20_N7<37>

USB_OC#06<30>

USB_OC#45<34>

SATA_CLK_DP<14>
SATA_CLK_DN<14>

USB

BT

New Card

WLAN

USB
USB
USB

CAMERA

R213 12K_0402_1%
C216 22P_0402_50V8J

R405 1K_0402_5%
R155 1K_0402_5%@

133MHz:Internal pull-down
66MHz:External pull-up

+3VALW

R549 10K_0402_5%

1 2

R550 10K_0402_5%

1 2

R551 10K_0402_5%

1 2

R552 10K_0402_5%

1 2

4

U11C

USB20_P0
USB20_N0
USB20_P1
USB20_N1
USB20_P2
USB20_N2
USB20_P3
USB20_N3
USB20_P4
USB20_N4
USB20_P5
USB20_N5
USB20_P6
USB20_N6
USB20_P7
USB20_N7

USB_OC#06
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#45

USB_OC#7

AVDD_SATARX
AVSS_SATARX

AVDD_SATAPLL33

AVSS_SATAPLL33

SATA_REXT

SATA_CLK_DP
SATA_CLK_DN

SB_PCIE_WAKE#
ATRAP
TRAP0

USB_OC#2
USB_OC#1
USB_OC#3
USB_OC#7

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D26

UV0+

D25

UV0-

E24

UV1+

E23

UV1-

A20

UV2+

B20

UV2-

C19

UV3+

D19

UV3-

A18

UV4+

B18

UV4-

C17

UV5+

D17

UV5-

A16

UV6+

B16

UV6-

C15

UV7+

D15

UV7-

A23

OC0#

F21

OC1#

A24

OC2#

B24

OC3#

C23

OC4#

C24

OC5#

A25

OC6#

B23

OC7#

AF14

AVDD_SATARX

AF15

AVSS_SATARX

AC9

AVDD_SATAPLL33

AD9

AVDD_SATAPLL33

AC8

AVSS_SATAPLL33

AD8

AVSS_SATAPLL33

AF7

REXT

AE15

CLK100P

AD15

CLK100N

E9

PCIEWAKE

D10

ATRAP

E22

TRAP0

SIS968-B0_TEBGA_570P

2005/03/01

3

AVDD_USBCMP18
AVSS_USBCMP18

AVDD_USBCMP33
AVSS_USBCMP33

USB

SATA

Compal Secret Data

OSC12MHI

OSC12MHO

USBREF

AVDD_USBPLL18
AVSS_USBPLL18

UVDD33
UVDD33
UVDD33

UVDD18
UVDD18
UVDD18
UVDD18
UVDD18
UVDD18
UVDD18
UVDD18
UVDD18
UVDD18

STX0+

STX0-

SRX0+

SRX0-

STX1+

STX1-

SRX1+

SRX1-

XOUT

HDACT

ISWITCHOPEN1
ISWITCHOPEN0

IPB_OUT0
IPB_OUT1

Deciphered Date

XIN

USB_CLK_12M

A22
B22

USBREF

F20

USBPVDD18

B26

USBPVSS18

B25

USBCMPAVDD18

E21

USBCMPAVSS18

E20

USBCMPAVDD33

D21

USBCMPAVSS33

C21

USBCMPAVDD33

F17
F19
F22

UVDD18

J15
H15
H16
H17
H18
J19
F16
F15
E18
E16

SATA_ITX_DRX_P0

AC13

SATA_ITX_DRX_N0

AD13

SATA_DTX_C_IRX_P0

AF12

SATA_DTX_C_IRX_N0

AE12
AC6
AD6
AF5
AE5

SOSC25MHI

AE8
AF8

H_SATA_LED#

AA3

ISWITCHOPEN1

AC1

ISWITCHOPEN0

AD1

D22
C22

SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_N1

H_SATA_LED# SATA_LED#

2006/03/01

2

USB_CLK_12M <14>

R402 127_0402_1%

1 2

USB20_P1
USB20_N1

USB20_N1 USB20_N1_2
USB20_P1 USB20_P1_2

C560 0.01U_0402_16V7K

1 2

C559 0.01U_0402_16V7K

1 2

SATA_DTX_C_IRX_P0 <24>
SATA_DTX_C_IRX_N0 <24>

1 2

R219 0_0402_5%

R207 1K_0402_5%

1 2

R209 1K_0402_5%

1 2

+5VS+3VS

12

R205

@

10K_0402_5%

A2Y

R577 0_0402_5%

1 2

1 2

R211 1K_0402_5%

1 2

R212 1K_0402_5%

1 4
2 3

RP19
0_0404_4P2R_5%

15W@

1 4
2 3

RP2
0_0404_4P2R_5%

14W@

SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0

C663 0.1U_0402_16V4Z@
R576 10K_0402_5%@

1

5

U39

P

OE#

G

TC7SET125FUF_SC70@

3

USB20_P1_1
USB20_N1_1

1 2
1 2

4

SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1

SATA_RXn/p need tie to ground when SATA port no used

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SIS968(3/5)-USB_SATA

JFWXX M/B LA-3961P Schematic

Thursday, September 06, 2007

USB20_P1_1 <33>
USB20_N1_1 <33>

USB20_N1_2 <33>
USB20_P1_2 <33>

SATA_ITX_C_DRX_P0 <24>
SATA_ITX_C_DRX_N0 <24>

SATA_LED# <32>

21 49

1

of

0.1

5

D D

+1.05VS

22mA

+3VS

29mA

C C

+3VALW

4mA

+3VALW

8mA

+1.8VS

153mA

B B

U11D

AA21

VTT

AB22

VTT

V16

PVDD

V15

PVDD

V14

PVDD

T8

PVDD

N8

PVDD

L9

PVDD

W17

OVDD

W16

OVDD

W15

OVDD

W14

OVDD

W13

OVDD

W12

OVDD

K8

OVDD

L8

OVDD

M8

OVDD

P8

OVDD

R8

OVDD

U8

OVDD

V8

OVDD

H19

OVDD_AUX

H9

OVDD_AUX

H8

OVDD_AUX

F7

OVDD_AUX

J11

OVDD_AUX

J12

OVDD_AUX

H10

GMIIVDD_AUX

H11

GMIIVDD_AUX

H12

GMIIVDD_AUX

H13

GMIIVDD_AUX

J13

GMIIVDD_AUX

K18

AVDDPEX

L18

AVDDPEX

L19

AVDDPEX

M18

AVDDPEX

M19

AVDDPEX

N19

AVDDPEX

H21

AVDDPEX

J21

AVDDPEX

K21

AVDDPEX

L21

AVDDPEX

M21

AVDDPEX

N21

AVDDPEX

M22

AVDDPEX

H22

AVDDPEX

SIS968-B0_TEBGA_570P

Power

IVDD_AUX
IVDD_AUX
IVDD_AUX
IVDD_AUX
IVDD_AUX
IVDD_AUX

AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA

IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD

VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ

4

T18
J14
U9
T9
R9
P9
N9
M9
K9
V10
V11
V12
V13
V17
R17
R18

N18
W19
V19
V18
U18
W18
P18
Y24
V24
T24
R24
AA25
W26
U26

J9
J8
J10
J16
J17
J18

W11
W10
W9
W8
V9
AF10
AE10
AD11
AD10
AC11
AC10
AB11
AB10
AB9
AB8

413mA

413mA

19mA

+1.8VS

190mA

+1.8VS

+1.8VS

+1.8VALW

Put under 968 solder side

C537

0.1U_0402_16V4Z

3

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.01U_0402_16V7K

0.01U_0402_16V7K

+1.8VS

0.1U_0402_16V4Z

1

C530

2

+3VS

1

C502

2

+1.8VS

1

C514

2

+1.8VS

1

C557

2

+1.8VS

1

C504

2

1

C520

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C507

2

0.1U_0402_16V4Z

1

C525

2

0.1U_0402_16V4Z

C557,C555,C217,C228,C551,C554
close to U30 Pin AVDD_SATA

1

C555

2

0.1U_0402_16V4Z

C504,C509,C494,C495,C513,C503
close to U30 Pin AVDDPEX

1

C509

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C517

2

1

C522

2

0.1U_0402_16V4Z

1

C526

2

1U_0603_10V4Z

1

C217

2

1U_0603_10V4Z

1

C494

2

1

C518

2

0.1U_0402_16V4Z

1

C534

2

0.1U_0402_16V4Z

1

C527

2

0.1U_0402_16V4Z

1

C228

2

10U_0805_10V4Z

1

C495

2

10U_0805_10V4Z

1

0.1U_0402_16V4Z

2

2

1U_0603_10V4Z

1

C542

2

1U_0603_10V4Z

1

C539

2

1U_0603_10V4Z

0.1U_0402_16V4Z

+3VS

1

C531

2

10U_0805_10V4Z

1

2

1

2

+1.8VALW

C501

C519

C543

10U_0805_10V4Z

C524

1

C497

0.1U_0402_16V4Z

2

+3VALW

1

2

1

2

C538

1U_0603_10V4Z

C540

0.1U_0402_16V4Z

1

C556

2

10U_0805_10V4Z

1

C523

2

10U_0805_10V4Z

1

2

1U_0603_10V4Z

1

C500

C148

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C532

C516

2

0.1U_0402_16V4Z

1

2

1

2

C488
1U_0603_10V4Z

1

C510

2

1U_0603_10V4Z

1

2

+1.05VS

1

C547

0.1U_0402_16V4Z

2

1

2

+1.05VS

1

2

1

C546

0.1U_0402_16V4Z

1

C561
1U_0603_10V4Z

2

+3VALW

1

C493

0.1U_0402_16V4Z

2

A A

1

C499

0.1U_0402_16V4Z

2

+3VALW

1

C482

0.1U_0402_16V4Z

2

1

C486

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01

3

+1.8VALW

1

C492

0.1U_0402_16V4Z

2

Compal Secret Data

Deciphered Date

1

C498

0.1U_0402_16V4Z

2

2006/03/01

+1.8VS +1.8VS

1

C513

0.1U_0402_16V4Z

2

2

1

C503

0.01U_0402_16V7K

2

Title

Size Document Number Rev

Custom

JFWXX M/B LA-3961P Schematic

Thursday, September 06, 2007

Date: Sheet of

1

C551

0.1U_0402_16V4Z

2

1

C554

0.01U_0402_16V7K

2

Compal Electronics, Inc.

SIS968(4/5)-POWER

22 49

1

0.1

5

D D

C C

B B

4

U11E

K10

VSS

K11

VSS

K12

VSS

L10

VSS

L11

VSS

L12

VSS

L14

VSS

L15

VSS

L16

VSS

M10

VSS

M11

VSS

M12

VSS

M13

VSS

Gound

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX
AVSSPEX

AD26
AC25

M14
M15
N10

B10
B12
D11
D13
U15
U14
U13
U12
U11
U10
T14
T13
T12
T11
T10
R14
R13
R12
R11
R10
P14
P13
P12
P11
P10
N14
N13
N12
N11

P24
P23
N22
N26
N25
M24
M23

K22
G22

K24
K23

H24
H23
G26
G25
F24
F23
E26
E25
P16
M17
N17
P17
M16
N16
N15

L22
J22
L26

L25

J26
J25

3

VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ
VSSZ

USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS
USBVSS

AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA

U17
U16
T16
R16
R15
T17
P15
T15
Y21
V21
T21
R22
W23
U23

D14
E15
A15
B15
C16
D16
A17
B17
E17
C18
D18
A19
B19
E19
C20
D20
A21
B21
D23
D24
C25
C26
K13
K14
K15
K16
K17
L13
L17

AB6
AB7
AB12
AB13
AB14
AB15
AC2
AC3
AC4
AC5
AC7
AC12
AC14
AC15
AD2
AD3
AD4
AD5
AD7
AD12
AD14
AE1
AE2
AE3
AE4
AE6
AE7
AE9
AE11
AE13
AE14
AF2
AF3
AF4
AF6
AF9
AF11
AF13

2

1

SIS968-B0_TEBGA_570P

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01

3

Compal Secret Data

Deciphered Date

2006/03/01

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SIS968(5/5)-GND

JFWXX M/B LA-3961P Schematic

Thursday, September 06, 2007

1

23 49

of

0.1

A

B

C

D

E

F

G

H

14W ODD Conn.

Placea caps. near ODD CONN.

+5VS

14W@

0.1U_0402_16V4Z

1

1 1

2 2

2

1000P_0402_50V7K

14W@

IDE_CSEL
Grounding for Master (When use SATA HDD)
Open or Hi gh fo r Slave r (N ormal)

C601

1

C595

2

1U_0603_10V4Z

14W@

IDE_DIOW#<19>

IDE_DIORDY<19>

IDE_IRQ<19>

IDE_DCS1#<19>

+5VS +5VS

R240 475_0402_1%

1

C599

2

1 2

14W@

10U_0805_10V4Z

1

C598

2

IDE_RST#
IDE_DD7
IDE_DD6
IDE_DD5
IDE_DD4

IDE_DD2
IDE_DD1
IDE_DD0

IDE_DIOW#
IDE_DIORDY
IDE_IRQ
IDE_DA1
IDE_DA0
IDE_DCS1#
IDE_LED#

IDE_CSEL

1

C594

2

10U_0805_10V4Z

14W@

+5VS

IDE_DD[0..15]<19>

IDE_DA[0..2]<19>

JP27

2

112

4

334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950

OCTEK_CDR-50DY1G

14W@

(NEW)

R487 100K_0402_5%

IDE_DD8

6

IDE_DD9

8

IDE_DD10

10

IDE_DD11

12

IDE_DD12

14

IDE_DD13IDE_DD3

16

IDE_DD14

18

IDE_DD15

20

IDE_DDREQ

22

IDE_DIOR#

24
26

IDE_DDACK#

28
30

IDE_PDIAG#

32

IDE_DA2

34

IDE_DCS3#

36
38
40
42
44
46
48
50

IDE_LED#

12

IDE_DD[0..15]
IDE_DA[0..2]

1 2

IDE_DDREQ <19>
IDE_DIOR# <19>

IDE_DDACK# <19>

R491

100K_0402_5%

IDE_DCS3# <19>

+5VS

IDE_HRESET#<20>

PCI_RST#<19,26,28,29,30,31,33>

IDE_HRESET#
PCI_RST#

SATA HDD Conn.

+5VS +3VS

0.1U_0402_16V4Z

1

C366

2

1000P_0402_50V7K

1

C365

2

1U_0603_10V4Z

1

C367

2

10U_0805_10V4Z

1

C353

2

1

C354

2

10U_0805_10V4Z

+3VS

C628 0.1U_0402_16V4Z

1 2

5

U36

2

P

B

4

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

1

C68

0.1U_0402_16V4Z

2

@

IDE_RST#

15W ODD Conn.

IDE_RST#
IDE_DD7

3 3

4 4

IDE_DD6
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
IDE_DD1
IDE_DD0
IDE_DIOW#
IDE_DIORDY
IDE_IRQ
IDE_DA1
IDE_DA0
IDE_DCS1#
IDE_LED#
IDE_CSEL R_IDE_CSEL

IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DDREQ
IDE_DIOR#
IDE_DDACK#
IDE_PDIAG#
IDE_DA2
IDE_DCS3#

+5VS_ODD +5VS +5VS_ODD

1

2

1000P_0402_50V7K

15W@

15W@

0.1U_0402_16V4Z

C310

C311

A

R265 0_0402_5%15W@

1 2

R264 0_0402_5%15W@

1 2

R263 0_0402_5%15W@

1 2

R262 0_0402_5%15W@

1 2

R261 0_0402_5%15W@

1 2

R260 0_0402_5%15W@

1 2

R259 0_0402_5%15W@

1 2

R258 0_0402_5%15W@

1 2

R257 0_0402_5%15W@

1 2

R256 0_0402_5%15W@

1 2

R254 0_0402_5%15W@

1 2

R255 0_0402_5%15W@

1 2

R252 0_0402_5%15W@

1 2

R253 0_0402_5%15W@

1 2

R250 0_0402_5%15W@

1 2

R486 0_0402_5%15W@

1 2

R246 0_0402_5%15W@

1 2

R516 0_0402_5%15W@

1 2

R513 0_0402_5%15W@

1 2

R512 0_0402_5%15W@

1 2

R509 0_0402_5%15W@

1 2

R508 0_0402_5%15W@

1 2

R505 0_0402_5%15W@

1 2

R504 0_0402_5%15W@

1 2

R500 0_0402_5%15W@

1 2

R499 0_0402_5%15W@

1 2

R497 0_0402_5%15W@

1 2

R493 0_0402_5%15W@

1 2

R490 0_0402_5%15W@

1 2

R251 0_0402_5%15W@

1 2

R248 0_0402_5%15W@

1 2

15W@

10U_0805_10V4Z

1

1

C309

2

2

1U_0603_10V4Z

15W@

1

C312

2

R_IDE_RST#
R_IDE_DD7
R_IDE_DD6
R_IDE_DD5
R_IDE_DD4
R_IDE_DD3
R_IDE_DD2
R_IDE_DD1
R_IDE_DD0
R_IDE_DIOW#
R_IDE_DIORDY
R_IDE_IRQ
R_IDE_DA1
R_IDE_DA0
R_IDE_DCS1#
R_IDE_LED#

R_IDE_DD8IDE_DD8
R_IDE_DD9
R_IDE_DD10
R_IDE_DD11
R_IDE_DD12
R_IDE_DD13
R_IDE_DD14
R_IDE_DD15
R_IDE_DDREQ
R_IDE_DIOR#
R_IDE_DDACK#
R_IDE_PDIAG#
R_IDE_DA2
R_IDE_DCS3#

1

C313

2

10U_0805_10V4Z

15W@

B

JP41

2

112

4

R_IDE_RST#
R_IDE_DD7
R_IDE_DD6
R_IDE_DD5
R_IDE_DD4
R_IDE_DD3
R_IDE_DD2
R_IDE_DD1
R_IDE_DD0

R_IDE_DIOW#
R_IDE_DIORDY
R_IDE_IRQ
R_IDE_DA1
R_IDE_DA0
R_IDE_DCS1#

+5VS_ODD +5VS_ODD

R_IDE_LED#

R_IDE_CSEL

1 2

R247 0_1206_5%15W@

1 2

R249 0_1206_5%15W@

334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950

OCTEK_CDR-50DY1G

15W@

12/4 Change J7 to 2x0 Ohm 1/4w resistors

C

R_IDE_DD8

6

R_IDE_DD9

8

R_IDE_DD10

10

R_IDE_DD11

12

R_IDE_DD12

14

R_IDE_DD13

16

R_IDE_DD14

18

R_IDE_DD15

20

R_IDE_DDREQ

22

R_IDE_DIOR#

24

26

R_IDE_DDACK#

28

30

R_IDE_PDIAG#

32

R_IDE_DA2

34

R_IDE_DCS3#

36

38

40

42

44

46

48

50

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

SATA_ITX_C_DRX_P0<21>

SATA_DTX_C_IRX_N0<21>

SATA_DTX_C_IRX_P0<21>

2006/08/18 2007/8/18

E

Compal Secret Data

Deciphered Date

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0

SATA_ITX_C_DRX_N0<21>

C400 0.01U_0402_16V7K
C395 0.01U_0402_16V7K

F

1 2
1 2

JP28

1

SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0

SATA_DTX_IRX_N0
SATA_DTX_IRX_P0

+3VS

+5VS

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

HDD & ODD Connector
JFWXX M/B LA-3961P Schematic

G

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

22

V12

SUYIN_127043FB022S338ZR_RV

ME@

(NEW)

Change Library

24 49Thursday, September 06, 2007

H

of

0.1

5

+3VS

C496 0.1U_0402_16V4Z

5

U28

R401 33_0402_5%

D D

SB_DPRSLPVR<20> PM_DPRSLPVR_D <48> SB_DPRSLPVR<20>

1 2

0.01U_0402_16V7K

C464

1

@

2

4

Vcc

A2Y

1

NC

G

NL17SZ17DFT2G_SOT353-5

3

4

1 2

R414 33_0402_5%

1 2

Connecte to CPU

3

R391 33_0402_5%

1 2

C460

0.01U_0402_16V7K

@

2

+3VS

C448 0.1U_0402_16V4Z

1 2

1

5

U24

P

NC

A2Y

G

1

2

NL17SZ14DFT2G_SOT353-5

3

R377 33_0402_5%

4

1 2

1

DPRSTP_N_INV

Use SA00001N400 FootPrint

R553 0_0402_5%@

1 2

+3VS

8/1 Rotate

+1.05VS

8/1 Rotate

R170

1.05K_0402_1%

1.05K_0402_1%

R171

R172

@

200K_0402_5%

12

R157

300_0402_5%

12

R165

300_0402_5%

7/20 Reserved

C C

DPRSTP_N_INV

H_DPSLP_N_LS

B B

CPUSTP_N_OLD<20>

U40

1

A1

2

GND

3

A2

NC7WZ07P6X_NL_SC70-6

H_DPRSTP#

6

Y1

5

VCC

Y2

R372 499_0402_1%

1 2

R380 33_0402_5%

100P_0402_50V8J

+3VALW

H_DPSLP#

4

C450 0.1U_0402_16V4Z

C447

1 2

1

2

1

C451

@

0.01U_0402_16V7K

2

+3VS +3VS

5

Vcc

A2Y

NC

G

U23

NL17SZ17DFT2G_SOT353-5

3

DPRSTP_N_INV

C458 0.1U_0402_16V4Z

1 2

Use SA00001N400 FootPrint

4
1

5

4

Vcc

A2Y

1

NC

G

U26

NL17SZ17DFT2G_SOT353-5

3

Use SA00001N400 FootPrint

H_DPSLP_N_LS

1 2

R371 33_0402_5%

1 2

R379 33_0402_5%

C173

0.01U_0402_16V7K

1

@

2

U10

7

VREF2

6

SCL2

5

SDA2

+3VS

5

2

B

1

A

3

+3VS

5

2

B

1

A

3

8

EN

2

VREF1

3

SCL1

4

SDA1

GND

PCA9306DCUR_VSSOP8

1

@

1 2

C446 0.1U_0402_16V4Z

U25

P

G

U22

Vcc
G

NC7SZ32P5X_NL_SC70-5

H_DPSLP_N_LS

4

Y

NC7SZ08P5X_NL_SC70-5

1 2

C452 0.1U_0402_16V4Z

CPUSTP#

4

Y

H_DPRSTP# <5,48>

H_DPSLP# <5>

CPUSTP# <14>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01

3

Compal Secret Data

Deciphered Date

2006/03/01

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

<Title>

<Doc> <RevCode>

Custom

Thursday, September 06, 2007

1

25 49

of

5

1

2

833@

1 2

833@

1 2

125
126
127

124
123

121
119

117

115
116

111
107
103
102

C563

270P_0402_50V7K

R456

56.2_0603_1%

833@

R449

56.2_0603_1%

1
2
3
5
6

9
11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53

7
21
35
45

33
23
25
24
29
26

8
30
31

71
70

69
66

99

97

Z3008

U29

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3#
C/BE2#
C/BE1#
C/BE0#

PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#

REQ#
GNT#

PCICLK
PCIRST#
GBRST#
CLKRUN#
PME#

INTA#
INTB#

HWSPND#
TEST

AGND
AGND
AGND
AGND
AGND

NC

R5C832_TQFP128~D

833@

12

R459

5.1K_0603_1%

833@

R458

1 2

56.2_0603_1%

833@

2

R452

1 2

1

56.2_0603_1%

833@

R5C833

PCI_AD[0..31]<19>

D D

PCI_CBE#3<19>
PCI_CBE#2<19>
PCI_CBE#1<19>
PCI_CBE#0<19>

PCI_PAR<19>
PCI_FRAME#<19>
PCI_TRDY#<19>
PCI_IRDY#<19>

+3VS

PCI_STOP#<19>
PCI_DEVSEL#<19>

PCI_PERR#<19>
PCI_SERR#<19>

PCI_REQ#0<19>

PCI_GNT#0<19>

CLK_PCI_1394<14>

PCI_RST#<19,24,28,29,30,31,33>

R447 10K_0402_5%@

1 2

R445 0_0402_5%833@

1 2

R5_PME#<31>
PCI_PIRQC#<19>
PCI_PIRQD#<19>

833@

1 2

R463 10K_0402_5%

@

1 2

R465 0_0402_5%

PCI_AD22 CBS_IDSEL

C C

Layout Note: Shield GND for
CLK_PCI_1394

833@

1 2

R423 100_0402_5%

PM_CLKRUN#<20,31>

SUSP#<30,31,40,43,46,47>

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#

PCI_PERR#
PCI_SERR#

PCI_REQ#0
PCI_GNT#0

CBS_GRST#

R5_PME#

12/1 Modified

B B

Layout Not e: Place close to R5C832

CLK_PCI_1394

12

R442
10_0402_5%

@

2

C544

4.7P_0402_50V8C

1

@

A A

+3VS

12

R466
100K_0402_5%

833@

CBS_GRST#

C572
1U_0603_10V4Z

833@

IEEE1394_TPBN0
IEEE1394_TPBP0
IEEE1394_TPAN0
IEEE1394_TPAP0

833@

IEEE1394_TPBIAS0

12/22 Change f r o m X 5 R to Y5V

5

C562

833@

0.01U_0402_16V7K

2

C558

1

4

10

VCC_PCI3V

20

VCC_PCI3V

27

VCC_PCI3V

32

VCC_PCI3V

41

VCC_PCI3V

128

VCC_PCI3V

61

VCC_RIN

16

VCC_ROUT

34

VCC_ROUT

64

VCC_ROUT

114

VCC_ROUT

120

VCC_ROUT

67

VCC_3V

86

VCC_MD3V

AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V

TPBIAS0

MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

UDIO0/SERIRQ#

0.33U_0603_16V4Z

TPAP0

TPAN0

TPBP0

TPBN0

MSEN

XDEN

REXT
VREF

UDIO1
UDIO2
UDIO3
UDIO4
UDIO5

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

FIL0

98
106
110
112

113
109

108
105

104
80

79
78
77
76
75
74
73
88
84
82
81
93
90
91
89
92
87
85
83

58
55

94

XI

95

XO

96
101
100

72
60
56
65
59
57

4
13
22
28
54
62
63
68
118
122

+3V_PHY

IEEE1394_TPBIAS0
IEEE1394_TPAP0

IEEE1394_TPAN0
IEEE1394_TPBP0

IEEE1394_TPBN0
SDCD#_XDCD0#

MSCD#_XDCD1
SDWP#_XDRB#

SDPWR0_MSPW R _XDPW R

SDCMD_MSBS
SDCLK_MSCLK
SDDATA0_MSDATA0
SDDATA1_MSDATA1
SDDATA2_MSDATA2
SDDATA3_MSDATA3

MSEN
XDEN

R5C832XI
R5C832XO

SERIRQ
TP_UDIO1
TP_UDIO2
UDIO3
UDIO4
UDIO5

SDPWR0_MSPW R _XDPW R

L50

@

1

1

4

4

WCM-2012-670T_4P

R454 0_0402_5%833@

1 2

R457 0_0402_5%833@

1 2

R460 0_0402_5%833@

1 2

R462 0_0402_5%833@

1 2

L51

@

1

1

4

4

WCM-2012-670T_4P

For EMI => Cha n g e L 5 0 , L 5 1 t o SM070000I00

4

+3VS

1

1

833@

833@

C529

C533

10U_0805_10V4Z

2

2

0.01U_0402_16V7K

833@

SDCD#_XDCD0# <27>
MSCD#_XDCD1 <27>

SDWP#_XDRB# <27>

SDCMD_MSBS <27>

SDCLK_MSCLK <27>
SDDATA0_MSDATA0 <27>
SDDATA1_MSDATA1 <27>
SDDATA2_MSDATA2 <27>
SDDATA3_MSDATA3 <27>

Layout Note: C268,C270,R125 Place close to R5C832

and Shield GND for FIL0,REXT,VREF

1 2

C570

0.01U_0402_16V7K833@

SERIR Q <20,31,33>

T32PAD
T31PAD

Layout Note: Shield GND for
CBS_CCLK_INTERNAL and CBS_CCLK

+3VS

1

C578

2

2

3

3

2

2

3

3

0.1U_0402_16V4Z

2

833@

IEEE1394TPA+/- and IEEE1394TPB+/­Same Wire Length

Layout Note: Shield GND for
IEEE1394_TPA and TPB

3

2

12/15 Modified 10u X6S to Y5V

+3VS

1

2

833@

C571

0.01U_0402_16V7K

1

2

2

1

+3VS

C575

10U_0805_10V4Z

C568

833@

0.01U_0402_16V7K

833@

1 2

833@

1

2

R461

10K_0603_1%

1

1

833@

833@

C528

C553

0.01U_0402_16V7K

+3VS

C541

2

2

0.01U_0402_16V7K

1 2

BLM21A601SPT_0805

833@

Layout Not e: Place close to R5C832
and Shield GND for SDCLK_MSCLK

C573

1 2

833@

27P_0402_50V8J

C574

1 2

833@

27P_0402_50V8J

833@

1

833@

C569

2

0.47U_0603_16V4Z

0.47U_0603_16V4Z

L20

C210

833@

10U_0805_10V4Z

R5C832XI

X3

833@

24.576MHz_16P_1BG24576CKIA

1 2

R5C832XO

1

2

1

2

C567

0.01U_0402_16V7K

1

1

833@

833@

C566

2

2

0.1U_0402_16V4Z

1

1

833@

833@

833@

C214

C211

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Layout Not e: Place close to R5C832
and Shield GND for SD_CLK

12/1 Modified from 15P to 18P

40mil

833@

C577

1

2

1U_0603_10V4Z

+VCC_3IN1

1

R467

833@

100K_0402_5%

1 2

833@

C579

10U_0805_10V4Z

1

833@

2

C580

2

0.1U_0402_16V4Z

12/22 Change from 10u_1206 to 10u_0805

Swap U38 Pin 1,Pin 3

U38

@

3

CH2

2

Vn

1

CH1

CM1293-04SO_SOT23-6

2006/08/04 2006/10/06

6

CH3

5

Vp

4

CH4

Compal Secret Data

Deciphered Date

2

For EMI => Add U38 (SC300000O00)
Use SC300000D00 FootPrint

U31

3

VIN

4

VIN/CE

2

GND

RT9701-PB_SOT23-5

833@

IEEE1394_R_TPBN0
IEEE1394_R_TPBP0
IEEE1394_R_TPAN0
IEEE1394_R_TPAP0

1

VOUT

5

VOUT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITH OUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

1

833@

C565

C564

10U_0805_10V4Z

2

0.01U_0402_16V7K

+3V_PHY

1

1

833@

C219

C224

2

2

1000P_0402_50V7K

1000P_0402_50V7K

SDDATA1_MSDATA1

SDDATA2_MSDATA2

+5VS+VCC_3IN1

1 2

R470 10K_0402_5%@

SDCD#_XDCD0#

JP25

1
2
3
4

5

TPB-

GND

6

TPB+

GND

7

TPA-

GND

8

TPA+

GND

SUYIN_020115FB004S512ZL

ME@

+3V_PHY

SD,MMC,MS muti-function pin define

MDIO
PIN Name
MDIO00

MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09 SDCCLK
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19

Function set pin define

Pull-up

MSEN
UDIO3
UDIO4
UDIO5

XDEN

Solve MS Duo Adaptor short problem

R471 0_0402_5%

2N7002_SOT23

12

D

S

1 3

833@

R469 0_0402_5%

Q33

G

2

@

2

G

D

1 3

833@

Q34

2N7002_SOT23

2

@

13

D

Q32
2N7002_SOT23

@

S

Title

Size Document Number Rev

Custom

JFWXX M/B LA-3961P Schematic

Date: Sheet

1

SD Card
PIN Name
SDCD#

MMC Card
PIN Name
MMCCD#

SDWP#
SDPWR0

MMCPWR
SDPWR1
SDLED#

SDCCMD

MMCLED#

MMCCMD

MMCCLK
SDCDAT0

MMCDAT
SDCDAT1
SDCDAT2
SDCDAT3

MSEN XDENUDIO3 UDIO4

Pull-upPull-up Enable

R453 10K_0402_5%833@

1 2

R464 10K_0402_5%833@

1 2

R455 10K_0402_5%833@

1 2

R451 100K_0402_5%833@

1 2

R448 10K_0402_5%833@

1 2

SD_MSDATA1

12

S

SD_MSDATA2

G

Pull-low

Function

SD,MS,MMC Card

Compal Electronics, Inc.

R5C833 Cardreader+1394

1

MS Card
PIN Name

MSCD#

MSWR

MSLED#
MSEXTCK
MSBS
MSCCLK
MSCDAT0
MSCDAT1
MSCDAT2
MSCDAT3

+3VS

SD_MSDATA1 <27>

SD_MSDATA2 <27>

26 49Thursday, September 06, 2007

of

0.1

5

4

3

2

1

3 in 1 Card Reader

D D

C C

+VCC_3IN1
SDDATA0_MSDATA0<26>
SD_MSDATA1<26>
SD_MSDATA2<26>
SDDATA3_MSDATA3<26>
SDCLK_MSCLK<26>
SDWP#_XDRB#<26>
SDCMD_MSBS<26>
SDCD#_XDCD0#<26>

SDDATA1_MSDATA1<26>

MSCD#_XDCD1<26>

SDDATA2_MSDATA2<26>

SDDATA0_MSDATA0
SD_MSDATA1
SD_MSDATA2
SDDATA3_MSDATA3

SDWP#_XDRB#
SDCMD_MSBS
SDCD#_XDCD0#

SDDATA1_MSDATA1

MSCD#_XDCD1
SDDATA0_MSDATA0
SDCMD_MSBS
SDDATA3_MSDATA3
SDDATA2_MSDATA2

R476 22_0402_5%

1 2

R477 22_0402_5%

1 2

SDCLKSDCLK_MSCLK

MSCLKSDCLK_MSCLK

JP24

6

VDD_SD

9

DAT0_SD

10

DAT1_SD

2

DAT2_SD

3

CD/DAT3_SD

7

CLK_SD

11

WP_SD

4

CMD_SD

1

CD_SD

5

VSS_SD

8

VSS_SD

19

VCC_MS

13

VCC_MS

14

SCLK_MS

16

INS_MS

18

SDIO_MS

20

BS_MS

15

RESERVED_MS

17

RESERVED_MS

21

VSS_MS

12

VSS_MS

22

GND

23

GND

PROCO_MDR019-C0-1202

ME@

B B

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/08/04 2006/10/06

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

3 IN 1 CardReader Conn.

JFWXX M/B LA-3961P Schematic

27 49Thursday, September 06, 2007

1

of

0.1

5

4

3

2

1

+3VALW

T1

TPRX+
TPRX-

PWFBOUT

R33 0_0603_5%

1

C56

0.1U_0402_16V4Z

R30 0_0603_5%

2

1

C50

0.1U_0402_16V4Z

2

Other CG use 1206

PWFBOUT

1

C95

10U_0805_10V4Z

2

Place C464, C465, L48 close to PWFBOUT and place C466 close to PWFBIN.

LED2

D7 RLS4148_LL34-2

LED3

D8 RLS4148_LL34-2

1

12

C31 680P_0402_50V7K

R12 150_0402_1%

1 2

8/1 Change R12 from 300ohm to 150ohm

For EMI => Change C31,C38 from SE071680J80
(68pF) to SE074681K80 (680pF)

L61

1 2
12

R34 75_0402_5%

1 2

R29 75_0402_5%

1 2

D33

1

PSOT24C_SOT23

@

12

12

D32

PSOT24C_SOT23

@

R572 75_0402_5%
R573 75_0402_5%

R574 75_0402_5%
R575 75_0402_5%

+3V_LAN

1

2

RTSET
ISOLATE

RPTR
SPEED
DUPLEX
ANE
LDPS
RESETB

+3V_LAN

FBM-L11-160808-601LMT_0603

1

1

C149

C147

0.1U_0402_16V4Z

2

2

+3V_LAN

1

C122

0.1U_0402_16V4Z

2

+3V_LAN_AVDD

PWFBOUT
PWFBIN

TPRX­TPRX+

TPTX­TPTX+

R351 2K_0402_1%

1 2

R361 4.7K_0402_5%

1 2

R356 4.7K_0402_5%

1 2

R353 4.7K_0402_5%

1 2

R123 4.7K_0402_5%

1 2

R116 4.7K_0402_5%

1 2

R357 4.7K_0402_5%

1 2

R363 0_0402_5%

1 2

R359 0_0402_5%@

1 2

L16

1 2

LED0 LINKLED#

Other CG use 1210

+3V_LAN

D D

R350 1.5K_0402_1%

1 2

R366 4.7K_0402_5%@

1 2

R152 4.7K_0402_5%@

1 2

R368 4.7K_0402_5%

1 2

R367 4.7K_0402_5%

1 2

R153 4.7K_0402_5%

1 2

R154 4.7K_0402_5%

1 2

R364 4.7K_0402_5%

1 2

R97 4.7K_0402_5%

1 2

R354 4.7K_0402_5%

1 2

C C

MDC<20>
MDIO<20>
TXD0<20>
TXD1<20>
TXD2<20>
TXD3<20>
TXEN<20>

TXCLK<20>
RXDV<20>
RXD0<20>
RXD1<20>
RXD2<20>
RXD3<20>
RXCLK<20>
COL<20>
CRS<20>
RXER<20>

+3V_LAN

B B

1 2

25MHZ_20PF_6X25000017

C115
33P_0402_50V8J

MDC
MDIO
TXD0
TXD1
TXD2
TXD3
TXEN

R156 33_0402_5%

1 2

R109 33_0402_5%

1 2

R117 33_0402_5%

1 2

R122 33_0402_5%

1 2

R129 33_0402_5%

1 2

R135 33_0402_5%

1 2

R138 33_0402_5%

1 2

R569 33_0402_5%

1 2

R570 33_0402_5%

1 2

R571 33_0402_5%

1 2

R360 4.7K_0402_5%

1 2

Y3

C117
33P_0402_50V8J

MDIO

ISOLATE

COL
LED0
LED1
LED2
LED3
LED4
RXER
CRS

TXC
RXD_V
RXD_0
RXD_1
RXD_2
RXD_3
RXC
COL_R
CRS_R
RXER_R

MII_SNIB

LAN_XTAL_IN
LAN_XTAL_OUT

LED0
LED1
LED2
LED3
LED4

R149
0_0603_5%

1

C150
10U_0805_10V4Z

2

U8

25

MDC

26

MDIO

6

TXD0

5

TXD1

4

TXD2

3

TXD3

2

TXEN

7

TXC

22

RXDV

21

RXD0

20

RXD1

19

RXD2

18

RXD3

16

RXC

1

COL

23

CRS

24

RXER/FXEN

44

MII/SNIB

46

X1

47

X2

9

PHYAD0/LED0

10

PHYAD1/LED1

12

PHYAD2/LED2

13

PHYAD3/LED3

15

PHYAD4/LED4

RTL8201CL-VD-LF

+3V_LAN

MII I/F

CLK

Other CG use

4.7U_0805_10V4Z

Place L47, C460, C462, C463 as close to each power pin
as possible.

DVDD33
DVDD33

AVDD33

PWFBOUT

PWFBIN

PWRGND

TPRX-

TPRX+

TPTX-

TPTX+

RTSET

ISOLATE

RPTR

SPEED

DUPLEX

LDPS

RESETB

Network I/F

DGND
DGND
DGND

AGND
AGND

ANE

C121

14
48

36

32
8

30
31

33
34

28
43

40
39
38
37
41
42

27

NC

11
17
45
29
35

0.1U_0402_16V4Z

PHY/LED

7/30 modified from 27P to 33P

TPRX-

R23 49.9_0402_1%

TPRX+

TPTX-

A A

TPTX+

1 2

R26 49.9_0402_1%

1 2

R36 49.9_0402_1%

1 2

R41 49.9_0402_1%

1 2

C41

1 2

C60

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3V_LAN_AVDD

1

C102

0.1U_0402_16V4Z

2

+3V_LAN

12

R362

4.7K_0402_5%

1

C435

0.1U_0402_16V4Z

2

+3V_LAN

PCI_RST# <19,24,26,29,30,31,33>

8/30 Add L61 FBMA-L10-160808-800LMT_0603 for EMI

R18 300_0402_5%

1 2

C38 680P_0402_50V7K

FBMA-L10-160808-800LMT_0603

RXCT
TXCT

RCT

TCT
TPTX+
TPTX-

7/20 Swap p in 1,2 to 7,8 and 16,15 to 10,9

L15

FBM-L11-160808-601LMT_0603

1

C101

0.1U_0402_16V4Z

2

8/27 Change D7,D8 footprint from RLS4148_LL34-2 to LL34

8/1 Change D7,D8 from SC1B751V010 to SC11N414880

2
3

1 2
1 2

1 2
1 2

2

+3V_LAN

3

1

RD+

2

RD-

3

CT

4

NC

5

NC

6

CT

7

TD+
TD-8TX-

350uH_NS0013LF

12

12
11

RX-

RX+
TX-

TX+

10

C42

1 2

1000P_1206_2KV7K

C26

0.1U_0402_16V4Z

RX+

RX-

CT
NC
NC

CT

TX+

PWFBIN

1

C153

0.1U_0402_16V4Z

2

Lan Conn.

JP23

Amber LED+
Amber LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+
Green LED-

9

Green LED+

TYCO_3-440470-4

<BOM Structu re>

1

2

RX+

16

RX-

15

RXCT

14
13
12

TXCT

11

TX+

10

TX-

9

SHLD2
SHLD1

SHLD2
SHLD1

1

C27

4.7U_0805_10V4Z

2

ACTIVITY LED

16
15

14
13

LINKLED

LANGND

LED0 LED1 LED2 LED3 LED4
Link Dupx 10Act 100Act COL

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

LAN RTL8201CL

JFWXX M/B LA-3961P Schematic

28 49Thursday, Sept em be r 06, 2007

1

0.1

of

A

1 1

2 2

B

C

D

E

Mini-Express Card for WLAN

8/31Add R593 connect net WLAN_ACTIVE to JP22 pin3

SB_PCIE_WAKE#<7,21,30>

C206

WLAN_ACTIVE
BT_ACTIVE

WLAN_CLKREQ#<14>

PCIE_CLK_WLAN#<14>

PCIE_CLK_WLAN<14>

PCIE_PTX_C_IRX_N0<20>
PCIE_PTX_C_IRX_P0<20>

PCIE_ITX_C_PRX_N0<20>

PCIE_ITX_C_PRX_P0<20>

1

0.1U_0402_16V4Z

2

WLAN_ACTIVE<33>
BT_ACTIVE<33>

3 3

4 4

0.01U_0402_16V7K

8/31Add R594 connect net BT_ACTIVE to JP22 pin5

SB_PCIE_WAKE#

R593 0_0402_5%

1 2

R594 0_0402_5%

1 2

WLAN_CLKREQ#
CLK_PCIE_WLAN#

CLK_PCIE_WLAN

+3VS +1.5VS

1

C205

4.7U_0805_10V4Z

2

A

C199

1

2

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

0.01U_0402_16V7K

***

JP22

1

1

3

3

5

5

7

7

9

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

GND1

GND2

FOX_AS0B226-S56N-7F

ME@

1

C241

0.1U_0402_16V4Z

2

2

2

4

4

6

6

8

8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

B

C207

MINI_RF_OFF#
PCI_RST#

DCLK
DDATA

USB20_N3_R
USB20_P3_R

WLAN_LED#

1

4.7U_0805_10V4Z

2

R583 0_0402_5%
R584 0_0402_5%

R222

1 2

100K_0402_5%

C203

PCI_RST# <19,24,26,28,30,31,33>
+3VALW

DCLK <14,30>
DDATA <14,30>

1 2
1 2

WLAN_LED# <34,37>

+5VS

1

2

+1.5VS +3VS

MINI_VCC

L21

1 2

KC FBM-L11-201209-221LMAT_0805

12/13 Add

USB20_N3 <21>
USB20_P3 <21>

+3VS

12

R208

+3VALW

1

C208

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

10K_0402_5%

MINI_RF_OFF#

Q11

2N7002_SOT23

2006/08/05 2007/08/05

R529

1 2

0_0402_5%

13

D

2

G

S

Compal Secret Data

@

RF_ON#

Deciphered Date

RF_ON# <31>

Kill SWITCH

12/28 modified to @

D18
DAN217_SC59

@

12/19 Chan ge SW2 to correct symbol (by EMI)

D

+3VALW

2

3

1

5

3

11223

G14G2

SW1
1BS003-1210L_3P

14W@

Title

Size Document Number Rev

JFWXX M/B LA-3961P Schematic

Date: Sheet

+3VALW

R268
100K_0402_5%

14W@

1 2

KILL_SW#

KILL_SW# <31,34>

Compal Electronics, Inc.

Mini-Card/Kill SW

29 49Thursday, September 06, 2007

E

of

0.1

A

B

C

D

E

New Card Socket (Left/TOP)

New Card Power Switch

U32

+3VS

NEWCARD@

NEWCARD@

1

C584
10U_0805_10V4Z

2

@

+3VALW

+1.5VS

CP_USB#
CP_PE#
SUSP#
SYSON
PCI_RST#

1 1

R475 100K_0402_5%

+3VALW

+3VS +1.5VS+3VALW

1

C592
10U_0805_10V4Z

2

@

2 2

1 2

R474 100K_0402_5%

1 2

SUSP#<26,31,40,43,46,47>
SYSON<31,40>

PCI_RST#<19,24,26,28,29,31,33>

5
6

21

18
19

14
15

4
2

1

C585
10U_0805_10V4Z

2

@

3.3Vin1

3.3Vin2

3.3Vaux_in

1.5Vin1

1.5Vin2

CPUSB#
CPPE#
STBY#
SHDN#3RCLKEN
SYSRST#

11

GND

3.3Vout1

3.3Vout2

1.5Vout1

1.5Vout2

PERST#

NC11NC210NC312NC413NC5

24

60mils

7
8

40mil

20

Aux_out

40mil

16
17

23

OC#

22
9

TPS2231PWPR_PWP24

NEWCARD@

Update Footprint

RCLKEN1
PERST1#

+3VS_CARD1

+3VALW_CARD1

+1.5VS_CARD1

+3VALW_CARD1 +3VS_CARD1 +1.5VS_CARD1

C588

10U_0805_10V4Z

NEWCARD@

10K_0402_5%

NEWCARD@

RCLKEN1

R479

2

G

1

2

+3VS

0.1U_0402_16V4Z

12

13

D

S

C589

NEWCARD@

10K_0402_5%

NEWCARD@

EXP_CLKREQ1#

Q35
2N7002_SOT23

NEWCARD@

1

10U_0805_10V4Z

2

NEWCARD@

+3VS +3VS

12

R478

1

C591

2

5

U33

2

B

Vcc

1

A

G

NC7SZ32P5X_NL_SC70-5

3

NEWCARD@

Imax = 1.35A Imax = 0.75AImax = 0.275A

C590

0.1U_0402_16V4Z

NEWCARD@

1

C593

0.1U_0402_16V4Z

2

NEWCARD@

4

Y

Update Footprint

1

10U_0805_10V4Z

2

1

C586

2

NEWCARD@

EXP_CLKREQ# <14>

C587

0.1U_0402_16V4Z

NEWCARD@

USB20_N2<21>
USB20_P2<21>

1

2

+1.5VS_CARD1

SB_PCIE_WAKE#<7,21,29>

+3VALW_CARD1

+3VS_CARD1

PCIE_CLK_EXP#<14>
PCIE_CLK_EXP<14>

PCIE_PTX_C_IRX_N1<20>
PCIE_PTX_C_IRX_P1<20>

PCIE_ITX_C_PRX_N1<20>
PCIE_ITX_C_PRX_P1<20>

DCLK<14,29>

DDATA<14,29>

CP_PE#<20>

CP_USB#

PERST1#

EXP_CLKREQ1#
CP_PE#

12/7 Let pi n 28 dummy by EMI request
12/13 Let pin 27 dummy by la yo u t request
12/27 change JP 15 footprint to FOX_1CX41201_26P_LT-S
04/17 Symbol Add Pi n 29,30

JP15

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

29

GND

30

GND

FOX_1CX41201_26P_LT-S

NEWCARD@

(NEW)

USB CONN. 1

+USB_VCCB

7/24 EMI added 7/24 EMI added

2200P_0402_25V7K

3 3

USB20_P0<21>

USB20_P0

+USB_VCCB

1

+

C667

C449

@

150U_D_6.3VM

2

R532 0_0402_5%

1 2

R533 0_0402_5%

1 2

L56

1

1

4

4

WCM-2012-670T_4P

@

W=80mils

1

C445
470P_0402_50V7K

2

2

2

3

3

USB20_R_N0
USB20_R_P0

JP16

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020173MR004G565ZR

ME@

SUYIN_020173MR004G533ZR_4P

USB20_N6<21>
USB20_P6<21>USB20_N0<21>

2200P_0402_25V7K

USB20_N6
USB20_P6

C668

USB CONN. 2

+USB_VCCB

+USB_VCCB

1

+

C505
150U_D_6.3VM

2

R534 0_0402_5%

1 2

R535 0_0402_5%

1 2

L57

@

1

1

4

4

WCM-2012-670T_4P

W=80mils

1

C508
470P_0402_50V7K

2

2

2

3

3

USB20_R_N6
USB20_R_P6USB20_N0

JP17

1

VCC

2

D-

3

D+

4

GND

5

GND1

6

GND2

7

GND3

8

GND4

SUYIN_020173MR004G565ZR

ME@

SUYIN_020173MR004G533ZR_4P

4.7U_0805_10V4Z

USB1_ON#<31>

C462

+5VALW

1

2

U27

1
2
3
4

G528_SO8

GND
IN
IN
EN#

+USB_VCCB

8

OUT

7

OUT

6

OUT

5

FLG

7/24 EMI added

R589

1 2

0_0402_5%

+3VALW

R411
10K_0402_5%

1 2

C487
2200P_0402_25V7K

USB_OC#06 <21>

For EMI => Add R532,R533,R534,R535 (SD028000080) ,L56,L57 (SM070000I00)

7/30 change L56,57 to SM070000K00 by EMI request

D27

1

2

PRTR5V0U2X_SOT143@

GND

I/O

VCC

4

3

I/O

+USB_VCCB

USB20_R_P6 USB20_R_N6USB20_R_P0 USB20_R_N0

D28

1

2

4

VCC

GND

3

I/O

I/O

PRTR5V0U2X_SOT143@

+USB_VCCB

For EMI => Change D27,D28 from SC300000100 to SC300000P00

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

NewCard & USB C onnector

JFWXX M/B LA-3961P Schematic

30 49Thursday, September 06, 2007

E

0.1

of

5

L29 FBM-11-160808-601-T_0603

+3VALW +EC_AVCC

D D

CLK_PCI_EC<14>

C C

+5VALW

1 2

0.1U_0402_16V4Z

1 2

L27 FBM-11-160808-601-T_0603

KB_RST#<20>

+3VALW

+3VALW

R5_PME#<26>

PCI_PME#<20>

@

1 2

R317 4.7K_0402_5%

@

1 2

R310 4.7K_0402_5%

2

C355

1

KB_RST#

C426

12

22P_0402_50V8J@

R331

1 2

47K_0402_5%

0.1U_0402_16V4Z

R347 10K_0402_5%

@

1 2

R348 0_0402_5%

1 2

R349 0_0402_5%

EC_SMB_CK1
EC_SMB_DA1

1

C363
1000P_0402_50V7K

2

ECAGND

1 2

R342 0_0402_5%
D26

@

2 1

RB751V_SOD323

@

12

R340 10_0402_5%

1

C391

2

12

PM_CLKRUN#<20,26>

EC_PME#

KSO[0..15]<32>

KSI[0..7]<32>

+3VALW +EC_DVCC

C417

0.1U_0402_16V4Z

C396

0.1U_0402_16V4Z

GATEA20<20>

LPC_FRAME#<20,33>

LPC_AD3<20,33>
LPC_AD2<20,33>
LPC_AD1<20,33>
LPC_AD0<20,33>

PCI_RST#<19,24,26,28,29,30,33>

EC_SCI#<20>

1

2

SERIRQ<20,26,33>

1

2

KSO[0..15]
KSI[0..7]

ISP MODE SUPPORT

@

1 2
1 2

@

1 2

@

1 2

1 2

@

1 2

EC_TX_P80_DATA
EC_RX_P80_CLK

12

100P_0402_50V8J

FRD#SPI_SO

FSEL#SPICS#

SUSP#
KSO17

R327 4.7K_0402_5%

+3VS

R309 4.7K_0402_5%
R308 4.7K_0402_5%

B B

+3VALW

R325 100K_0402_1%

R335 100K_0402_1%

C413 100P_0402_50V8J@
R307 10K_0402_5%

SPI_CS#<33>
SPI_CLK_R<33>
SPI_SI<33>

A A

EC DEBUG PORT

+3VALW

KSO3

EC_SMB_CK2
EC_SMB_DA2

C357

@

R341 0_0402_5%

SPI_CLK_R

R332 0_0402_5%

SPI_SI

R326 0_0402_5%

1
2
3
4

5

1

1

C358

@

100P_0402_50V8J

2

2

1 2
1 2
1 2

JP61

1
2
3
4

ACES_85205-0400

ME@

EC_SMB_CK1<33,42>
EC_SMB_DA1<33,42>

EC_SMB_CK2<4>
EC_SMB_DA2<4>

PM_SLP_S3#<20>
PM_SLP_S5#<20>

EC_SMI#<20>

LID_SW#<34>

SUSP#<26,30,40,43,46,47>

PBTN_OUT#<20>

USB2_ON#<34>

FAN_SPEED1<4>

EC_TX_P80_DATA<12,13>

EC_RX_P80_CLK<12,13>

ON/OFF#<34>

MUTE_LED1#<32,35>

NUM_LED#<32>

FSEL#SPICS#SPI_CS#
SPI_CLK
FWR#SPI_SI

12P_0402_50V8J

XCLKO XCLKI

C381

7/30 modified from 15P to 12P

X2

32.768KHZ_12.5PF_Q13MC14610002

4

L28

1 2

FBM-11-160808-601-T_0603

C386

0.1U_0402_16V4Z

C406

0.1U_0402_16V4Z

GATEA20
SERIRQ

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_EC
PCI_RST#
EC_RST#
EC_SCI#

1 2

R329 0_0402_5%

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PM_SLP_S5#
EC_SMI#
LID_SW#
SUSP#

PBTN_OUT#
EC_PME#
USB2_ON#
FAN_SPEED1

EC_TX_P80_DATA
EC_RX_P80_CLK
ON/OFF#
MUTE_LED1#
NUM_LED#

XCLKI
XCLKO

R328

@

1 2

20M_0603_5%

OSC4OSC

NC3NC

1

2

@

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

KSO17

1

2

1

2

4

1000P_0402_50V7K

U21

1
2
3
4
5
7
8

10
12

13
37
20
38

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

77
78
79
80

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

KB926QFA1 LQFP 128P

<BOM Structu re>

C380
12P_0402_50V8J

1

1

2

2

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1

LPC & MISC

LAD0
PCICLK

PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

XCLK1
XCLK0

C359

1000P_0402_50V7K

C373

Int. K/B
Matrix

SM Bus

+EC_AVCC

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

INVT_PWM/PWM1/GPIO0F

ACOFF/FANPWM2/GPIO13

PWM Output

AD Input

DA Output

PS2 Interface

TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

SPI Flash ROM

BATT_CHGI_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO54

GPO

GPIO

GPI

GND

GND

GND

GND

GND

11

24

35

94

113

3

67

AVCC

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B

AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

CAPS_LED#/GPIO53
SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

AGND

69

ECAGND

INVT_PWM

21

BEEP#

23

CHGSEL

26

ACOFF

27

BATT_TEMP

63

BATT_OVP

64

ADP_I

65
66
75

MB_ID

76

DAC_BRIG

68

EN_FAN1

70

IREF

71
72

EC_MUTE#

83

USB1_ON#

84

POWER_USB_LED#

85

MUTE_LED#

86

TP_CLK

87

TP_DATA

88

R320 10K_0402_5%

97

EMAIL_BTN#

98

POWER_USB_BTN#

99

MUTE_BTN#

109

FRD#SPI_SO

119

FWR#SPI_SI

120

SPI_CLK

126

FSEL#SPICS#

128

S3AUXSW#

73

PSON#

74

FSTCHG

89

CHARGE_LED0#

90

CAPS_LED#

91

CHARGE_LED1#

92

PWR_LED#

93

SYSON

95

VR_ON

121

ACIN

127

AUX_PWRGDPM_SLP_S3#

100

EC_LID_OUT#

101

EC_ON

102
103

SB_PWRGD

104

BKOFF#

105

RF_ON#

106

BT_ON#

107

SCROLL_LED#

108

KILL_SW#

110

ENBKL_Q

112

EAPD

114

EC_THERM#

115

SMART_CHARGE_BTN#

116

WW W_USER_BTN#

117
118

124

ENBKL<18>

1 2

+3VS

+3VALW

INVT_PWM <16>
BEEP# <35>
CHGSEL <43>
ACOFF <41,43>

1 2

C370 0.01U_0402_16V7K

BATT_OVP <43>
ADP_I <43>

DAC_BRIG <16>
EN_FAN1 <4>
IREF <43>

EC_MUTE# <36>
USB1_ON# <30>
POWER_USB_LED# <32>
MUTE_LED# <32>

TP_CLK <33>

TP_DATA <33>

KB926 SPI STRAP PIN

EMAIL_BTN# <32>
POWER_USB_BTN# <32>
MUTE_BTN# <32>

FRD#SPI_SO <33>

S3AUXSW# <8>
PSON# <20>

FSTCHG <43>

CHARGE_LED0# <34,37>

CAPS_LED# <32>

CHARGE_LED1# <34,37>

PWR_LED# <32,34,37>

SYSON <30,40>

VR_ON <48>

ACIN <41>

AUX_PWRGD <9,20>

EC_LID_OUT# <20>

EC_ON <34>
SB_PWRGD <9,20>

BKOFF# <16>
RF_ON# <29>
BT_ON# <33>

SCROLL_LED# <32>

KILL_SW# <29,34>
EAPD <35,36>

EC_THERM# <20>

SMART_CHARGE_BTN# <32>
WWW_USER_BTN# <32>

R545 15K_0402_5%

1 2

R547 10K_0402_5%

1 2

R546

1 2

47K_0402_5%

2

B

2

ECAGND

C

Q39
MMBT3904_SOT23

E

3 1

Level Shift Circuit

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01

3

Compal Secret Data

Deciphered Date

2006/03/01

2

BATT_TEMP <42>

C

2

B

E

3 1

1

+3VALW

12

R312

RA@

Ra

100K_0402_5%

MB_ID

Rb

1 2
1 2

1 2

1

2

100P_0402_50V8J

C416

1 2
1 2
1 2

1

12

R311

14_A@

0_0402_5%

12
12
12
12
12

1

2

100P_0402_50V8J

C418

C360

1

2

100P_0402_50V8J

C415

C361

31 49

100P_0402_50V8J

100P_0402_50V8J

1

C356

0.1U_0402_16V4Z

TP_CLK
TP_DATA

MUTE_BTN#
WW W_USER_BTN#
EMAIL_BTN#
SMART_CHARGE_BTN#
POWER_USB_BTN#
EC_MUTE#

AUX_PWRGD
BEEP#
SYSON
EC_SCI#
EC_THERM#
SERIRQ

SB_PWRGD
PBTN_OUT#
EN_FAN1

ENBKL_Q

Q40
MMBT3904_SOT23

Title

Size Document Number Rev

Custom

Date: Sheet

ACIN
VR_ON
ENBKL_Q

Compal Electronics, Inc.

EC_KB926

JFWXX M/B LA-3961P Schematic

Thursday, September 06, 2007

2

R316 4.7K_0402_5%
R315 4.7K_0402_5%

R322 10K_0402_5%
R64 10K_0402_5%
R60 10K_0402_5%
R59 10K_0402_5%
R63 10K_0402_5%
R318 10K_0402_5%@

1

1

2

2

100P_0402_50V8J

100P_0402_50V8J

C401

C419

C389 100P_0402_50V8J
C382 100P_0402_50V8J
C374 100P_0402_50V8J

1

2

C371

1

2

C372

of

+3VALW

1

2

100P_0402_50V8J

1

2

100P_0402_50V8J

+5VS

0.1

5

INT_KBD Conn.

4

3

2

1

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3

KSI[0..7]

KSO[0..15]

C140 100P_0402_50V8J
C143 100P_0402_50V8J
C136 100P_0402_50V8J
C137 100P_0402_50V8J
C133 100P_0402_50V8J
C135 100P_0402_50V8J
C146 100P_0402_50V8J
C144 100P_0402_50V8J
C134 100P_0402_50V8J
C139 100P_0402_50V8J
C141 100P_0402_50V8J
C123 100P_0402_50V8J

For JFW91 For JFW01

KSI1
KSI7

D D

C C

KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

JP43

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25
GND
GND

ACES_88502-2501

ME@

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

27
26

JP44

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25
GND
GND

ACES_88502-2501

ME@

27
26

Switch Board Conn.

+5VALW

JP48

20

ON/OFFBTN#
PWR_LED#

+5VS

PWR_LED#
POWER_USB_LED#
R_MUTE_LED#
MUTE_BTN#
SMART_CHARGE_BTN#
+VCC_LED

SATA_LED#
CAPS_LED#
NUM_LED#
SCROLL_LED#
ON/OFFBTN#
EMAIL_BTN#
WW W_USER_BTN#
D_POWER_USB_BTN#

PWR_LED#<31,34,37>

POWER_USB_LED#<31>

MUTE_BTN#<31>
+5VALW
+3VALW

B B

1 2

R48 0_0402_5%

1 2

R47 0_0402_5%@

SMART_CHARGE_BTN#<31>

SATA_LED#<21>
CAPS_LED#<31>
NUM_LED#<31>

SCROLL_LED#<31>

ON/OFFBTN#<34>

EMAIL_BTN#<31>

WWW_USER_BTN#<31>

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_85201-2005

ME@

D_POWER_USB_BTN#

D13

1

2
3

DAN202UT106_SC70-3

+3VALW

12

R62
10K_0402_5%

POWER_USB_BTN#
51_ON#

KSI[0..7] <31>
KSO[0..15] <31>

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

MUTE_LED1#<31,35>

POWER_USB_BTN# <31>

51_ON# <34,41>

KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

2

G

Q28

2N7002_SOT23

C142 100P_0402_50V8J

1 2

C138 100P_0402_50V8J

1 2

C132 100P_0402_50V8J

1 2

C130 100P_0402_50V8J

1 2

C131 100P_0402_50V8J

1 2

C145 100P_0402_50V8J

1 2

C128 100P_0402_50V8J

1 2

C127 100P_0402_50V8J

1 2

C124 100P_0402_50V8J

1 2

C125 100P_0402_50V8J

1 2

C126 100P_0402_50V8J

1 2

C129 100P_0402_50V8J

1 2

MUTE_LED#<31>

+3VS

12

13

R304
10K_0402_5%

D

S

2

G

R314

0_0402_5%@

R313 0_0402_5%

13

D

Q27

S

2N7002_SOT23

12/14 Add for MUTE_LED#

12

R_MUTE_LED#

12

7/30 EMI added

D_POWER_USB_BTN#
WW W_USER_BTN#

SMART_CHARGE_BTN#
MUTE_BTN#

A A

D35

3
2

PSOT24C_SOT23

@

D37

3
2

PSOT24C_SOT23

@

5

1

1

PWR_LED#
ON/OFFBTN#

POWER_USB_LED#
PWR_LED#

D36

3
2

PSOT24C_SOT23

@

D38

3
2

PJSOT05C_SOT23

@

1

1

EMAIL_BTN#
SATA_LED#

D39

3
2

PSOT24C_SOT23

@

1

7/30 change D38 pn as SCA00000200
8/1 Change D38 value PSOT24C_SOT23 from to PJSOT05C_SOT23 , Add D39

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

2

Date: Sheet

Compal Electronics, Inc.

KB /SW Conn.

JFWXX M/B LA-3961P Schematic

32 49Thursday, Sept em be r 06, 2007

1

0.1

of

EEPROM_VCC

1 2

R298 4.7K_0402_5%

1 2

R299 4.7K_0402_5%

EEPROM_VCC

R301 0_0603_5%

R302 0_0603_5%

12

@

12

EC_SMB_CK1
EC_SMB_DA1

EEPROM_VCC+5VALW+3VALW

C348 0.1U_0402_16V4Z

1 2

U19

8

VCC

7

WP

EC_SMB_CK1<31,42>
EC_SMB_DA1<31,42>

6

SCL

5

SDA

AT24C16AN-10SU-2-7_SO8

GND

EEPROM_VCC

12

R300
100K_0402_5%

1

A0

2

A1

3

A2

4

12

R297
100K_0402_5%

0206 => change PN to SA00001N800
12/19 change pn to SA00001MP00 ( original part EOL )
12/25 change back to SA024160140 ( Samples can not on time )

JP62

2

112

4

334

6

556

8

778

E&T_2941-G08N-00E~D

ME@

SPI_CLK_R
SPI_SI

+3VALW

SPI_CS#
SPI_SO

0.1U_0402_16V4Z

+3VALW

C108

SPI_CS#<31>
SPI_CLK_R<31>
SPI_SI<31>

8M SPI ROM

+3VALW

20mils

1

2

U5

8

VCC

3

W

7

HOLD

SPI_CS#

1

S

SPI_CLK_R

6

C

SPI_SI SPI_SO

5

D

SST25LF080A_SO8-200mil

VSS

4

2

Q

R110 0_0402_5%

12

FRD#SPI_SO <31>

TP_CLK<31>
TP_DATA<31>

+5VS

To TP/B Conn.

TP_CLK
TP_DATA

+5VS

C189

0.1U_0402_16V4Z

JP12

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_85201-06051

ME@

2

1

TP_DATA
TP_CLK

3

D15

@

PSOT24C_SOT23

Update Footprint

Bluetooth Conn.

Need to check BT pin definition again!
9/20 modified this block

+5VS

12

R14
10K_0402_5%

BT_LED#<34,37>

BT_ON#<31>

BT_LED#

2N7002_SOT23

13

D

Q4

2

G

S

0.1U_0402_16V4Z

15W@

1 2

R21 100K_0402_5%

For 15W BT Conn. located at Right corner For 14W BT Conn. located at Left corner

USB20_P1_1<21>
USB20_N1_1<21>

12

R13
10K_0402_5%

+BT_VCC

R579 0_0402_5%

1 2

R580 0_0402_5%

1 2

BTON_LED

WLAN_ACTIVE<29>

BT_ACTIVE<29>

WLAN_ACTIVE
BT_ACTIVE

USB20_P1_1_R
USB20_N1_1_R

JP42

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND1

10

GND2

MOLEX_53780-0870

ME@

JP56

BT_ACTIVE
WLAN_ACTIVE

R582

USB20_N1_2<21>
USB20_P1_2<21>

1 2
1 2

R581

BTON_LED

0_0402_5%
0_0402_5%

+BT_VCC_1

USB20_N1_2_R
USB20_P1_2_R

1
2
3
4
5
6
7

8

ACES_87212-0800

ME@

7/20 Swap USB signals

15W@

C39

2

4.7U_0805_10V4Z

G

C37

@

+3VALW

S

Q6
SI2301BDS_SOT23

15W@

D

W=40mils

1 3

1

2

1

C40

15W@

1U_0603_10V4Z

2

C34

15W@

0.1U_0402_16V4Z

+BT_VCC

C24

14W@

0.1U_0402_16V4Z

14W@

BT_ON#<31>

1 2

R11 100K_0402_5%

4.7U_0805_10V4Z

G

2

C21

@

+3VALW

1 3

1

2

D

S

Q3
SI2301BDS_SOT23

14W@

W=40mils

1

C23

14W@

1U_0603_10V4Z

2

C19

14W@

0.1U_0402_16V4Z

+BT_VCC_1

FOR LPC DEBUG PORT

+3VS

JP57

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_85201-1005N

ME@

CLK_PCI_DB
LPC_AD0

LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

PCI_RST#

1

C576

@

2

0.1U_0402_16V7K

FOR LPC SIO DEBUG PORT

JP54

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

+5VS

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
PCI_RST#

CLK_PCI_DB
SERIRQ

+3VS

CLK_14M_SIO <14>

LPC_DRQ0# <20>

SERIRQ <20,26,31>

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

ACES_85201-2005

ME@

CLK_PCI_DB <14>
LPC_AD0 <20,31>

LPC_AD1 <20,31>
LPC_AD2 <20,31>
LPC_AD3 <20,31>
LPC_FRAME# <20,31>

PCI_RST# <19,24,26,28,29,30,31>

R468 10K_0402_5%

12

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

BIOS, I/O Port & K/B Connector

JFWXX M/B LA-3961P Schematic

of

33 49Thursday, September 06, 2007

0.1

A

ON/OFF switch

1 1

ON/OFFBTN#<32>

SMT1-05_4P
SW3

@

1
2

2 2

ON/OFFBTN#

3
4

5

6

7/30 add for debug 7/30 change L58,59 to SM070000K00 by EMI request

TOP Side

J2 JOPEN@
J3 JOPEN@

Bottom Side

ON/OFFBTN#

12
12

Power Button

EC_ON<31>

DAN202UT106_SC70-3

EC_ON

R305

10K_0402_5%

D22

1

1 2

2

G

+3VALW

2
3

B

R303
100K_0402_5%

1 2

ON/OFF#

51_ON#

C351
1000P_0402_50V7K

13

D

Q29

2N7002_SOT23

S

C

D

E

For JFW01 IO Conn.

L58

@

4

ON/OFF# <31>

51_ON# <32,41>

USB20_N4<21>

2

1

12

D21
RLZ20A_LL34

USB20_P4<21>

USB20_N5<21>
USB20_P5<21>

USB20_N4
USB20_P4

USB20_N5 USB20_R_N5
USB20_P5 USB20_R_P5

4

1

1

WCM-2012-670T_4P

R536 0_0402_5%

1 2

R537 0_0402_5%

1 2

R538 0_0402_5%

1 2

R539 0_0402_5%

1 2

L59

4

4

1

1

WCM-2012-670T_4P

For EMI => Add R536,R537,R538,R539 (SD028000080) ,L58, L59 (SM070000I00)
Swap L58,L59 Pin 1 & Pin 4 , Pin 2 & Pin 3

3

3

2

2

USB20_R_N4
USB20_R_P4

@

3

3

2

2

+USB_VCCC+USB_VCCC

JP52

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

G1

14

G2

E&T_3703-E12N-03R

ME@

Front LED Board

+5VALW+3VALW +5VS

JP51

1

1

2

2

3

3

4

4

5

5

6

PWR_LED#<31,32,37>
CHARGE_LED0#<31,37>
CHARGE_LED1#<31,37>

BT_LED#<33,37>

WLAN_LED#<29,37>

KILL_SW#<29,31>

3 3

PWR_LED#
CHARGE_LED0#
CHARGE_LED1#
BT_LED#

WLAN_LED#
KILL_SW#
LID_SW#

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

G1

18

G2

ACES_87213-1600G

ME@

Lid Switch

+USB_VCCC

+USB_VCCC

1

+

C51
150U_D_6.3VM

2

2006/08/18 2007/8/18

14W@

C315

+VCC_LID

1

2

14W@

+3VALW

4 4

1 2

R267 0_0402_5%

0.1U_0402_16V4Z

R266 100K_0402_5%14W@

1 2

2

VDD

3

OUTPUT

GND

U13

1

A3212ELHLT-T_SOT23W-3

14W@

2

C314

14W@

10P_0402_50V8J

1

LID_SW# <31>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

W=80mils

1

C53
470P_0402_50V7K

2

Compal Secret Data

Deciphered Date

4.7U_0805_10V4Z

For JFW91 IO Conn.

+USB_VCCC +USB_VCCC

USB20_R_N4
USB20_R_P4

USB20_R_N5
USB20_R_P5

+5VALW

U20

1

GND

2

IN

3

IN

1

C349

2

USB2_ON#<31>

D

4

EN#

G528_SO8

Size Document Number Rev

Date: Sheet

JP59

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

G1

14

G2

ACES_85201-1205_12P

ME@

+3VALW

+USB_VCCC

8

OUT

7

OUT

6

OUT

5

FLG

Title

PWROK/LID/Front/IO Board

B

JFWXX M/B LA-3961P Schematic

12

R169
10K_0402_5%

1

C362

@

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

E

USB_OC#45 <21>

of

34 49Thursday, September 06, 2007

0.1

5

L55

+VDDA

D D

1 2

FBMA-L11-160808-800LMT_0603

10U_0805_10V4Z

C632

C615 100P_0402_50V8J@
C619 100P_0402_50V8J@

0.1U_0402_16V4Z

1

2

1 2
1 2

C639

1

2

680P_0402_50V7K

1

C634

2

0.1U_0402_16V4Z

C621

1

2

2/01 Let the m flo a tin g

C623 100P_0402_50V8J@

MIC1_L<36>

C C

B B

MIC1_R<36>

MIC1_L MIC1_C_L

SENSE FOR Ext. Mic.

MIC_SENSE<36>

SENSE FOR Solo Int. Mic.

1 2

R519 20K_0402_1%

A A

1 2

C633 2.2U_0603_6.3V6K
C640 2.2U_0603_6.3V6K

C627 100P_0402_50V8J@

1 2

C607 100P_0402_50V8J@

1 2

EAPD<31,36>

1 2

R495 20K_0402_1%

SENSE_B

MUTE_LED1#<31,32>

HDA_RST_AUDIO#<20>
HDA_SYNC_AUDIO<20>

HDA_SDOUT_AUDIO<20>

R494

@

10_0402_5%

1 2
1

C614

@

15P_0402_50V8J

2

SENSE_A

MIC1_C_RMIC1_R

MONO_IN

MUTE_LED1#
SENSE_A
SENSE_B

DGND

Sense Pin Impedance Codec Signals

SENSE A / B

SENSE B

4

HD Audio Codec

+AVDD_AC97

+3VS_DVDD

40mil

C624
100P_0402_50V8J

U35

AVDD125AVDD2

14

NC

15

NC

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1_L

22

MIC1_R

12

PCBEEP

11

RESET#

10

SYNC

5

SDATA_OUT

2

GPIO0

3

GPIO3

13

SENSE A

34

SENSE B

47

EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

ALC268-GR_LQFP48

38

20mil

LINE_OUT_L

LINE_OUT_R

HP_OUT_L
HP_OUT_R

DMIC_CLK

BIT_CLK

SDATA_IN

MONO_OUT

LINE1_VREFO

MIC1_VREFO_L
MIC1_VREFO_R

MIC2_VREFO

JDREF

AVSS1
AVSS2

39.2K
20K
10K

5.1K

39.2K
20K
10K

5.1K

1

GPIO1

VREF

0.1U_0402_16V4Z

1

C611

2

DVDD_IO

35
36
39
41
45
46
43
44

6

8
37
29
31
28
32
30
27
40
33
26

42

0.1U_0402_16V4Z

AMP_LEFT
AMP_RIGHT
AMP_LEFT_HP
AMP_RIGHT_HP

HDA_BITCLK_AUDIO

SDIN0

10mil
10mil

ACZ_VREF
ACZ_JDREF

9

DVDD

NC

NC
NC

NC

AGND

PORT-A (PIN 39, 41)
PORT-B (PIN 21, 22)
PORT-C (PIN 23, 24)
PORT-D (PIN 35, 36)
PORT-E (PIN 14, 15)
PORT-F (PIN 16, 17)
PORT-G (PIN 43, 44)
PORT-H (PIN 45, 46)

10U_0805_10V4Z

1

C609

2

10P_0402_50V8J

+MIC1_VREFO_L
+MIC1_VREFO_R

R510

20K_0402_1%

3

1

C612

C603

2

680P_0402_50V7K

1

1

C637

@

1 2

R489 33_0402_5%

C638

@

10P_0402_50V8J

2

2

10mil

12

1

C617

@

100P_0402_50V8J

2

Funnction
HP
MIC
LINE IN
LINE Out
HP
MIC
LINE IN
LINE Out

680P_0402_50V7K

C610

AMP_LEFT <36>
AMP_RIGHT <36>
AMP_LEFT_HP <36>
AMP_RIGHT_HP <36>

HDA_BITCLK_AUDIO <20>

HDA_SDIN0 <20>

1

C635
10U_0805_10V4Z

2

L53

1 2

FBMA-L11-160808-800LMT_0603

1

C608
100P_0402_50V8J

2

+3VS

EC Beep

BEEP#<31>

PCI Beep

SB_SPKR<20>

CardBus Beep

1

C636
100P_0402_50V8J

2

Regulator for CODEC

L54

1 2

FBMA-L11-160808-800LMT_0603

C613

4.7U_0805_10V4Z

2

9/22 Update footprint, N eed to check

C600

1U_0603_10V4Z

C597

1U_0603_10V4Z

1 2

1 2

R484

1 2

560_0402_5%

R482

1 2

560_0402_5%

10K_0402_5%

7/20 modified

Adjustable Output

U34

4

C604

0.1U_0402_16V4Z

VIN

2

DELAY
ERROR7CNOISE

8

SD

SI9182DH-AD_MSOP8

VOUT

SENSE or ADJ

GND

R483

12

5
6
1
3

+VDDA

12

R481
10K_0402_5%

C596

12

1U_0603_10V4Z

R480
10K_0402_5%

1

C

Q36

2

B

E

2SC2411K_SOT23

3

D29
RB751V_SOD323

9/19 Realtek suggest

2 1

Add bypass schematic.

HDA_BITCLK_AUDIO

C622

0.1U_0402_16V4Z

1

1 2

C602

1 2

1U_0603_10V4Z

1 2

R485

2.4K_0402_5%

MONO_INMONO_IN_1

Need Update Footprint

R496

@

10_0402_5%

1 2
1

C605

@

10P_0402_50V8J

2

+VDDA+5VS

+VDDA+5VS_VDDA

R502
30K_0402_1%

1 2

12

R507
10K_0402_1%

C606

4.7U_0805_10V4Z

Moat Bridge

SENSE FOR HP

HP_SENSE<36>

5

R498 39.2K_0402_1%

12

SENSE_A

1 2

R521 0_0805_5%

1 2

R520 0_0805_5%

1 2

R506 0_0805_5%

1 2

R503 0_0805_5%

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/05

3

Compal Secret Data

Deciphered Date

2007/08/05

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

<Title>

Custom

HD Audio Codec ALC268

LA-3541P

Thursday, September 06, 2007

1

35 49

of

0.1

A

APA2056 SPK/HP Amplifier

U37

APA2057A

2057@

1 1

fo=1/(2*3.14*R*C)=106Hz
R=1.5K / C= 1uF

AMP_RIGHT<35>
AMP_LEFT<35>

AMP_RIGHT_HP<35>
AMP_LEFT_HP<35>

C620 1U_0603_10V4Z
C618 1U_0603_10V4Z

C616 4.7U_0805_10V4Z
C625 4.7U_0805_10V4Z
R524

1 2

0_0402_5%

9/5 If implement AMP BEEP, Swap C641 and R524.
R524 change from 0 Ohm to 47K

2 2

1 2
1 2

1 2
1 2

R514 1.5K_0402_1%@

1 2

R515 1.5K_0402_1%@

1 2

R523 100K_0402_5%
R526 100K_0402_5%@

+5VS

AMP_RHPIN
AMP_LHPIN
AMP_SD#

C641 0.47U_0603_16V4Z

1 2
1 2

R517 39K_0402_5%
R518 39K_0402_5%

1 2

AMPR
AMPL

1 2
1 2

C626 1U_0805_10V7K
C649 2.2U_0603_6.3V6K
C646 0.1U_0402_16V4Z

IN_A Gain = 10dB (Internal Speaker)
IN_H Gain = 0dB (Headphone)

B

7/20 Add U37 for APA2057A SA00001QD00

+5VALW

W=40mil

1

2

0.1U_0402_16V4Z

27
24

26
28
12

14
25

1

C648

2

10U_0805_10V4Z

3

INR_A

5

INL_A
/AMP EN
HP EN

4

INR_H

6

INL_H
/SD
BEEP
CP+

CP­BIAS

APA2056_TSSOP28

2056@

+3VALW

11

CVDD

19

HVDD

20

10

PVDD

PVDD

Thermal pad

C630

1 2

C631

680P_0402_50V7K

AMP_BEEP

12

R522 0_0402_5%

AMP_CP+
AMP_CP-

AMP_BIAS

12

AMP_EN#
HP_EN
INR_H

INL_H

1

VDD

ROUT+
ROUT-

LOUT+

LOUT-

HP_R

HP_L

CVSS

VSS

GND
PGND
PGND
CGND

U37

2

C629
1U_0603_10V4Z

1

22
21

8
9

17
18

15
16
2

23
7
13
29

CVSS

SPKR+
SPKR-

SPKL+
SPKL-

HP_R
HP_L

C

1

C642
1U_0805_10V7K

2

D

+MIC1_VREFO_R+MIC1_VREFO_L

12

10mil 10mil

MIC_SENSE<35>

MIC1_R<35>
MIC1_L<35>

HP_SENSE<35>

MIC_SENSE
MIC1_R
MIC1_L

220P_0402_50V7K

HP_SENSE
HP_R
HP_L

1K_0402_5%

R525

@

C645

12

R274

2.2K_0402_5%

1

220P_0402_50V7K

2

12

R527

@

1K_0402_5%

12

R275

2.2K_0402_5%

1

C647

2

10P_0402_50V8J

C643

1

1

C644
10P_0402_50V8J

2

2

E

JP55

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

G1

14

G2

ACES_87212-1200

ME@

12/13 Modified this symbol for pin 13 and 14.
Do not re-copy this symbol for other use

12/1 Modified to X7R
12/27 C46 change PN to SE092105K80

4/19 Modified this symbol to
add pin29 for thermal pad use.

Do not re-copy this symbol for other use

7/20 Add below circuit for APA2057 gain tunning use

8/1 Add R591 for @

3 3

EC_MUTE#<31>

EAPD<31,35>

AMP_SD#

EC_MUTE#

EAPD

R592 0_0402_5%2056@

1 2

R590 10K_0402_5%2057@

1 2

@

1 2

R591 0_0402_5%

@

12

R488 0_0402_5%

12

R492 0_0402_5%

HP_EN

1

C671

2057@

0.1U_0402_16V4Z

2

HP_EN

8/1 Add R590 & C671 for 2057@ and R592 for 2056@

Gain (dB) Low (V) High (V) Recommended (V)

4 4

10
11
12
13
15

3.45

3.56

3.68

3.80

4.02

3.51

3.62

3.73

3.85

4.07

A

3.48

3.59

3.70

3.82

4.05

+5VALW assume equal 5.1V
10 dB ---> 5.1 x 220 / 320 = 3.5

2056@

R587 0_0402_5%

D34

RB751V_SOD323

@

R588

2057@

10K_0402_5%

2

G

Q42

2057@

SSM3K7002FU_SC70-3

Gain= 10dB

B

12

8/1 Change D34 from 2057@ to @

21

+3VALW

1 2

2

G

13

D

S

8/1 Change Q41,Q42,R588 from @ to 2057@

12/1 Modified to X7R
12/27 C48 change PN to SE092105K80

+5VALW

12

12

1

C666

2057@

0.01U_0402_16V7K

13

D

S

Q41

2057@

SSM3K7002FU_SC70-3

2

8/2 Change R585,R586 from 100k,220k to 10k,22k

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R585

2057@

10K_0402_1%

AMP_SD#

R586

2057@

22K_0402_1%

C

Compal Secret Data

Deciphered Date

12/7 Added for 15w" use

SPKL+
SPKL­SPKR+
SPKR-

R220 0_0603_5%
R221 0_0603_5%
R223 0_0603_5%
R226 0_0603_5%

20mil

Speaker Conn.

D

1 2
1 2
1 2
1 2

2007/08/052006/08/05

MIC_SENSE
MIC1_R

MIC1_L
HP_SENSE
HP_R

HP_L

@

D31
PSOT05C-LF-T7 SOT-23-3

10

2

2

3

1

3

@

1

D30
PSOT05C-LF-T7 SOT-23-3

11
12
13
14

E&T_3703-E12N-03R

1/31 change JP9 following JP50

SPK_L1+
SPK_L1­SPK_R1+
SPK_R1-

2

3

2

3

D17

PSOT24C_SOT23

@

1

1

D16
PSOT24C_SOT23

@

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

AMP/VR/Audio Jack/MIC

LA-3541P

E

36 49Thursday, September 06, 2007

JP58

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9
10
11
12
G1
G2

ME@

JP9

1

1

2

2

3

3

4

4

5

GND1

6

GND2

ACES_88231-0400

ME@

of

0.1

MDC Conn.

JP2

1

GND1

HDA_SDOUT_MDC<20>
HDA_SYNC_MDC<20>

HDA_SDIN1<20>

HDA_RST_MDC#<20> HDA_BITCLK_MDC <20>

R306 33_0402_5%

1 2

MDC@

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

GND13GND14GND15GND16GND17GND

Connector for MDC Rev1.5

ACES_88018-124G

ME@

RES0
RES1

3.3V
GND3
GND4

IAC_BITCLK

18

2
4

20mil

6
8
10
12

1

2

C352

@

22P_0402_50V8J

+3VALW

Camera Conn

9/3 change R531,C30,R191,R201,R578 from CAM@ to mount

USB20_N7<21>
USB20_P7<21>

USB20_N7

R19 0_0402_5%

1 2

R20 0_0402_5%

1 2

L60

@

1

1

4

4

WCM-2012-670T_4P

For EMI => Add L60 (SM070000I00)

7/30 change L60 to SM070000K00 by EMI request

R530 0_0603_5%@

+5VALW

2

3

+5VS

2

3

1 2

R531 0_0603_5%

1 2

1

C33

@

4.7U_0805_10V4Z

2

USB20_R_P7 USB20_R_N7

1

C30

0.1U_0402_16V4Z

2

USB20_R_N7
USB20_R_P7USB20_P7

D9

1

GND

2

I/O

PRTR5V0U2X_SOT143@

+CAMVDD

VCC

I/O

20mil

R578
0_0603_5%

1 2

4

3

JP3

1
2
3
4
5
6
7

ACES_88266-05001

ME@

+5VS

For EMI => Change D9 from SC300000100 to SC300000P00

1
2
3
4
5
GND1
GND2

LED

+5VALW

+5VALW

+5VALW

+5VS

+5VS

R269

14W@

4.3K_0402_5%

1 2

R273

14W@

3.3K_0402_5%

1 2

R272

14W@

1 2

3.3K_0402_5%

R270

14W@

3.3K_0402_5%

1 2

R271

14W@

1 2

3.3K_0402_5%

2 1

HT-191NB_BLUE_0603

14W@

4 3

2 1

LED1

LED3

A

B

HT-297UD/ C B _ B L U E/ A M B _0603

14W@

Blue&Amber

LED2

A

4 3

B

2 1

HT-297UD/ C B _ B L U E/ A M B _0603

14W@

Amber
Blue

Amber
Blue

PWR_LED# <31,32,34>

CHARGE_LED0# <31,34>

CHARGE_LED1# <31,34>

BT_LED# <33,34>

WLAN_LED# <29,34>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

LED/MDC/CAMERA

JFWXX M/B LA-3961P Schematic

37 49Thursday, September 06, 2007

of

0.1

H1
HOLEA

1

H2
HOLEA

1

Hole=5.6mm

H3
HOLEA

1

H15
HOLEA

1

H18
HOLEA

1

H27
HOLEA

1

H32
HOLEA

1

H4
HOLEA

1

H16
HOLEA

1

H20
HOLEA

1

H28
HOLEA

1

H34
HOLEA

1

H5
HOLEA

1

H21
HOLEA

1

H23
HOLEA

1

H29
HOLEA

1

Hole=4.4mm

H6
HOLEA

1

H22
HOLEA

1

H30
HOLEA

1

H7
HOLEA

1

H8
HOLEA

1

H9
HOLEA

1

H11
HOLEA

1

7/24 change H21/H22 from H_3P2 to H_3P25

H31
HOLEA

1

Pad only on bottom side

H12
HOLEA

1

H13
HOLEA

1

H14
HOLEA

1

FD1

FD4

FD3

FD2

@

@

1

@

@

1

1

1

H35
HOLEA

H_6P0x7P5N

1

H36
HOLEA

1

H_3P1x5P6N

H37
HOLEA

1

H_3P1x5P6N

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

FAN & Screw Hole

JFWXX M/B LA-3961P Schematic

38 49Thursday, September 06, 2007

of

0.1

5

D D

C C

4

3

2

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005/03/01

3

Compal Secret Data

Deciphered Date

2006/03/01

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

<Title>

JFWXX M/B LA-3961P Schematic

Thursday, September 06, 2007

1

39 49

of

0.1

A

B

C

D

E

1 1

1

C335

@

10U_0805_10V4Z

2 2

+VSB

2

R288
33K_0402_5%

+5VALW TO +5VS +1.8VALW to +1.8VS

C345

@

10U_0805_10V4Z

SUSP

2N7002_SOT23

Q19

+5VALW

1

2

2

G

U18

8

D

7

D

6

D

5

D

AO4468_SO8

5VS_GATE

13

D

S

S
S
S
G

1
2
3
4

+5VS

1

C344

@

10U_0805_10V4Z

2

1

C323

0.1U_0603_25V7K

2

1

C334

2

1U_0603_10V4Z

R295

@

470_0603_5%

1 2
13

D

SUSP SUSP

2

G

Q25

S

2N7002_SOT23

@

10U_0805_10V4Z

+VSB

C324

@

1

2

1 2

R286
47K_0402_5%

SYSON#

2N7002_SOT23

+3VALW TO +3VS

+3VALW

U16

8

S

D

7

S

D

6

S

D

1

C339

C325

@

10U_0805_10V4Z

+VSB

3 3

10U_0805_10V4Z

2

1 2

R287
47K_0402_5%

SUSP

2N7002_SOT23

5

1

@

2

2

G

Q17

D

AO4468_SO8

3VS_GATE

13

D

S

G

1
2
3
4

+3VS

1

C331

@

10U_0805_10V4Z

2

1

C320

0.1U_0603_25V7K

2

1

C343

2

1U_0603_10V4Z

R292

@

470_0603_5%

1 2
13

D

Q23

S

2N7002_SOT23

@

1

C336

@

10U_0805_10V4Z

SUSP

2

G

+VSB

2

1 2

R283
47K_0402_5%

SUSP

2N7002_SOT23

+1.8VALW TO +1.8V

+1.8VALW +1.8V

U17

8

S

D

7

S

D

6

S

D

5

1

C341

@

10U_0805_10V4Z

2

2

G

Q18

D

AO4468_SO8

1.8V_GATE

13

D

S

G

+1.2VALW TO +1.2VS

+1.2VALW +1.2VS

U14

8

S

D

7

S

D

6

S

D

5

1

C321

@

10U_0805_10V4Z

2

2

G

Q16

D

AO4468_SO8

1.2VS_GATE

13

D

S

G

1
2
3
4

1
2
3
4

1

C340

@

10U_0805_10V4Z

2

1

C318

0.1U_0603_25V7K

2

1

C327

@

10U_0805_10V4Z

2

1

C317

0.1U_0603_25V7K

2

1

C329

2

1U_0603_10V4Z

1

C338

2

1U_0603_10V4Z

R294

@

470_0603_5%

1 2
13

D

Q24

S

2N7002_SOT23

@

R290

@

470_0603_5%

1 2
13

D

Q21

S

2N7002_SOT23

@

G

G

2

2

SYSON#

SUSP

C322

10U_0805_10V4Z

+VSB

@

1

2

R284
47K_0402_5%

SUSP

+1.8VALW

1

C337

@

10U_0805_10V4Z

2

12

2

G

Q15

2N7002_SOT23

SYSON<30,31>

U15

8

D

7

D

6

D

5

D

AO4468_SO8

1.8VS_GATE

13

D

S

10K_0402_5%

S
S
S
G

SYSON

R281

1
2
3
4

1

2

SYSON#

2

12

+1.8VS

1

C330

@

10U_0805_10V4Z

2

C319

0.1U_0603_25V7K

+5VALW

R285
100K_0402_5%

1 2

13

D

Q14
2N7002_SOT23

G

S

1

C342

2

1U_0603_10V4Z

R293

@

470_0603_5%

1 2
13

D

S

2

G

Q22
2N7002_SOT23

@

+1.5VS +1.05VS +0.9VS

R289
470_0603_5%

@

1 2
13

D

SUSP SUSP SUSP

2

G

Q20

S

2N7002_SOT23

@

4 4

R280
470_0603_5%

@

1 2
13

D

S

2

G

Q12
2N7002_SOT23

@

R296
470_0603_5%

@

1 2
13

D

S

2

G

Q26
2N7002_SOT23

@

7/24 Change R281 from 100K to 10K

SUSP#<26,30,31,43,46,47>

R282

10K_0402_5%

+5VALW

R278
100K_0402_5%

1 2

SUSP

13

D

Q13

2

2N7002_SOT23

G

S

12

1

C316
100P_0402_50V8J

2

SUSP <47>

3/14 Change R16 from 100K to 10K

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/08/18 2007/8/18

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

B

D

Date: Sheet

Compal Electronics, Inc.

DC Interface

JFWXX M/B LA-3961P Schematic

E

of

40 49Thursday, September 06, 2007

0.1

A

B

C

D

DC301001Y00

SINGA_2DW-0268-B16

@

1

1

2

2

3

3

4

4

PJP1

1 1

VIN

12

PR11

PR14

84.5K_0402_1%

22K_0402_1%

1 2

12

3.3V

PR24
560_0603_5%

1 2

PJ15
PAD-OPEN 3x3m

12

PC6

1000P_0603_50V7K

RTCVREF

12

21

PR15

20K_0402_1%

G920AT24U_SOT89-3
PU2

3

OUT

PC9

4.7U_0805_6.3V6K

+1.5VS+1.5VSP

GND

1

+1.8VALWP

2 2

PR23
560_0603_5%

1 2

+CHGRTC

3 3

ADPIN

12

PR5
10K_0402_1% @

1 2

12

3
2

PC7

PR17
10K_0402_1%

0.1U_0402_16V7K

2

IN

12

PC1

0.01U_0402_50V7K

PC5

0.01U_0402_25V7K@

1 2

PR9
1M_0402_1%

1 2

VS

8

P

+

O

-

G

PU1A
LM393DG_SO8

4

12

PR25
200_0805_5%

12

PC8

1U_0805_25V4Z

PJ16 PAD-OPEN 3x3m

1 2

PL1

HCB4532KF-800T90_1812

1 2

<BOM Structu re>

PC2

0.01U_0402_50V7K

1

RTCVREF

3.3V

BATT+

RLS4148_LL34-2

CHGRTCP

12

PR29
22K_0402_1%

51_ON#<32,34>

1 2

+1.8VALW

PD5

12

VS

12

12

PC3

0.022U_0603_50V7K

PR10

10K_0402_1%

PD3

RLZ4.3B_LL34

12

12

PR26

12

PC4

0.022U_0603_50V7K

1 2

12

PR16

10K_0402_1%

12

PC10

100K_0402_5%

PR12
10K_0402_1%

PACIN

0.22U_1206_25V7K

PQ4

TP0610K-T1-E3_SOT23-3

VIN

12

PR1

10_1206_5%

12

PD1

RLZ24B_LL34

ACIN <31>

PACIN <43>

Vin Detector

High 18.764 17.901 17.063
Low 17.745 16.9 16.03

VIN

PD4
RLS4148_LL34-2

1 2

12

12

VS

PR20

PR21

68_1206_5%

68_1206_5%

13

12

PC11

2

0.1U_0603_25V7K

(7A,280mils ,Via NO.=14) (8A,320mils ,Via NO.= 16)

PJ18
PAD-OPEN 3x3m

+5VALWP

1 2

(6A,240mils ,Via NO.= 12)

4 4

+3VALWP

PJ20
PAD-OPEN 3x3m

1 2

(6A,240mils ,Via NO.=12)

PJ21
PAD-OPEN 3x3m

1 2

(6A,240mils ,Via NO.=12)

+5VALW

+3VALW

A

+0.9VSP

(2A,80mils ,Via NO.= 4)

+1.05VSP

(16A,800mils ,Via NO.= 24)

+VSBP +VSB+1.2VALWP +1.2VALW

(0.3A,40mils ,Via NO.= 2)

PJ19
PAD-OPEN 3x3m

1 2

PJ17 PAD-OPEN 3x3m

1 2

PJ22
PAD-OPEN 3x3m

1 2

+0.9VS

+1.05VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/10/17 2006/10/17

ACIN

Precharge detector

Min. typ. Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V

PD2

VIN

MAINPWON<42,44>

ACON<43>

12

RLS4148_LL34-2

PD6

2
3

RB715F_SOT323-3

1

RTCVREF

Compal Secret Data

Deciphered Date

C

ACOFF<31,43>

VL

12

12

PR2
1K_1206_5%

1 2

PR3
1K_1206_5%

1 2

PR4
1K_1206_5%

1 2

PR8
1K_1206_5%

1 2

PR22

100K_0402_1%

LM393DG_SO8

PC13

0.1U_0603_25V7K

2

7

O

PU1B

PR30
34K_0402_1%

12

13

PR18

2.2M_0402_5%

VS

8

5

P

+

6

-

G

4

12

12

PR6

100K_0402_5%

PQ2
DTC115EUA_SC70-3

12

PC14

1000P_0402_50V7K

BATT ONLY

Precharge detector

Min. typ. Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

PQ1

TP0610K-T1-E3_SOT23-3

13

12

PR7

100K_0402_5%

12

PR32

@

66.5K_0402_1%

Title

Size Document Number Rev

B

Date: Sheet

2

12

PR13

100K_0402_5%

13

PQ3
DTC115EUA_SC70-3

2

12

PR27

191K_0402_1%

PRG++

PQ5

13

D

RHU002N06_SOT323-3

S

2

G

13

Compal Electronics, Inc.

DCIN/DECTOR

D

12

PR19

499K_0402_1%

12

PR28

499K_0402_1%

PR31
47K_0402_1%

12

PQ6
DTC115EUA_SC70-3

2

B+

12

PC12

41 49Thursday, September 06, 2007

0.01U_0402_25V7K

PACIN <43>

+5VALWP

of

0.2

A

B

C

D

DC040003600

PJP2

1
2
3

1 1

4
5
6
7
8

9
G1
G2

SUYIN_200275MR009G180ZR

BATT++

1
2

CNT1

3

CNT2

4

EC_SMCA

5

EC_SMDA

6

TS_A

7

GND

8
9
10
11

12

12

PR40

100_0402_1%

PR36

1 2

PR41

100_0402_1%

PR34

1 2

100K_0402_5%@

1K_0402_1%

+3VALWP

PR35

1 2

1K_0402_1%

1 2

PR33

@

100K_0402_5%

+3VALWP

BATT++

12

PC15

1000P_0603_50V7K

12

EC_SMB_CK1 <31,33>
EC_SMB_DA1 <31,33>

2 2

12

PR46

1K_0402_1%

1 2

PR44

6.49K_0402_1%

PQ7

TP0610K-T1-E3_SOT23-3

B+

12

12

PC21

PR47

100K_0402_5%

2

0.22U_1206_25V7K

PR48

3 3

VL

22K_0402_1%

1 2

+3VALWP

BATT_TEMP <31>

13

+VSBP

12

PC22

0.1U_0603_25V7K

PJ23
PAD-OPEN 3x3m

1 2

PC16

1000P_0603_50V7K

BATT+

PH1 under CPU botten side :

CPU thermal protection at 85 degree C

2/16 Change to 89 degree C for thermal request

Recovery at 70 degree C

12

PC17

0.01U_0603_50V7K

12

VL

12

12

PC19

1000P_0402_50V7K

PR38

10K_0402_1%

PR42

78.7K_0603_1%

1 2

PH1

100K_0603_1%_TH11-4H104FT

12

TM_REF1

LM358ADR_SO8

12

PC20

1U_0603_6.3V6M

PC18

12

0.1U_0603_25V7K

PU3A

3

+

2

-

PR43
150K_0402_1%

PR45

150K_0402_1%

VS

1 2

8

P

G

4

12

PR39
442K_0603_1%

1 2

1

0

VL

VL

PR37

1 2

150K_0402_1%

PD8

1SS355TE-17_SOD323-2

MAINPWON <41,44>

PR49

PR50

10K_0402_1%

1 2

0_0402_5%

SPOK<44,45>

1 2

12

13

D

2

G

PQ8
RHU002N06_SOT323-3

S

PC23

0.1U_0402_16V7K

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

BATTERY CONN. / OTP

D

42 49Thursday, September 06, 2007

of

0.1

A

B

65W, Iadapter=0~3.42A, Current sense=0.02ohm, PR74=39.2K, CP=3.079A

ADP_I = 19.9*Iadapter*Rsense

C

D

P2

12

0.1U_0603_25V7K

12

13

PR54
200K_0402_1%

D

S

S TR AO4407 1P SO8 W/D

1

S

2

S

3

S

4

G

PQ18
RHU002N06_SOT323-3

<BOM Structure>

143K_0402_1%

IREF<31>ACON<41>

8

D

7

D

6

D

5

D

PQ11

PC29

FSTCHG<31>

0.01U_0402_25V7K

PR68

12

PR70

100K_0402_1%

6251VREF

PR74

100K_0402_1%@

5600P_0402_25V7K

1 2

PQ10

D
D
D
D

1 3

PR66

22K_0402_1%

1 2

1

S

2

S

3

S

4

G

PQ12
DTA144EUA_SC70-3

150K_0402_1%

13

12

PC28

PR60

2

G

Be careful the

VIN

1 1

12

PR53
47K_0402_1%

2

PQ16

13

D

RHU002N06_SOT323-3

2

G

S

2 2

PACIN<41>

8
7
6
5

S TR AO4407 1P SO8 W/D

2

13

PQ14
DTC115EUA_SC70-3

PACIN

ACON

IREF voltage!!

ACOFF<31,41>

3 3

CP mode

2

PQ20

DTC115EUA_SC70-3

Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)

P3

1 2

1SS355TE-17_SOD323-2

PD16

1 2

PR58

0_0402_5%

PC38

ADP_I<31>

12

12

PC44

12

P3

1
2

0.02_2512_1%

TP0610K-T1-E3_SOT23-3

12

PR209

100K_0402_1%

1 2

PR57
10K_0402_1%
PC56

1 2

0.1U_0402_16V7K

PC35

680P_0402_50V7K@

CSON

1 2

1 2

PC36 6800P_0402_25V7K

PR63

1 2

10K_0402_1%

1 2

PC39

100P_0402_50V8J

PC40

1 2

0.1U_0402_16V7K

6251VREF

1 2

2

39.2K_0402_1%

PQ21

SI2301BDS-T1-E3_SOT23-3 @

0.01U_0402_25V7K

PR51

2

6251VDD

12

PR59

PR64

1 2

100_0402_1%

PR69

12

PR72
10K_0402_1%

1 2

13

274K_0402_1%@

4
3

PQ42

12

100K_0402_1%

6251VREF

PR73

13

PC31

6251_EN

where Vaclm=0.5535V, Iinput=3.079A
where Vaclm=0.6667V, Iinput=4.263A

CC=0.6~3.4A

If this area float, Charge voltage is 4.2V/cell

CHGSEL<31>

VCHLM=0.24V~1.36V

IREF=0.972*Icharge

IREF=0.5832V~3.3V

BATT Type

2800mAH 3S pack

4 4

Normal 3S LI-ON Cells

Charging Voltage
(0x15)

13050mV

12600mV

CHGSEL

LOW 12.90V

HIGH

CV mode

12.60V

B+

6251DC_IN

12

PC97

0.1U_0603_25V7K

PR210

1 2

100K_0402_1%

12

PU4

1

VDD

2.2U_0603_6.3V6K

2

ACSET

3

EN

4

CELLS

5

ICOMP

6

VCOMP

7

ICM

8

VREF

9

CHLIM

10

ACLIM

11

VADJ

12

GND

ISL6251AHAZ-TR5283_QSOP24

ACPRN

CSON

CSOP

PHASE

UGATE

BOOT

VDDP

LGATE

PGND

BATT_OVP<31>

PQ43

13

DTC115EUA_SC70-3

24

DCIN

23

22

21

20

CSIN

19

CSIP

18

17

16

15

14

13

PJ14

112

JUMP_43X118

PD17

FSTCHG

2

1

2

RB715F_SOT323-3

6251DC_IN

PC34 0.047U_0603_16V7K

PC37 0.1U_0603_25V7K

LX_CHG

DH_CHG

BST_CHG

6251VDDP

DL_CHG

PR213

20_0603_5%

1 2

1 2

1 2

PR214 20_0603_5%

PR62 20_0603_5%

1 2

1 2

PR61 2.2_0603_5%

PR67

1 2

2.2_0603_5%

PC45

1 2

4.7U_0805_6.3V6K

PR77

10K_0402_1%

1 2

12

PC47

@

0.01U_0402_25V7K

3

12

1 2

PD10

1SS355TE-17_SOD323-2

2

CSIP
CSIN

SUSP#<26,30,31,40,46,47>

PR141
0_0603_5%

BST_CHGA

12

1 2

4.7_0603_5%
PR71

PC41

6251VDD

7

0

CHG_B+

12

PC25

PC24

10U_1206_25VAK

10U_1206_25VAK

CSON

CSOP

12

0.1U_0603_25V7K

VS

12

8

PU3B

5

P

+

6

-

G

LM358ADR_SO8

4

12

PC46

12

PC26

0.1U_0603_25V7K

0.01U_0402_25V7K

12

PC27

2200P_0402_50V7K

5

4

5

4

BATT+

12

PR75

340K_0402_1%

12

PR76

499K_0402_1%

12

PR78

105K_0402_1%

DTC115EUA_SC70-3

D8D7D6D

PQ17

SI4800BDY-T1-E3_SO8

S1S2S3G

If charge current is small,
you can change to 16uH choke.

10UH_SIL1045RA-100PF_4.5A_30%

D8D7D6D

PQ19
SI4800BDY-T1-E3_SO8

S1S2S3G

12

0.01U_0402_25V7K

PR55

10K_0402_1%

PQ13

1 2

12

PR79

4.7_1206_5%

@

12

PC30
680P_0603_50V7K

@

PC48

S TR AO4407 1P SO8 W/D

1
2
3
4

1 2

13

PL3

8

S

D

7

S

D

6

S

D

5

G

D

PQ9

PR52

47K_0402_1%

1 2

PD7

1 2

1SS355TE-17_SOD323-2

PD9

1 2

2

1SS355TE-17_SOD323-2

CHG

1
2

0.02_2512_1%

VIN

12

PC33

0.1U_0603_25V7K

PR65

OVP voltage :

LI-3S :13.50V--BATT-OVP=1.5V
BATT-OVP=0.111*BATT+

PR56

1 2

200K_0402_1%

PQ15

13

D

RHU002N06_SOT323-3

2

G

S

4
3

ACOFF <31,41>

VIN

12

PC42

10U_1206_25VAK

PACIN <41>

BATT+

12

PC43

10U_1206_25VAK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

2007/05/182006/05/18

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CHARGER

CHARGER

D

43 49Thursday, Septe m b er 06, 2007

1.0

of

A

12

12

ISL6237_B+

PQ28

SI4810BDY-T1-E3_SO8

1 2

0_0402_5%

B+

PJ28 PAD-OPEN 3x3m

1 2

1 1

+3VALWP

1

+

220U_6.3V_M

PC59

2

2 2

4.7UH_SIL104R-4R7PF_5.7A_30%

PR219

0_0402_5%

1 2

PC120

4.7U_1206_25V6K

PL6

1 2

12

PC119

2200P_0402_50V7K

PR216

@

2.2_1206_5%

PC131

@

680P_0603_50V8J

VL

12

3.3VALWP Ipeak=6.6A~10A

Rds(on) = 20m ohm(max) ; Rds(on) = 16m ohm(typical)

PZD1

RLZ5.1B_LL34

VS

1 2

3 3

MAINPW O N<41,42>

PR225

100K_0402_5%

1 2

5

D8D7D6D

S1S2S3G

4

5

D8D7D6D

S1S2S3G

4

PR80

PR226

200K_0402_5%

0_0402_5%

B

PQ25
SI4800BDY-T1-E3_SO8

1 2

PR221

10K_0402_1%

1 2

@

PC133

0.22U_0603_25V7K

1 2

1 2

PR231

12

PC134

1U_0603_6.3V6M

PR81

1 2

0_0603_5%

PR217

0_0603_5%

PC128

0.1U_0603_25V7K

2VREF_ISL6237

1 2

PC132 0.22U_0603_10V7K

PR229

0_0402_5%@

1 2

PR232

@

47K_0402_1%

12

@

1U_1206_25V7K

DH3

BST3A

12

LX3

FB3

1 2

12

PC135

0.047U_0402_16V7K

PC124

33
26
24

25

23

30

32

20

14

27

PR230

1 2

2VREF_ISL6237

1 2

PU5

TP
UGATE2
BOOT2

PHASE2

LGATE2

OUT2

REFIN2

1

REF

8

LDOREFIN

NC

4

EN_LDO

EN1

EN2

0_0402_5%

C

D

ISL6237_B+

PQ26

SI4800BDY-T1-E3_SO8

PQ27

5

D8D7D6D

PC121

S1S2S3G

4

5

4

SI4810BDY-T1-E3_SO8

4.7U_1206_25V6K

12

D8D7D6D

PR215

2.2_1206_5%

@

12

S1S2S3G

PC130

@

680P_0603_50V8J

VL

1U_0603_10V6K

7

UGATE1

PHASE1

LGATE1

LDO

PVCC

BOOT1

PGND

OUT1

FB1

12

PC126

PC127

4.7U_0805_6.3V6K
1U_0603_10V6K

1 2

19

DH5

15
17

16

18

22

10

11

BST5A

0_0603_5%

0.1U_0603_25V7K

LX5

DL5DL3

FB5

PR218

12

PC129

1 2

1 2

PC125

6

3

VIN

VCC

12

12

PC122

4.7U_1206_25V6K

4.7UH_SIL104R-4R7PF_5.7A_30%

12

PC123

2200P_0402_50V7K

PL5

12

PR220

61.9K_0402_1%

1 2

PR222

1 2

10K_0402_1%

+5VALWP

1

+

2

220U_6.3V_M

PC64

VFB=0.7V

9

BYP

29

SKIP

28

POK2

13

POK1

12

ILIM1

31

ILIM2

TON

2

2VREF_ISL6237

GND

ISL6237IRZ-T_QFN32_5X5

21

NC

5

PR223 0_0402_5%@

PR224 0_0402_5%

1 2

ILM1

ILIM2

12

PR227

330K_0402_1%

PR228

330K_0402_1%

VL

SPOK <42,45>

12

12

5VALWP Ipeak=6.6A~10A

Rds(on) = 20m ohm(max) ; Rds(on) = 16m ohm(typical)

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

+5VALWP/+3VALWP

D

44 49Thursday, September 06, 2007

of

0.1

5

4

3

2

1

PC136

PR233

10_0603_1%

12

5

VIN1

PU6

12

12

4

1U_0402_6.3V6K

+5VALW +5VALW

D D

PJ24

2

B+

JUMP_43X118

PR243

1 2

8.2K_0402_1%

C C

PC146

0.022U_0402_16V7K

1 2

+1.2VALWP

PC84

220U_6.3V_M

B B

1.2VALWP Ipeak=6.6A~10A

1 2

1.8UH_SIL104R-1R8PF_9.5A_30%

1

+

DCR 10 mOHM

2

SPOK<42,44>

112

PL7

ISL6228_B+

1000P_0402_50V7K

PC142

12

34K_0402_1%

12

PR247

8.2K_0402_1%

1 2

PQ46

SI4810BDY-T1-E3_SO8

PR254

0_0402_5%

1 2

PR241

ISL6228_B+

12

PC144

4.7U_1206_25V6K

12

12

3.3K_0402_5%
PR240

12

PC145

D8D7D6D

S1S2S3G

4.7U_1206_25V6K

D8D7D6D

S1S2S3G

1.2V_EN

PC155

33.2K_0402_1%

5

PQ45

SI4800BDY-T1-E3_SO8

4

DH_1.2-2

1 2

0_0603_5%

5

PC151

4

0.1U_0402_16V7K

PR239

PR248

1 2

12

0_0603_5%

DL_1.2

+5VALW

OCSET_1.2

1.2V_EN

LX_1.2

DH_1.2-1

PR251

FB_1.2

VO_1.2

BST_1.2

12

ISL6228_B+ ISL6228_B+

PC140

1000P_0402_50V7K

PR324

1 2

@

0_0402_5%

8

FB1

9

VO1

10

OCSET1

11

EN1

12

PHASE1

13

UGATE1

14

BOOT1

+5VALW

PC153

1U_0402_6.3V6K

PC138

0.1U_0603_25V7K

PR235

12

10_0603_1%

12

PR237

22K_0402_1%

1 2

7

6

FSET1

PGOOD1

ISL6228HRTZ-T_QFN28_4X4

PVCC115LGATE116PGND117PGND218LGATE219PVCC220BOOT2

1 2

VFB=0.6V

VCC1

PC137

12

1U_0402_6.3V6K

2.2_0603_1%

1 2

3

VCC2

PR234

12

PC139

0.1U_0603_25V7K

PR236

10_0603_1%

PC141

1000P_0402_50V7K

12

2

1

GND_T

VIN2

FSET2

PGOOD2

OCSET2

PHASE2

UGATE2

21

BST_1.8

+5VALW

PC154
1U_0402_6.3V6K

1 2

12

18.2K_0402_1%

1 2

FB2

VO2

EN2

PR238

29

28

27

26

25

24

23

DH_1.8-1

22

PR253

1 2

0_0603_5%

FB_1.8

VO_1.8

OCSET_1.8

PR249

0_0402_5%

1 2

PC147

1 2

0.01U_0402_25V7K@

LX_1.8

PR323

1 2

@

0_0402_5%

SI4800BDY-T1-E3_SO8
PR252

1 2

0_0603_5%

PC152

1 2

0.1U_0402_16V7K

DL_1.8

SPOK <42,44>

PQ30

DH_1.8-2

+5VALW

5

D8D7D6D

S1S2S3G

4

5

D8D7D6D

SI4810BDY-T1-E3_SO8

S1S2S3G

4

ISL6228_B+

PQ32

3.3K_0402_5%

PR242

16.5K_0402_1%

1 2

12

12

PC148

PC150

4.7U_1206_25V6K

4.7U_1206_25V6K

1000P_0402_50V7K

PR244

10K_0402_1%

1 2

1.8UH_SIL104R-1R8PF_9.5A_30%

PC143

1 2

12

PR245

1 2

34K_0402_1%

PR246

1 2

10K_0402_1%

0.022U_0402_16V7K
PC149

1 2

PR250

PL8

1 2

DCR 10 mOHM

1

+

PC86
220U_6.3V_M

2

+1.8VALWP

1.8VALWP Ipeak=6.6A~10A

0.01U_0402_25V7K

@

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

1.2VALWP/1.8VP

Thursday, Sep tem ber 06, 2007

0.1

of

1

45 49

5

4

3

2

1

PJ25

D D

C C

B+

SUSP#<26,30,31,40,43,47>

2

JUMP_43X118@

PR262

1 2

0_0402_5%

112

4.7U_1206_25V6K

6269_B+

PC156

2.2U_0603_6.3V6K

12

12

12

PC160

PC162

0.1U_0402_16V7K

@

PC157

4.7U_1206_25V6K

6269_1.05V

12

22P_0402_50V8J

PR260

1 2

0_0402_5%

PC164

12

49.9K_0402_1%

6269_1.05V

PR257

10K_0402_1%

PU7

1

VIN

2

VCC

3

FCCM

4

EN

12

PR265

12

PC166

6800P_0402_25V7K

12

17

16

GND

PGOOD

COMP5FB6FSET

FB_1.05V

PR266

57.6K_0402_1%

15

PHASE

PHASE_1.05V

DH_1.05-1

14

UG

7

12

PR255

1 2

PR256

1 2

0_0603_5%

BOOT_1.05V

13

BOOT

12

PVCC

PC159 2.2U_0603_6.3V6K

11

LG

10

PGND

9

ISEN

VO

8

12

PC165

0.01U_0402_25V7K

0_0603_5%

PC158

1 2

PR258
0_0603_5%

PR259

1 2

4.7_0603_5%

1 2

LG_1.05V

1 2

PR263

4.42K_0402_1%

<BOM Structure>

0.1U_0402_16V7K

+5VALW

12

ISEN_1.05V

ISL6269ACRZ-T_QFN16_4X4

DH_1.05-2

6269_1.05V

SI4810BDY-T1-E3_SO8

PQ48

5

PQ47

D8D7D6D

4

5

4

SI4800BDY-T1-E3_SO8

S1S2S3G

1.8UH_SIL104R-1R8PF_9.5A_30%

12

PR261

4.7_1206_5%

D8D7D6D

@

S1S2S3G

12

PC163
680P_0603_50V7K

@

PL10

1 2

12

PR264
3K_0402_1%

12

PR267

4.02K_0402_1%

1

+

PC161
220U_6.3V_M

2

+1.05VSP

+1.05VSP

OCP==>7A~~8.5A
Vripple==>40mV

VFB=0.6V

B B

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

1.05VSP/1.5VSP

Thursday, Sep tem ber 06, 2007

0.1

of

1

46 49

5

4

3

2

1

D D

C C

+1.8VS

1

PJ26

1

JUMP_43X79

2

2

12

PC168
10U_0805_6.3V6M

PR268

0_0402_5%

0.1U_0402_16V7K@

1 2

PC171

SUSP#<26,30,31,40,43,46>

+5VS

12

PC167

1U_0603_6.3V6M

PU8

6

VCNTL

5

VIN

9

VIN

8

EN

7

12

POK

3

VOUT

4

VOUT

2

FB

GND

APL5913-KAC-TRL_SO8

1

3K_0402_1%

PR269

12

12

PR270

3.4K_0402_1%

12

PC170

0.01U_0402_25V7K

12

PC169

22U_1206_6.3V6M

+1.5VSP

VFB=0.8V

+1.8V

1

PJ27

1

JUMP_43X118

2

2

B B

10U_0805_6.3V6M

PR272

0_0402_5%

SUSP<40>

1 2

0.1U_0402_16V7K@

PC176

PC172

2

G

12

12

PR271

1K_0402_1%

13

D

1K_0402_1%

S

PR273

PQ49

RHU002N06_SOT323-3

12

12

0.1U_0402_16V7K

12

PC174

PU9

2
3
4

APL5331KAC-TRL_SO8

+0.9VSP

12

PC175
22U_1206_6.3V6M

VIN1VCNTL
GND
VREF
VOUT

6
5

NC

7

NC

8

NC

9

TP

+3VALW

12

PC173
1U_0603_6.3V6M

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2005/10/17 2006/10/17

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

+1.5VSP/0.9VSP

Thursday, Sep tem ber 06, 2007

0.1

of

1

47 49

5

4

3

2

1

+5VS

<5>

<5>

<5>

<5>

<5>

36
35
34
33
32
31
30
29
28
27
26
25

PU10

ISEN1
ISEN2

<5>

BOOT_CPU1

UGATE_CPU1-1

PHASE_CPU1

UGATE_CPU2-1

BOOT_CPU2

1 2

PR301

0_0603_5%

+5VS

+CPU_B+

PC181

0_0603_5%

PR287

1 2

LGATE_CPU1

LGATE_CPU2

PHASE_CPU2

PR299

1 2

2.2_0603_5%

0.22U_0603_10V7K

0.022U_0402_16V7K

<5>

D D

PR275 499_0402_1%

PM_DPRSLPVR_D<25>

H_DPRSTP#<5,25>

CLK_EN#

12

1 2

12

PR286 0_0402_5%

12

PR288

PC2010.018U_0603_50V7J

12

PC202

0.018U_0603_50V7J

+3VS

+3VS

PR289

499_0402_1%

VGATE<14>

H_PSI#<5>

PR298 4.22K_0402_1%@

PGD_IN

VR_TT#

1 2

1 2

100K_0603_1%_TH11-4H104FT@

PR297 147K_0402_1%

1 2

PC1890.015U_0402_16V7K@

C C

PR300 13K_0402_1%

PR309 97.6K_0402_1%

1 2

B B

PC198 220P_0402_50V7K
255_0402_1%

1 2

PR314 1K_0402_1%

VCCSENSE<5>

+CPU_CORE

1 2

PR316 20_0402_5%

VSSSENSE<5>

1 2

1 2

PR296 0_0402_5%@

1 2

PH2

PC1900.022U_0603_50V7K

1 2

1 2
1 2

PC1921000P_0402_50V7K

PR303 6.81K_0402_1%

1 2

1 2

PC193 1000P_0402_50V7K

PC195 470P_0402_50V7K

1 2

PC199 1000P_0402_50V7K

PR312

1 2

1 2

PR315 0_0402_5%

PR319

20_0402_5%

PR321 1K_0402_1%

VCC_PRM

0.22U_0603_10V7K

A A

PR276 0_0402_5%

PR277 0_0402_5%

1 2

1 2

12

PC183

1U_0603_6.3V6M

1.91K_0402_1%

1

PGOOD

2

PSI#

3

PMON

4

RBIAS

5

VR_TT#

6

NTC

7

SOFT

8

OCSET

9

VW

10

COMP

11

FB

12

FB2

PR310

@

0_0402_5%

1 2

1 2

1 2

PR318 0_0402_5%

PC204180P_0402_50V8J

1 2

1 2

PC206

1 2

1 2

48

49

3V3

GND

VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1

12

PR311
1K_0402_1%

1 2

PR322 4.02K_0402_1%

VR_ON

PR285

12

0_0402_5%

46

47

44

45

VR_ON

CLK_EN#

DPRSTP#

DPRSLPVR

ISL6262ACRZ-T_QFN48_7X7

12

PC203

0.018U_0603_50V7J

PC2050.1U_0402_16V7K

1 2

PC2070.22U_0402_6.3V6K

12

CPU_VID6

PR278

12

0_0402_5%

43

12

CPU_VID4

CPU_VID5

PR279

PR280

12

12

0_0402_5%

12

PR320

<31>

CPU_VID3

CPU_VID2

PR281

PR282

12

12

0_0402_5%

0_0402_5%

0_0402_5%

12

10_0603_5%

1 2

PC200

0.1U_0603_25V7K

12

PR317

12

11K_0402_1%

1 2

CPU_VID1

CPU_VID0

PR283

PR284

12

12

0_0402_5%

0_0402_5%

VID037VID138VID239VID340VID441VID542VID6

BOOT1
UGATE1
PHASE1

PGND1

LGATE1

PVCC

LGATE2

PGND2
PHASE2
UGATE2

BOOT2

NC

24

1 2

PR308 1_0603_5%
PC197

1U_0402_6.3V6K

PR313

VSUM

2.61K_0402_1%
10KB_0603_5%_ERTJ1VR103J

PH3

PR274
1_0603_5%

1 2

12

12

PC182

2.2U_0603_6.3V6K

0.22U_0603_10V7K
PC184

1 2

1 2

2.2_0603_5%
PR290

PQ51
SI4856DY-T1-E3_SO8

1 2

PC191

SI4856DY-T1-E3_SO8

UGATE_CPU1-2

UGATE_CPU2-2

PQ54

+CPU_B+

12

PC178

PQ50
SI7686DP-T1-E3_SO8

3 5

241

5

4

5

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

4

PQ52

SI4856DY-T1-E3_SO8

10U_1206_25VAK

PR291

PC185

PQ53
SI7686DP-T1-E3_SO8

12

PC179

10U_1206_25VAK

12

4.7_1206_5%

12

680P_0603_50V8J

PC187

12

PC180

10U_1206_25VAK

PC177

0.36UH_MPC1040LR36_24A_20%

12

12

PR292

PR293

10K_0402_1%

3.65K_0805_1%

VSUM

ISEN1

0.22U_0603_10V7K

12

12

PC188

10U_1206_25VAK

3 5

241

5

5

D8D7D6D

S1S2S3G

4

4

12

PR302

D8D7D6D

S1S2S3G

4.7_1206_5%

12

PC194
680P_0603_50V8J

0.36UH_MPC1040LR36_24A_20%

12

PR304

PR305

10K_0402_1%

3.65K_0805_1%

VSUM

PQ55

SI4856DY-T1-E3_SO8

PL11

HCB4532KF-800T90_1812

1 2

1

+

2

220U_25V_M

12

12

PL12

PR295 0_0603_5%@

1 2

PC186

1 2

+CPU_B+

VCC_PRM

10U_1206_25VAK

12

PL13

12

PR307 0_0603_5%@

1 2

PC196

1 2

0.22U_0603_10V7K

ISEN2

PR294

1_0402_5%

12

PR306

1_0402_5%

VCC_PRM

B+

+CPU_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

2005/10/17 2006/10/17

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

+CPU_CORE

48 49Thursday, Septemb er 06, 2007

1

0.1

of