INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,
AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING T O SALE AND/OR USE OF INTEL PRODUCT S INCLUDING
LIABILITY OR WARRANTIES RELA TING T O FITNES S FOR A PARTICULAR PURPOSE, MERCHANT ABILITY, OR INFRINGEMENT OF ANY
PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving,
life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoev er for conflicts or incompatibilities arising from future
changes to them.
The Intel® Xeon® E5-2400 Product Family may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Requires a system with Intel® Turbo Boost Technology. Intel Turbo Boost Technology and Intel Turbo Boost Technology 2.0 are only
available on select Intel® processors. Consult your PC manufacturer. Performance varies depending on hardware, software, and
system configuration. For more information, visit http://www.intel.com/go/turbo
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained
by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel, Xeon, and the Intel logo are tr ademarks or r egistered tr ad emarks of Intel Corpor ation or its subsidiaries in the United States
This document provides guidelines for the design of thermal and mechanical solutions
for server and workstation processors in the Intel® Xeon® Processor E5-2400 Product
Family platform. The processors covered include those listed in the Intel® Xeon® Processor E5-2400 Product Family Datasheet - Volume One. The components described
in this document include:
• The processor thermal solution (heatsink) and associated retention hardware.
• The LGA1356 socket, the Independent Loading Mechanism (ILM) and back plate.
Material and concepts available in the following documents may be beneficial when
reading this document.
Table 1-1.Reference Documents
DocumentNumberNotes
European Blue Angel Recycling Standards2
Intel® Xeon® Processor E5-2400 Product Family Datasheet -
Volume One
Platform Environment Control Interface (PECI) Specification4
Intel® Xeon® Processor E5-2400 Processor Product Family
Mechanical Model
Intel® Xeon® Processor E5-2400 Processor Product Family
Thermal Model
Manufacturing With Intel Components Using Lead-Free
Technology
Platform Digital Thermal Sensor (DTS) Based Thermal
Specifications and Overview
Notes:
1.Available at http://www.intel.com. Document numbers are subject to change.
2.Available at http://www.blauer-engel.de/en/index.php
3.Available at https://learn.intel.com/portal/scripts/general/logon.aspx.
4.Contact your local Intel Field Sales Representative.
Introduction
3272481
3273221
3273211
3
4
1.2Definition of Terms
Table 1-2.Terms and Descriptions (Sheet 1 of 2)
TermDescription
BypassBypass is the area between a passive heatsink and any object that can act to form a
DTSDigital Thermal Sensor reports a relative die temperature as an offset from TCC
FSCFan Speed Control
IHSIntegrated Heat Spreader: a component of the processor pac k age used to enhance the
ILMIndependent Loading Mechanism provides the force needed to seat the 1356-LGA land
LGA1356 socketThe processor mates with the system board through this surface mount, 1356-contact
PECIThe Platform Environment Control Interface (PECI) is a one- wire in terface that pro vides
Ψ
CA
Ψ
CS
Ψ
SA
duct. For this example, it can be expressed as a dimension away from the outside
dimension of the fins to the nearest surface.
activation temperature.
thermal performance of the package. Component thermal solutions interface with the
processor at the IHS surface.
package onto the socket contacts.
socket.
a communication channel between Intel processor and chipset components to external
monitoring devices.
Case-to-ambient thermal characterization parameter (psi). A measure of thermal
solution performance using t otal package power. Defined as (T
Package Power. Heat source should always be specified for Ψ measurements.
Case-to-sink thermal characterization parameter. A measure of thermal interface
material performance using total package po wer. Defined as (T
Package Power.
Sink-to-ambient thermal characterization parameter. A measure of heatsink thermal
performance using total package power. Defined as (T
– TLA) / Total
CASE
– TS) / Total
CASE
– TLA) / Total Package Power.
S
10 Intel® Xeon® Processor E5-2400 Product Family
Thermal/Mechanical Design Guide
Page 11
Introduction
Table 1-2.Terms and Descriptions (Sheet 2 of 2)
TermDescription
T
CASE
T
CASE_MAX
TCCThermal Control Circuit: Thermal monitor uses the TCC to reduce the die temperature
T
CONTROL
TDPThermal Design Power: Thermal solution should be designed to dissipate this target
Thermal MonitorA power reduction feature designed to decrease temperature after the processor has
Thermal ProfileLine that defines the temperature specification of a processor at a given power level.
TIMThermal Interface Material: The thermally conductive compound between the heatsink
T
LA
T
SA
UA unit of measure used to define server rack spacing height. 1U is equal to 1.75 in, 2U
The case temperature of the p rocessor measure d at the geomet ric center of the topside
of the IHS.
The maximum case temperature as specified in a component specification.
by using clock modulation and/or operating frequency and input voltage adjustment
when the die temperature is very near its operating limits.
T
control.
is a static value below TCC activation used as a trigger point for fan speed
CONTROL
power level. TDP is not the maximum power that the processor can dissipate.
reached its maximum operating temperature.
and the processor case. This material fills the air gaps and voids, and enhances the
transfer of the heat from the processor case to the heatsink.
The measured ambient temperature locally surrounding the proces sor. The ambient
temperature should be measured just upstream of a p assive he atsink or at the fan inle t
for an active heatsink.
The system ambient air temperature external to a system chassis. This temperature is
usually measured at the chassis air inlets.
This chapter describes a surface mount, LGA (Land Grid Array) socket intended for
processors in the E5-2400 Product Family Platform. The socket provides I/O , power and
ground contacts. The socket contains 1356 contacts arrayed about a cavity in the
center of the socket with lead-free solder balls for surface mounting on the
motherboard.
The socket has 1356 contacts with 1.016 mm X 1.016 mm pitch (X by Y) in a 43x41
grid array with 21x17 grid depopulation in the center of the array and selective
depopulation elsewhere.
The socket must be compatible with the package (processor) and the Independent
Loading Mechanism (ILM). The design includes a back plate which is a key contributor
in producing a uniform load on the socket solder joints. Socket loading specifications
are listed in Section 4.4.
Figure 2-1. LGA1356 Socket with Pick and Place Cover Removed
Figure 2-2. LGA1356 Socket Contact Numbering (Top View of Socket)
LGA1356 Socket
14Intel® Xeon® Processor E5-2400 Product Family
Thermal/Mechanical Design Guide
Page 15
LGA1356 Socket
2.1Board Layout
The land pattern for the LGA1356 socket is 40 mils X 40 mils (X by Y). Note that there
is no round-off (conversion) error between socket pitch (1.016 mm) and board pitch
(40 mil) as these values are equivalent.
In general, metal defined (MD) pads perform better than solder mask defined (SMD)
pads under thermal cycling, and SMD pads perform better than MD pads under
dynamic stress. At this time, complete recommendations for pad definition and pad size
do not exist for the LGA1356 socket. See Section 2.9 for more information on pad
definition and pad size.
Figure 2-3. LGA1356 Socket Land Pattern (Top View of Board)
The socket is attached to the motherboard by 1356 solder balls. There are no additional
external methods (that is, screw, extra solder, adhesive, and so on) to attach the
socket.
As indicated in Figure 2-4, the Independent Loading Mechanism (ILM) is not present
during the attach (reflow) process.
Figure 2-4. Attachment to Motherboard
LGA1356 Socket
2.3Socket Components
The socket has two main components, the socket body and Pick and Place (PnP) cover,
and is delivered as a single integral assembly. Refer to Appendix C for detailed
drawings.
2.3.1Socket Body Housing
The housing material is thermoplastic or equivalent with UL 94 V -0 flame rating capable
of withstanding 260 °C for 40 seconds (typical reflow/rework). The socket coefficient of
thermal expansion (in the XY plane), and creep properties, must be such that the
integrity of the socket is maintained for the conditions listed in the LGA1366 Socket
Validation Reports, and the LGA1356 Addendum.
The color of the housing will be dark as compared to the solder balls to provide the
contrast needed for pick and place vision systems.
2.3.2Solder Balls
A total of 1356 solder balls corresponding to the contacts are on the bottom of the
socket for surface mounting with the motherboard.
The socket has the following solder ball material:
• Lead free SAC (SnAgCu) solder alloy with a silver (Ag) content between 3% and
4% and a melting temperature of approximately 217 °C. The alloy must be
16Intel® Xeon® Processor E5-2400 Product Family
Thermal/Mechanical Design Guide
Page 17
LGA1356 Socket
ILM Installation
Pick and
Place Cover
Pin 1
ILM cover
compatible with immersion silver (ImAg) motherboard surface finish and a SAC
alloy solder paste.
The co-planarity (profile) and true position requirements are defined in Appendix C.
2.3.3Contacts
Base material for the contacts is high strength copper alloy.
For the area on socket contacts where processor lands will mate, there is a 0.381 μm
No contamination by solder in the contact area is allowed during solder reflow.
2.3.4Pick and Place Cover
The cover provides a planar surface for vacuum pick up used to place components in
the Surface Mount Technology (SMT) manufacturing line. The cover remains on the
socket during reflow to help prevent contamination during reflow. The cover can
withstand 260 °C for 40 seconds (typical reflow/rework profile) and the conditions
listed in the LGA1366 Socket Validation Reports, and LGA1356 Addendum, without
degrading. Reports are available from socket suppliers listed in Appendix A.
As indicated in Figure 2-5, the Pick and Place cover remains on the socket during ILM
installation. Use of the ILM cover can mitigate against bent socket contacts associated
with reinstalling the Pick and Place cover. A cover should remain on whenever possible
to help prevent damage to the socket contacts. See Section 3.2 and Section 3.3 for
additional information on the ILM cover.
Pick and Place cover retention must be sufficient to support the socket weight during
lifting, translation, and placement (board manufacturing), and during board and
system shipping and handling.
Pick and Place covers are designed to be interchangeable between socket suppliers. As
indicated in Figure 2-5, a Pin1 indicator on the Pick and Place cover provides a visual
reference for proper orientation with the socket.
As indicated in Figure 2-6, access is provided to facilitate manual installation and
removal of the package.
To assist in package orientation and alignment with the socket:
• The package Pin1 triangle and the socket Pin1 chamfer provide visual reference for
proper orientation.
• The package substrate has orientation notches along two opposing edges of the
package, offset from the centerline. The socket has two corresponding orientation
posts to physically prevent mis-orientation of the package. These orientation
features also provide initial rough alignment of package to socket.
• As shown in Figure 2-7, the package substrate has a “-2” mark near the orientation
notch on the Pin 1 side. Similarly, space has been reserved for a “-2” mark on the
motherboard in the Board Keepin / Keepout Z on es in Figure B-1 and Figure B-2.
These matching marks help prevent system assemblers from installing the
incorrect processor into the socket.
• The socket has alignment walls at the four corners to provide final alignment of the
package.
See Appendix D for information regarding a tool designed to provide mechanical
.
Figure 2-6. Package Installation / Removal Features
assistance during processor installation and removal.
LGA1356 Socket
18Intel® Xeon® Processor E5-2400 Product Family
Thermal/Mechanical Design Guide
Page 19
LGA1356 Socket
Figure 2-7. Package and Board Enabling Mark (-2)
2.4.1Socket Standoffs and Package Seating Plane
Standoffs on the bottom of the socket base establish the minimum socket height after
solder reflow and are specified in Appendix C.
Similarly, a seating plane on the topside of the socket establishes the minimum
package height. See Section 3.2 for the calculated IHS height above the motherboard.
2.5Durability
The socket must withstand 30 cycles of processor insertion and removal. The max
chain contact resistance from Table 4-4 must be met when mated in the 1st and 30th
cycles.
The socket Pick and Place cover must withstand 15 cycles of insertion and removal.
2.6Markings
There are three markings on the socket:
• LGA1356: Font type is Helvetica Bold - minimum 6 point (2.125 mm).
• Manufacturer's insignia (font size at supplier's discretion).
• Lot identification code (allows traceability of manufacturing date and location).
All markings must withstand 260 °C for 40 seconds (typical reflow/rework profile)
without degrading, and must be visible after the socket is mounted on the
motherboard.
LGA1356 and the manufacturer's insignia are molded or laser marked on the side wall.
Any actuation must meet or exceed SEMI S8-95 Safety Guidelines for Ergonomics/
Human Factors Engineering of Semiconductor Manufacturing Equipment, example T able
R2-7 (Maximum Grip Forces). The socket must be designed so that it requires no force
to insert the package into the socket.
2.8Socket Size
Socket information needed for motherboard design is given in Appendix C.
This information should be used in conjunction with the reference motherboard keepout
drawings provided in Appendix B to ensure compatibility with the reference thermal
mechanical components.
2.9LGA1356 Socket NCTF Solder Joints
Intel has defined selected solder joints of the socket as non-critical to function (NCTF)
for post environmental testing. The processor signals at NCTF locations are typically
redundant ground or non-critical reserved, so the loss of the solder joint continuity at
end of life conditions will not affect the overall product functionality. Figure 2-8
identifies the NCTF solder joints.
LGA1356 Socket
Since corner pads are often more susceptible to solder joint damage, NCTF locations
are often placed in the corners. When possible, larger pads may be chosen at NCTF
locations to further mitigate against solder joint damage. At this time, complete
recommendations for pad definition and pad size do not exist at NCTF locations. CTF
and NCTF locations are 18mil solder mask defined on Intel reference designs.
Independent Loading Mechanism (ILM) and Back Plate
3Independent Loading
Mechanism (ILM) and Back
Plate
The Independent Loading Mechanism (ILM) provides the force needed to seat the
1356-LGA land package onto the socket contacts. The ILM is physically separate from
the socket body. The assembly of the ILM to the board is expected to occur after wave
solder. The exact assembly location is dependent on manufacturing preference and test
flow.
Note:The ILM has two critical functions: deliver the force to seat the processor onto the
socket contacts and distribute the resulting compressive load evenly through the socket
solder joints.
Note:The mechanical design of the ILM is a key contributor to the over all fun ctionality of the
LGA1356 socket. Intel performs detailed studies on integration of processor package,
socket and ILM as a system. These studies directly impact the design of the ILM. The
Intel reference ILM will be “build to print” from Intel controlled drawings. Intel
recommends using the Intel Reference ILM. Custom non-Intel ILM designs do not
benefit from Intel's detailed studies and may not incorporate critical design
parameters.
3.1Design Concept
The ILM and back plate are assemblies and can be procured from the enabled vendors.
3.1.1ILM Assembly Design Overview
The ILM assembly consists of four major pieces: load lever, load plate, frame and the
captive fasteners.
The load lever and load plate are stainless steel. The frame and fasteners are high
carbon steel with appropriate plating. The fasteners are fabricated from a high carbon
steel. The frame provides the hinge locations for the load lever and load plate.
The ILM assembly design ensures that once assembled to the back plate and the load
lever is closed, the only features touching the board are the captive fasteners. The
nominal gap of the frame to the board is ~1 mm when the load plate is closed on the
empty socket or when closed on the processor package.
When closed, the load plate applies two point loads onto the IHS at the “dimpled”
features shown in Figure 3-1. The reaction force from closing the load plate is
transmitted to the frame and through the captive fasteners to the back plate. Some of
the load is passed through the socket body to the board inducing a slight compression
on the solder joints.
Independent Loading Mechanism (ILM) and Back Plate
3.1.2ILM Back Plate Design Overview
The unified back plate consists of a flat steel back plate with threaded studs for ILM
attach, and internally threaded nuts for heatsink attach. The threaded studs have a
smooth surface feature that provides alignment for the back plate to the motherboard
for proper assembly of the ILM around the socket. A clearance hole is located at the
center of the plate to allow access to test points and backside capacitors. An additional
cut-out on two sides provides clearance for backside voltage regulator components. An
insulator is pre-applied. To stay within the temperature limit of the insulator, remove
the back plate prior to board component rework.
3.1.3Durability
The ILM durability requirement is 30 processor cycles. 1 processor cycle = install
processor, close load plate, latch load lever, unlatch load lever, open load plate.
The ILM durability requirement is 6 assembly cycles. See Section 3.2 for assembly
procedure. 1 assembly cycle = fasten the ILM assembly to the back plate with the four
captive screws, torque to 9 ± 1 inch-pounds, unfasten ILM assembly from the back
plate.
24Intel® Xeon® Processor E5-2400 Product Family
Thermal/Mechanical Design Guide
Page 25
Independent Loading Mechanism (ILM) and Back Plate
Figure 3-2. Back Plate
3.2Assembly of ILM to a Motherboard
The ILM design allows a bottoms up assembly of the components to the board. In step
1 (see Figure 3-3), the back plate is placed in a fixture. Holes in the motherboard
provide alignment to the threaded studs.
In step 2, the ILM assembly is placed over the socket and threaded studs. The Intel
Reference Design ILM cover is not designed to nest over the Pick and Place cover. This
feature helps prevent reinstallation of the Pick and Place cover, a step that can lead to
socket bent contacts.
To prevent the ILM cover from popping off during ILM assembly, the load plate can be
unlatched from the load lever when the fasteners are torqued as shown is Step 3. Using
a T20 Torx* driver, fasten the ILM assembly to the back plate with the four captive
fasteners. Torque to 9 ± 1 inch-pounds.
The Pick and Place cover can then be removed as shown in Step 4, and the load plate
can then closed and latched as shown in Step5.
The length of the threaded studs accommodate board thicknesses from
Step 1: With socket body reflowed
on board, and back plate in fixture,
align board holes to back plate studs.
Step 2: With back plate against
bottom of board, align ILM assembly
to back plate studs.
ILM cover
Pick and
Place Cover
Step 3
Step 4Step 5
Figure 3-3. ILM Assembly
Independent Loading Mechanism (ILM) and Back Plate
26Intel® Xeon® Processor E5-2400 Product Family
Thermal/Mechanical Design Guide
Page 27
Independent Loading Mechanism (ILM) and Back Plate
As indicated in Figure 3-4, socket protrusion and ILM key features prevent 180-degree
rotation of ILM assembly with respect to the socket. The result is a specific Pin 1
orientation with respect to the ILM lever.
Figure 3-4. Pin1 and ILM Lever
3.3ILM Cover
As indicated in Table A-4, ILM covers are available as discrete components and preassembled to the ILM load plate.
The ILM cover will interfere with a processor and pop off if the ILM is closed with a
processor in the socket.
The ILM cover is designed to be interchangeable between different suppliers validated
by Intel. Performance of the pop off feature may decline if the ILM cover supplier is
different than the ILM supplier. The ILM cover can be removed manually if the pop off
feature is not desirable, or not functional.
The ILM cover has UL94 V-0 flammability rating.
The ILM cover durability requirement is 20 cycles (1 cycle = install and remove).
Independent Loading Mechanism (ILM) and Back Plate
28Intel® Xeon® Processor E5-2400 Product Family
Thermal/Mechanical Design Guide
Page 29
LGA1356 Socket, ILM and Back Plate Electrical, Mechanical, and Environmental Specifications
4LGA1356 Socket, ILM and Back
Plate Electrical, Mechanical,
and Environmental
Specifications
This chapter describes the electrical, mechanical, and environmental specifications for
the LGA1356 socket, Independent Loading Mechanism and Back Plate.
4.1Component Mass
Table 4-1.Component Mass
ComponentMass
Socket Body, Contacts and PnP Cover15 gm
ILM Assembly43 gm
Back Plate100 gm
4.2Package/Socket Stackup Height
Table 4-2 provides the stackup height of a processor in the 1356-land LGA package and
LGA1356 socket with the ILM closed and the processor fully seated in the socket.
Table 4-2.1356-land Package and LGA1356 Socket Stackup Height
Integrated Stackup Height (mm)
From Top of Board to Top of IHS
Notes:
1.This data is provided for information only, and is derived from: (a) the height of the socket seating plane
above the motherboard after reflow, given in Appendix C, (b) the height of the packag e, fr om the pac kage
seating plane to the top of the IHS, and accounting for its nominal variation and tolerances that are given
in the corresponding processor EDS and expected values for the follow-on processor.
2.This value is a RSS calculation.
7.753 ± 0.262 mm
4.3Socket Maximum Temperature
The power dissipated within the socket is a function of the current at the pin level and
the effective pin resistance. To ensure socket long term reliability, Intel defines socket
maximum temperature using a via on the underside of the motherboard. Exceeding the
temperature guidance may result in socket body deformation, or increases in thermal
and electrical resistance which can cause a thermal runaway and eventual electrical
failure. The guidance for socket maximum temperature is listed below:
LGA1356 Socket, ILM and Back Plate Electrical, Mechanical, and Environmental Specifications
4.4Loading Specifications
The socket will be tested against the conditions listed in the LGA1366 Socket Validation
Reports, and LGA1356 Addendum, with heatsink, ILM and back plate attached, under
the loading conditions outlined in this chapter.
Table 4-3 provides load specifications for the LGA1356 socket with the ILM and back
plate installed. The maximum limits should not be exceeded during heatsink assembly,
shipping conditions, or standard use condition. Exceeding these limits during test may
result in component failure. The socket body should not be used as a mechanical
reference or load-bearing surface for thermal solutions.
Table 4-3.Socket and ILM Mechanical Specifications
ParameterMinMaxNotes
Static compressive load from ILM to processor
IHS
Thermal Solution Static Compressive Load0 N [0 lbf]266 N [60 lbf]1, 2, 3
Total Static Compressive Load
(ILM plus Heatsink)
Dynamic Compressive Load
(with heatsink installed)
Target Pick and Place Cover allowable removal
force
Load Lever actuation forceN/A38.3 N [8.6 lbf] in the
445 N [100 lbf]623 N [140 lbf]3, 4
445 N (100 lbf)890 N (200 lbf)3, 4
N/A890 N [200 lbf] 1, 3, 5, 6
N/A4.45 - 6.68 N [1.0 -
1.5 lbf]
vertical direction
10.2 N [2.3 lbf] in the
lateral direction.
Notes:
1.These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top
surface.
2.This is the minimum and maximum static force that can be applied by the heatsink and it’s retention
solution to maintain the heatsink to IHS interface. This does not imply the Intel reference TIM is validated
to these limits. TIM load range is documented in Section 5.2 for the Intel Reference Design.
3.Loading limits are for the LGA1356 socket.
4.This minimum limit defines th e compressi ve forc e required to electrically seat the processor onto the sock et
contacts.
5.Dynamic loading is defined as an 11 ms duration average load superimposed on the static load
requirement.
6.T est condition used a heatsink mass of 550 gm [1.21 lb] with 50 g acceler ation measured at heatsi nk mass.
The dynamic portion of this specification in the product application can have flexibility in specific values, but
the ultimate product of mass times acceleration should not exceed this dynamic load.
4.5Electrical Requirements
LGA1356 socket electrical requirements are measured from the socket-seating plane of
the processor to the component side of the socket PCB to which it is attached. All
specifications are maximum values (unless otherwise stated) for a single socket
contact, but includes effects of adjacent contacts where indicated.
30Intel® Xeon® Processor E5-2400 Product Family
Thermal/Mechanical Design Guide
Page 31
LGA1356 Socket, ILM and Back Plate Electrical, Mechanical, and Environmental Specifications
Table 4-4.Electrical Requirements for LGA1356 Socket
ParameterValueComment
The inductance calculated for two contacts,
Mated loop inductance, Loop<3.9 nH
Maximum mutual capacitance, C.<1 pF The capacitance between two contacts
considering one forward conductor an d one return
conductor. These values must be satisfied at the
worst-case height of the socket.
The socket average contact resistance target is
derived from average of every chain contact
resistance for each part used in testing, with a
chain contact resistance defined as the resistance
of each chain minus resistance of shorting bars
divided by number of lands in the daisy chain.
The specification listed is at room temperature
and has to be satisfied at all time.
Socket Contact Resistance: The resistance of
the socket contact, solderball, and interface
resistance to the interposer land.
The specification listed is at room temperature
and has to be satisfied at all time.
Socket Contact Resistance: The resistance of
the socket contact, solderball, and interface
resistance to the interposer land; gaps included.
The bulk resistance increase per contact from
24 °C to 107 °C
4.6Environmental Requirements
The reliability targets in this chapter are based on the expected field use environment
for these products. The test sequence for the LGA1356 socket was developed using the
knowledge-based reliability evaluation methodology, which is acceleration factor
dependent. A simplified process flow of this methodology can be seen in Figure 4-1.
Since the LGA1356 socket is very similar to the LGA1366 socket, the LGA1356 socket is
expected to perform similarly and full validation for the LGA1356 socket is avoided.
This section describes a 1U reference heatsink and thermal design guidelines for the
Intel® Xeon® Processor E5-2400 Product Family.
5.1Boundary Conditions
Table 5-1 provides values for boundary conditions and performance targets used to
generate processor thermal specifications and to provide guidance for heatsink design.
Table 5-1.Values Used to Generate Processor Thermal Specifications
ParameterValue
Altitude, system
ambient temp
TDP
1
Ψ
CA
2
T
LA
3
Airflow
System height
(form factor)
Heatsink
volumetric
Heatsink
technology
5
7
Sea level, 35
50W (4-
core)
o
C/W0.296oC/W0.296oC/W0.315oC/W
0.312
60W70W80W (4-core)95W
o
49
C48.1
9.7 CFM @ 0.23” dP
1U (EEB)
90 x 90 x 25.5 mm (1U/SSI blade)
Cu base, Al fins
4
o
C
0.296
0.298
o
C/W
(8-core),
o
C/W
(6-core)
6
80W (2-core,
1 socket)
o
0.285
C/W
o
C
13 CFM @
0.28” dP
1U
(non-specific,
1-socket)
1. Max target (mean + 3 sigma + offset) for thermal characterization parameter (Section 5.4.1).
2. Local ambient temperature of the air entering the heatsink.
3. Airflow through the heatsink fins with zero bypa ss. Max target for pressure drop (dP) meas ured in inches H2O.
4. Reference system configuration. Processor is downstream from me mory in EEB (Entry-Level Electronics Bay).
Values above do not apply to LR-DIMM in an Intel Reference Design. Ducting is utilized to direct airflow.
5. Dimensions of heatsink do not include socket or processor.
6. Heatsink height + socket/processor height (Table 4-2) complies with TEB 1U Rack Height Constraints
(36 mm) in EEB Specification 2011, and with Maximum Component Height (33.5 mm) in SSI Compute Blade
Specification, both at http://www.ssiforum.org.
Table 5-2 provides approximate boundary conditions and approximate performance
expectations in Compact Electronics Bay. These values are not used to generate
processor thermal specifications, but may provide guidance for heatsink design.
Table 5-2.Performance Expectations in Compact Electronics Bay (CEB)
inches H
Electronics Bay). With the values above, the 25.5mm tall heatsink can meet the processor thermal
specifications in Intel's Reference Design 10.5x12 inches CEB board. However, these CEB values are
not used to generate processor thermal specifications. Ducting is utilized to direct airflow.
Constraints (36 mm) in EEB Specification 2011, and with Maximum Component Height (33.5 mm)
in SSI Compute Blade Specification, both at http://www.ssiforum.org.
0.273oC/W0.265oC/W0.264oC/W0.278oC/W
13 CFM @ 0.32” dP
4
1U (CEB)
90 x 90 x 25.5 mm (1U/SSI blade)
7
O.
2
Cu base, Al fins
0.265
0.269
6
Thermal Solutions
o
C/W (8-core),
o
C/W (6-core)
Table 5-1 and Table 5-2 spe c ify ΨCA and pressure drop targets for specific airflows. To
determine ΨCA and pressure drop targets for other airflows, use Best-fit equations in
Figure 5-1. Heatsink detailed drawings are in Appendix A.
Figure 5-1. Best-fit Equations
34Intel® Xeon® Processor E5-2400 Product Family
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Thermal Solutions
5.2Assembly
Figure 5-2. 1U Reference Heatsink Assembly
The assembly process for the 1U reference heatsink begins with application of
Honeywell PCM45F thermal interface material to improve conduction from the IHS.
Tape and roll format is recommended. Pad size is 35 x 35 mm, thickness is 0.25 mm.
Next, position the heatsink such that the heatsink fins are parallel to system airflow.
While lowering the heatsink onto the IHS, align the four captive screws of the heatsink
to the four threaded nuts of the back plate.
Using a #2 Phillips driver, torque the four captive screws to 8 inch-pounds. Fastener
sequencing, in other words starting the threads on all four screws before torquing, may
mitigate against cross threading.
This assembly process is designed to produce a static load of 39 - 51 lbf, for 0.062" -
0.100" board thickness respectively. Honeywell PCM45F is expected to meet the
performance targets in Table 5-1 and Table 5-2 from 30 - 60 lbf. From Table 4-3, the
Heatsink Static Compressive Load of 0 - 60 lbf allows for designs that vary from the 1U
reference heatsink. Example: A customer’s unique heatsink with very little static load
(as little as 0 lbf) is acceptable from a socket loading perspective as long as the
thermal specifications are met.
Compliance to Board Keepout Zones in Appendix A is assumed for this
assembly process.
TIM should be verified to be within its recommended shelf life before use.
Surfaces should be free of foreign materials prior to application of TIM.
Use isopropyl alcohol and a lint free cloth to remove old TIM before applying new TIM.
5.3Structural Considerations
Target mass of heatsinks should not exceed 500 gm.
From Table 4-3, the Dynamic Compressive Load of 200 lbf max allows for designs that
exceed 500 gm as long as the mathematical product does not exceed 200 lbf. Example:
A heatsink of 2-lb mass (908 gm) x 50 g (acceleration) x 2.0 Dynamic Amplification
Factor = 200 lbf. The Total Static Compressive Load (Table 4-3) should also be
considered in dynamic assessments.
Direct contact between back plate and chassis pan will help minimize board deflection
during shock. Placement of board-to-chassis mounting holes also impacts board
deflection and resultant socket solder ball stress. Customers need to assess shock for
their designs as their heatsink retention (back plate), heatsink mass and chassis
mounting holes may vary.
Thermal Solutions
5.4Thermal Design
5.4.1Thermal Characterization Parameter
The case-to-local ambient Thermal Characterization Parameter (ΨCA) is defined by:
Equation 5-1.ΨCA = (T
Where:
T
CASE
T
LA
TDP=TDP (W) assumes all power dissipates through the integrated heat
Equation 5-2.Ψ
= ΨCS + ΨSA
CA
Where:
Ψ
CS
Ψ
SA
Figure 5-3 illustrates the thermal characterization parameters.
CASE
- TLA) /
TDP
=Processor case temperature (°C). For T
appropriate External Design Specification (EDS).
=Local ambient temperature in chassis at processor (°C).
spreader. This inexact assumption is convenient for heatsink design.
TTVs are often used to dissipate TDP. Correction offsets account for
differences in temperature distribution between processor and TTV.
=Thermal characterization parameter of the TIM (°C/W) is dependent
on the thermal conductivity and thickness of the TIM.
=Thermal characterization parameter from heatsink-to-local ambient
(°C/W) is dependent on the thermal conductivity and geometry of the
heatsink and dependent on the air velocity through the heatsink fins.
In server platforms, processors often share airflow provided by system fans with other
system components such as chipset, memory and hard drives. As such, the thermal
control features in chipset, memory and other components not covered in this
document, should influence system fan speed control to reduce fan power consumption
and help systems meet acoustic targets.
The addition of thermal sensors placed in the system (for example, on front panel or
motherboard) to augment internal device sensors (for example, in processor, chipset
and memory) will improve the ability to implement need-based fan speed control. The
placement of system sensors in cooling zones, where each zone has dedicated fan(s),
can improve the ability to tune fan speed control for optimal performance and/or
acoustics.
System events such as fan or power supply failure, device events such as TCC
Activation or THERMTRIP, and maintenance events such as hot swap time allowance,
need to be comprehended to implement appropriate fan speed control to prevent
undesirable performance or loss of data. For more information on device events and
features see the appropriate processor Datasheet.
Tcontrol and its upper and lower limits defined by hysteresis, can be used to avoid fan
speed oscillation and undesirable noise variations.
5.6Thermal Features
More information regarding processor thermal features is contained in the appropriate
datasheet.
Improved acoustics and lower fan power can be achieved by understanding the
Table 5-3.T
T
CONTROL
CONTROL
DTS ≤ T
DTS > T
and DTS relationship, and implementing fan speed control accordingly.
and DTS Relationship
ConditionFan Speed Control
CONTROL
CONTROL
Adjust fan speed to maintain DTS ≤ T
Adjust fan speed to keep T
EDS, or adjust fan speed to keep DTS at or below the DTS based thermal profile in
the EDS.
CASE
CONTROL
at or below the T
5.6.1.1Sign Convention and Temperature Filtering
Digital Thermal Sensor (DTS) and Tcontrol are relative die temperatures offset below
the Thermal Control Circuit (TCC) activation temperature. As such, negative sign
conventions are understood. While DTS and Tcontrol are available over PECI and MSR,
use of these values in fan speed control algorithms requires close attention to sign
convention. See Table 5-4 for the sign convention of various sources.
Table 5-4.Sign Convention
MSR (BWG)PECI (EDS)
DTS
T
CONTROL
(+) using
PACKAGE_THERM_STA TUS (22:16,
Digital Readout)
(+) using TEMPERATURE_TARGET
(15:8, Temperature Control Offset)
(-) using GetTemp()
(+) using T emperature T arget R ead
from RdPkgConfig()
.
based thermal profile in the
CASE
Where a positive (+) sign convention is shown in Table 5-4, no sign bit is actually
assigned, so writers of firmware code may mistakenly assign a positive sign convention
in firmware equations. As appropriate, a negative sign should be introduced.
Where a negative (-) sign convention is shown in Table 5-4, a sign bit is assigned, so
firmware code will read a negative sign convention in firmware equations, as desired.
DTS obtained thru MSR (PACKAGE_THERM_STATUS) is an instantaneous value. As
such, temperature readings over short time intervals may vary considerably using this
MSR. For this reason, DTS obtained thru PECI GetTemp() may be preferred since
temperature filtering will provide the thermal trend.
5.6.1.2Tcontrol Relief
Factory configured T
Letter or may be extracted by issuing a Mailbox or an RDMSR instruction. See the
appropriate External Design Specification (EDS) for more information.
Due to increased thermal headroom based on thermal characterization on the latest
processors, customers have the option to reduce T
factory configured values.
In some situations, use of T
acoustics. There are no plans to change Intel's specification or the factory configured
T
CONTROL
values on individual processors.
CONTROL
values are available in the appropriate Dear Customer
to values lower than the
CONTROL
CONTROL
Relief can reduce average fan power and improve
38Intel® Xeon® Processor E5-2400 Product Family
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Thermal Solutions
Table 5-5.T
To implement this relief, customers must re-write code to set T
CONTROL
to the reduced
values provided in the table below. Implementation is optional. Alternately, the factory
configured T
CONTROL
configured and Relief. Regardless of T
values can still be used, or some value between factory
CONTROL
values used, BIOS needs to identify the
processor type.
CONTROL
Relief for Intel® Xeon® Processor E5-2400 Product Family
TDP, # CoreT
95W 8C-62.30 GHz or lower-10
95W 6C-62.40 GHz or lower-10
70W 8C-61.80 GHz or lower-10
60W 6C-62.00 GHz or lower-10
80W 4C-62.20 GHz or lower-10
80W 2C, 1S-62.80 GHz or lower-10
CONTROL
ReliefMax Core FrequencyFactory Configured
In some cases, use of Tcontrol Relief as the trigger point for fan speed control may
result in excessive TCC activation. To avoid this, the adjusted trigger point for fan
speed control (FSC) is defined as:
Tcontrol_FSC = - T
CONTROL
+ Tcontrol_offset
Tcontrol_offset must be chosen such that Tcontrol_FSC < Tcontrol Relief. As such,
Tcontrol_FSC is an earlier trigger point for fan speed control, as compared to Tcontrol
Relief, and can be interpreted as overcooling. When overcooling to Tcontrol_FSC,
margin as defined in Section 5.8.3 and Section 5.8.6 can be ignored. As compared to
cooling to Tcontrol Relief, overcooling to Tcontrol_FSC:
• May increase frequency benefit from Intel TBT as defined in Section 5.6.3.
• Will increase acoustics
• May result in lower wall power
Customers must characterize a Tcontrol_offset value for their system to meet their
goals for frequency, acoustics and wall power.
5.6.2Short Duration TCC Activation and Catastrophic Thermal
Management for Intel® Xeon® Processor E5-2400 Product
Family
Systems designed to meet thermal capacity may encounter short durations of
throttling, also known as TCC activation, especially when running non-steady processor
stress applications. This is acceptable and is functionally within the intended
temperature control parameters of the processor. Such short duration TCC activ ation is
not expected to provide noticeable reductions in application performance, and is
typically within the normal range of processor to processor performance variation.
Normal amounts of TCC activation occur at PECI values less than -0.25. Such
occurrences may cause utilities or operating systems to issue error log.
PECI = -0.25 indicates a catastrophic thermal failure condition in all studies conducted.
As such, to help prevent loss of data, a soft shutdown can be initiated at PECI = -0.25.
Since customer designs, boundary conditions, and failure scenarios differ, this guidance
should be tested in the customer's system to prevent loss of data during shutdown.
PECI command GetTemp() can be used to obtain non-integer PECI values.
Intel® Turbo Boost Technology (Intel®TBT), available on certain processor SKUs,
opportunistically , and automatically, allows the processor to run faster than the marked
frequency if the part is operating below its power, temperature and current limits.
Thermal Solutions
Heatsink performance (lower Ψ
factors that can impact the amount of Intel TBT frequency benefit. Intel TBT
performance is also constrained by ICC, and VCC limits.
Increased IMON accuracy may provide more Intel TBT benefit on TDP limited
applications, as compared to lower Ψ
these workloads.
With Intel TBT enabled, the processor may run more consistently at higher power levels
(but still within TDP), and be more likely to operate above T
when Intel TBT is disabled. This may result in higher acoustics.
5.7Thermal Guidance
5.7.1Thermal Excursion
Under fan failure or other anomalous thermal excursions, Tcase may exceed the
thermal profile for a duration totaling less than 360 hours per year without affecting
long term reliability (life) of the processor. For more typical thermal excursions,
Thermal Monitor is expected to control the processor power level as long as conditions
do not allow the Tcase to exceed the temperature at which Thermal Control Circuit
(TCC) activation initially occurred. Under more severe anomalous thermal excursions
when the processor temperature cannot be controlled at or below this Tcase level by
TCC activation, then data integrity is not assured. At some higher threshold,
THERMTRIP_N will enable a shut down in an attempt to prevent permanent damage to
the processor. Thermal Test Vehicle (TTV) may be used to check anomalous thermal
excursion compliance by ensuring that the processor Tcase value, as measured on the
TTV, does not exceed Tcase_max at the anomalous power level for the environmental
condition of interest. This anomalous power level is equal to 75% of the Thermal
Design Power (TDP) limit.
as described in Section 5.4.1) is one of several
CA
, as temperature is not typically the limiter for
CA
CONTROL
, as compared to
This guidance can be applied to 95W, 80W, 70W, 60W Standard or Basic SKUs in the
Intel® Xeon® Processor E5-2400 Product Family.
5.7.2Absolute Processor Temperature
Intel does not test any third party software that reports absolute processor
temperature. As such, Intel cannot recommend the use of software that claims this
capability. Since there is part-to-part variation in the TCC (thermal control circuit)
activation temperature, use of software that reports absolute temperature can be
misleading.
See the appropriate Datasheet for details regarding use of TEMPERATURE_TARGET
register to determine the minimum absolute temperature at which the TCC will be
activated and PROCHOT# will be asserted.
40Intel® Xeon® Processor E5-2400 Product Family
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Thermal Solutions
5.8DTS Based Thermal Specification
5.8.1Compliance to Tcase Based Thermal Profile
Processor heatsink design must still comply with the Tcase based thermal profile
provided in the Intel® Xeon® Processor E5-2400 Product Family Datasheet - Volume One. Heatsink design compliance can be determined with thermocouple and TTV as
with previous processors.
The heat sink is sized to comply with the Tcase based thermal profile. Customers have
an option to either follow processor based Tcase spec or follow the DTS based thermal
specification. In some situations, implementation of DTS based thermal specification
can reduce average fan power and improve acoustics as compared to the Tcase based
thermal profile.
When all cores are active, a properly sized heatsink will be able to meet the DTS based
thermal specification. When all cores are not active or when Intel Turbo Boost
Technology is active, attempting to comply with the DTS based thermal specification
may drive system fans to maximum speed. In such situations, the T
will be below the T
5.8.2Considerations for Follow-on Processor
based thermal profile by design.
CASE
temperature
CASE
The follow-on processor in the platform will have new capabilities as compared to the
Intel® Xeon® Processor E5-2400 Product Family. For example, the follow-on processor
has a new Package Configuration Space (PCS) command to read margin (M) from the
processor: RdPkgConfig(), Index 10. For the Intel® Xeon® Processor E5-2400 Product
Family, margin (M) must be calculated in firmware.
In the following sections, implementation details specified for the Intel® Xeon®
Processor E5-2400 Product Family can also be used for the follow-on processor.
For more information regarding the differences between the follow-on processor and
the Intel® Xeon® Processor E5-2400 Product Family see Platform Digital Thermal Sensor (DTS) Based Thermal Specifications and Overview.
5.8.3DTS Based Thermal Profile, Tcontrol and Margin for the
Intel® Xeon® Processor E5-2400 Product Family
The calculation of the DTS based thermal specification is based on both Tcontrol and
the DTS Based Thermal Profile (T
+ Ψpa are the intercept and slope terms from the T
LA
appropriate External Design Specification (EDS). To implement the DTS based thermal
specification, these equations must be programmed in firmware. Since the equations
differ with processor SKU, SKUs can be identified by TDP, Core Count and a profile
identifier (CSR bits). For associated commands, see Platform Digital Thermal Sensor
(DTS) Based Thermal Specifications and Overview.
DTS
):
equations in the
DTS
Power (P) is calculated in Section 5.8.4. As power dynamically changes, the
specification also changes, so power and T
calculations are recommended every 1
DTS
second.
Correction factor (F) compensates for the error in power monitoring. The current
The Tcontrol portion of the DTS based thermal specification is a one time calculation:
T
control_spec
= TEMPERATURE_TARGET [23:16] - Tcontrol + Tcontrol_offset
Tcontrol is defined in Section 5.6.1.1. Tcontrol_offset is defined in Section 5.6.1.2.
The final DTS based thermal specification is the maximum of both:
T
DTS_max
= max[T
control_spec
, T
DTS
]
The margin (M) between the actual die temperature and the DTS based thermal
specification is used in the fan speed control algorithm. When M < 0, increase fan
speed. When M ≥ 0, fan speed may decrease.
M = T
DTS_max
- Tsensor
OR
M = T
DTS_ave
– Tsensor
Tsensor represents the absolute temperature of the processor as power changes:
Tsensor = TEMPERATURE_TARGET [23:16] + DTS
T
DTS_ave
is defined in Section 5.8.5.
TEMPERATURE_TARGET [23:16], the temperature at which the processor thermal
control circuit activates, is a one time PECI readout: RdPkgConfig(), Temperature
Target Read, 23:16.
DTS, the relative temperature from thermal control circuit activation, is negative by
definition, and changes instantaneously. DTS command info is given in Section 5.6.1.1.
5.8.4Power Calculation for the Intel® Xeon® Processor E52400 Product Family
To imple ment DTS based thermal specification, average power over time must be
calculated:
P = (E2 - E1) / (t2 - t1)
Where:
t1 = time stamp 1
t2 = time stamp 2
E1 = Energy readout at time t1
E2 = Energy readout at time t2
The recommended time interval between energy readings is 1 second. This helps
ensure the power calculation is accurate by making the error between time stamps
small as compared to the duration between time stamps.
For details regarding energy readings, see Platform Digital Thermal Sensor (DTS)
Based Thermal Specifications and Overview.
5.8.5Averaging the DTS Based Thermal Specification for the
Intel® Xeon® Processor E5-2400 Product Family
Averaging the DTS Based Thermal Specification helps keep the rate of change of the
temperature specification on the same scale as the actual processor temperature, and
helps avoid rapid changes in fan speed when power changes rapidly.
42Intel® Xeon® Processor E5-2400 Product Family
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Thermal Solutions
An exponential average of the specification can be calculated using a two time constant
model:
= αf x DT x T
T
DTS_f
T
DTS_s
T
DTS_ave
= αs x DT x T
= C x T
DTS_max
DTS_f
Where:
T
DTS_max
T
DTS_f
T
DTS_ave
and αs are the time constant coefficients
α
f
is the instantaneous spec
and T
are the fast and slow time averages
DTS_s
is the final two time constant average specification
C is a scale factor
DT is the scan rate and is recommended to be approximately 1 second
Table 5-6 below shows the coefficients recommended for averaging. These values may
change per processor SKU. Customers should tune these coefficients based on their
thermal solutions.
Table 5-6.Averaging Coefficients
+ T
DTS_max
+ T
+ (1-C) x T
DTS_f_previous
DTS_s_previous
DTS_s
x (1- αf x DT)
x (1- αs x DT)
Heatsink
Performance
Low1.00.040.30based on typical processor
Medium1.00.070.30based on typical processor
High1.00.100.40based on typical processor
α
(1/s)αs (1/s)CComment
f
5.8.6Capabilities for the Follow-on Processor
For the follow-on processor, the intercept and slope terms from the T
(TLA, Ψpa), as defined in Section 5.8.3, are stored in the processor. This allows margin
(M) to be reported by the processor. The PECI command for margin (M) will be
RdPkgConfig(), Index 10.
M < 0; gap to spec, fan speed must increase
M ≥ 0; margin to spec, fan speed may decrease
Use of RdPkgConfig(), Index 10 with the Intel® Xeon® Processor E5-2400 Product
Family will return an illegal command.
For the follow-on processor, coefficients (α
(F) will be factory configured.
Test Conditions, Qualification and Visual Criteria vary by customer.
Socket Test Conditions are provided in the LGA1366 Socket Validation Reports, and
LGA1356 Addendum and are available from socket suppliers listed in Appendix A.
6.2Intel Reference Component Validation
Intel tests reference components both individually and as an assembly on mechanical
test boards, and assesses performance to the envelopes specified in previous sections
by varying boundary conditions.
While component validation shows that a reference design is tenable for a limited range
of conditions, customers need to assess their specific boundary conditions and perform
reliability testing based on their use conditions.
Intel reference components are also used in board functional tests to assess
performance for specific conditions.
6.2.1Board Functional Test Sequence
Each test sequence should start with components (baseboard, heatsink assembly, and
so on) that have not been previously submitted to any reliability testing.
The test sequence should always start with a visual inspection after assembly and
BIOS/Processor/memory test. The stress test should be then followed by a visual
inspection and then BIOS/Processor/memory test.
6.2.2Post-Test Pass Criteria
The post-test pass criteria are:
1. No significant physical damage to the heatsink and retention hardware.
2. Heatsink remains seated and its bottom remains mated flat against the IHS
surface. No visible gap between the heatsink base and processor IHS. No visible tilt
of the heatsink with respect to the retention hardware.
3. No signs of physical damage on baseboard surface due to impact of heatsink.
4. No visible physical damage to the processor package.
5. Successful BIOS/Processor/memory test.
6. Thermal compliance testing to demonstrate that the case temperature specification
can be met.
6.2.3Recommended BIOS/Processor/Memory Test Procedures
This test is to ensure proper operation of the product before and after environmental
stresses, with the thermal mechanical enabling components assembled. The test shall
be conducted on a fully operational baseboard that has not been exposed to any
battery of tests prior to the test being considered.
The testing setup should include the following components, properly assembled and/or
connected:
• Appropriate system baseboard.
• Processor and memory.
• All enabling components, including socket and thermal solution parts.
The pass criterion is that the system under test shall successfully complete the
checking of BIOS, basic processor functions and memory, without any errors.
6.3Material and Recycling Requirements
Material shall be resistant to fungal growth. Examples of non-resistant materials
include cellulose materials, animal and vegetable based adhesives, grease, oils, and
many hydrocarbons. Synthetic materials such as PVC formulations, certain
polyurethane compositions (for example, polyester and some polyethers), plastics
which contain organic fillers of laminating materials, paints, and varnishes also are
susceptible to fungal growth. If materials are not fungal growth resistant, then MILSTD-810E, Method 508.4 must be performed to determine material performance.
Any plastic component exceeding 25 gm should be recyclable per the European Blue
Angel recycling standards.
The following definitions apply to the use of the terms lead-free, Pb-free, and RoHS
compliant.
Lead-free and Pb-free: Lead has not been intentionally added, but lead may still
exist as an impurity below 1000 ppm.
RoHS compliant: Lead and other materials banned in RoHS Directive are either
(1) below all applicable substance thresholds as proposed by the EU or (2) an
approved/pending exemption applies.
Note:RoHS implementation details are not fully defined and may change.
§
46Intel® Xeon® Processor E5-2400 Product Family
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Component Suppliers
AComponent Suppliers
Various suppliers have developed support components for processors in the Intel®
Xeon® Processor E5-2400 Product Family-based platform. These suppliers and
components are listed as a convenience to customers. Intel does not guarantee
quality, reliability, functionality or compatibility of these components. The supplier list
and/or the components may be subject to change without notice. Customers are
responsible for the thermal, mechanical, and environmental verification of the
components with the supplier.
A.1Intel Enabled Supplier Information
Performance targets for heatsinks are described in Section 5.1. Mechanical drawings
are provided in Appendix A. Mechanical models are listed in Table 1-1. Heatsinks
assemble to server back plate Table A-4.
A.1.1Intel Reference Thermal Solution
Customers can purchase the Intel reference thermal solutions from the suppliers listed
in Table A-1.
Table A-1. Suppliers for the Intel Reference Thermal Solution
AssemblyComponentDescriptionSupplier PNSupplier Contact Info
1) Standard - Design and technology similar to Intel Reference or Collaboration designs, however, may not meet thermal
requirements for all processor SKUs.
2) Performance - 1U Heatsink designed with premium materials or technology expected to provide optimum thermal performance
for all processor SKUs.
3) Low Cost - 2U Cost-Optimized Heatsink, expected to meet thermal targets for lower power processor SKUs.
Tower
Alternative
URS Heatsink
Pedestal/2U
Active
Heatsink
Standard
Standard
Active
TaiSol Corporation
1A0-9051000960-A
www.Taisol.com
Thermaltake
CL-P0485
www.Thermaltake.com
Asia Vital Components
SS40W00001
www.avc.com.tw
Dynatron Corporation* (Top
Motor/Dynaeon)
G555
www.Dynatron-Corp.com
up to 95W capable
up to 95W capable
up to 95W capable
up to 95W capable
A.1.4Socket, ILM and Back Plate
The LGA1356 Socket, ILM and Back Plate are described in Chapter 2 and Chapter 3,
respectively. Socket mechanical drawings are provided in Appendix C. Mechanical
models are listed in Table 1-1.
Table A-4. LGA1356 Socket, ILM and Back Plate
ItemIntel PNFoxconnTycoMol ex
ILM AssemblyD92428-003PT44L13-41021554105-1475939000
ILM Assembly
with ILM Cover
ILM CoverG14954-001012-1000-57761-2134711-1475930403
Back Plate D92433-002PT44P12-41041981467-2475937000
LGA1356
Socket
Supplier Contact InfoJulia Jiang
G13666-001PT44L13-41111-1554105-1475939070
E81085-001PE135627-4371-01H 1554116-1475943001
juliaj@foxconn.com
408-919-6178
Billy Hsieh
billy.hsieh@tycoel
ectronics.com
+81 44 844 8292
§
Carol Liang
carol.liang@molex.com
Tel #: +86-21-5048-0889 ext
3301
50Intel® Xeon® Processor E5-2400 Product Family
Thermal/Mechanical Design Guide
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Mechanical Drawings
BMechanical Drawings
Table B-1.Mechanical Drawing List
DescriptionFigure
Board Keepin / Keepout Zones (Sheet 1 of 4)Figure B-1
Board Keepin / Keepout Zones (Sheet 2 of 4)Figure B-2
Board Keepin / Keepout Zones (Sheet 3 of 4)Figure B-3
Board Keepin / Keepout Zones (Sheet 4 of 4)Figure B-4
1U Reference Heatsink Assembly (Sheet 1 of 2)Figure B-5
1U Reference Heatsink Assembly (Sheet 2 of 2)Figure B-6
1U Reference Heatsink Fin and Base (Sheet 1 of 2)Figure B-7
1U Reference Heatsink Fin and Base (Sheet 2 of 2)Figure B-8
Heatsink Shoulder Screw (1U, 2U and Tower)Figure B-9
Heatsink Compression Spring (1U, 2U and Tower)Figure B-10
Heatsink Retaining Ring (1U, 2U and Tower)Figure B-11
Heatsink Load Cup (1U, 2U and Tower)Figure B-12
2U Collaborative Heatsink Assembly (Sheet 1 of 2)Figure B-13
2U Collaborative Heatsink Assembly (Sheet 2 of 2)Figure B-14
2U Collaborative Heatsink Volumetric (Sheet 1 of 2)Figure B-15
2U Collaborative Heatsink Volumetric (Sheet 2 of 2)Figure B-16
Tower Collaborative Heatsink Assembly (Sheet 1 of 2)Figure B-17
Tower Collaborative Heatsink Assembly (Sheet 2 of 2)Figure B-18
Tower Collaborative Heatsink Volumetric (Sheet 1 of 2)Figure B-19
Tower Collaborative Heatsink Volumetric (Sheet 2 of 2)Figure B-20
1U Reference Heatsink Assembly with TIM (Sheet 1 of 2)Figure B-21
1U Reference Heatsink Assembly with TIM (Sheet 2 of 2)Figure B-22
2U Reference Heatsink Assembly with TIM (Sheet 1 of 2)Figure B-23
2U Reference Heatsink Assembly with TIM (Sheet 2 of 2)Figure B-24
Tower Reference Heatsink Assembly with TIM (Sheet 1 of 2)Figure B-25
Tower Reference Heatsink Assembly with TIM (Sheet 2 of 2)Figure B-26
25.5 mm Reference Heatsink Assembly (Sheet 1 of 2)Figure B-27
25.5 mm Reference Heatsink Assembly (Sheet 2 of 2)Figure B-28
25.5 mm Reference Heatsink Fin and Base (Sheet 1 of 2)Figure B-29
25.5 mm Reference Heatsink Fin and Base (Sheet 2 of 2)Figure B-30
25.5 mm Reference Heatsink Assembly with TIM (Sheet 1 of 2)Figure B-31
25.5 mm Reference Heatsink Assembly with TIM (Sheet 2 of 2)Figure B-32
Embedded Server SKU’s target higher case temperatures and/or NEBS thermal profiles
for embedded communications server and storage form factors. This section describes
reference heatsinks for NEBS (Network Equipment Building Systems) compliant ATCA
(Advanced Telecommunications Computing Architecture) systems. These higher case
temperature processors are sufficient for any form factor that needs to meet NEBS
requirements.
E.1Performance Targets
Table E-1 provides boundary conditions and performance targets for 1U and ATCA
heatsinks. These values are used to generate processor thermal specifications and to
provide guidance for heatsink design.
Detailed drawings for the ATCA reference heatsink can be found in Section E.3.
0
0.4
0.8
1.2
1.6
2
0
0.5
1
1.5
2
2.5
05101520253035
ΔP, inch water
Ψca, C/W
CFM Through Fins
ΔP = 1.3e-04CFM2 +1.1e-02CFM
Mean Ψca= 0.337 + 1.625 CFM
-0.939
Table E-1 above specifies ΨCA and pressure drop targets and Figure E-1 below shows
and pressure drop for the ATCA heatsink versus the airflow provided. Best-fit
Ψ
CA
equations are provided to prevent errors associated with reading the graph.
Figure E-1. ATCA Heatsink Performance Curves
Embedded Thermal Solutions
Other LGA1366 compatible thermal solutions may work with the same retention.
®
ATCA 13 mm heatsink performance using Intel
Xeon® processor 5500 series TTV.
E.2Thermal Design Guidelines
E.2.1High Case Temperature Thermal Profile
Processors that offer a High case temperature thermal profile are specified in the
Intel® Xeon® Processor E5-2400 Product Family Datasheet - Volume One.
High case temperature thermal profiles help relieve thermal constraints for Short-Term
NEBS conditions. To help reliability, processors must meet the nominal thermal profile
under standard operating conditions and can only rise up to the Short-Term spec for
NEBS excursions (see Figure E-2). The definition of Short-Term time is clearly defined
for NEBS Level 3 conditions but the key is that it cannot be longer than 360 hours per
year.
Fan speed control is treated the same as standard processors. When DTS (Digital
Te mperature Sensor) value is less than Tcontrol, the thermal profile can be ignored.
94Intel® Xeon® Processor E5-2400 Product Family
Thermal/Mechanical Design Guide
Page 95
Embedded Thermal Solutions
Thermal Profile
40
50
60
70
80
90
051015202530354045505560
Power [ W ]
Tcase [C]
Tc = 0.302 * P + 66.9
Nominal Thermal Profile
Tc = 0.302* P + 51.9
Short-term Thermal Profile may only be used for short term
excursions to higher ambient temperatures, not to exceed 360
hours per year
Figure E-2. NEBS Thermal Profile
\
Short-Term Thermal Profile
Notes:
1.) The Nominal Thermal Profile must be used for all normal operating conditions, or for products that do not
require NEBS Level 3 compliance.
2.) The Short-Term Thermal Profile may only be used for short-term excursions to higher ambient operating
temperatures, not to exceed 360 hours per year as compliant with NEBS Level 3.
3.) Implementation of either thermal profile should result in virtually no TCC activation.
4.) Utilization of a thermal solution that exceeds the Short-Term Thermal Profile, or which operate s at the Shor tTerm Thermal Profile for a duration longer than the limits specified in Note 3 above, do not meet the processo r
thermal specifications and may result in permanent damage to the processor.
§
E.3Mechanical Drawings and Supplier Information
See Appendix B for retention and keep out drawings.
The part number below represent Intel reference designs for a ATCA reference
heatsink. Customer implementation of these components may be unique and require
validation by the customer. Customers can obtain these components directly from the
supplier below.
Table E-3. Embedded Heatsink Component Suppliers
ComponentDescriptionSupplier PNSupplier Contact Info
ATCA Reference Heat Sink Assembly (Sheet 1 of 2)Figure E-3
ATCA Reference Heat Sink Assembly (Sheet 2 of 2)Figure E-4
ATCA Reference Heatsink Fin and Base (Sheet 1 of 2)Figure E-5
ATCA Reference Heatsink Fin and Base (Sheet 2 of 2)Figure E-6