Intel BFCBASE - Motherboard - 7300, Xeon 7300 Series, Xeon 7200 Series Datasheet
Intel® Xeon® Processor 7200 Series
and 7300 Series
Datasheet
September 2008
Notice: The Intel® Xeon® Processor 7200 Series and 7300 Series may contain design defects or errors known
as errata which may cause the product t o deviate from published specifications. Current characterized errata are
available on request.
Document Number: 318080-002
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Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoev er for conflicts or incompatibilities arising from future
changes to them.
The Intel
®
Xeon® Processor 7200 Series and 7300 Series may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be
obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com
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.
Check with your vendor for more information.
* Other names and brands may be claimed as the property of others.
Copyright © 2006 - 2008, Intel Corporation
2 Document Number: 318080-002
Contents
1Introduction..............................................................................................................9
1.1 Terminology .....................................................................................................11
1.2 State of Data........................ .......................... .. .. ......................... .. ...................13
1.3 References.......................................................................................................13
2 Electrical Specifications...........................................................................................15
2.1 Front Side Bus and GTLREF ......................... ... .. .. ........................... .....................15
2.2 Decoupling Guidelines ........................................................................................15
2.2.1 VCC
2.2.2 VTT
2.2.3 Front Side Bus AGTL+ Decoupling ......................................... .. ... .. ............16
2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking.......................................16
2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])..................................17
2.3.2 PLL Power Supply...................................................................................17
2.4 Voltage Identification (VID) ................................................................................17
2.5 Reserved, Unused, or Test Signals.......................................................................20
2.6 Front Side Bus Signal Groups............. .. ........................... ....................................20
2.7 CMOS Asynchronous and Open Drain Asynchronous Signals....................................22
2.8 Test Access Port (TAP) Connection.......................................................................22
2.9 Mixing Processors..............................................................................................23
2.10 Absolute Maximum and Minimum Ratings........................................ .. .. ... ..............23
2.11 Processor DC Specifications................................................................................24
2.11.1 Flexible Motherboard Guidelines (FMB)......................................................25
2.11.2 Platform Environmental Control Interface (PECI) DC Specifications................35
2.11.3 VCC Overshoot Specification....................................................................37
2.11.4 AGTL+ FSB Specifications........................................................................38
2.12 Front Side Bus AC Specifications .................................................. .......................40
2.13 Processor AC Timing Waveforms .........................................................................45
3 Mechanical Specifications........................................................................................57
3.1 Package Mechanical Drawing...................... .........................................................57
3.2 Processor Component Keepout Zones....................... .. ............................ .. ............60
3.3 Package Loading Specifications .......................................... .. .. ........................... ..66
3.4 Package Handling Guidelines............................. .. .. .. ........................... .................67
3.5 Package Insertion Specifications................................................... .. .. .. ... ..............67
3.6 Processor Mass Specifications .............................................................................67
3.7 Processor Materials............................................................................................67
3.8 Processor Markings............................................................................................68
3.9 Processor Pin-Out Coordinates ............................................................................69
4 Pin Listing ...............................................................................................................71
4.1 Pin Assignments................................................................................................71
4.1.1 Pin Listing by Pin Name...........................................................................71
4.1.2 Pin Listing by Pin Number........................................................................79
5 Signal Definitions ....................................................................................................87
5.1 Signal Definitions. ............................ .. ........................... ....................................87
6 Thermal Specifications ............................................................................................95
6.1 Package Thermal Specifications.... ........................... ............................................95
6.1.1 Thermal Specifications............................................................................95
6.1.2 Thermal Metrology ............................................................................... 102
6.2 Processor Thermal Features.............................................................................. 103
6.2.1 Thermal Monitor Features...................................................................... 103
6.2.2 Thermal Monitor................................................................................... 103
Decoupling......................................................................................16
Decoupling......................................................................................16
Document Number: 318080-002 3
6.2.3 Thermal Monitor 2 ....................................................... .. .......................104
6.2.4 On-Demand Mode.................................................................................105
6.2.5 PROCHOT# Signal .............................................. .. .......................... .. .. ..106
6.2.6 FORCEPR# Signal.................................................................................106
6.2.7 THERMTRIP# Signal......... .. .. ......................... .. .. .......................... .. .. ......106
6.3 Platform Environment Control Interface (PECI)....................................................107
6.3.1 Introduction.........................................................................................107
6.3.2 PECI Specifications ...............................................................................108
7Features................................................................................................................111
7.1 Power-On Configuration Options........................................................................111
7.2 Clock Control and Low Power States...... .. ................................................... .. .. .. ..111
7.2.1 Normal State .......................................................................................112
7.2.2 HALT or Extended HALT State.................................................................112
7.2.3 Stop-Grant State..................................................................................114
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant
Snoop State.........................................................................................115
7.3 Enhanced Intel SpeedStep® Technology............................................................. 115
7.4 System Management Bus (SMBus) Interface .......................................................116
7.4.1 SMBus Device Addressing ......................................................................117
7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions.......................118
7.4.3 Processor Information ROM (PIROM).......................................................119
7.4.4 Checksums..........................................................................................137
7.4.5 Scratch EEPROM...................................................................................137
8 Boxed Processor Specifications.............................................................................. 139
8.1 Introduction....................................................................................................139
8.2 Thermal Specifications........................... .. .. ..................................................... ..139
8.2.1 Boxed Processor Cooling Requirements....................................................139
9 Debug Tools Specifications ....................................................................................141
9.1 Debug Port System Requirements........... ........................... ................................141
9.2 Logic Analyzer Interface (LAI) ...........................................................................141
9.2.1 Mechanical Considerations .....................................................................141
9.2.2 Electrical Considerations........................................................................142
4 Document Number: 318080-002
Figures
2-1 Quad-Core Intel® Xeon® L7345 Processor Load Current versus Time .....................27
2-2 Dual-Core Dual-Core Intel® Xeon® Processor 7200 Series Load Current
versus Time.......................... ... ......................... .. .. ......................... .. .................28
2-3 Quad-Core Intel
Time28
2-4 Quad-Core Intel® Xeon® X7350 Processor Load Current versus Time .................29
2-5 Quad-Core Intel
Tolerance Load Lines ....................................... ......................... .. .. .....................31
2-6 Quad-Core Intel® Xeon® X7350 Processor VCC Static and Transient Tolerance
Load Lines......................................... .. ......................... .......................... .. ........32
2-7 Quad-Core Intel® Xeon® L7345 Processor V
Load Lines......................................... .. ......................... .......................... .. ........33
2-8 Dual-Core Intel® Xeon® Processor 7200 Series VCC Static and Transient
Tolerance Load Lines ....................................... ......................... .. .. .....................34
2-9 Input Device Hysteresis .....................................................................................37
2-10 VCC Overshoot Example Waveform......................................................................38
2-11 Electrical Test Circuit .........................................................................................46
2-12 TCK Clock Waveform .........................................................................................46
2-13 Differential Clock Waveform................................................................................47
2-14 Differential Clock Crosspoint Specification.............................................................47
2-15 BCLK Waveform at Processor Pad and Pin.............................................................48
2-16 FSB Common Clock Valid Delay Timing Waveform ............................ .. .. ... .. .. .. .. .. .. ..48
2-17 FSB Source Synchronous 2X (Address) Timing Waveform .......................................49
2-18 FSB Source Synchronous 4X (Data) Timing Waveform............................................50
2-19 TAP Valid Delay Timing Waveform.......................................................................51
2-20 Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform............... 51
2-21 THERMTRIP# Power Down Sequence ...................................................................51
2-22 SMBus Timing Waveform....................................................................................52
2-23 SMBus Valid Delay Timing Waveform...................................................................52
2-24 Voltage Sequence Timing Requirements ...............................................................53
2-25 FERR#/PBE# Valid Delay Timing .............................................. .. .........................54
2-26 VID Step Timings..............................................................................................54
2-27 VID Step Times and Vcc Waveforms ....................................................................55
3-1 Processor Package Assembly Sketch ....................................................................57
3-2 Processor Package Drawing (Sheet 1 of 2)............................................................58
3-3 Processor Package Drawing (Sheet 2 of 2)............................................................59
3-4 Top Side Board Keepout Zones (Part 1)................................................................61
3-5 Top Side Board Keepout Zones (Part 2)................................................................62
3-6 Bottom Side Board Keepout Zones.......................................................................63
3-7 Board Mounting-Hole Keepout Zones ...................................................................64
3-8 Volumetric Height Keep-Ins................................................................................65
3-9 Processor Topside Markings................................................................................68
3-10 Processor Bottom-Side Markings .........................................................................68
3-11 Processor Pin-Out Coordinates, Top View..............................................................69
6-1 Quad-Core Intel® Xeon® E7300 Processor Thermal Profile.....................................97
6-2 Quad-Core Intel® Xeon® X7350 Processor Thermal Profile.....................................98
6-3 Quad-Core Intel® Xeon® L7345 Processor Thermal Profile................................... 100
6-4 Dual-Core Intel® Xeon® Processor 7200 Series Thermal Profile ........................... 101
6-5 Case Temperature (TCASE) Measurement Location.............................................. 103
6-6 Thermal Monitor 2 Frequency and Voltage Ordering ............................................. 105
6-7 PECI Topology ................................................................................................ 107
®
Xeon® Processor 7200 Series and 7300 Series Load Current versus
®
Xeon® Processor 7200 Series and 7300 Series VCC Static and Transient
Static and Transient Tolerance
CC
Document Number: 318080-002 5
6-8 Conceptual Fan Control Diagram For a PECI-Based Platform ..................... ... .. .. ......108
7-1 Stop Clock State Machine..................................................................................114
7-2 Logical Schematic of SMBus Circuitry..................................................................117
Tables
1-1 Quad-Core Intel® Xeon® Processor 7300 Series Processor Features ........................10
1-2 Dual-Core Intel® Xeon® Processor 7200 Series Processor Features .........................10
2-1 Core Frequency to FSB Multiplier Configuration......................................................17
2-2 BSEL[2:0] Frequency Table.................................................................................17
2-3 Voltage Identification Definition ...........................................................................19
2-4 FSB Signal Groups.............................................................................................21
2-5 AGTL+ Signal Description Table...........................................................................22
2-6 Non AGTL+ Signal Description Table.....................................................................22
2-7 Signal Reference Voltages...................................................................................22
2-8 Processor Absolute Maximum Ratings............................. .. .. ..................................23
2-9 Voltage and Current Specifications.......................................................................25
2-10 VCC Static and Transient Tolerance......................................................................30
2-11 AGTL+ Signal Group DC Specifications............................................. .....................34
2-12 CMOS Signal Input/Output Group DC Specifications................................................35
2-13 Open Drain Signal Group DC Specifications ...........................................................35
2-14 SMBus Signal Group DC Specifications..................................................................35
2-15 PECI DC Electrical Limits.....................................................................................36
2-16 VCC Overshoot Specifications..............................................................................37
2-17 AGTL+ Bus Voltage Definitions ............................................................................39
2-18 FSB Differential BCLK Specifications.....................................................................39
2-19 Front Side Bus Differential Clock AC Specifications .................................................40
2-20 Front Side Bus Common Clock AC Specifications ....................................................40
2-21 FSB Source Synchronous AC Specifications............................................................41
2-22 Miscellaneous GTL+ AC Specifications...................................................................42
2-23 Front Side Bus AC Specifications (Reset Conditions) ...............................................42
2-24 TAP Signal Group AC Specifications ......................................................................42
2-25 VID Signal Group AC Specifications ......................................................................44
2-26 SMBus Signal Group AC Specifications ..................................................................44
3-1 Processor Loading Specifications..........................................................................66
3-2 Package Handling Guidelines...............................................................................67
3-3 Processor Materials............................................................................................67
4-1 Pin Listing by Pin Name ......................................................................................71
4-2 Pin Listing by Pin Number ...................................................................................79
5-1 Signal Definitions...............................................................................................87
6-1 Quad-Core Intel® Xeon® E7300 Processor Thermal Specifications ...........................96
6-2 Quad-Core Intel® Xeon® E7300 Processor Thermal Profile Table............... ..............97
6-3 Quad-Core Intel® Xeon® X7350 Processor Thermal Specifications........................ .. .98
6-4 Quad-Core Intel® Xeon® X7350 Processor Thermal Profile Table.............................99
6-5 Quad-Core Intel® Xeon® L7345 Processor Thermal Specifications ................ .... .. .. ...99
6-6 Quad-Core Intel® Xeon® L7345 Processor Thermal Profile....................................100
6-7 Dual-Core Intel® Xeon® Processor 7200 Series Thermal Specifications ..................101
6-8 Dual-Core Intel® Xeon® Processor 7200 Series Thermal Profile................. ............102
6-9 BREQ# signal assertion during power on.............................................................109
6-10 PECI Address assigned to processor ...................................................................109
6-11 GetTemp0() and GetTemp1() Error Codes........... .. .. .. .. ........................... ... .. .. .. ....110
7-1 Power-On Configuration Option pins...................................................................111
6 Document Number: 318080-002
7-2 Extended HALT Maximum Power......... .. ......................... .. .......................... ........ 113
7-3 Memory Device SMBus Addressing..................................................................... 118
7-4 Read Byte SMBus Packet.................................................................................. 118
7-5 Write Byte SMBus Packet ................................................................................. 118
7-6 Processor Information ROM Data Sections .......................................................... 119
7-7 128 Byte ROM Checksum Values ....................................................................... 137
Document Number: 318080-002 7
Revision History
Document
Number
318080 -001 • Initial Release September 2007
318080 -002 • Changed Product Name to Intel
Revision Description Date
®
7300 Series
• Updated Power Specifications
• The character byte ordering was reversed for the following fields:
SQNUM: S-Spec QDF Number
PREV: Package Revision
PPN: Processor Part Number
• Updated the Processor Mechanical drawings to add an optional small
shallow depression in the top right-hand side corner of the integrated
heat spreader (IHS). This feature, which supports anti-mixing, may be
seen on some processor packages. There are no major electrical,
mechanical, or thermal differences in the form, fit or function of the
processors with or without this feature.
• Update d PROC_ID[1:0] Definition
Xeon® Processor 7200 Series and
September 2008
§
8 Document Number: 318080-002
Introduction
1 Introduction
ALL INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE.
The Intel® Xeon® Processor 7200 Series and 7300 Series are multi-processor servers
utilizing four Intel® CoreTM microarchitecture cores. These processors are based on
Intel’s 65 nanometer process technology combining high performance with the power
efficiencies of a low-power microarchitecture. The Quad-Core Intel
Series consists of two die, each die containing two processor cores. The Dual-Core
®
Xeon® 7200 Series consists of two die, each die containing one processor core.
Intel
All processors maintain the tradition of compatibility with IA-32 software. Some key
features include on-die, 64 KB Level 1 instruction data caches per die and 2x4MB
shared Level 2 cache with Advanced Transfer Cache Architecture. The processor’s Data
Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests
occurs, resulting in reduced bus cycle penalties and improved performance. The 1066
MHz Front Side Bus (FSB) is a quad-pumped bus running off a 266 MHz system clock
making 8.5 GBytes per second data transfer rates possible. The Quad-Core Intel
Xeon® X7350 processor offers higher clock frequencies than the other Quad-Core
®
Xeon® Processor 7300 Series for platforms that are targeted for the
Intel
performance optimized segment. The Quad-Core Intel® Xeon® L7345 Processor is a
lower voltage, lower power processor.
®
Xeon® 7300
®
Enhanced thermal and power management capabilities are implemented including
Thermal Monitor (TM1), Thermal Monitor 2 (TM2) and Enhanced Intel SpeedStep
®
Technology. TM1 and TM2 provide efficient and effective cooling in high temperature
situations. Enhanced Intel SpeedStep Technology allows trade-offs to be made
between performance and power consumption. This may lower average power
consumption (in conjunction with OS support).
®
The Intel
Xeon® Processor 7200 Series and 7300 Series features include Advanced
Dynamic Execution, enhanced floating point and multi-media units, Streaming SIMD
Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3). Advanced Dynamic
Execution improves speculative execution and branch prediction internal to the
processor. The floating point and multi-media units include 128-bit wide registers and a
separate register for data movement. SSE3 instructions provide highly efficient doubleprecision floating point, SIMD integer, and memory management operations.
®
The Intel
Xeon® Processor 7200 Series and 7300 Series support Intel® 64 as an
enhancement to Intel's IA-32 architecture. This enhancement allows the processor to
execute operating systems and applications written to take advantage of the 64-bit
extension technology. Further details on Intel
model can be found in the Intel
®
64 and IA-32 Architectures Software Developer's
®
64 Technology and its programming
Manual.
®
In addition, the Intel
Xeon® Processor 7200 Series and 7300 Series support the
Execute Disable Bit functionality. When used in conjunction with a supporting operating
system, Execute Disable allows memory to be marked as executable or non executable.
This feature can prevent some classes of viruses that exploit buffer overrun
vulnerabilities and can thus help improve the overall security of the system. Further
details on Execute Disable can be found at
http://www.intel.com/cd/ids/developer/asmo-na/eng/149308.htm.
Document Number: 318080-002 9
The Intel® Xeon® Processor 7200 Series and 7300 Series support Intel® Virtualization
Te chnology for hardware-assisted virtualization within the processor. Intel
Virtualization Technology is a set of hardware enhancements that can improve
virtualization solutions. Intel Virtualization Technology is used in conjunction with
Virtual Machine Monitor software enabling multiple, independent software
environments inside a single platform. Further details on Intel Virtualization T echnology
can be found at http://developer.intel.com/technology/vt.
®
The Intel
Xeon® Processor 7200 Series and 7300 Series are intended for high
performance multi-processor server systems. The processors support a Multi
Independent Bus (MIB) architecture with one processor on each bus. The MIB
architecture provides improved performance by allowing increased FSB speeds and
bandwidth. All versions of the Intel
®
Xeon® Processor 7200 Series and 7300 Series will
include manageability features. Components of the manageability features include an
OEM EEPROM and Processor Information ROM which are accessed through an SMBus
interface and contain information relevant to the particular processor and system in
which it is installed. The Intel
packaged in a 604-pin Flip Chip Micro Pin Grid Array (FC-mPGA6) package and utilizes
a surface-mount Zero Insertion Force (ZIF) mPGA604 socket. The Intel
®
Xeon® Processor 7200 Series and 7300 Series is
®
Xeon®
Processor 7200 Series and 7300 Series support 40-bit addressing.
Table 1-1. Quad-Core Intel® Xeon® Processor 7300 Series Processor Features
Introduction
# of Processor
Cores
4 32 KB instruction
L1 Cache per core
32 KB data
L2 Advanced
Transfer Cache
4M Shared L2
Cache per die
8M Total Cache
Front Side Bus
Frequency
1066 MHz FC-mPGA6
Table 1-2. Dual-Core Intel® Xeon® Processor 7200 Series Processor Features
# of Processor
Cores
2 32 KB instruction
®
Xeon® Processor 7200 Series and 7300 Series-based platforms implement
Intel
independent core voltage (V
voltage (V
TT
L1 Cache per core
32 KB data
) power planes for each processor. FSB termination
CC
) is shared and must connect to all FSB agents. The processor core voltage
L2 Advanced
Transfer Cache
4M L2 Cache per die
8M Total Cache
Front Side Bus
Frequency
1066 MHz FC-mPGA6
utilizes power delivery guidelines specified by VRM/EVRD 11.0 and its associated load
line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 11.0 Design Guidelines for further details). VRM/EVRD 11.0 will support the
power requirements of all frequencies of the processors including Flexible Motherboard
Guidelines (FMB) (see Section 2.11.1). Refer to the appropriate platform design
guidelines for implementation details.
®
The Intel
Xeon® Processor 7200 Series and 7300 Series supports 1066 MHz Front
Side Bus operation. The FSB utilizes a split-transaction, deferred reply protocol and
Source-Synchronous Transfer (SST) of address and data to improve performance. The
processor transfers data four times per bus clock (4X data transfer r ate, as in AGP 4X).
Along with the 4X data bus, the address bus can deliver addresses two times per bus
clock and is referred to as a ‘double-clocked’ or a 2X address bus. In addition, the
Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 8.5 GBytes per second. The FSB is
also used to deliver interrupts.
Package
Package
10 Document Number: 318080-002
Introduction
Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages.
Section 2.1 contains the electrical specifications of the FSB while implementation
details are fully described in the appropriate platform design guidelines (refer to
Section 1.3).
1.1 Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the asserted state when driven to a low level. For example, when RESET# is low, a
reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
Commonly used terms are explained here for clarification:
• Enhanced Intel SpeedStep
Technology is the next generation implementation of the Geyserville technology
which extends power management capabilities of servers.
• FC-mPGA6 — The Intel
available in a Flip-Chip Micro Pin Grid Array 6 package, consisting of a processor
core mounted on a pinned substrate with an integrated heat spreader (IHS). This
packaging technology employs a 1.27 mm [0.05 in] pitch for the substrate pins.
• mPGA604 — The Intel® Xeon® Processor 7200 Series and 7300 Series package
mates with the system board through this surface mount, 604-pin, zero insertion
force (ZIF) socket.
• Processor core – Processor core with integrated L1 cache. L2 cache and system
bus interface are shared between the two cores on the die. All AC timing and signal
integrity specifications are at the pads of the processor die.
• FSB (Front Side Bus) – The electrical interface that connects the processor to the
chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
• Multi Independent Bus (MIB) – A front side bus architecture with one processor
on each bus, rather than a FSB shared between multiple processor agents. The MIB
architecture provides improved performance by allowing increased FSB speeds and
bandwidth.
• Flexible Motherboard Guidelines (FMB) – Are estimates of the maximum
values the Intel® Xeon® Processor 7200, 7300 Series will have over certain time
periods. The values are only estimates and actual specifications for future
processors may differ.
• Functional Operation – Refers to the normal operating conditions in which all
processor specifications, including DC, AC, FSB, signal quality, mechanical and
thermal are satisfied.
• Storage Conditions – Refers to a non-operational state. The processor may be
installed in a platform, in a tray , or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor pins should not be
connected to any supply voltages, have any I/Os biased or receive any clocks.
Upon exposure to “free air” (that is, unsealed packaging or a device removed from
packaging material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.
®
Technology — Enhanced Intel SpeedStep®
®
Xeon® Processor 7200 Series and 7300 Series package is
Document Number: 318080-002 11
Introduction
• Processor Information ROM (PIROM) — A memory device located on the
processor and accessible via the System Management Bus (SMBus) which contains
information regarding the processor’s features. This device is shared with the
Scratch EEPROM, is programmed during manufacturing, and is write-protected.
• Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory)
— A memory device located on the processor and addressable via the SMBus which
can be used by the OEM to store information useful for system management.
• SMBus — System Management Bus. A two-wire interface through which simple
system and power management related devices can communicate with the rest of
the system. It is based on the principals of the operation of the I
2
C* two-wire serial
bus from Phillips Semiconductor.
Note: I2C is a two-wire communications bus/protocol developed by Phillips.
SMBus is a subset of the I
Implementations of the I
2
C bus/protocol and was developed by Intel.
2
C bus/protocol or the SMBus bus/protocol may
require licenses from various entities, including Phillips Electronics N.V. and
North American Phillips Corporation.
• Priority Agent – The priority agent is the host bridge to the processor and is
typically known as the chipset.
• Symmetric Agent – A symmetric agent is a processor which shares the same I/O
subsystem and memory array, and runs the same operating system as another
processor in a system. Systems using symmetric agents are known as Symmetric
Multiprocessing (SMP) systems.
• Integrated Heat Spreader (IHS) – A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
• Thermal Design Power – Processor thermal solutions should be designed to meet
this target. It is the highest expected sustainable power while running known
power intensive real applications. TDP is not the maximum power that the
processor can dissipate.
•Intel® 64 – Instruction set architecture and programming environment of Intel’s
64-bit processors, which are a superset of and compatible with IA-32. This 64-bit
instruction set architecture was formerly known as IA-32 with EM64T or Intel
®
EM64T.
• Platform Environment Control Interface (PECI) – A proprietary one-wire bus
interface that provides a communication channel between Intel processor and
chipset components to external thermal monitoring devices, for use in fan speed
control. PECI communicates readings from the processor’s Digital Thermal Sensors
(DTS). The DTS replaces the thermal diode available in previous processors.
®
• Intel
Virtualization Technology – Processor virtualization which when used in
conjunction with Virtual Machine Monitor software enables multiple, robust
independent software environments inside a single platform.
• VRM (Voltage Regulator Module) – DC-DC converter built onto a module that
interfaces with a card edge socket and supplies the correct voltage and current to
the processor based on the logic state of the processor VID bits.
• EVRD (Enterprise Voltage Regulator Down) – DC-DC converter integrated
onto the system board that provides the correct voltage and current to the
processor based on the logic state of the processor VID bits.
• V
• V
• V
– The processor core power supply.
CC
– The processor ground.
SS
– FSB termination voltage.
TT
12 Document Number: 318080-002
Introduction
1.2 State of Data
This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales
office that you have the latest datasheet before finalizing a design
1.3 References
Material and concepts available in the following documents may be beneficial when
reading this document:
Document
®
AP-485, Intel
®
Intel
64 and IA-32 Architectures Software Developer's Manual
Processor Identification and the CPUID Instruction 241618 1
• Volume 1: Basic Architecture
• Volume 2A: Instruction Set Reference, A-M
• Volume 2B: Instruction Set Reference, N-Z
• Volume 3A: System Programming Guide Part 1
• Volume 3B: System Programming Guide, Part 2
®
IA-32 Intel
Documentation Changes
IA-32 Intel
Intel
Architecture and Intel® 64 Software Developer's Manual
®
Architecture Optimization Reference Manual 248966 1
®
Extended Memory 64 Technology
• Volume I
• Volume 2
®
Intel
Virtualization Technology for IA-32 Processors (VT-x) Preliminary
Specification
Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon®
Processor 7300 Series Specification Update
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD)
11.0 Design Guidelines
EPS12V Power Supply Design Guide: A Server system Infrastructure (SSI)
Specification for Entry Chassis Power Supplies
Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon®
Processor 7300 Series Thermal / Mechanical Design Guide
®
Intel
Xeon® Processor 7200 Series and 7300 Series Package Mechanical Models 1
mPGA604 Socket Design Guide 254239 1
®
Intel
Xeon® Processor 7200 Series and 7300 Series Enabled Components (CEK)
Thermal Models
®
Xeon® Processor 7200 Series and 7300 Series Enabled Components (CEK)
Intel
Mechanical Models
Document
Number
1
253665
253666
253667
253668
253669
252046
300834
300835
C97063 1
318081 1
315889 1
318086 1
Notes
1
1
1
2
1
1
Intel® Xeon® Processor 7200 Series and 7300 Series Boundary Scan Descriptive
Language (BSDL) Model
Notes:
1. Document is available publicly at http://developer.intel.com.
2. Document available on www.ssiforum.org.
Document Number: 318080-002 13
1
§
Introduction
14 Document Number: 318080-002
Electrical Specifications
2 Electrical Specifications
2.1 Front Side Bus and GTLREF
Most Intel® Xeon® Processor 7200 Series and 7300 Series FSB signals use Assisted
Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides
improved noise margins and reduced ringing through low voltage swings and controlled
edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the
high logic level and termination. AGTL+ output buffers differ from GTL+ buffers with
the addition of an active PMOS pull-up transistor to “assist” the pull-up resistors during
the first clock of a low-to-high voltage transition. Platforms implement a termination
voltage level for AGTL+ signals defined as V
power planes for each processor (and chipset), separate V
necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address buses have made
signal integrity considerations and platform design methods even more critical than
with previous processor families. Design guidelines for the processor FSB are detailed
in the appropriate platform design guidelines (refer to Section 1.3).
The AGTL+ inputs require reference voltages (GTLREF_DATA_MID,
GTLREF_DAT A_END , GTLREF_ADD_MID and GTLREF_ADD_END) which are used by the
receivers to determine if a signal is a logical 0 or a logical 1. GTLREF_DATA_MID and
GTLREF_DATA_END are used for the 4X front side bus signaling group and
GTLREF_ADD_MID and GTLREF_ADD_END are used for the 2X and common clock front
side bus signaling groups. GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END must be generated on the baseboard (See
Table 2-17 for GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID and
GTLREF_ADD_END specifications). Refer to the applicable platform design guidelines
for details. Termination resistors (R
silicon and are terminated to VTT. The on-die termination resistors are always enabled
on the processor to control reflections on the transmission line. Intel chipsets also
provide on-die termination, thus eliminating the need to terminate the bus on the
baseboard for most AGTL+ signals.
) for AGTL+ signals are provided on the processor
TT
. Because platforms implement separate
TT
and VTT supplies are
CC
Some FSB signals do not include on-die termination (R
the baseboard. See Table 2-4 and Table 2-6 for details regarding these signals.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for
AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog
signal simulation of the FSB, including trace lengths, is highly recommended when
designing a system. Contact your Intel Field Representative to obtain the processor
signal integrity models, which includes buffer and package models.
2.2 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large average current swings between low and full power states.
This may cause voltages on power planes to sag below their minimum values if bulk
decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic
capacitors, supply current during longer lasting changes in current demand by the
component, such as coming out of an idle condition. Similarly, they act as a storage
well for current when entering an idle condition from a running condition. Care must be
taken in the baseboard design to ensure that the voltage provided to the processor
Document Number: 318080-002 15
) and must be terminated on
TT
Electrical Specifications
remains within the specifications listed in Table 2-9. Failure to do so can result in
timing violations or reduced lifetime of the component. For further information and
guidelines, refer to the appropriate platform design guidelines.
2.2.1 V
2.2.2 V
Decoupling
CC
Vcc regulator solutions need to provide bulk capacitance with a low Effective Series
Resistance (ESR). Bulk decoupling must be provided on the baseboard to handle large
current swings. The power delivery solution must ensure the voltage and current
specifications are met (as defined in Table 2-9). For further information regarding
power delivery, decoupling and layout guidelines, refer to the appropriate platform
design guidelines.
Decoupling
TT
Bulk decoupling must be provided on the baseboard. Decoupling solutions must be
sized to meet the expected load. To ensure optimal performance, various factors
associated with the power delivery solution must be considered including regulator
type, power plane and trace sizing, and component placement. A conservative
decoupling solution consists of a combination of low ESR bulk capacitors and high
frequency ceramic capacitors. For further information regarding power delivery,
decoupling and layout guidelines, refer to the appropriate platform design guidelines.
2.2.3 Front Side Bus AGTL+ Decoupling
The processor integrates signal termination on the die, as well as a portion of the
required high frequency decoupling capacitance on the processor package. However,
additional high frequency capacitance must be added to the baseboard to properly
decouple the return currents from the FSB. Bulk decoupling must also be provided by
the baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in
the appropriate platform design guidelines.
2.3 Front Side Bus Clock (BCLK[1:0]) and Processor
Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous processor generations, the processor core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is set during
manufacturing. The default setting is for the maximum speed of the processor.
The processor core frequency is configured during reset by using values stored
internally during manufacturing. The stored value sets the highest bus fraction at which
the particular processor can operate. If lower speeds are desired, the appropriate ratio
can be configured via the CLOCK_FLEX_MAX Model Specific Register (MSR).
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread
spectrum clocking. Processor DC and AC specifications for the BCLK[1:0] inputs are
provided in Table 2-18 and Table 2-19, respectively. These specifications must be met
while also meeting signal integrity requirements as outlined in Table 2-18. The
processor utilizes differential clocks. Table 2-1 contains processor core frequency to
FSB multipliers and their corresponding core frequencies.
16 Document Number: 318080-002
Electrical Specifications
Table 2-1. Core Frequency to FSB Multiplier Configuration
Core Frequency to FSB
Multiplier
1/6 1.60 GHz 1, 2, 3, 4
1/7 1.86 GHz 1, 2, 3
1/8 2.13 GHz 1, 2, 3
1/9 2.40 GHz 1, 2, 3
1/10 2.66 GHz 1, 2, 3
1/11 2.93 GHz 1, 2, 3
Notes:
1. Individual processors operate only at or below the frequency marked on the package.
2. Listed frequencies are not necessarily committed production frequencies.
3. For valid processor core frequencies, refer to the Dual-Core Intel® Xeon® Processor 7200 Series and
Quad-Core Intel® Xeon® Processor 7300 Series Specification Update.
4. The lowest bus ratio supported is 1/6.
Core Frequency with
266 MHz FSB Clock
Notes
2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])
Upon power up, the FSB frequency is set to the maximum supported by the individual
processor. BSEL[2:0] are CMOS outputs that are used to select the FSB frequency.
Please refer to Table 2-11 for DC specifications. Table 2-2 defines the possible
combinations of the signals and the frequency associated with each combination. The
frequency is determined by the processor(s), chipset, and clock synthesizer. All FSB
agents must operate at the same core and FSB frequency. See the appropriate
platform design guidelines for further details.
Table 2-2. BSEL[2:0] Frequency Tab le
BSEL2 BSEL1 BSEL0 Bus Clock Frequency
000 266 MHz
001 Reserved
010 Reserved
011 Reserved
100 Reserved
101 Reserved
110 Reserved
111 Reserved
2.3.2 PLL Power Supply
An on-die PLL filter solution is implemented on the processor. The V
to provide power to the on chip PLL of the processor. Please refer to Table 2-9 for DC
specifications. Refer to the appropriate platform design guidelines for decoupling and
routing guidelines.
2.4 Voltage Identification (VID)
The Voltage Identification (VID) specification for the processor is defined by the
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0
Design Guidelines. The voltage set by the VID signals is the reference VR output
voltage to be delivered to the processor Vcc pins. VID signals are asynchronous CMOS
input is used
CCPLL
Document Number: 318080-002 17
Electrical Specifications
outputs. Please refer to Table 2-12 for the DC specifications for these signals. A voltage
range is provided in Table 2-3 and changes with frequency. The specifications have
been set such that one voltage regulator can operate with all supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core frequency may have different default VID settings. This is
reflected by the VID range values provided in Table 2-3.
The processor uses six voltage identification signals, VID[6:1], to support automatic
selection of power supply voltages. Table 2-3 specifies the voltage level corresponding
to the state of VID[6:1]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers
to a low voltage level. The definition provided in Table 2-3 is not related in any way to
previous Intel
®
Xeon® processors or voltage regulator designs. If the processor socket
is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply the
voltage that is requested, the voltage regulator must disable itself. See the Voltage
Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines for further details.
Although the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 11.0 Design Guidelines defines VID [7:0], VID 7 and VID 0 are not used on the
Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon®
Processor 7300 Series.
The Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon®
Processor 7300 Series provides the ability to operate while transitioning to an adjacent
VID and its associated processor core voltage (V
). This will represent a DC shift in
CC
the load line. It should be noted that a low-to-high or high-to-low voltage state change
may result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted. Table 2-10 includes VID step
sizes and DC shift ranges. Minimum and maximum voltages must be maintained as
shown in Table 2-2 and Table 2-3.
The VRM or EVRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in Table 2-9
and Table 2-10, while AC specifications are included in Table 2-25. Refer to the Voltage
Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines for further details.
Power source characteristics must be guaranteed to be stable whenever the supply to
the voltage regulator is stable.
18 Document Number: 318080-002
Electrical Specifications
Table 2-3. Voltage Identification Definition
VID5
VID4
VID3
VID2
HEX
VID6
400
mV
200
mV
100
mV
50
mV
25
mV
VID1
12.5
mV
V
CC_MAX
HEX
7A111101 0.8500 3C 0 1 1 1 1 0 1.2375
7811110
7611101
7411101
7211100
7011100
6E11011
6C11011
6A11010
0 0.8625 3A 0 1 1 1 0 1 1.2500
1 0.8750 38 0 1 1 1 0 0 1.2625
0 0.8875 36 0 1 1 0 1 1 1.2750
1 0.9000 34 0 1 1 0 1 0 1.2875
0 0.9125 32 0 1 1 0 0 1 1.3000
1 0.9250 30 0 1 1 0 0 0 1.3125
0 0.9375 2E 0 1 0 1 1 1 1.3250
1 0.9500 2C 0 1 0 1 1 0 1.3375
68 1 1 0 1 0 0 0.9625 2A 0 1 0 1 0 1 1.3500
66 1 1 0 0 1 1 0.9750 28 0 1 0 1 0 0 1.3625
64 1 1 0 0 1 0 0.9875 26 0 1 0 0 1 1 1.3750
62 1 1 0 0 0 1 1.0000 24 0 1 0 0 1 0 1.3875
60 1 1 0 0 0 0 1.0125 22 0 1 0 0 0 1 1.4000
5E 1 0 1 1 1 1 1.0250 20 0 1 0 0 0 0 1.4125
5C 1 0 1 1 1 0 1.0375 1E 0 0 1 1 1 1 1.4250
5A 1 0 1 1 0 1 1.0500 1C 0 0 1 1 1 0 1.4375
58 1 0 1 1 0 0 1.0625 1A 0 0 1 1 0 1 1.4500
56 1 0 1 0 1 1 1.0750 18 0 0 1 1 0 0 1.4625
54 1 0 1 0 1 0 1.0875 16 0 0 1 0 1 1 1.4750
52 1 0 1 0 0 1 1.1000 14 0 0 1 0 1 0 1.4875
50 1 0 1 0 0 0 1.1125 12 0 0 1 0 0 1 1.5000
4E 1 0 0 1 1 1 1.1250 100010001.5125
4C 1 0 0 1 1 0 1.1375 0E0001111.5250
4A 1 0 0 1 0 1 1.1500 0C0001101.5375
48 1 0 0 1 0 0 1.1625 0A0001011.5500
46 1 0 0 0 1 1 1.1750 080001001.5625
44 1 0 0 0 1 0 1.1875 060000111.5750
42 1 0 0 0 0 1 1.2000 040000101.5875
40 1 0 0 0 0 0 1.2125 020000011.6000
3E 0 1 1 1 1 1 1.2250 00000000OFF
VID6
400
mV
VID5
200
mV
VID4
100
mV
VID3
50
mV
VID2
25
mV
VID1
12.5
mV
V
CC_MAX
1
Notes:
1. When this VID pattern is observed, the voltage regulator output should be disabled.
2. Shading denotes the expected VID range of the Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel®
Xeon® Processor 7300 Series.
3. The VID range includes VID transitions that may be initiated by thermal events, assertion of the FORCEPR# signal (see
Section 6.2.3), Extended HALT state transitions (see Section 7.2.2), or Enhanced Intel SpeedStep
(see Section 7.3). The Extended HALT state must be enabled for the processor to remain within its specifications.
4. Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a specifi c VID o ff code i s
received, the VRM/EVRD must turn off its output (the output should go to high impedance) within 500 ms and latch off until
power is cycled. Refer to Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines.
Document Number: 318080-002 19
®
Technology transitions
2.5 Reserved, Unused, or Test Signals
All Reserved signals must remain unconnected. Connection of these signals to VCC, VTT,
, or to any other signal (including each other) can result in component malfunction
V
SS
or incompatibility with future processors. See Section 4 for a pin listing of the processor
and the location of all Reserved signals.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active high inputs, should be connected through a
resistor to ground (V
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. Resistor values should be within ± 20% of the impedance of the baseboard
trace for FSB signals, unless otherwise noticed in the appropriate platform design
guidelines. For unused AGTL+ input or I/O signals, use pull-up resistors of the same
value as the on-die termination resistors (R
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include ondie termination. Inputs and utilized outputs must be terminated on the baseboard.
Unused outputs may be terminated on the baseboard or left unconnected. Note that
leaving unused outputs unterminated may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing. Signal termination for
these signal types is discussed in the appropriate platform design guidelines.
). Unused outputs can be left unconnected; however, this may
SS
). For details see Table 2-24.
TT
Electrical Specifications
For each processor socket, connect the TESTIN1 and TESTIN2 signals together, then
terminate the net with a 51 Ω resistor to V
TT
The TESTHI signal must be tied to the processor VTT using a matched resistor, where a
matched resistor has a resistance value within ± 20% of the impedance of the board
transmission line traces. For example, if the trace impedance is 50 Ω, then a value
between 40 Ω and 60 Ω is required.
The TESTHI signals may use individual pull-up resistors or be grouped together as
detailed below. A matched resistor must be used for each group:
• TESTHI[1:0] - can be grouped together with a single pull-up to V
2.6 Front Side Bus Signal Groups
The FSB signals have been combined into groups by buffer type. AGTL+ input signals
have differential input buffers, which use GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END as reference levels. In this document, the
term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group
when receiving. Similarly , “AGTL+ Output” refers to the AGTL+ output group as well as
the AGTL+ I/O group when driving. AGTL+ asynchronous outputs can become active
anytime and include an active PMOS pull-up transistor to assist during the first clock of
a low-to-high voltage transition.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals whose timings are
specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the
second set is for the source synchronous signals which are relative to their respective
strobe lines (data and address) as well as rising edge of BCLK0. Asynchronous signals
are still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 2-4 identifies which signals are common clock, source synchronous
and asynchronous.
TT
20 Document Number: 318080-002
Electrical Specifications
Table 2-4. FSB Signal Groups
Signal Group Type Signals
AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#,
AGTL+ Common Clock Output Synchronous to BCLK[1:0] BPM4#, BPM[2:1]#, BPMb[2:1]#
AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, AP[1:0]#, BINIT#
AGTL+ Source Synchronous
I/O
Synchronous to assoc.
strobe
1
TRDY#;
2
BPM3#, BPM0#, BPMb3#, BPMb0#,
BR[1:0]#, DBSY#, DP[3:0]#, DRDY#, HIT#
2
, LOCK#, MCERR#
HITM#
, BNR#2, BPM5#,
2
Signals Associated Strobe
REQ[4:0]#
A[37:36,16:3]#
ADSTB0#
A[39:38, 35:17]# ADSTB1#
D[15:0]#, DBI0# DSTBP0#, DSTBN0#
D[31:16]#, DBI1# DSTBP1#, DSTBN1#
D[47:32]#, DBI2# DSTBP2#, DSTBN2#
D[63:48]#, DBI3# DSTBP3#, DSTBN3#
2
,
AGTL+ Strobes I/O Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
Open Drain Output Asynchronous FERR#/PBE#, IERR#, PROCHOT#,
THERMTRIP#, TDO
CMOS Asynchronous Input Asynchronous A20M#, FORCEPR#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#,
STPCLK#, TCK, TDI, TMS TRST#
CMOS Asynchronous Output Asynchronous BSEL[2:0], VID[6:1]
FSB Clock Clock BCLK[1:0]
SMBus Synchronous to SM_CLK SM_CLK, SM_DAT, SM_EP_A[2:0], SM_WP
Power/Other Power/Other COMP[3:0], GTLREF_ADD_MID,
Notes:
1. Refer to Section 5 for signal descriptions.
2. These signals may be driven simultaneously by multiple agents (Wired-OR).
GTLREF_ADD_END, GTLREF_DATA_MID,
GTLREF_DATA_END, LL_ID[1:0],
PROC_ID[1:0], PECI, RESERVED,
SKTOCC#,SM_VCC, TESTHI[1:0], TESTIN1,
TESTIN2, VCC, VCC_SENSE, VCC_SENSE2,
VCCPLL, VSS_SENSE, VSS_SENSE2, VSS,
VTT, VTT_SEL
Document Number: 318080-002 21
Table 2-5 outlines the signals which include on-die termination (RTT). Table 2-6
outlines non AGTL+ signals including open drain signals. Table 2-7 provides signal
reference voltages.
Table 2-5. AGTL+ Signal Description Table
AGTL+ signals with R
A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#,
DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
1
TT
Electrical Specifications
AGTL+ signals with no R
BPM[5:0]#, BPMb[3:0]#, RESET#, BR[1:0]
TT
Note:
1. Signals that have RTT in the package with 50 Ω pullup to V
.
TT
Table 2-6. Non AGTL+ Signal Description Table
Signals with R
TT
A20M#, BCLK[1:0], BSEL[2:0], COMP[3:0],
FERR#/PBE#, FORCEPR#, GTLREF_ADD_MID,
GTLREF_ADD_END, GTLREF_DATA_MID,
GTLREF_DATA_END, IERR#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, LL_ID[1:0], PROC_ID[1:0],
PECI, PROCHOT#, PWRGOOD, SKTOCC#, SMI#,
STPCLK#, TCK, TDI, TDO, TESTHI[1:0], TESTIN1,
TESTIN2, THERMTRIP#, TMS, TRST#, VCC_SENSE,
VCC_SENSE2, VID[6:1], VSS_SENSE, VSS_SENSE2,
VTT_SEL
Signals with no R
Table 2-7. Signal Reference Voltages
GTLREF CMOS
A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BPM[5:0]#, BPMb[3:0]#, BPRI#, BR[1:0]#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#,
HIT#, HITM#, LOCK#, MCERR#, RESET#,
REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
A20M#, LINT0/INTR, LINT1/NMI, IGNNE#, INIT#,
PWRGOOD, SMI#, STPCLK#, TCK, TDI, TMS, TRST#
2.7 CMOS Asynchronous and Open Drain
Asynchronous Signals
TT
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize
CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#,
THERMTRIP#, and TDO utilize open drain output buffers. All of the CMOS and Open
Drain signals are required to be asserted/deasserted for at least eight BCLKs in order
for the processor to recognize the proper signal state. See Section 2.11 and
Section 2.12 for the DC and AC specifications. See Section 7 for additional timing
requirements for entering and leaving the low power states.
2.8 Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Similar considerations must be made for
TCK, TMS, and TRST#. Two copies of each signal may be required with each driving a
different voltage level.
22 Document Number: 318080-002
Electrical Specifications
2.9 Mixing Processors
Intel supports and validates multi-processor configurations only in which all processors
operate with the same FSB frequency, core frequency, number of cores, and have the
same internal cache sizes. Mixing components operating at different internal clock
frequencies or number of cores is not supported and will not be validated by Intel.
Note: Processors within a system must operate at the same frequency per bits [12:8] of the
CLOCK_FLEX_MAX MSR; however this does not apply to frequency transitions initiated
due to thermal events, Extended HALT, Enhanced Intel SpeedStep technology
transitions, or assertion of the FORCEPR# signal (See Section 6).
Mixing processors of different steppings but the same model (as per CPUID instruction)
is supported. Details regarding the CPUID instruction are provided in the AP-485 Intel®
Processor Identification and the CPUID Instruction application note.
2.10 Absolute Maximum and Minimum Ratings
Table 2-8 specifies absolute maximum and minimum r atings only, which lie outside the
functional limits of the processor. Only within specified operation limits, can
functionality and long-term reliability be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.
Table 2-8. Processor Absolute Maximum Ratings
Symbol Parameter Min Max Unit Notes
V
CC
V
TT
T
CASE
T
STORAGE
Notes:
1. For functional operation, all processor electri cal, signal quality, mechanical and thermal specifications must
be satisfied.
2. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not
receive a clock, and no pins can be connected to a voltage bias. Storage within these limits will not affect
the long-term reliability of the device. For functional operation, please refer to the processor case
temperature specifications.
3. This rating applies to the processor and does not include any tray or packaging.
4. Failure to adhere to this specification can affect the long-term reliability of the processor.
Core voltage with respect to V
FSB termination voltage with respect to
V
SS
Processor case temperature See Section 6 See Section 6 °C
Storage temperature -40 85 ° C 2, 3, 4
SS
1
-0.30 1.55 V
-0.30 1.55 V
Document Number: 318080-002 23
2.11 Processor DC Specifications
The following notes apply:
• The processor DC specifications in this section are defined at the processor die and
not at the package pins unless noted otherwise.
• The notes associated with each parameter are part of the specification for that
parameter.
• Unless otherwise noted, all specifications in the tables apply to all frequencies and
cache sizes.
See Section 5 for the pin signal definitions. Most of the signals on the processor FSB
are in the AGTL+ signal group. The DC specifications for these signals are listed in
Table 2-11.
Table 2-9 through Table 2-17 list the DC specifications and are valid only while meeting
specifications for case temperature (Tcase as specified in Section 6), clock frequency,
and input voltages.
Electrical Specifications
24 Document Number: 318080-002
Electrical Specifications
2.11.1 Flexible Motherboard Guidelines (FMB)
The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the
Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon®
Processor 7300 Series will have over certain time periods. The values are only
estimates and actual specifications for future processors may differ. Processors may or
may not have specifications equal to the FMB value in the foreseeable future. System
designers should meet the FMB values to ensure their systems will be compatible with
future processors.
Table 2-9. Voltage and Current Specifications (Sheet 1 of 2)
Symbol Parameter Min Typ Max Unit
VID VID range 1.0000 1.5000 V
V
CC
V
CC_BOOT
V
VID_STEP
V
VID_SHIFT
V
TT
V
CCPLL
VCC for processor core
Launch - FMB
See Table 2-10, Figure 2-5,
Figure 2-6 and Figure 2-7
Default VCC Voltage for initial power up 1.10 V 2
VID step size during a transition ± 12.5 mV
Total allowable DC load line shift from
VID steps
FSB termination voltage (DC + AC
1.14 1.20 1.26 V 8, 13
450 mV 10
specification)
PLL supply voltage (DC + AC
specification)
1.425 1.50 1.605 V
SM_VCC SMBus supply voltage 3.135 3.300 3.465 V
I
CC
ICC for Quad-Core Intel® Xeon® L7345
Processor with multiple VID
60 A 4, 5, 6, 9
Launch - FMB
I
CC_RESET
I
L7345 Processor with multiple VID
for Quad-Core Intel® Xeon®
CC_RESET
60 A 17
Launch - FMB
I
CC
ICC for Dual-Core Intel® Xeon®
Processor 7200 Series with multiple
VID
90 A 4, 5, 6, 9
Launch - FMB
I
CC_RESET
I
Processor 7200 Series with multiple
VID
for Dual-Core Intel® Xeon®
CC_RESET
90 A 17
Launch - FMB
I
CC
ICC for Intel® Xeon® Processor 7200
Series and 7300 Series with multiple
VID
90 A 4, 5, 6, 9
Launch - FMB
I
CC_RESET
I
7200 Series and 7300 Series with
for Intel® Xeon® Processor
CC_RESET
90 A 17
multiple VID
Launch - FMB
I
CC
ICC for Intel® Xeon® X7350 Processor
with multiple VID
130 A 4, 5, 6, 9
Launch - FMB
I
CC_RESET
I
CC_RESET
Processor with multiple VID
for Intel® Xeon® X7350
130 A 17
Launch - FMB
I
SM_VCC
Icc for SMBus supply 100 122.5 mA
Notes
1,17
V 2, 3, 4, 6,
9
Document Number: 318080-002 25
Table 2-9. Voltage and Current Specifications (Sheet 2 of 2)
Electrical Specifications
Symbol Parameter Min Typ Max Unit
I
TT
I
CC_TDC
ICC for VTT supply before VCC stable
I
for VTT supply after VCC stable
CC
Thermal Design Current (TDC) QuadCore Intel® Xeon® L7345 Processor
8.0
7.0
50 A 6,14
Launch - FMB
I
CC_TDC
Thermal Design Current (TDC) DualCore Intel® Xeon® Processor 7200
Series
75 A 6,14
Launch - FMB
I
CC_TDC
Thermal Design Current (TDC) Intel®
®
Processor 7200 Series and 7300
Xeon
75 A 6,14
Series
Launch - FMB
I
CC_TDC
Thermal Design Current (TDC) Intel®
Xeon® X7350 Processor
110 A 6,14
Launch - FMB
I
CC_VTT_OUT
I
CC_GTLREF
I
CC_VCCPLL
I
TCC
I
TCC
I
TCC
I
TCC
DC current that may be drawn from
per pin
V
TT_OUT
ICC for
GTLREF_DATA_MID,
GTLREF_DATA_END,
GTLREF_ADD_MID, and
GTLREF_ADD_END
ICC for PLL supply 260 mA 12
ICC for Quad-Core Intel® Xeon® L7345
Processor during active thermal control
circuit (TCC)
ICC for Dual-Core Intel® Xeon®
Processor 7200 Series during active
thermal control circuit (TCC)
ICC for Dual-Core Intel® Xeon®
Processor 7200 Series and Quad-Core
Intel® Xeon® Processor 7300 Series
during active thermal control circuit
(TCC)
ICC for Intel® Xeon® X7350 Processor
during active thermal control circuit
(TCC)
580 mA 16
200 µA 7
60 A
90 A
90 A
130 A
Notes
1,17
A15
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processors and are based on estimates
and simulations, not empirical data. These specifications will be updated with characterized data from
silicon measurements at a later date.
2. These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See Section 2.4 for more information.
3. The voltage specification requirements are measured across the VCC_SENSE and VSS_SENSE pins and
across the VCC_SENSE2 and VSS_SENSE2 pins with an oscilloscope set to 100 MHz bandwidth, 1.5 pF
maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope pr obe.
4. The processor must not be subjected to any static V
particular current. Failure to adhere to this specification can shorten processor lifetime.
5. I
6. FMB is the flexible motherboard guideline. These guidelines are fo r estimation purposes only. See
7. This specification represents the total current for GTLREF_DATA_MID, GTLREF_DATA_END,
8. V
specification is based on maximum V
CC_MAX
capable of drawing I
current draw over various time durations.
Section 2.11.1 for further details on FMB guidelines.
GTLREF_ADD_MID, and GTLREF_ADD_END.
must be provided via a separate voltage source and must not be connected to VCC. This specification is
TT
measured at the pin.
26 Document Number: 318080-002
level that exceeds the V
CC
loadline Refer to Figure 2-10 for details. The processor is
for up to 10 ms. Refer to Figure 2-9 for further details on the average processor
CC_MAX
CC
associated with any
CC_MAX
Electrical Specifications
9. Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE)
shown in Figure 6-2.
10. This specification refers to the total reduction of the load line due to VID transitions below the specified
VID.
11. Individual processor VID values may be calibrated during man ufacturing such that two devices at the same
frequency may have different VID settings.
12. This specification applies to the VCCPLL pin.
13. Baseboard bandwidth is limited to 20 MHz.
14. I
15. This is the maximum total current drawn from the V
16. I
17. I
is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and
CC_TDC
should be used for the voltage regulator temperature assessment. The voltage regulator is responsible for
monitoring its temperature and asserting the necessary signal to inform the processor of a thermal
excursion. Please see the applicable design guidelines for further details. The processor is capable of
drawing I
over various time durations. This parameter is based on design characterization and is not tested.
specification does not include the current coming from on-board termination (R
Refer to the appropriate platform design guide and the Voltage Regulator Design Guidelines to determine
the total I
CC_VTT_OUT
CC_RESET
RESET# de-assertion time specification and Table 2-23 for the RESET# Pulse Width specification.
indefinitely. Refer to Figure 2-9 for further details on the average processor current draw
CC_TDC
plane by only one processor with RTT enabled. This
TT
drawn by the system. This parameter is based on design characterization and is not tested.
TT
is specified at 1.2 V.
is specified while PWRGOOD and RESET# are asserted. Refer to Table 2- 22 for the PWRGOOD to
), through the signal line.
TT
Figure 2-1. Quad-Core Intel® Xeon® L7345 Processor Load Current versus Time
65
60
55
50
Sustained Current (A)
45
40
0.01 0.1 1 10 100 1000
Time Dur ation (s)
Notes:
1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than
2. Not 100% tested. Specified by design characterization.
I
CC_TDC
.
Document Number: 318080-002 27
Electrical Specifications
Figure 2-2. Dual-Core Dual-Core Intel® Xeon® Processor 7200 Series Load Current
versus Time
10 0
95
90
85
80
75
70
Sustained Current (A)
65
60
0.01 0.1 1 10 100 1000
Time Duration (s)
Notes:
1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than
I
.
CC_TDC
2. Not 100% tested. Specified by design characterization
Figure 2-3. Quad-Core Intel® Xeon® Processor 7200 Series and 7300 Series Load Current
versus Time
10 0
95
90
85
80
75
70
Sustained Current (A)
65
60
0.01 0.1 1 10 100 1000
Time Duration (s)
Notes:
1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than
2. Not 100% tested. Specified by design characterization.
I
CC_TDC
.
28 Document Number: 318080-002
Electrical Specifications
Figure 2-4. Quad-Core Intel® Xeon® X7350 Processor Load Current versus Time
13 0
12 5
12 0
115
110
10 5
Sustained Current (A)
10 0
0.01 0.1 1 10 100 1000
Time Duration (s)
Notes:
1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than
2. Not 100% tested. Specified by design characterization.
I
CC_TDC
.
Document Number: 318080-002 29
Table 2-10. VCC Static and Transient Tolerance
Electrical Specifications
ICC (A) V
(V) V
CC_Max
(V) V
CC_Typ
(V) Notes
CC_Min
0 VID - 0.000 VID - 0.015 VID - 0.030 1, 2, 3
5 VID - 0.006 VID - 0.021 VID - 0.036 1, 2, 3
10 VID - 0.013 VID - 0.028 VID - 0.043 1, 2, 3
15 VID - 0.019 VID - 0.034 VID - 0.049 1, 2, 3
20 VID - 0.025 VID - 0.040 VID - 0.055 1, 2, 3
25 VID - 0.031 VID - 0.046 VID - 0.061 1, 2, 3
30 VID - 0.038 VID - 0.053 VID - 0.068 1, 2, 3
35 VID - 0.044 VID - 0.059 VID - 0.074 1, 2, 3
40 VID - 0.050 VID - 0.065 VID - 0.080 1, 2, 3
45 VID - 0.056 VID - 0.071 VID - 0.086 1, 2, 3
50 VID - 0.069 VID - 0.084 VID - 0.099 1, 2, 3
55 VID - 0.069 VID - 0.077 VID - 0.093 1, 2, 3
60 VID - 0.075 VID - 0.090 VID - 0.105 1, 2, 3
65 VID - 0.081 VID - 0.096 VID - 0.111 1, 2, 3, 4
70 VID - 0.087 VID - 0.103 VID - 0.118 1, 2, 3, 4
75 VID - 0.094 VID - 0.109 VID - 0.124 1, 2, 3, 4
80 VID - 0.100 VID - 0.115 VID - 0.130 1, 2, 3, 4
85 VID - 0.106 VID - 0.121 VID - 0.136 1, 2, 3, 4
90 VID - 0.113 VID - 0.128 VID - 0.143 1, 2, 3, 4
95 VID - 0.119 VID - 0.134 VID - 0.149 1, 2, 3, 4, 5
100 VID - 0.125 VID - 0.140 VID - 0.155 1, 2, 3, 4, 5
105 VID - 0.131 VID - 0.146 VID - 0.161 1, 2, 3, 4, 5
110 VID - 0.138 VID - 0.153 VID - 0.168 1, 2, 3, 4, 5
115 VID - 0.144 VID - 0.159 VID - 0.174 1, 2, 3, 4, 5
120 VID - 0.150 VID - 0.165 VID - 0.180 1, 2, 3, 4, 5
125 VID - 0.156 VID - 0.171 VID - 0.186 1, 2, 3, 4, 5
130 VID - 0.163 VID - 0.178 VID - 0.193 1, 2, 3, 4, 5
Notes:
1. The V
2. This table is intended to aid in reading discrete points on Figure 2-5 for Intel
3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins and
4. I
5. I
overshoot specifications.
V
CC
Series and 7300 Series, Figure 2-6 for Intel® Xeon® X7350 Processor , Figure 2-7 for Quad-Core Intel®
Xeon® L7345 Processor and Figure 2-8 for Dual-Core Intel® Xeon® Processor 7200 Series
across the VCC_SENSE2 and VSS_SENSE2 pins. Voltage regulation feedback for voltage regulator
circuits must also be taken from processor VCC_SENSE2 and VSS_SENSE2 pins. Refer to the Voltage
Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for
socket load line guidelines and VR implementation. Please refer to the appropriate platform design guide
for details on VR implementation.
values greater than 60 A are not applicable for the Quad-Core Intel® Xeon® L7345 Processor.
cc
values greater than 90 A are not applicable for the Intel® Xeon® Processor 7200 Series and 7300
cc
Series and Dual-Core Intel® Xeon® Processor 7200 Series.
CC_MIN
and V
loadlines represent static and transient limits. Please see Section 2.11.3 for
CC_MAX
®
Xeon® Processor 7200
30 Document Number: 318080-002
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