Intel Xeon 5600 Series Specification Update

Intel® Xeon® Processor 5600 Series

Specification Update

March 2010

Reference Number:323372-001

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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. All products, platforms, dates, and figures specified are preliminary based on current expectations, and are subject to change

without notice. All dates specified are target dates, are provided for planning purposes only and are subject to change. This document contains information on products in the desig n phase of development. Do not finalize a design with this information.

Revised information will be published when the product is available. Verify with your local sales office that you have the latest datasheet before finalizing a design.

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See the http://processorfinder.intel.com/ or contact your Intel representative for more information. Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology-

enabled chipset, BIOS and operat ing syste m. Performance will vary de pending on the specific hardware and software you use. For more information including details on which processors support HT Technology, see http://www.intel.com/technology/platform-

technology/hyper-threading/index.htm.

Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology.For more information, see http://www.intel.com/

technology/turboboost.

Intel, Xeon, Pentium, Celeron, Intel Enhanced SpeedStep Technology, Intel Core, the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

2 Intel® Xeon® Processor 5600 Series

Specification Update, March 2010

Contents

Revision History...............................................................................................................5

Preface ..............................................................................................................................6

Identification Information................................................................................................8

Summary Table of Changes..........................................................................................11

Errata Summary..............................................................................................................14

Specification Changes...................................................................................................44

Specification Clarifications...........................................................................................45

Documentation Changes...............................................................................................46

§ §

Intel® Xeon® Processor 5600 Series 3 Specification Update, March 2010

Intel® Xeon® Processor 5600 Series 4 Specification Update, March 2010

Revision History

Doc ID Revision Description Date

323372 -001 • Initial Release March 2010

Intel® Xeon® Processor 5600 Series 5 Specification Update, March 2010

Preface

This document is an update to the specifications contained in the Affected Documents able below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware systemmanufacturers and software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specificationupdate and are no longer published in other documents.

This document may also contain information that was not previously published.

Affected Documents

Intel® Xeon® Processor 5600 Series Datasheet Volume 1 & 2 323369 & 323370

Nomenclature

S-Spec Number is a five-digit code used to identify products. Products are

differentiated by their unique characteristics, e.g., core speed, L2 cache size, package type, etc. as described in the processor identification information table. Read all notes associated with each S-Spec number.

Errata are design defects or errors. from published specifications.

These may cause the processor behavior to deviate

Hardware and software designed to be used with any

given stepping must assume that all errata documented for that stepping are present on all devices.

Specification Changes are modifications to the current published specifications. These changes will be incorporated in the next release of the specification.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in any new release of the specification.

Documentation Changes include typographical errors, omissions, or incorrect information from the current published specifications. These will be incorporated in the next release of the specification.

Note: Errata remain in the specification update throughout the product’s life cycle, or until a

particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request.

Specification changes, specification clarifications, and documentation changes are removed from the sightings report and/or specification update when the appropriate changes are made to the appropriate product specification or user documentation.

Intel® Xeon® Processor 5600 Series 7 Specification Update, March 2010

Identification Information

Component Identification

The Intel® Xeon® Processor 5600 Series stepping can be identified by the following register contents.

Table 1. Intel® Xeon® Processor 5600 Series Signature /Version

Reserved

31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0

Notes:

1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, sp ecific in bits [11:8],

2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are

3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM

4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX

5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX

6. The Stepping ID in bits [3:0] indicates the revi sion number of th at model. See Table 2 for the processor

Extended

Family

00000000b 0010b 00b 0110 1100b XXXXb

to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4, or Intel® Core™ processor family.

used to identify the model of the processor within the processor family. processor, an OverDrive processor, or a dual processor (capable of being used in a dual processor

system). register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of

the Device ID register accessible through Boundary Scan. register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the

Device ID register accessible through Boundary Sca n. stepping ID number in the CPUID information.

Extended

Model

Reserved

Processor

Type

Family

Code

Model

Number

Stepping

When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family Code, Model Number, and Stepping ID in the EAX register. Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.

Intel® Xeon® Processor 5600 Series 8 Specification Update, March 2010

Component Marking

The Intel® Xeon® Processor 5600 Series can be identified by the following component markings:

Figure 1. Processor Top-side Markings (Example)

Table 2. Intel® Xeon® Processor 5600 Series Identification (Sheet 1 of 2)

Core Frequency (GHz) 17/

S-Spec

Number

SLBV5 B-1 0x000206C2 3.33 / 6.40 / 1333 / 1333 1/1/1/1/2/2 12 130 SLBV9 B-1 0x000206C2 2.93 / 6.40 / 1333 / 1333 2/2/2/2/3/3 12 130 SLBV7 B-1 0x000206C2 2.80 / 6.40 / 1333 / 1333 2/2/2/2/3/3 12 95

SLBVA B-1 0x000206C2 3.06 / 6.40 / 1333 / 1333

SLBV6 B-1 0x000206C2 2.80 / 6.40 / 1333 / 1333 2/2/2/2/3/3 12 95 SLBV3 B-1 0x000206C2 2.66 / 6.40 / 1333 / 1333 2/2/2/2/3/3 12 95

SLBVC B-1 0x000206C2 2.66 / 5.86 / 1066 / 1066

SLBVB B-1 0x000206C2 2.53 / 5.86 / 1066 / 1066 2/2/2/2/3/3 12 80

SLBV4 B-1 0x000206C2 2.40 / 5.86 / 1066 /1066

SLBV8 B-1 0x000206C2 2.26 / 5.86 / 1333 / 1333 2/2/3/3/4/4 12 60

SLBVD B-1 0x000206C2 2.13 / 5.86 / 1066 / 1066

SLBVJ B-1 0x000206C2 1.86 / 4.80 / 1066 / 1066 na 12 40

Steppin

CPUID

Intel QuickPath

Interconnect (GT/s) /

DDR3 (MHz) / DDR3L

(MHz)

Available bins of Intel Turbo Boost

Technology

na/na/2/2/3/ 3

na/na/1/1/2/ 2

Cache

Size

(MB)

12 95

12 80

12 40

TDP (W)

Notes

2 3 4

5 6

Intel® Xeon® Processor 5600 Series 9 Specification Update, March 2010

Table 2. Intel® Xeon® Processor 5600 Series Identification (Sheet 2 of 2)

Core Frequency (GHz) 17/

S-Spec

Number

Steppin

CPUID

Intel QuickPath

Interconnect (GT/s) /

DDR3 (MHz) / DDR3L

(MHz)

SLBWZ B-1 0x000206C2 2.40 / 5.86 / 1333 / 1333 1/1/2/2/3/3 12 80 SLBWY B-1 0x000206C2 2.00 / 5.86 / 1333 / 1333 1/1/2/2/3/3 12 60

SLBX3 B-1 0x000206C2 1.86 / 5.86 / 1066 / 1066

Notes:

1. CPUID is 0000206Csh, where ‘s’ is the stepping number.

2. This is an Intel® Xeon Processor X5680.

3. This is an Intel® Xeon Processor X5677.

4. This is an Intel® Xeon Processor X5670.

5. This is an Intel® Xeon Processor X5660.

6. This is an Intel® Xeon Processor X5650.

7. This is an Intel® Xeon Processor X5667.

8. This is an Intel® Xeon Processor E5640.

9. This is an Intel® Xeon Processor E5630

10. This is an Intel® Xeon Processor E5620

11. This is an Intel® Xeon Processor L5640.

12. This is an Intel® Xeon Processor L5630.

13. This is an Intel® Xeon Processor L5609.

14. This is an Intel® Xeon Processor E5645.

15. This is an Intel® Xeon Processor L5638.

16. This is an Intel® Xeon Processor L5618.

17. The core frequency reported in the processor br an d string is rou nded to 2 decimal digi ts. (For example, core frequency of 2.6666, repeating 6, is reported as @2.67 in brand string. Core frequency of 2.1333, is reported as @2.13 in brand string.)

Available bins of Intel Turbo Boost

Technology

na/na/1/1/

2/3

Cache

Size

(MB)

12 40

TDP (W)

Notes

14 15

Intel® Xeon® Processor 5600 Series 10 Specification Update, March 2010

Summary Table of Changes

The table included in this section indicate the errata, Specification Changes, Specification Clarifications, or Document Changes which apply to the Intel® Xeon® Processor 5600 Series. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted.

Definitions are listed below for terminology used in the Summary Tables below.

Affected Stepping Column:

X: Errata exists in the stepping indicated. Specification Change or Specification

Clarification that applies to this stepping. Blank: This erratum is fixed, or does not exist, in the listed stepping. Specification

Change does not apply to listed stepping.

Status Column:

No Fix: There are no plans to fix this erratum. Plan Fix: This erratum may be fixed in a future stepping of the product. Fixed: This erratum has been fixed.

A change bar to the left of the table row indicates this erratum is either new or has been modified from the previous revision of this document.

A = Intel® Xeon® processor 7000 sequence C = Intel® Celeron® processor D = Intel® Xeon® processor 2.80 GHz E = Intel® Pentium® III processor F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor I = Intel® Xeon® processor 5000 series J = 64-bit Intel® Xeon® processor MP with 1MB L2 cache K = Mobile Intel® Pentium® III processor L = Intel® Celeron® D processor M = Mobile Intel® Celeron® processor N = Intel® Pentium® 4 processor O = Intel® Xeon® processor MP P = Intel ® Xeon® processor Q = Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology

R = Intel® Pentium® 4 processor on 90 nm process S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache

on 90-nm process technology

versions)

Intel® Xeon® Processor 5600 Series 11 Specification Update, March 2010

T = Mobile Intel® Pentium® 4 processor-M U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA package W= Intel® Celeron® M processor X = Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and Intel®

processor A100 and A110 with 512-KB L2 cache Y = Intel® Pentium® M processor Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor Extreme

Edition 955, 965 AB = Intel® Pentium® 4 processor 6x1 sequence AC = Intel® Celeron® processor in 478 pin package AD = Intel® Celeron® D processor on 65 nm process AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65 nm process AF = Intel® Xeon® processor LV AG = Intel® Xeon® processor 5100 series AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor

E6000 and E4000 sequence AJ = Intel® Xeon® processor 5300 series AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2

Quad processor Q6000 sequence AL = Intel® Xeon® processor 7100 series AM = Intel® Celeron® processor 400 sequence AN = Intel® Pentium® dual-core processor AO = Intel® Xeon® processor 3200 series AP = Intel® Xeon® processor 3000 series AQ = Intel® Pentium® dual-core desktop processor E2000 sequence AR = Intel® Celeron® processor 500 series AS = Intel® Xeon® processor 7200, 7300 series AT = Intel® Celeron® processor 200 series AU = Intel® Celeron® Dual Core processor T1400 AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad processor Q9000

series AW = Intel® Core™ 2 Duo processor E8000 series AX = Intel® Xeon® processor 5400 series AY = Intel® Xeon® processor 5200 series AZ= Intel® Core™2 Duo processor and Intel® Core™2 Extreme processor on 45-nm

process AAA= Intel® Xeon® processor 3300 series

Intel® Xeon® Processor 5600 Series 12 Specification Update, March 2010

AAB= Intel® Xeon® E3110 processor AAC= Intel® Celeron® dual-core processor E1000 series AAD = Intel

Core™2 Extreme processor QX9775 AAE = Intel® Atom™ processor Z5xx series AAF = Intel® Atom™ processor 200 series AAG = Intel® Atom™ processor N series AAH = Intel® Atom™ processor 300 series AAI = Intel® Xeon® processor 7400 series AAJ = Intel® Core™ i7 processor and Intel® Core™ i7 Extreme Edition processor AAK= Intel® Xeon® processor 5500 series AAL = Intel® Pentium Dual-Core processor E5000 series BD= Intel® Xeon® processor 5600 series

Intel® Xeon® Processor 5600 Series 13 Specification Update, March 2010

Errata Summary

Table 3. Errata Summary Table (Sheet 1 of 4)

Errata

Number

BD1 X No Fix The Processor may Report a #TS Instead of a #GP Fault

BD2 X No Fix

BD3 X No Fix BD4 X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values

BD5 X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation BD6 X No Fix MOV To/From Debug Registers Causes Debug Exception

BD7 X No Fix BD8 X No Fix Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM

BD9 X No Fix Single Step Interrupts with Floating Point Exception Pending May Be Mishandled

BD10 X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame BD11 X No Fix

BD12 X No Fix

BD13 X No Fix

BD14 X No Fix

BD15 X No Fix BD16 X No Fix Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled Breakpoints

BD17 X No Fix MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang BD18 X No Fix BD19 X No Fix A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as Armed

BD20 X No Fix Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately BD21 X No Fix

BD22 X No Fix

BD23 X No Fix

BD24 X No Fix IA32_MPERF Counter Stops Counting During On-Demand TM1

Steppings

Status ERRATA

B-1

REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations

Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack

Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update

IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception

General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted

General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit

LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode

MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error

Corruption of CS Segment Register During RSM While Transitioning From Real Mode to Protected Mode

#GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code

Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint is Set on a #GP Instruction

An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/ POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception

Intel® Xeon® Processor 5600 Series 14 Specification Update, March 2010

+ 32 hidden pages

Intel Xeon 5600 Series Specification Update

Specifications and Main Features

Frequently Asked Questions

User Manual

Intel® Xeon® Processor 5600 Series

Revision History

Preface

Affected Documents

Related Documents

Nomenclature

Identification Information

Component Identification

Component Marking

Summary Table of Changes

Errata Summary