Intel E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor, Xeon 5300 Series Datasheet
Quad-Core Intel® Xeon® Processor
5300 Series
Datasheet
November 2006
Order Number: 315569, Revision: 001
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Copyright © 2006, Intel Corporation
2 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Contents
1 Introduction.................................................................................................................9
1.1 Terminology ..................................................................................................... 11
1.2 State of Data .................................................................................................... 13
1.3 References ....................................................................................................... 13
2 Electrical Specifications ............................................................................................... 15
2.1 Front Side Bus and GTLREF ................................................................................ 15
2.2 Power and Ground Lands.................................................................................... 16
2.3 Decoupling Guidelines........................................................................................ 16
2.3.1 VCC Decoupling...................................................................................... 16
2.3.2 VTT Decoupling ...................................................................................... 16
2.3.3 Front Side Bus AGTL+ Decoupling ............................................................ 17
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ....................................... 17
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0]).................................. 18
2.4.2 PLL Power Supply................................................................................... 19
2.5 Voltage Identification (VID) ................................................................................ 19
2.6 Reserved, Unused, or Test Signals....................................................................... 21
2.7 Front Side Bus Signal Groups.............................................................................. 22
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals .................................... 24
2.9 Test Access Port (TAP) Connection....................................................................... 24
2.10 Platform Environmental Control Interface (PECI) DC Specifications........................... 24
2.10.1 DC Characteristics .................................................................................. 24
2.10.2 Input Device Hysteresis .......................................................................... 25
2.11 Mixing Processors.............................................................................................. 26
2.12 Absolute Maximum and Minimum Ratings ............................................................. 26
2.13 Processor DC Specifications ................................................................................ 27
2.13.1 Flexible Motherboard Guidelines (FMB)...................................................... 27
2.13.2 VCC Overshoot Specification .................................................................... 33
2.13.3 Die Voltage Validation............................................................................. 34
2.14 AGTL+ FSB Specifications................................................................................... 34
3 Mechanical Specifications............................................................................................. 39
3.1 Package Mechanical Drawings ............................................................................. 39
3.2 Processor Component Keepout Zones................................................................... 43
3.3 Package Loading Specifications ........................................................................... 43
3.4 Package Handling Guidelines............................................................................... 44
3.5 Package Insertion Specifications.......................................................................... 44
3.6 Processor Mass Specifications ............................................................................. 44
3.7 Processor Materials............................................................................................ 44
3.8 Processor Markings............................................................................................ 45
3.9 Processor Land Coordinates ................................................................................ 45
4 Land Listing ............................................................................................................... 49
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments ........................... 49
4.1.1 Land Listing by Land Name...................................................................... 49
4.1.2 Land Listing by Land Number................................................................... 60
5 Signal Definitions ....................................................................................................... 71
5.1 Signal Definitions .............................................................................................. 71
6 Thermal Specifications ................................................................................................ 79
6.1 Package Thermal Specifications........................................................................... 79
6.1.1 Thermal Specifications ............................................................................ 79
6.1.2 Thermal Metrology ................................................................................. 83
6.2 Processor Thermal Features................................................................................ 84
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 3
6.2.1 Thermal Monitor Features ........................................................................84
6.2.2 Thermal Monitor (TM1)............................................................................84
6.2.3 Thermal Monitor 2 ..................................................................................85
6.2.4 On-Demand Mode...................................................................................86
6.2.5 PROCHOT# Signal ..................................................................................87
6.2.6 FORCEPR# Signal ...................................................................................87
6.2.7 THERMTRIP# Signal................................................................................88
6.3 Platform Environment Control Interface (PECI) ......................................................88
6.3.1 Introduction...........................................................................................88
6.3.2 PECI Specifications .................................................................................89
7 Features ....................................................................................................................91
7.1 Power-On Configuration Options ..........................................................................91
7.2 Clock Control and Low Power States.....................................................................91
7.2.1 Normal State .........................................................................................92
7.2.2 HALT or Extended HALT State...................................................................92
7.2.3 Stop-Grant State ....................................................................................94
7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant
Snoop State...........................................................................................94
7.3 Enhanced Intel SpeedStep® Technology...............................................................95
8 Boxed Processor Specifications .....................................................................................97
8.1 Introduction......................................................................................................97
8.2 Mechanical Specifications....................................................................................99
8.2.1 Boxed Processor Heat Sink Dimensions (CEK).............................................99
8.2.2 Boxed Processor Heat Sink Weight ..........................................................107
8.2.3 Boxed Processor Retention Mechanism and Heat Sink
Support (CEK)......................................................................................107
8.3 Electrical Requirements ....................................................................................107
8.3.1 Fan Power Supply (Active CEK)...............................................................107
8.3.2 Boxed Processor Cooling Requirements.................................................... 108
8.4 Boxed Processor Contents.................................................................................109
9 Debug Tools Specifications .........................................................................................111
9.1 Debug Port System Requirements......................................................................111
9.2 Target System Implementation..........................................................................111
9.2.1 System Implementation.........................................................................111
9.3 Logic Analyzer Interface (LAI) ...........................................................................111
9.3.1 Mechanical Considerations .....................................................................112
9.3.2 Electrical Considerations ........................................................................112
4 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Figures
2-1 Input Device Hysteresis ..................................................................................... 25
2-2 Quad-Core Intel® Xeon® Processor E5300 Series Load Current versus Time............. 29
2-3 Quad-Core Intel® Xeon® Processor X5300 Series Load Current versus Time ............ 30
2-4 Quad-Core Intel® Xeon® Processor E5300 Series VCC Static and
Transient Tolerance Load Lines........................................................................... 31
2-5 Quad-Core Intel® Xeon® Processor X5300 Series VCC Static and
Transient Tolerance Load Lines........................................................................... 32
2-6 VCC Overshoot Example Waveform...................................................................... 34
2-7 Electrical Test Circuit ......................................................................................... 36
2-8 Differential Clock Waveform................................................................................ 36
2-9 Differential Clock Crosspoint Specification............................................................. 37
3-1 Processor Package Assembly Sketch .................................................................... 39
3-2 Processor Package Drawing (Sheet 1 of 3)............................................................ 40
3-3 Processor Package Drawing (Sheet 2 of 3)............................................................ 41
3-4 Processor Package Drawing (Sheet 3 of 3)............................................................ 42
3-5 Processor Top-side Markings (Example)................................................................ 45
3-6 Processor Land Coordinates, Top View.................................................................. 46
3-7 Processor Land Coordinates, Bottom View............................................................. 47
6-1 Quad-Core Intel® Xeon® Processor E5300 Series Thermal Profile ........................... 81
6-2 Quad-Core Intel® Xeon® Processor X5300 Series Thermal Profiles.......................... 82
6-3 Case Temperature (TCASE) Measurement Location ................................................ 84
6-4 Thermal Monitor 2 Frequency and Voltage Ordering ............................................... 86
6-5 PECI Topology .................................................................................................. 88
6-6 Conceptual Fan Control Diagram For A PECI-Based Platform.................................... 89
7-1 Stop Clock State Machine ................................................................................... 93
8-1 Boxed Quad-Core Intel® Xeon® Processor 5300 Series 1U Passive/3U+
Active Combination Heat Sink (With Removable Fan) ............................................. 97
8-2 Boxed Quad-Core Intel® Xeon® Processor 5300 Series 2U Passive Heat Sink ........... 98
8-3 2U Passive Quad-Core Intel® Xeon® Processor 5300 Series Processor
Thermal Solution (Exploded View) ....................................................................... 98
8-4 Top Side Board Keepout Zones (Part 1).............................................................. 100
8-5 Top Side Board Keepout Zones (Part 2).............................................................. 101
8-6 Bottom Side Board Keepout Zones..................................................................... 102
8-7 Board Mounting-Hole Keepout Zones ................................................................. 103
8-8 Volumetric Height Keep-Ins .............................................................................. 104
8-9 4-Pin Fan Cable Connector (For Active CEK Heat Sink) ......................................... 105
8-10 4-Pin Base Board Fan Header (For Active CEK Heat Sink)...................................... 106
8-11 Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution ....................... 108
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 5
Tables
1-1 Quad-Core Intel® Xeon® Processor 5300 Series Features.......................................10
2-1 Core Frequency to FSB Multiplier Configuration ......................................................18
2-2 BSEL[2:0] Frequency Table.................................................................................18
2-3 Voltage Identification Definition ...........................................................................20
2-4 Loadline Selection Truth Table for LL_ID[1:0] ........................................................21
2-5 Market Segment Selection Truth Table for MS_ID[1:0] ...........................................21
2-6 FSB Signal Groups .............................................................................................22
2-7 AGTL+ Signal Description Table...........................................................................23
2-8 Non AGTL+ Signal Description Table.....................................................................23
2-9 Signal Reference Voltages...................................................................................24
2-10 PECI DC Electrical Limits.....................................................................................25
2-11 Processor Absolute Maximum Ratings ...................................................................26
2-12 Voltage and Current Specifications .......................................................................27
2-13 VCC Static and Transient Tolerance......................................................................30
2-14 AGTL+ Signal Group Specifications.......................................................................32
2-15 CMOS Signal Input/Output Group and TAP Signal Group DC Specifications.................33
2-16 Open Drain Output Signal Group DC Specifications .................................................33
2-17 VCC Overshoot Specifications ..............................................................................33
2-18 AGTL+ Bus Voltage Definitions ............................................................................35
2-19 FSB Differential BCLK Specifications .....................................................................35
3-1 Package Loading Specifications............................................................................43
3-2 Package Handling Guidelines ...............................................................................44
3-3 Processor Materials ............................................................................................44
4-1 Land Listing by Land Name .................................................................................49
4-2 Land Listing by Land Number ..............................................................................60
5-1 Signal Definitions...............................................................................................71
6-1 Quad-Core Intel® Xeon® Processor E5300 Series Thermal Specifications..................80
6-2 Quad-Core Intel® Xeon® Processor E5300 Series Thermal Profile Table ...................81
6-3 Quad-Core Intel® Xeon® Processor X5300 Series Thermal Specifications .................82
6-4 Quad-Core Intel® Xeon® Processor X5300 Series Thermal Profile A Table ................83
6-5 Quad-Core Intel® Xeon® Processor X5300 Series Thermal Profile B Table ................83
6-6 GetTemp0() and GetTemp1() Error Codes.............................................................90
7-1 Power-On Configuration Option Lands...................................................................91
7-2 Extended HALT Maximum Power ..........................................................................93
8-1 PWM Fan Frequency Specifications for 4-Pin Active CEK Thermal Solution................ 108
8-2 Fan Specifications for 4-Pin Active CEK Thermal Solution.......................................108
8-3 Fan Cable Connector Pin Out for 4-Pin Active CEK Thermal Solution........................108
6 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Revision History
Document
Number
315569 -001 Initial Release November 2006
Revision Description Date
§
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 7
8 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Introduction
1 Introduction
The Quad-Core Intel® Xeon® Processor 5300 Series are 64-bit server/workstation
processors utilizing four Intel Core™ microarchitecture cores. These processors are
based on Intel’s 65 nanometer process technology combining high performance with
the power efficiencies of low-power Intel Core™ microarchitecture cores. The
Quad-Core Intel® Xeon® Processor 5300 Series consists of two die, each containing
two processor cores. All processors maintain the tradition of compatibility with IA-32
software. Some key features include on-die, 32 KB Level 1 instruction data caches per
core and 4 MB shared Level 2 cache per die (8 MB Total Cache per processor) with
Advanced Transfer Cache Architecture. The processor’s Data Prefetch Logic
speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting
in reduced bus cycle penalties and improved performance. The 1333 MHz Front Side
Bus (FSB) is a quad-pumped bus running off a 333 MHz system clock, which results in
10.6 GBytes per second data transfer. The 1066 MHz Front Side Bus is based on a
266 MHz system clock for an 8.5 GBytes per second data transfer rate. The Quad-Core
Intel® Xeon® Processor X5300 Series offers higher clock frequencies than the
Quad-Core Intel® Xeon® Processor E5300 Series for platforms that are targeted for
the performance optimized segment..
Enhanced thermal and power management capabilities are implemented including
Thermal Monitor 1 (TM1), Thermal Monitor 2 (TM2) and Enhanced Intel SpeedStep®
Technology. TM1 and TM2 provide efficient and effective cooling in high temperature
situations. Enhanced Intel SpeedStep® Technology provides power management
capabilities to servers and workstations.
The Quad-Core Intel® Xeon® Processor 5300 Series features include Advanced
Dynamic Execution, enhanced floating point and multi-media units, Streaming SIMD
Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3). Advanced Dynamic
Execution improves speculative execution and branch prediction internal to the
processor. The floating point and multi-media units include 128-bit wide registers and a
separate register for data movement. SSE3 instructions provide highly efficient doubleprecision floating point, SIMD integer, and memory management operations.
The Quad-Core Intel® Xeon® Processor 5300 Series supports Intel® 64 architecture
as an enhancement to Intel's IA-32 architecture. This enhancement allows the
processor to execute operating systems and applications written to take advantage of
the 64-bit extension technology. Further details on Intel 64 architecture and its
programming model can be found in the Intel® 64 and IA-32 Architecture Software
Developer's Manual.
In addition, the Quad-Core Intel® Xeon® Processor 5300 Series supports the Execute
Disable Bit functionality. When used in conjunction with a supporting operating system,
Execute Disable allows memory to be marked as executable or non executable. This
feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities
and can thus help improve the overall security of the system. Further details on
Execute Disable can be found at:
http://www3.intel.com/cd/ids/developer/asmo-na/eng/149308.htm
The Quad-Core Intel® Xeon® Processor 5300 Series supports Intel® Virtualization
Technology for hardware-assisted virtualization within the processor. Intel Virtualization
Technology is a set of hardware enhancements that can improve virtualization
solutions. Intel Virtualization Technology is used in conjunction with Virtual Machine
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 9
Monitor software enabling multiple, independent software environments inside a single
platform. Further details on Intel Virtualization Technology can be found at
http://developer.intel.com/technology/virtualization/index.htm.
The Quad-Core Intel® Xeon® Processor 5300 Series are intended for high performance
server and workstation systems. The processors support a Dual Independent Bus (DIB)
architecture with one processor on each bus, up to two processor sockets in a system.
The DIB architecture provides improved performance by allowing increased FSB speeds
and bandwidth. The processors will be packaged in an FC-LGA6 Land Grid Array
package with 771 lands for improved power delivery. It utilizes a surface mount
LGA771 socket that supports Direct Socket Loading (DSL).
Table 1-1. Quad-Core Intel® Xeon® Processor 5300 Series Features
Introduction
# of Processor
Cores
4 32 KB instruction
L1 Cache (per
core)
32 KB data
L2 Advanced
Transfer Cache
4MB Shared L2
Cache per die
8MB Total Cache
Front Side Bus
Frequency
1333 MHz
1066 MHz
Package
FC-LGA6
771 Lands
Quad-Core Intel® Xeon® Processor 5300 Series based platforms implement
independent core voltage (V
) power planes for each processor. FSB termination
CC
voltage (VTT) is shared and must connect to all FSB agents. The processor core voltage
utilizes power delivery guidelines specified by VRM/EVRD 11.0 and its associated load
line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 11.0 Design Guidelines for further details). VRM/EVRD 11.0 will support the
power requirements of all frequencies of the processors including Flexible Motherboard
Guidelines (FMB) (see Section 2.13.1). Refer to the appropriate platform design
guidelines for implementation details.
The Quad-Core Intel® Xeon® Processor 5300 Series support either 1333 or 1066 MHz
Front Side Bus operation. The FSB utilizes a split-transaction, deferred reply protocol
and Source-Synchronous Transfer (SST) of address and data to improve performance.
The processor transfers data four times per bus clock (4X data transfer rate, as in AGP
4X). Along with the 4X data bus, the address bus can deliver addresses two times per
bus clock and is referred to as a ‘double-clocked’ or a 2X address bus. In addition, the
Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 10.66 GBytes (1333 MHz) or 8.5
GBytes (1066 MHz) per second. The FSB is also used to deliver interrupts.
Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages.
Section 2.1 contains the electrical specifications of the FSB while implementation
details are fully described in the appropriate platform design guidelines (refer to
Section 1.3).
10 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Introduction
1.1 Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the asserted state when driven to a low level. For example, when RESET# is low, a
reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
Commonly used terms are explained here for clarification:
• Quad-Core Intel® Xeon® Processor 5300 Series – Intel 64-bit microprocessor
intended for dual processor servers and workstations. The Quad-Core Intel®
Xeon® Processor 5300 Series is based on Intel’s 65 nanometer process, in the
FC-LGA6 package with four processor cores. For this document, “processor” is used
as the generic term for the “Quad-Core Intel® Xeon® Processor 5300 Series”. The
term ‘processors’ and “Quad-Core Intel® Xeon® Processor 5300 Series” are
inclusive of Quad-Core Intel® Xeon® Processor E5300 Series and Quad-Core
Intel® Xeon® Processor X5300 Series.
• Quad-Core Intel® Xeon® Processor E5300 Series – A mainstream
performance version of the Quad-Core Intel® Xeon® Processor E5300 Series. For
this document “Quad-Core Intel® Xeon® Processor E5300 Series” is used to call
out specifications that are unique to the Quad-Core Intel® Xeon® Processor E5300
Series SKU.
• Quad-Core Intel® Xeon® Processor X5300 Series – An accelerated
performance version of the Quad-Core Intel® Xeon® Processor X5300 Series. For
this document “Quad-Core Intel® Xeon® Processor X5300 Series” is used to call
out specifications that are unique to the Quad-Core Intel® Xeon® Processor X5300
Series SKU.
• FC-LGA6 (Flip Chip Land Grid Array) Package – The Quad-Core Intel® Xeon®
Processor 5300 Series package is a Land Grid Array, consisting of a processor core
mounted on a pinless substrate with 771 lands, and includes an integrated heat
spreader (IHS).
• LGA771 socket – The Quad-Core Intel® Xeon® Processor 5300 Series interfaces
to the baseboard through this surface mount, 771 Land socket. See the LGA771
Socket Design Guidelines for details regarding this socket.
• Processor core – Processor core with integrated L1 cache. L2 cache and system
bus interface are shared between the two cores on the die. All AC timing and signal
integrity specifications are at the pads of the processor die.
• FSB (Front Side Bus) – The electrical interface that connects the processor to the
chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 11
Introduction
• Dual Independent Bus (DIB) – A front side bus architecture with one processor
on each bus, rather than a FSB shared between two processor agents. The DIB
architecture provides improved performance by allowing increased FSB speeds and
bandwidth.
• Flexible Motherboard Guidelines (FMB) – Are estimates of the maximum
values the Quad-Core Intel® Xeon® Processor 5300 Series will have over certain
time periods. The values are only estimates and actual specifications for future
processors may differ.
• Functional Operation – Refers to the normal operating conditions in which all
processor specifications, including DC, AC, FSB, signal quality, mechanical and
thermal are satisfied.
• Storage Conditions – Refers to a non-operational state. The processor may be
installed in a platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased or receive any clocks.
Upon exposure to “free air” (that is, unsealed packaging or a device removed from
packaging material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.
• Priority Agent – The priority agent is the host bridge to the processor and is
typically known as the chipset.
• Symmetric Agent – A symmetric agent is a processor which shares the same I/O
subsystem and memory array, and runs the same operating system as another
processor in a system. Systems using symmetric agents are known as Symmetric
Multiprocessing (SMP) systems.
• Integrated Heat Spreader (IHS) – A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
• Thermal Design Power – Processor thermal solutions should be designed to meet
this target. It is the highest expected sustainable power while running known
power intensive real applications. TDP is not the maximum power that the
processor can dissipate.
• Intel® 64 Architecture – Instruction set architecture and programming
environment of Intel’s 64-bit processors, which are a superset of and compatible
with IA-32. This 64-bit instruction set architecture was formerly known as IA-32
with EM64T or Intel® EM64T.
• Enhanced Intel SpeedStep® Technology – Technology that provides power
management capabilities to servers and workstations.
• Platform Environment Control Interface (PECI) – A proprietary one-wire bus
interface that provides a communication channel between Intel processor and
chipset components to external thermal monitoring devices, for use in fan speed
control. PECI communicates readings from the processor’s Digital Thermal Sensor
(DTS). The replaces the thermal diode available in previous processors.
• Intel® Virtualization Technology (Intel® VT) – Processor virtualization which
when used in conjunction with Virtual Machine Monitor software enables multiple,
robust independent software environments inside a single platform.
• VRM (Voltage Regulator Module) – DC-DC converter built onto a module that
interfaces with a card edge socket and supplies the correct voltage and current to
the processor based on the logic state of the processor VID bits.
• EVRD (Enterprise Voltage Regulator Down) – DC-DC converter integrated onto
the system board that provides the correct voltage and current to the processor
based on the logic state of the processor VID bits.
12 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Introduction
• V
• V
• V
– The processor core power supply.
CC
– The processor ground.
SS
– FSB termination voltage. (Note: In some Intel processor EMTS documents,
TT
VTT is instead called V
1.2 State of Data
The data contained within this document is the most accurate information available by
the publication date of this document.
1.3 References
Material and concepts available in the following documents may be beneficial when
reading this document:
AP-485, Intel® Processor Identification and the CPUID Instruction 241618 1
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B
IA-32 Intel® Architecture Optimization Reference Manual 248966 1
Intel® Virtualization Technology Specification for the IA-32 Intel® Architecture C97063 1
Quad-Core Intel® Xeon® Processor 5300 Series Specification Update 315338 1
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD)
11.0 Design Guidelines
Quad-Core Intel® Xeon® Processor 5300 SeriesThermal/Mechanical Design
Guidelines
LGA771 Socket Mechanical Design Guide 313871 1
Quad-Core Intel® Xeon® Processor 5300 Series Boundary Scan Description
Language (BSDL) Model
Debug Port Design Guide for UP/DP Systems 1
Notes:
1. Document is available publicly at http://developer.intel.com.
2. Document not available at the time of printing.
.)
CCP
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Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 13
§
Introduction
14 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Electrical Specifications
2 Electrical Specifications
2.1 Front Side Bus and GTLREF
Most Quad-Core Intel® Xeon® Processor 5300 Series FSB signals use Assisted
Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides
improved noise margins and reduced ringing through low voltage swings and controlled
edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the
high logic level and termination. AGTL+ output buffers differ from GTL+ buffers with
the addition of an active PMOS pull-up transistor to “assist” the pull-up resistors during
the first clock of a low-to-high voltage transition. Platforms implement a termination
voltage level for AGTL+ signals defined as V
power planes for each processor (and chipset), separate V
necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address buses have made
signal integrity considerations and platform design methods even more critical than
with previous processor families. Design guidelines for the processor FSB are detailed
in the appropriate platform design guidelines (refer to Section 1.3).
The AGTL+ inputs require reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID and GTLREF_ADD_END) which are used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF_DATA_MID and
GTLREF_DATA_END are used for the 4X front side bus signaling group and
GTLREF_ADD_MID and GTLREF_ADD_END are used for the 2X and common clock front
side bus signaling groups. GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END must be generated on the baseboard (See
Ta b le 2- 18 for GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID and
GTLREF_ADD_END specifications). Refer to the applicable platform design guidelines
for details. Termination resistors (R
silicon and are terminated to VTT. The on-die termination resistors are always enabled
on the processor to control reflections on the transmission line. Intel chipsets also
provide on-die termination, thus eliminating the need to terminate the bus on the
baseboard for most AGTL+ signals.
) for AGTL+ signals are provided on the processor
TT
. Because platforms implement separate
TT
and V
CC
supplies are
TT
Some FSB signals do not include on-die termination (R
the baseboard. See Tab le 2- 7 and Tab le 2- 8 for details regarding these signals.
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for
AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog
signal simulation of the FSB, including trace lengths, is highly recommended when
designing a system. Contact your Intel Field Representative to obtain the applicable
signal integrity models, which includes buffer and package models.
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 15
) and must be terminated on
TT
2.2 Power and Ground Lands
For clean on-chip processor core power distribution, the processor has 223 VCC (power)
and 267 V
plane, while all VSS lands must be connected to the system ground plane. The
processor V
Voltage IDentification (VID) signals. See Tab le 2- 3 for VID definitions.
Twenty two lands are specified as VTT, which provide termination for the FSB and
provides power to the I/O buffers. The platform must implement a separate supply for
these lands which meets the V
(ground) inputs. All VCC lands must be connected to the processor power
SS
lands must be supplied with the voltage determined by the processor
CC
specifications outlined in Ta b le 2- 1 2.
TT
2.3 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large average current swings between low and full power states.
This may cause voltages on power planes to sag below their minimum values if bulk
decoupling is not adequate. Larger bulk storage (C
supply current during longer lasting changes in current demand by the component,
such as coming out of an idle condition. Similarly, they act as a storage well for current
when entering an idle condition from a running condition. Care must be taken in the
baseboard design to ensure that the voltage provided to the processor remains within
the specifications listed in Ta b le 2- 1 2. Failure to do so can result in timing violations or
reduced lifetime of the component. For further information and guidelines, refer to the
appropriate platform design guidelines.
Electrical Specifications
), such as electrolytic capacitors,
BULK
2.3.1 V
Vcc regulator solutions need to provide bulk capacitance with a low Effective Series
Resistance (ESR), and the baseboard designer must assure a low interconnect
resistance from the regulator (EVRD or VRM pins) to the LGA771 socket. Bulk
decoupling must be provided on the baseboard to handle large current swings. The
power delivery solution must insure the voltage and current specifications are met (as
defined in Tab l e 2- 12 ). For further information regarding power delivery, decoupling
and layout guidelines, refer to the appropriate platform design guidelines.
2.3.2 V
Bulk decoupling must be provided on the baseboard. Decoupling solutions must be
sized to meet the expected load. To insure optimal performance, various factors
associated with the power delivery solution must be considered including regulator
type, power plane and trace sizing, and component placement. A conservative
decoupling solution consists of a combination of low ESR bulk capacitors and high
frequency ceramic capacitors. For further information regarding power delivery,
decoupling and layout guidelines, refer to the appropriate platform design guidelines.
Decoupling
CC
Decoupling
TT
16 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Electrical Specifications
2.3.3 Front Side Bus AGTL+ Decoupling
The processor integrates signal termination on the die, as well as a portion of the
required high frequency decoupling capacitance on the processor package. However,
additional high frequency capacitance must be added to the baseboard to properly
decouple the return currents from the FSB. Bulk decoupling must also be provided by
the baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in
the appropriate platform design guidelines.
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor
Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous processor generations, the processor core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is set during
manufacturing. The default setting is for the maximum speed of the processor. It is
possible to override this setting using software (see the Intel® 64 and IA-32
Architectures Software Developer’s Manual). This permits operation at lower
frequencies than the processor’s tested frequency.
The processor core frequency is configured during reset by using values stored
internally during manufacturing. The stored value sets the highest bus fraction at which
the particular processor can operate. If lower speeds are desired, the appropriate ratio
can be configured via the CLOCK_FLEX_MAX Model Specific Register (MSR). For details
of operation at core frequencies lower than the maximum rated processor speed, refer
to the Intel® 64 and IA-32 Architectures Software Developer’s Manual.
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread
spectrum clocking. Processor DC and AC specifications for the BCLK[1:0] inputs are
provided in Tab le 2- 19 . These specifications must be met while also meeting signal
integrity requirements as outlined in Tab l e 2 - 19 . The processor utilizes differential
clocks. Tab le 2- 1 contains processor core frequency to FSB multipliers and their
corresponding core frequencies.
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 17
Table 2-1. Core Frequency to FSB Multiplier Configuration
Electrical Specifications
Core Frequency to FSB
Multiplier
1/6 2 GHz 1.60 GHz 1, 2, 3, 4
1/7 2.33 GHz 1.86 GHz 1, 2, 3
1/8 2.66 GHz 2.13 GHz 1, 2, 3
1/9 3 GHz 2.40 GHz 1, 2, 3
Notes:
1. Individual processors operate only at or below the frequency marked on the package.
2. Listed frequencies are not necessarily committed production frequencies.
3. For valid processor core frequencies, refer to the Quad-Core Intel® Xeon® Processor 5300 Series
Specification Update.
4. The lowest bus ratio supported is 1/6.
Core Frequency with
333.333 MHz Bus Clock
Core Frequency with
266.666 MHz Bus Clock
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])
Upon power up, the FSB frequency is set to the maximum supported by the individual
processor. BSEL[2:0] are CMOS outputs which must be pulled up to VTT, and are used
to select the FSB frequency. Please refer to Tab le 2-1 5 for DC specifications. Ta b le 2- 2
defines the possible combinations of the signals and the frequency associated with each
combination. The frequency is determined by the processor(s), chipset, and clock
synthesizer. All FSB agents must operate at the same core and FSB frequency. See the
appropriate platform design guidelines for further details.
Table 2-2. BSEL[2:0] Frequency Table
BSEL2 BSEL1 BSEL0 Bus Clock Frequency
0 0 0 266.666 MHz
0 0 1 Reserved
0 1 0 Reserved
0 1 1 Reserved
1 0 0 333.333 MHz
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
Notes
18 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Electrical Specifications
2.4.2 PLL Power Supply
An on-die PLL filter solution is implemented on the processor. The V
to provide power to the on chip PLL of the processor. Please refer to Tab le 2- 1 2 for DC
specifications. Refer to the appropriate platform design guidelines for decoupling and
routing guidelines.
2.5 Voltage Identification (VID)
The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines. The voltage set by the VID signals is the reference VR output voltage to be
delivered to the processor Vcc pins. Please refer to Tab le 2- 1 6 for the DC specifications
for these signals. A voltage range is provided in Tab l e 2- 1 2 and changes with
frequency. The specifications have been set such that one voltage regulator can
operate with all supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core frequency may have different default VID settings. This is
reflected by the VID range values provided in Tab le 2-3 .
The Quad-Core Intel® Xeon® Processor 5300 Series uses six voltage identification
signals, VID[6:1], to support automatic selection of power supply voltages. Tab l e 2- 3
specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table
refers to a high voltage level and a ‘0’ refers to a low voltage level. The definition
provided in Tab l e 2 - 3 is not related in any way to previous Intel® Xeon® processors or
voltage regulator designs. If the processor socket is empty (VID[6:1] = 111111), or
the voltage regulation circuit cannot supply the voltage that is requested, the voltage
regulator must disable itself. See the Voltage Regulator Module (VRM) and Enterprise
Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details.
input is used
CCPLL
Although the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 11.0 Design Guidelines defines VID [7:0], VID 7 and VID 0 are not used on the
Quad-Core Intel® Xeon® Processor 5300 Series. Please refer to the appropriate
platform design guide for details.
The Quad-Core Intel® Xeon® Processor 5300 Series provide the ability to operate
while transitioning to an adjacent VID and its associated processor core voltage (V
CC
).
This will represent a DC shift in the load line. It should be noted that a low-to-high or
high-to-low voltage state change may result in as many VID transitions as necessary to
reach the target core voltage. Transitions above the specified VID are not permitted.
Ta b le 2- 12 includes VID step sizes and DC shift ranges. Minimum and maximum
voltages must be maintained as shown in Tab l e 2- 13 .
The VRM or EVRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in
Ta b le 2- 12 .
Power source characteristics must be guaranteed to be stable whenever the supply to
the voltage regulator is stable.
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 19
Table 2-3. Voltage Identification Definition
Electrical Specifications
HEX
VID6
400
mV
VID5
200
mV
VID4
100
mV
VID3
50
mV
VID2
25
mV
VID1
12.5 mVV
CC_MAX
HEX
VID6
400
mV
VID5
200
mV
VID4
100
mV
VID3
50
mV
VID2
25
mV
VID1
12.5 mVV
CC_MAX
7A111101 0.8500 3C 0 1 1 1 1 0 1.2375
7811110
7611101
7411101
7211100
7011100
6E11011
6C11011
6A11010
0 0.8625 3A 0 1 1 1 0 1 1.2500
1 0.8750 38 0 1 1 1 0 0 1.2625
0 0.8875 36 0 1 1 0 1 1 1.2750
1 0.9000 34 0 1 1 0 1 0 1.2875
0 0.9125 32 0 1 1 0 0 1 1.3000
1 0.9250 30 0 1 1 0 0 0 1.3125
0 0.9375 2E 0 1 0 1 1 1 1.3250
1 0.9500 2C 0 1 0 1 1 0 1.3375
68 1 1 0 1 0 0 0.9625 2A 0 1 0 1 0 1 1.3500
66 1 1 0 0 1 1 0.9750 28 0 1 0 1 0 0 1.3625
64 1 1 0 0 1 0 0.9875 26 0 1 0 0 1 1 1.3750
62 1 1 0 0 0 1 1.0000 24 0 1 0 0 1 0 1.3875
60 1 1 0 0 0 0 1.0125 22 0 1 0 0 0 1 1.4000
5E 1 0 1 1 1 1 1.0250 20 0 1 0 0 0 0 1.4125
5C 1 0 1 1 1 0 1.0375 1E 0 0 1 1 1 1 1.4250
5A 1 0 1 1 0 1 1.0500 1C 0 0 1 1 1 0 1.4375
58 1 0 1 1 0 0 1.0625 1A 0 0 1 1 0 1 1.4500
56 1 0 1 0 1 1 1.0750 18 0 0 1 1 0 0 1.4625
54 1 0 1 0 1 0 1.0875 16 0 0 1 0 1 1 1.4750
52 1 0 1 0 0 1 1.1000 14 0 0 1 0 1 0 1.4875
50 1 0 1 0 0 0 1.1125 12 0 0 1 0 0 1 1.5000
4E 1 0 0 1 1 1 1.1250 100010001.5125
4C 1 0 0 1 1 0 1.1375 0E0001111.5250
4A 1 0 0 1 0 1 1.1500 0C0001101.5375
48 1 0 0 1 0 0 1.1625 0A0001011.5500
46 1 0 0 0 1 1 1.1750 080001001.5625
44 1 0 0 0 1 0 1.1875 060000111.5750
42 1 0 0 0 0 1 1.2000 040000101.5875
40 1 0 0 0 0 0 1.2125 020000011.6000
3E 0 1 1 1 1 1 1.2250 00000000OFF
1
Notes:
1. When the “111111” VID pattern is observed, the voltage regulator output should be disabled.
2. Shading denotes the expected VID range of the Quad-Core Intel® Xeon® Processor 5300 Series.
3. The VID range includes VID transitions that may be initiated by thermal events, assertion of the FORCEPR# signal (see
Section 6.2.3), Extended HALT state transitions (see Section 7.2.2), or Enhanced Intel SpeedStep® Technology transitions
(see Section 7.3). The Extended HALT state must be enabled for the processor to remain within its specifications.
4. Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a specific VID off code is
received, the VRM/EVRD must turn off its output (the output should go to high impedance) within 500 ms and latch off until
power is cycled.
20 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Electrical Specifications
Table 2-4. Loadline Selection Truth Table for LL_ID[1:0]
LL_ID1 LL_ID0 Description
00Reserved
0 1 Dual-Core Intel® Xeon® Processor 5000 Series
10Reserved
1 1 All Quad-Core Intel® Xeon® Processor 5300 Series
Note: The LL_ID[1:0] signals are used by the platform to select the correct loadline slope for the processor.
Dual-Core Intel® Xeon® Processor 5100 Series
Table 2-5. Market Segment Selection Truth Table for MS_ID[1:0]
MS_ID1 MS_ID0 Description
0 0 Dual-Core Intel® Xeon® Processor 5000 Series
0 1 Dual-Core Intel® Xeon® Processor 5100 Series
1 0 All Quad-Core Intel® Xeon® Processor 5300 Series
11Reserved
Note: The MS_ID[1:0] signals are provided to indicate the Market Segment for the processor and may be
used for future processor compatibility or for keying.
2.6 Reserved, Unused, or Test Signals
All Reserved signals must remain unconnected. Connection of these signals to VCC, VTT,
, or to any other signal (including each other) can result in component malfunction
V
SS
or incompatibility with future processors. See Section 4 for a land listing of the
processor and the location of all Reserved signals.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active high inputs, should be connected through a
resistor to ground (V
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. Resistor values should be within ± 20% of the impedance of the baseboard
trace for FSB signals, unless otherwise noticed in the appropriate platform design
guidelines. For unused AGTL+ input or I/O signals, use pull-up resistors of the same
value as the on-die termination resistors (R
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and utilized outputs must be terminated on the baseboard. Unused
outputs may be terminated on the baseboard or left unconnected. Note that leaving
unused outputs unterminated may interfere with some TAP functions, complicate debug
probing, and prevent boundary scan testing. Signal termination for these signal types
is discussed in the appropriate platform design guidelines.
For each processor socket, connect the TESTIN1 and TESTIN2 signals together, then
terminate the net with a 51 Ω resistor to V
). Unused outputs can be left unconnected; however, this may
SS
). For details see Tab l e 2- 18 .
TT
.
TT
The TESTHI signals must be tied to the processor V
matched resistor has a resistance value within ± 20% of the impedance of the board
transmission line traces. For example, if the trace impedance is 50 Ω, then a value
between 40 Ω and 60 Ω is required.
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 21
using a matched resistor, where a
TT
The TESTHI signals may use individual pull-up resistors or be grouped together as
detailed below. A matched resistor must be used for each group:
• TESTHI[1:0] - can be grouped together with a single pull-up to V
• TESTHI[7:2] - can be grouped together with a single pull-up to V
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI11 – cannot be grouped with other TESTHI signals
2.7 Front Side Bus Signal Groups
The FSB signals have been combined into groups by buffer type. AGTL+ input signals
have differential input buffers, which use GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END as reference levels. In this document, the
term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group
when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as
the AGTL+ I/O group when driving. AGTL+ asynchronous outputs can become active
anytime and include an active PMOS pull-up transistor to assist during the first clock of
a low-to-high voltage transition.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals whose timings are
specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the
second set is for the source synchronous signals which are relative to their respective
strobe lines (data and address) as well as rising edge of BCLK0. Asynchronous signals
are still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Tab le 2- 6 identifies which signals are common clock, source synchronous
and asynchronous.
Electrical Specifications
TT
TT
Table 2-6. FSB Signal Groups (Sheet 1 of 2)
Signal Group Type Signals
AGTL+ Common Clock Input Synchronous to
AGTL+ Common Clock Output Synchronous to
AGTL+ Common Clock I/O Synchronous to
AGTL+ Source Synchronous I/O Synchronous to assoc.
AGTL+ Strobes I/O Synchronous to
Open Drain Output Asynchronous FERR#/PBE#, IERR#, PROCHOT#, THERMTRIP#
BCLK[1:0]
BCLK[1:0]
BCLK[1:0]
strobe
BCLK[1:0]
1
BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#,
TRDY#;
BPM4#, BPM[2:1]#, BPMb[2:1]#
2
ADS#, AP[1:0]#, BINIT#
BPM3#, BPM0#, BPMb3#, BPMb0#, BR[1:0]#,
DBSY#, DP[3:0]#, DRDY#, HIT#
LOCK#, MCERR#
Signals Associated Strobe
REQ[4:0]#,A[16:3]#,
A[37:36]#
A[35:17]# ADSTB1#
D[15:0]#, DBI0# DSTBP0#, DSTBN0#
D[31:16]#, DBI1# DSTBP1#, DSTBN1#
D[47:32]#, DBI2# DSTBP2#, DSTBN2#
D[63:48]#, DBI3# DSTBP3#, DSTBN3#
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
2
3
, BNR#2, BPM5#,
2
, HITM#2,
ADSTB0#
22 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Electrical Specifications
Table 2-6. FSB Signal Groups (Sheet 2 of 2)
Signal Group Type Signals
CMOS Asynchronous Input Asynchronous A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/
CMOS Asynchronous Output Asynchronous BSEL[2:0], VID[6:1]
FSB Clock Clock BCLK[1:0]
TAP Input Synchronous to TCK TCK, TDI, TMS, TRST#
TAP Output Synchronous to TCK TDO
Power/Other Power/Other COMP[3:0], GTLREF_ADD_MID,
Notes:
1. Refer to Section 5 for signal descriptions.
2. These signals may be driven simultaneously by multiple agents (Wired-OR).
3. Not all Quad-Core Intel® Xeon® Processor 5300 Series support the additional signals A[37:36]#.
Processors that support these signals will be outlined in the Quad-Core Intel® Xeon® Processor 5300
Series Specification Update.
1
INTR, LINT1/NMI, PWRGOOD, SMI#, STPCLK#,
GTLREF_ADD_END, GTLREF_DATA_MID,
GTLREF_DATA_END, LL_ID[1:0], MS_ID[1:0],
PECI, RESERVED, SKTOCC#, TESTHI[11:10],
TESTHI[7:0], TESTIN1, TESTIN2, VCC,
VCC_DIE_SENSE, VCC_DIE_SENSE2, VCCPLL,
VID_SELECT, VSS_DIE_SENSE,
VSS_DIE_SENSE2, VSS, VTT, VTT_OUT,
VTT_SEL
Ta b le 2- 7 and Ta bl e 2- 8 outline the signals which include on-die termination (RTT).
Ta b le 2- 7 denotes AGTL+ signals, while Tab l e 2 - 8 outlines non AGTL+ signals including
open drain signals. Tab l e 2 - 9 provides signal reference voltages.
Table 2-7. AGTL+ Signal Description Table
AGTL+ signals with R
A[37:3]#1, ADS#, ADSTB[1:0]#, AP[1:0]#,
BINIT#, BNR#, BPRI#, D[63:0]#, DBI[3:0]#,
DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
Note:
1. Not all Quad-Core Intel® Xeon® Processor 5300 Series support the additional signals A[37:36]#.
Processors that support these signals will be outlined in the Quad-Core Intel® Xeon® Processor 5300
Series Specification Update.
TT
Table 2-8. Non AGTL+ Signal Description Table
Signals with R
FORCEPR#1, PROCHOT#
TT
1
AGTL+ signals with no R
BPM[5:0]#, BPMb[3:0]#, RESET#, BR[1:0]#
Signals with no R
A20M#, BCLK[1:0], BSEL[2:0], COMP[3:0], FERR#/
PBE#, GTLREF_ADD_MID, GTLREF_ADD_END,
GTLREF_DATA_MID, GTLREF_DATA_END, IERR#,
IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, LL_ID[1:0],
MS_ID[1:0], PECI, PWRGOOD, SKTOCC#, SMI#,
STPCLK#, TCK, TDI, TDO, TESTHI[11:10], TESTHI[7:0],
TESTIN1, TESTIN2, THERMTRIP#, TMS, TRST#,
VCC_DIE_SENSE, VCC_DIE_SENSE2, VID[6:1],
VID_SELECT, VSS_DIE_SENSE, VSS_DIE_SENSE2,
VTT_SEL
TT
TT
Note:
1. Signals that have a 50 Ω pullup to V
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 23
on package.
TT
Table 2-9. Signal Reference Voltages
GTLREF CMOS
A[37:3]#
BINIT#, BNR#, BPM[5:0]#, BPMb[3:0]#, BPRI#,
BR[1:0]#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,
HIT#, HITM#, LOCK#, MCERR#, RESET#,
REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
Note:
1. Not all Quad-Core Intel® Xeon® Processor 5300 Series support the additional signals A[37:36]#.
1
, ADS#, ADSTB[1:0]#, AP[1:0]#,
Processors that support these signals will be outlined in the Quad-Core Intel® Xeon® Processor 5300
Series Specification Update.
A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR,
LINT1/NMI, PWRGOOD, SMI#, STPCLK#, TCK, TDI,
TMS, TRST#
2.8 CMOS Asynchronous and Open Drain
Asynchronous Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize
CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#,
and THERMTRIP# utilize open drain output buffers. All of the CMOS and Open Drain
signals are required to be asserted/deasserted for at least eight BCLKs in order for the
processor to recognize the proper signal state. See Section 2.13 for the DC
specifications. See Section 7 for additional timing requirements for entering and
leaving the low power states.
Electrical Specifications
2.9 Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Similar considerations must be made for
TCK, TDO, TMS, and TRST#. Two copies of each signal may be required with each
driving a different voltage level.
2.10 Platform Environmental Control Interface (PECI)
DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processor and external thermal monitoring devices. The Quad-Core
Intel® Xeon® Processor 5300 Series contains Digital Thermal Sensors (DTS)
distributed throughout the die. These sensors are implemented as analog-to-digital
converters calibrated at the factor for reasonable accuracy to provide a digital
representation of relative processor temperature. PECI provides an interface to relay
the highest DTS temperature within a die to external management devices for thermal/
fan speed control.
2.10.1 DC Characteristics
A PECI device interface operates at a nominal voltage set by VTT. The set of DC
electrical specifications shown in Tab l e 2 - 10 is used with devices normally operating
from a V
PECI devices will operate at the V
system. For V
interface supply. VTT nominal levels will vary between processor families. All
TT
specifications, refer to Tab le 2- 1 2.
TT
level determined by the processor installed in the
TT
24 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Electrical Specifications
Table 2-10. PECI DC Electrical Limits
Symbol Definition and Conditions Min Max Units Notes
V
in
V
hysteresis
V
N
V
p
I
source
I
sink
I
leak+
I
leak-
C
bus
V
noise
Input Voltage Range -0.150 V
Negative-edge threshold
Positive-edge threshold
High level output source
(V
Low level output sink
(V
High impedance state
High impedance leakage
Bus capacitance per node N/A 10 pF 3
Signal noise immunity
Hysteresis 0.1 * V
voltage
voltage
= 0.75 * VTT)
OH
= 0.25 * VTT)
OL
leakage to V
= VOL)
(V
leak
TT
0.275 * V
0.550 * V
to GND
= VOH)
(V
leak
above 300 MHz
0.1 * V
V
V
TT
V
TT
TT
TT
TT
TT
N/A V
0.500 * V
0.725 * V
-6.0 N/A mA
0.5 1.0 mA
N/A 50 µA 2
N/A 10 µA 2
TT
N/A V
p-p
1
Note:
1. V
2. The leakage specification applies to powered devices on the PECI bus.
3. One node is counted for each client and one node for the system host. Extended trace lengths might appear
supplies the PECI interface. PECI behavior does not affect VTT min/max specifications.
TT
as additional nodes.
2.10.2 Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use Figure 2-1 as a guide for input buffer design.
Figure 2-1. Input Device Hysteresis
V
TT
Maximum V
Minimum V
Maximum V
Minimum V
PECI Ground
P
P
N
N
PECI High Range
PECI Low Range
Minimum
Hysteresis
Valid Input
Signal Range
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 25
2.11 Mixing Processors
Intel supports and validates dual processor configurations only in which both
processors operate with the same FSB frequency, core frequency, number of cores, and
have the same internal cache sizes. Mixing components operating at different internal
clock frequencies is not supported and will not be validated by Intel. Combining
processors from different power segments is also not supported.
Electrical Specifications
Note: Processors within a system must operate at the same frequency per bits [12:8] of the
CLOCK_FLEX_MAX MSR; however this does not apply to frequency transitions initiated
due to thermal events, Extended HALT, Enhanced Intel SpeedStep® Technology
transitions, or assertion of the FORCEPR# signal.
Not all operating systems can support dual processors with mixed frequencies. Mixing
processors of different steppings but the same model (as per CPUID instruction) is
supported. Details regarding the CPUID instruction are provided in the AP-485 Intel®
Processor Identification and the CPUID Instruction application note.
2.12 Absolute Maximum and Minimum Ratings
Tab le 2- 1 1 specifies absolute maximum and minimum ratings only, which lie outside
the functional limits of the processor. Only within specified operation limits, can
functionality and long-term reliability be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
.
electric fields.
Table 2-11. Processor Absolute Maximum Ratings
Symbol Parameter Min Max Unit Notes
V
CC
V
TT
T
CASE
T
STORAGE
Notes:
1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must
be satisfied.
2. Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Section 3.
Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
26 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Core voltage with respect to VSS -0.30 1.55 V
FSB termination voltage with respect to
V
SS
Processor case temperature See
Storage temperature -40 85 °C3, 4, 5
-0.30 1.55 V
Section 6
See
Section 6
1, 2
°C
Electrical Specifications
3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not
receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect
the long-term reliability of the device. For functional operation, please refer to the processor case
temperature specifications.
4. This rating applies to the processor and does not include any tray or packaging.
5. Failure to adhere to this specification can affect the long-term reliability of the processor.
2.13 Processor DC Specifications
The processor DC specifications in this section are defined at the processor die
(pads) unless noted otherwise. See Tab le 4- 1 for the Quad-Core Intel® Xeon®
Processor 5300 Series land listings and Ta bl e 5 -1 for signal definitions. Voltage and
current specifications are detailed in Ta b le 2- 1 2. For platform planning refer to
Ta b le 2- 13 , which provides V
is presented graphically in Figure 2-4 and Figure 2-5 .
The FSB clock signal group is detailed in Tab l e 2- 19 . The DC specifications for the
AGTL+ signals are listed in Ta b le 2- 1 4. Legacy signals and Test Access Port (TAP)
signals follow DC specifications similar to GTL+. The DC specifications for the
PWRGOOD input and TAP signal group are listed in Tab le 2- 1 5.
Ta b le 2- 12 through Tab le 2- 1 6 list the DC specifications for the processor and are valid
only while meeting specifications for case temperature (T
clock frequency, and input voltages. Care should be taken to read all notes associated
with each parameter.
Static and Transient Tolerances. This same information
CC
as specified in Section 6),
CASE
2.13.1 Flexible Motherboard Guidelines (FMB)
The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the
Quad-Core Intel® Xeon® Processor 5300 Series will have over certain time periods.
The values are only estimates and actual specifications for future processors may differ.
Processors may or may not have specifications equal to the FMB value in the
foreseeable future. System designers should meet the FMB values to ensure their
systems will be compatible with future processors.
Table 2-12. Voltage and Current Specifications (Sheet 1 of 2)
Symbol Parameter Min Typ Max Unit Notes
VID VID range for Quad-Core
V
CC
V
CC_BOOT
V
VID_STEP
V
VID_SHIFT
V
TT
V
CCPLL
Intel® Xeon® Processor
E5300 Series and Quad-Core
Intel® Xeon® Processor
X5300 Series
VCC for processor core
Launch - FMB
Default VCC Voltage for initial
power up 1.10 V 2
VID step size during a
transition ± 12.5 mV
Total allowable DC load line
shift from VID steps 450 mV 10
FSB termination voltage
(DC + AC specification) 1.14 1.20 1.26 V 8,13
PLL supply voltage (DC + AC
specification) 1.455 1.500 1.605 V
1.0000 1.5000 V
See Ta b le 2- 1 3, Figure 2-4, Figure 2-5
V
1,11
2, 3, 4, 6, 9
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 27
Table 2-12. Voltage and Current Specifications (Sheet 2 of 2)
Symbol Parameter Min Typ Max Unit Notes
I
CC
I
CC_RESET
I
CC
I
CC_RESET
I
TT
I
CC_TDC
I
CC_TDC
I
CC_VTT_OUT
I
CC_GTLREF
I
CC_VCCPLL
I
TCC
I
TCC
ICC for Quad-Core Intel®
Xeon® Processor E5300
Series core with multiple VID
Launch - FMB
I
Intel® Xeon® Processor
E5300 Series core with
multiple VID
CC_RESET
for Quad-Core
Launch - FMB
ICC for Quad-Core Intel®
Xeon® Processor X5300
Series core with multiple VID
Launch - FMB 125 A 4,5,6,9
I
Intel® Xeon® Processor
X5300 Series core with
CC_RESET
for Quad-Core
multiple VID
Launch - FMB
ICC for VTT supply before VCC
stable
for VTT supply after VCC
I
CC
stable
Thermal Design Current
(TDC) Quad-Core Intel®
Xeon® Processor E5300
Series
Launch - FMB
Thermal Design Current
(TDC) Quad-Core Intel®
Xeon® Processor X5300
Series
Launch - FMB
DC current that may be
drawn from V
ICC for
GTLREF_DATA_MID,
GTLREF_DATA_END,
GTLREF_ADD_MID,
per land 580 mA 16
TT_OU T
GTLREF_ADD_END 200 µA 7
ICC for PLL supply 260 mA 12
I
for Quad-Core Intel®
CC
Xeon® Processor E5300
Series during active thermal
control circuit (TCC)
I
for Quad-Core Intel®
CC
Xeon® Processor X5300
Series during active thermal
control circuit (TCC) 125 A
Electrical Specifications
90 A 4,5,6,9
90 A 17
125 A 17
8.0
7.0
A
15
A
70 A 6,14
110 A 6,14
90 A
1,11
Notes:
1. Unless otherwise noted, all specifications in this table are based on final silicon characterization data.
2. These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See Section 2.5 for more information.
3. The voltage specification requirements are measured across the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands with an oscilloscope set to 100 MHz
bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of
ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled
in the scope probe.
4. The processor must not be subjected to any static V
particular current. Failure to adhere to this specification can shorten processor lifetime.
5. I
specification is based on maximum V
CC_MAX
capable of drawing I
average processor current draw over various time durations.
28 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
level that exceeds the V
CC
loadline Refer to Figure 2-6 for details. The processor is
for up to 10 ms. Refer to Figure 2-2 and Figure 2-3 for further details on the
CC_MAX
CC
associated with any
CC_MAX
Electrical Specifications
6. FMB is the flexible motherboard guideline. These guidelines are for estimation purposes only. See
Section 2.13.1 for further details on FMB guidelines.
7. This specification represents the total current for GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END.
must be provided via a separate voltage source and must not be connected to VCC. This specification is
8. V
TT
measured at the land.
9. Minimum V
in Figure 6-1.
10. This specification refers to the total reduction of the load line due to VID transitions below the specified
VID.
11. Individual processor VID values may be calibrated during manufacturing such that two devices at the same
frequency may have different VID settings.
12. This specification applies to the VCCPLL land.
13. Baseboard bandwidth is limited to 20 MHz.
14. I
CC_TDC
should be used for the voltage regulator temperature assessment. The voltage regulator is responsible for
monitoring its temperature and asserting the necessary signal to inform the processor of a thermal
excursion. Please see the applicable design guidelines for further details. The processor is capable of
drawing I
current draw over various time durations. This parameter is based on design characterization and is not
tested.
15. This is the maximum total current drawn from the V
specification does not include the current coming from on-board termination (R
Refer to the appropriate platform design guide and the Voltage Regulator Design Guidelines to determine
the total I
16. I
CC_VTT_OUT
17. I
.
CC_RESET
and maximum ICC are specified at the maximum processor case temperature (T
CC
CASE
) shown
is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and
indefinitely. Refer to Figure 2-2 and Figure 2-3 for further details on the average processor
CC_TDC
plane by only one processor with RTT enabled. This
TT
drawn by the system. This parameter is based on design characterization and is not tested.
TT
is specified at 1.2 V.
), through the signal line.
TT
is specified while PWRGOOD and RESET# are asserted.
Figure 2-2. Quad-Core Intel® Xeon® Processor E5300 Series Load Current versus Time
10 0
95
90
85
80
75
70
Sustained Current (A)
65
60
0.01 0.1 1 10 100 1000
Time Duration (s)
Notes:
1. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than
2. Not 100% tested. Specified by design characterization.
I
CC_TDC
.
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 29
Electrical Specifications
Figure 2-3. Quad-Core Intel® Xeon® Processor X5300 Series Load Current versus Time
13 0
12 5
12 0
115
110
10 5
Sustained Current (A)
10 0
0.01 0.1 1 10 100 1000
Time Duration (s)
Notes:
1. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than
2. Not 100% tested. Specified by design characterization.
I
CC_TDC
.
Table 2-13. VCC Static and Transient Tolerance (Sheet 1 of 2)
ICC (A) V
(V) V
CC_Max
(V) V
CC_Typ
(V) Notes
CC_Min
0 VID - 0.000 VID - 0.015 VID - 0.030 1, 2, 3
5 VID - 0.006 VID - 0.021 VID - 0.036 1, 2, 3
10 VID - 0.013 VID - 0.028 VID - 0.043 1, 2, 3
15 VID - 0.019 VID - 0.034 VID - 0.049 1, 2, 3
20 VID - 0.025 VID - 0.040 VID - 0.055 1, 2, 3
25 VID - 0.031 VID - 0.046 VID - 0.061 1, 2, 3
30 VID - 0.038 VID - 0.053 VID - 0.068 1, 2, 3
35 VID - 0.044 VID - 0.059 VID - 0.074 1, 2, 3
40 VID - 0.050 VID - 0.065 VID - 0.080 1, 2, 3
45 VID - 0.056 VID - 0.071 VID - 0.086 1, 2, 3
50 VID - 0.069 VID - 0.084 VID - 0.099 1, 2, 3
55 VID - 0.069 VID - 0.077 VID - 0.093 1, 2, 3
60 VID - 0.075 VID - 0.090 VID - 0.105 1, 2, 3
65 VID - 0.081 VID - 0.096 VID - 0.111 1, 2, 3
70 VID - 0.087 VID - 0.103 VID - 0.118 1, 2, 3
75 VID - 0.094 VID - 0.109 VID - 0.124 1, 2, 3
80 VID - 0.100 VID - 0.115 VID - 0.130 1, 2, 3
85 VID - 0.106 VID - 0.121 VID - 0.136 1, 2, 3
90 VID - 0.113 VID - 0.128 VID - 0.143 1, 2, 3,
95 VID - 0.119 VID - 0.134 VID - 0.149 1, 2, 3, 4
100 VID - 0.125 VID - 0.140 VID - 0.155 1, 2, 3, 4
105 VID - 0.131 VID - 0.146 VID - 0.161 1, 2, 3, 4
110 VID - 0.138 VID - 0.153 VID - 0.168 1, 2, 3, 4
115 VID - 0.144 VID - 0.159 VID - 0.174 1, 2, 3, 4
30 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
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