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Intel Xeon 3500 Series Datasheet

Intel® Xeon® Processor 3500 Series

Datasheet, Volume 1
July 2009
Document Number: 321332-002
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Xeon® Processor 3500 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.
Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology­enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For more information including details on which processors support HT Technology, see
http://www.intel.com/products/ht/hyperthreading_more.htm
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information.
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.
Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see www.intel.com.
Enhanced Intel SpeedStep® Technology. See the http://processorfinder.intel.com or contact your Intel representative for more information.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Pentium, Intel Xeon, Intel Atom, Enhanced Intel SpeedStep Technology, Intel Turbo Boost Technology, Intel Hyper-Threading Technology, Intel Virtualization Technology, Intel® Advanced Digital Media Boost, and the Intel logo are trademarks or registered trademarks of Intel Corporation in the U. S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2009 Intel Corporation.
2 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1

Contents

1Introduction..............................................................................................................9
1.1 Terminology ..................................................................................................... 10
1.2 References ....................................................................................................... 11
2 Electrical Specifications ........................................................................................... 13
2.1 Intel® QPI Differential Signaling ......................................................................... 13
2.2 Power and Ground Lands.................................................................................... 13
2.3 Decoupling Guidelines........................................................................................ 13
2.3.1 VCC, VTTA, VTTD, VDDQ Decoupling......................................................... 14
2.4 Processor Clocking (BCLK_DP, BCLK_DN) ............................................................. 14
2.4.1 PLL Power Supply................................................................................... 14
2.5 Voltage Identification (VID) ................................................................................ 14
2.6 Reserved or Unused Signals................................................................................ 17
2.7 Signal Groups ................................................................................................... 18
2.8 Test Access Port (TAP) Connection....................................................................... 19
2.9 Platform Environmental Control Interface (PECI) DC Specifications........................... 20
2.9.1 DC Characteristics .................................................................................. 20
2.9.2 Input Device Hysteresis .......................................................................... 21
2.10 Absolute Maximum and Minimum Ratings ............................................................. 21
2.11 Processor DC Specifications ................................................................................ 22
2.11.1 DC Voltage and Current Specification ........................................................ 23
2.11.2 VCC Overshoot Specification .................................................................... 29
2.11.3 Die Voltage Validation............................................................................. 30
3 Package Mechanical Specifications .......................................................................... 31
3.1 Package Mechanical Drawing............................................................................... 31
3.2 Processor Component Keep-Out Zones................................................................. 34
3.3 Package Loading Specifications ........................................................................... 34
3.4 Package Handling Guidelines............................................................................... 34
3.5 Package Insertion Specifications.......................................................................... 34
3.6 Processor Mass Specification............................................................................... 35
3.7 Processor Materials............................................................................................ 35
3.8 Processor Markings............................................................................................ 35
3.9 Processor Land Coordinates ................................................................................ 36
®
4Intel
4.1 Intel Xeon Processor 3500 Series Land Assignments .............................................. 37
5 Signal Definitions .................................................................................................... 75
5.1 Signal Definitions .............................................................................................. 75
6 Thermal Specifications ............................................................................................ 79
6.1 Package Thermal Specifications........................................................................... 79
6.2 Processor Thermal Features................................................................................ 84
6.3 Platform Environment Control Interface (PECI)...................................................... 88
6.4 Storage Conditions Specifications ........................................................................ 90
Xeon® Processor 3500 Series Land Listing .................................................... 37
4.1.1 Land Listing by Land Name...................................................................... 38
4.1.2 Land Listing by Land Number................................................................... 56
6.1.1 Thermal Specifications ............................................................................ 79
6.1.2 Thermal Metrology ................................................................................. 83
6.2.1 Processor Temperature ........................................................................... 84
6.2.2 Adaptive Thermal Monitor........................................................................ 84
6.2.3 THERMTRIP# Signal ............................................................................... 87
6.3.1 Introduction .......................................................................................... 88
6.3.2 PECI Specifications ................................................................................. 89
Intel® Xeon® Processor 3500 Series Datasheet, Volume 1 3
7Features..................................................................................................................93
7.1 Power-On Configuration (POC).............................................................................93
7.2 Clock Control and Low Power States.....................................................................93
7.2.1 Thread and Core Power State Descriptions .................................................94
7.2.2 Package Power State Descriptions.............................................................95
7.3 Sleep States .....................................................................................................96
7.4 ACPI P-States (Intel
7.5 Enhanced Intel SpeedStep® Technology ...............................................................97
8 Boxed Processor Specifications................................................................................99
8.1 Introduction......................................................................................................99
8.2 Mechanical Specifications..................................................................................100
8.2.1 Boxed Processor Cooling Solution Dimensions...........................................100
8.2.2 Boxed Processor Fan Heatsink Weight .....................................................102
8.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly ...102
8.3 Electrical Requirements ....................................................................................102
8.3.1 Fan Heatsink Power Supply .................................................................... 102
8.4 Thermal Specifications......................................................................................103
8.4.1 Boxed Processor Cooling Requirements....................................................103
8.4.2 Variable Speed Fan ...............................................................................105
®
Turbo Boost Technology) .....................................................96

Figures

1-1 High-Level View of Processor Interfaces................................................................. 9
2-1 Active ODT for a Differential Link Example ............................................................13
2-2 Input Device Hysteresis......................................................................................21
2-3 VCC Static and Transient Tolerance Load Lines ......................................................25
2-4 VTT Static and Transient Tolerance Load Line ........................................................27
2-5 VCC Overshoot Example Waveform ......................................................................30
3-1 Processor Package Assembly Sketch.....................................................................31
3-2 Processor Package Drawing (Sheet 1 of 2) ............................................................32
3-3 Processor Package Drawing (Sheet 2 of 2) ............................................................33
3-4 Processor Top-Side Markings...............................................................................35
3-5 Processor Land Coordinates and Quadrants (Bottom View) ......................................36
6-1 Processor Thermal Profile....................................................................................81
6-2 Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location ..........83
6-3 Frequency and Voltage Ordering ..........................................................................86
7-1 Power States.....................................................................................................94
8-1 Mechanical Representation of the Boxed Processor .................................................99
8-2 Space Requirements for the Boxed Processor (side view) ...................................... 100
8-3 Space Requirements for the Boxed Processor (top view) ....................................... 101
8-4 Space Requirements for the Boxed Processor (overall view) ..................................101
8-5 Boxed Processor Fan Heatsink Power Cable Connector Description.......................... 102
8-6 Baseboard Power Header Placement Relative to Processor Socket...........................103
8-7 Boxed Processor Fan Heatsink Airspace Keepout Requirements (top view)...............104
8-8 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side view).............. 104
8-9 Boxed Processor Fan Heatsink Set Points ............................................................105
4 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1

Tables

1-1 References ....................................................................................................... 11
2-1 Voltage Identification Definition........................................................................... 15
2-2 Market Segment Selection Truth Table for MS_ID[2:0] ........................................... 17
2-3 Signal Groups ................................................................................................... 18
2-4 Signals with ODT............................................................................................... 19
2-5 PECI DC Electrical Limits .................................................................................... 20
2-6 Processor Absolute Minimum and Maximum Ratings............................................... 22
2-7 Voltage and Current Specifications....................................................................... 23
2-8 VCC Static and Transient Tolerance ..................................................................... 24
2-9 VTT Voltage Identification (VID) Definition............................................................ 25
2-10 VTT Static and Transient Tolerance...................................................................... 25
2-11 DDR3 Signal Group DC Specifications................................................................... 27
2-12 RESET# Signal DC Specifications......................................................................... 28
2-13 TAP Signal Group DC Specifications ..................................................................... 28
2-14 PWRGOOD Signal Group DC Specifications............................................................ 28
2-15 Control Sideband Signal Group DC Specifications................................................... 29
2-16 VCC Overshoot Specifications.............................................................................. 29
3-1 Processor Loading Specifications ......................................................................... 34
3-2 Package Handling Guidelines............................................................................... 34
3-3 Processor Materials............................................................................................ 35
4-1 Land Listing by Land Name................................................................................. 38
4-2 Land Listing by Land Number.............................................................................. 56
5-1 Signal Definitions .............................................................................................. 75
6-1 Processor Thermal Specifications......................................................................... 80
6-2 Processor Thermal Profile ................................................................................... 81
6-3 Thermal Solution Performance above TCONTROL ................................................... 82
6-4 Supported PECI Command Functions and Codes .................................................... 89
6-5 GetTemp0() Error Codes .................................................................................... 90
6-6 Storage Condition Ratings .................................................................................. 90
7-1 Power On Configuration Signal Options................................................................. 93
7-2 Coordination of Thread Power States at the Core Level ........................................... 94
7-3 Processor S-States ............................................................................................ 96
8-1 Fan Heatsink Power and Signal Specifications...................................................... 103
8-2 Fan Heatsink Power and Signal Specifications...................................................... 105
Intel® Xeon® Processor 3500 Series Datasheet, Volume 1 5

Intel® Xeon® Processor 3500 Series Features

• Available at 3.33 GHz, 3.20 GHz, 3.06 GHz,
2.93 GHz, and 2.66 GHz
• Enhanced Intel Speedstep® Tec h n o lo g y
®
• Supports Intel
64Φ Architecture
• Supports Intel® Virtualization Technology
®
• Intel
Turbo Boost Technology
• Supports Execute Disable Bit capability
• Binary compatible with applications running
on previous members of the Intel microprocessor line
• Intel
®
Wide Dynamic Execution
• Very deep out-of-order execution
• Enhanced branch prediction
• Optimized for 32-bit applications running on
advanced 32-bit operating systems
®
• Intel
Smart Cache
• 8 MB Level 3 cache
®
• Intel
Advanced Digital Media Boost
• Enhanced floating point and multimedia unit
for enhanced video, audio, encryption, and 3D performance
• New accelerators for improved string and
text processing operations
• Power Management capabilities
• System Management mode
• Multiple low-power states
• 8-way cache associativity provides improved
cache hit rate on load/store operations
• System Memory Interface
— Memory controller integrated in
processor package — 3 channels — 2 DIMMs/channel supported (6 total) — 24 GB maximum memory supported — Support unbuffered DIMMs only — Single Rank and Dual Rank DIMMs
supported — DDR3 speeds of 800/1066 MHz
supported — 512Mb, 1Gb, 2Gb,
Technologies/Densities supported
®
• Intel
QuickPath Interconnect (Intel® QPI) — Fast/narrow unidirectional links — Concurrent bi-directional traffic — Error detection via CRC — Error correction via Link level retry — Packet based protocol — Point to point cache coherent
interconnect
®
—Intel
Interconnect Built In Self Test
®
(Intel
IBIST) toolbox built-in
• 1366-land Package
• ECC and DCA (Direct Cache Access)
6 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1

Revision History

Revision
Number
321332-001 • Public release March 2009
• Added Processor Information for W3580, W3550 July 2009
Description Date
§
Intel® Xeon® Processor 3500 Series Datasheet, Volume 1 7
8 Intel® Xeon® Processor 3500 Series Datasheet, Volume 1
Introduction

1 Introduction

The Intel® Xeon® Processor 3500 Series are intended for Uni-processor (UP) and workstation systems. Several architectural and microarchitectural enhancements have been added to this processor including four processor cores in the processor package and increased shared cache.
The Intel Xeon Processor 3500 Series is the first multi-core processor to implement key new technologies:
• Integrated memory controller
• Point-to-point link interface based on Intel
Figure 1-1 shows the interfaces used with these new technologies.
Figure 1-1. High-Level View of Processor Interfaces
Processor
®
QuickPath Interconnect (Intel® QPI)
CH 0
CH 1
CH 2
System
Memory
(DDR3)
Intel® QuickPath Interconnect (Intel
®
QPI)
Note: In this document the Intel Xeon Processor 3500 Series will be referred to as “the
processor.”
The processor is optimized for performance with the power efficiencies of a low-power microarchitecture.
This document provides DC electrical specifications, differential signaling specifications, pinout and signal definitions, package mechanical specifications and thermal requirements, and additional features pertinent to the implementation and operation of the processor. For information on register descriptions, refer to the Intel® Xeon® Processor 3500 Series Datasheet, Volume 2.
The processor is a multi-core processor built on the 45 nm process technology, that uses up to 130 W thermal design power (TDP). The processor features an Intel QPI point-to-point link capable of up to 6.4 GT/s, 8 MB Level 3 cache, and an integrated memory controller.
The processor supports all the existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and Streaming SIMD Extensions 4 (SSE4). The processor supports several Advanced Technologies: Intel Enhanced Intel SpeedStep
®
Turbo Boost Technology, and Intel® Hyper-Threading Technology.
Intel
®
Tec h nol o gy, In t el® Virtualization Technology (Intel® VT),
®
64 Technology (Intel® 64),
Intel® Xeon® Processor 3500 Series Datasheet Volume 1 9

1.1 Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when VTTPWRGOOD is high, the V stable.
‘_N’ and ‘_P’ after a signal name refers to a differential pair.
Commonly used terms are explained here for clarification:
• Intel® Xeon® Processor 3500 Series — The entire product, including processor substrate and integrated heat spreader (IHS).
• 1366-land LGA package — The Intel® Xeon® Processor 3500 Series is available in a Flip-Chip Land Grid Array (FC-LGA) package, consisting of the processor mounted on a land grid array substrate with an integrated heat spreader (IHS).
• LGA1366 Socket — The processor (in the LGA 1366 package) mates with the system board through this surface mount, 1366-contact socket.
• DDR3 — Double Data Rate 3 Synchronous Dynamic Random Access Memory (SDRAM) is the name of the new DDR memory standard that is being developed as the successor to DDR2 SRDRAM.
®
• Intel point-to-point link based electrical interconnect specification for Intel processors and chipsets.
• Integrated Memory Controller — A memory controller that is integrated into the processor die.
• Integrated Heat Spreader (IHS) — A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.
• Functional Operation — Refers to the normal operating conditions in which all processor specifications, including DC, AC, signal quality, mechanical, and thermal, are satisfied.
• Enhanced Intel SpeedStep Technology allows the operating system to reduce power consumption when performance is not needed.
• Execute Disable Bit — Execute Disable allows memory to be marked as executable or non-executable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel for more detailed information. Refer to http://developer.intel.com/ for future reference on up to date nomenclatures.
• Intel the processor to execute operating systems and applications written to take advantage of Intel model can be found at http://developer.intel.com/technology/intel64/.
• Intel® Virtualization Technology (Intel® VT) — A set of hardware enhancements to Intel server and client platforms that can improve virtualization solutions. Intel solutions and enables a more robust hardware assisted virtualization solution. More information can be found at: http://www.intel.com/technology/virtualization/
QuickPath Interconnect (Intel® QPI)— Intel QPI is a cache-coherent,
®
64 Architecture — An enhancement to Intel's IA-32 architecture, allowing
®
Introduction
power rail is
TT
®
Technology — Enhanced Intel SpeedStep
®
Architecture Software Developer's Manual
®
64. Further details on Intel® 64 architecture and programming
VT provides a foundation for widely-deployed virtualization
10 Intel® Xeon® Processor 3500 Series Datasheet Volume 1
Introduction
• Unit Interval (UI) — Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for every edge of the forwarded clock, whether it is a rising edge or a falling edge. If a number of edges are collected at instances
, t2, tn,...., tk then the UI at instance “n” is defined as:
t
1
• Jitter — Any timing variation of a transition edge or edges from the defined Unit Interval.
• Storage Conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks.
• OEM — Original Equipment Manufacturer.

1.2 References

Material and concepts available in the following documents may be beneficial when reading this document.
Table 1-1. References
Intel® Xeon® Processor 3500 Series Specification Update 321333 1
Intel® Xeon® Processor Series Datasheet, Volume 2 321344 1
Intel® Xeon® Processor 3500 Series and LGA1366 Socket Thermal and Mechanical Design Guide
Note:
1. Document is available publicly at http://www.intel.com.
UI n = t n – t
Document Reference # Notes
n – 1
321461 1
§
Intel® Xeon® Processor 3500 Series Datasheet Volume 1 11
Introduction
12 Intel® Xeon® Processor 3500 Series Datasheet Volume 1
Electrical Specifications

2 Electrical Specifications

2.1 Intel® QPI Differential Signaling

The processor provides an Intel QPI port for high speed serial transfer between other Intel QPI-enabled components. The Intel QPI port consists of two unidirectional links (for transmit and receive). Intel QPI uses a differential signalling scheme where pairs of opposite-polarity (D_P, D_N) signals are used.
On-die termination (ODT) is provided on the processor silicon and termination is to V Intel chipsets also provide ODT; thus, eliminating the need to terminate the Intel QPI links on the system board.
Intel strongly recommends performing analog simulations of the Intel
Figure 2-1 illustrates the active ODT. Signal listings are included in Table 2-3 and Table 2-4. See Chapter 5 for the pin signal definitions. All Intel QPI signals are in the
differential signal group.
Figure 2-1. Active ODT for a Differential Link Example
T
X
Signal
Signal
R
TT
R
TT

2.2 Power and Ground Lands

For clean on-chip processor core power distribution, the processor has 210 VCC pads and 119 VSS pads associated with V
; 28 VTTD pads and 17 VSS pads associated with V
V
TTA
pads associated with V
; and 3 VCCPLL pads. All VCCP, VTTA, VTTD, VDDQ and
DDQ
VCCPLL lands must be connected to their respective processor power planes, while all VSS lands must be connected to the system ground plane. The processor VCC lands must be supplied with the voltage determined by the processor Voltage IDentification (VID) signals. Table 2-1 specifies the voltage level for the various VIDs.
; 8 VTTA pads and 5 VSS pads associated with
CC
®
QPI interface.
R
X
R
TT
, 28 VDDQ pads and 17 VSS
TTD
R
TT
SS
.

2.3 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage (C current during longer lasting changes in current demand; such as, coming out of an idle condition. Similarly, capacitors act as a storage well for current when entering an idle condition from a running condition. Care must be taken in the baseboard design to
Intel® Xeon® Processor 3500 Series Datasheet Volume 1 13
), such as electrolytic capacitors, supply
BULK
Electrical Specifications
ensure that the voltage provided to the processor remains within the specifications listed in Ta b le 2- 7. Failure to do so can result in timing violations or reduced lifetime of the processor.
2.3.1 VCC, V
Voltage regulator solutions need to provide bulk capacitance and the baseboard designer must assure a low interconnect resistance from the regulator to the LGA1366 socket. Bulk decoupling must be provided on the baseboard to handle large current swings. The power delivery solution must insure the voltage and current specifications are met (as defined in Table 2-7).
TTA
, V
TTD
, V
Decoupling
DDQ

2.4 Processor Clocking (BCLK_DP, BCLK_DN)

The processor core, Intel QPI, and integrated memory controller frequencies are generated from BCLK_DP and BCLK_DN. Unlike previous processors based on front side bus architecture, there is no direct link between core frequency and Intel QPI link frequency (such as, no core frequency to Intel QPI multiplier). The processor maximum core frequency, Intel QPI link frequency and integrated memory controller frequency, are set during manufacturing. It is possible to override the processor core frequency setting using software. This permits operation at lower core frequencies than the factory set maximum core frequency.
The processor’s maximum non-turbo core frequency is configured during power-on reset by using values stored internally during manufacturing. The stored value sets the highest core multiplier at which the particular processor can operate. If lower max non­turbo speeds are desired, the appropriate ratio can be configured via the CLOCK_FLEX_MAX MSR.
The processor uses differential clocks (BCLK_DP, BCLK_DN). Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which requires a constant frequency BCLK_DP, BCLK_DN input, with exceptions for spread spectrum clocking. The processor core frequency is determined by multiplying the ratio by 133 MHz.

2.4.1 PLL Power Supply

An on-die PLL filter solution is implemented on the processor. Refer to Ta bl e 2 - 7 for DC specifications.

2.5 Voltage Identification (VID)

The voltage set by the VID signals is the reference voltage regulator output voltage to be delivered to the processor VCC pins. VID signals are CMOS push/pull drivers. Refer to Table 2-15 for the DC specifications for these signals. The VID codes will change due to temperature and/or current load changes in order to minimize the power of the part. A voltage range is provided in Table 2-7. The specifications have been set such that one voltage regulator can operate with all supported frequencies.
Individual processor VID values may be set during manufacturing such that two devices at the same core frequency may have different default VID settings. This is reflected by the VID range values provided in Table 2-1.
14 Intel® Xeon® Processor 3500 Series Datasheet Volume 1
Electrical Specifications
The processor uses eight voltage identification signals, VID[7:0], to support automatic selection of voltages. Table 2-1 specifies the voltage level corresponding to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[7:0] = 11111111), or the voltage regulation circuit cannot supply the voltage that is requested, the voltage regulator must disable itself.
The processor its associated processor core voltage (V
provides the ability to operate while transitioning to an adjacent VID and
). This will represent a DC shift in the
CC
loadline. It should be noted that a low-to-high or high-to-low voltage state change will result in as many VID transitions as necessary to reach the target core voltage. Transitions above the maximum specified VID are not permitted. Table 2-8 includes VID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 2-8.
The VR used must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 2-7 and
Table 2-8.
Table 2-1. Voltage Identification Definition (Sheet 1 of 3)
VID7VID6VID5VID4VID3VID2VID1VID
0 0 0 0 0 0 0 0 OFF 0 1 0 1 1 0 1 1 1.04375
0 0 0 0 0 0 0 1 OFF 0 1 0 1 1 1 0 0 1.03750
0 0 0 0 0 0 1 0 1.60000 0 1 0 1 1 1 0 1 1.03125
0 0 0 0 0 0 1 1 1.59375 0 1 0 1 1 1 1 0 1.02500
0 0 0 0 0 1 0 0 1.58750 0 1 0 1 1 1 1 1 1.01875
0 0 0 0 0 1 0 1 1.58125 0 1 1 0 0 0 0 0 1.01250
0 0 0 0 0 1 1 0 1.57500 0 1 1 0 0 0 0 1 1.00625
000 001
000 010
0 0 0 0 1 0 0 1 1.55625 0 1 1 0 0 1 0 0 0.98750
0 0 0 0 1 0 1 0 1.55000 0 1 1 0 0 1 0 1 0.98125
0 0 0 0 1 0 1 1 1.54375 0 1 1 0 0 1 1 0 0.97500
0 0 0 0 1 1 0 0 1.53750 0 1 1 0 0 1 1 1 0.96875
0 0 0 0 1 1 0 1 1.53125 0 1 1 0 1 0 0 0 0.96250
0 0 0 0 1 1 1 0 1.52500 0 1 1 0 1 0 0 1 0.95626
0 0 0 0 1 1 1 1 1.51875 0 1 1 0 1 0 1 0 0.95000
0 0 0 1 0 0 0 0 1.51250 0 1 1 0 1 0 1 1 0.94375
0 0 0 1 0 0 0 1 1.50625 0 1 1 0 1 1 0 0 0.93750
0 0 0 1 0 0 1 0 1.50000 0 1 1 0 1 1 0 1 0.93125
0 0 0 1 0 0 1 1 1.49375 0 1 1 0 1 1 1 0 0.92500
0 0 0 1 0 1 0 0 1.48750 0 1 1 0 1 1 1 1 0.91875
0 0 0 1 0 1 0 1 1.48125 0 1 1 1 0 0 0 0 0.91250
0 0 0 1 0 1 1 0 1.47500 0 1 1 1 0 0 0 1 0.90625
0 0 0 1 0 1 1 1 1.46875 0 1 1 1 0 0 1 0 0.90000
0 0 0 1 1 0 0 0 1.46250 0 1 1 1 0 0 1 1 0.89375
0 0 0 1 1 0 0 1 1.45625 0 1 1 1 0 1 0 0 0.88750
0 0 0 1 1 0 1 0 1.45000 0 1 1 1 0 1 0 1 0.88125
0 0 0 1 1 0 1 1 1.44375 0 1 1 1 0 1 1 0 0.87500
0 0 0 1 1 1 0 0 1.43750 0 1 1 1 0 1 1 1 0.86875
0 0 0 1 1 1 0 1 1.43125 0 1 1 1 1 0 0 0 0.86250
0 0 0 1 1 1 1 0 1.42500 0 1 1 1 1 0 0 1 0.85625
1 1 1.56875 0 1 1 0 0 0 1 0 1.00000
0 0 1.56250 0 1 1 0 0 0 1 1 0.99375
V
CC_MAX
0
VID7VID6VID5VID4VID3VID2VID1VID
0
V
CC_MAX
Intel® Xeon® Processor 3500 Series Datasheet Volume 1 15
Electrical Specifications
Table 2-1. Voltage Identification Definition (Sheet 2 of 3)
VID7VID6VID5VID4VID3VID2VID1VID
V
CC_MAX
0
0 0 0 1 1 1 1 1 1.41875 0 1 1 1 1 0 1 0 0.85000
0 0 1 0 0 0 0 0 1.41250 0 1 1 1 1 0 1 1 0.84374
0 0 1 0 0 0 0 1 1.40625 0 1 1 1 1 1 0 0 0.83750
0 0 1 0 0 0 1 0 1.40000 0 1 1 1 1 1 0 1 0.83125
0 0 1 0 0 0 1 1 1.39375 0 1 1 1 1 1 1 0 0.82500
0 0 1 0 0 1 0 0 1.38750 0 1 1 1 1 1 1 1 0.81875
0 0 1 0 0 1 0 1 1.38125 1 0 0 0 0 0 0 0 0.81250
0 0 1 0 0 1 1 0 1.37500 1 0 0 0 0 0 0 1 0.80625
0 0 1 0 0 1 1 1 1.36875 1 0 0 0 0 0 1 0 0.80000
0 0 1 0 1 0 0 0 1.36250 1 0 0 0 0 0 1 1 0.79375
0 0 1 0 1 0 0 1 1.35625 1 0 0 0 0 1 0 0 0.78750
0 0 1 0 1 0 1 0 1.35000 1 0 0 0 0 1 0 1 0.78125
0 0 1 0 1 0 1 1 1.34375 1 0 0 0 0 1 1 0 0.77500
0 0 1 0 1 1 0 0 1.33750 1 0 0 0 0 1 1 1 0.76875
0 0 1 0 1 1 0 1 1.33125 1 0 0 0 1 0 0 0 0.76250
0 0 1 0 1 1 1 0 1.32500 1 0 0 0 1 0 0 1 0.75625
0 0 1 0 1 1 1 1 1.31875 1 0 0 0 1 0 1 0 0.75000
0 0 1 1 0 0 0 0 1.31250 1 0 0 0 1 0 1 1 0.74375
0 0 1 1 0 0 0 1 1.30625 1 0 0 0 1 1 0 0 0.73750
0 0 1 1 0 0 1 0 1.30000 1 0 0 0 1 1 0 1 0.73125
0 0 1 1 0 0 1 1 1.29375 1 0 0 0 1 1 1 0 0.72500
0 0 1 1 0 1 0 0 1.28750 1 0 0 0 1 1 1 1 0.71875
0 0 1 1 0 1 0 1 1.28125 1 0 0 1 0 0 0 0 0.71250
0 0 1 1 0 1 1 0 1.27500 1 0 0 1 0 0 0 1 0.70625
0 0 1 1 0 1 1 1 1.26875 1 0 0 1 0 0 1 0 0.70000
0 0 1 1 1 0 0 0 1.26250 1 0 0 1 0 0 1 1 0.69375
0 0 1 1 1 0 0 1 1.25625 1 0 0 1 0 1 0 0 0.68750
0 0 1 1 1 0 1 0 1.25000 1 0 0 1 0 1 0 1 0.68125
0 0 1 1 1 0 1 1 1.24375 1 0 0 1 0 1 1 0 0.67500
0 0 1 1 1 1 0 0 1.23750 1 0 0 1 0 1 1 1 0.66875
0 0 1 1 1 1 0 1 1.23125 1 0 0 1 1 0 0 0 0.66250
0 0 1 1 1 1 1 0 1.22500 1 0 0 1 1 0 0 1 0.65625
0 0 1 1 1 1 1 1 1.21875 1 0 0 1 1 0 1 0 0.65000
0 1 0 0 0 0 0 0 1.21250 1 0 0 1 1 0 1 1 0.64375
0 1 0 0 0 0 0 1 1.20625 1 0 0 1 1 1 0 0 0.63750
0 1 0 0 0 0 1 0 1.20000 1 0 0 1 1 1 0 1 0.63125
0 1 0 0 0 0 1 1 1.19375 1 0 0 1 1 1 1 0 0.62500
0 1 0 0 0 1 0 0 1.18750 1 0 0 1 1 1 1 1 0.61875
0 1 0 0 0 1 0 1 1.18125 1 0 1 0 0 0 0 0 0.61250
0 1 0 0 0 1 1 0 1.17500 1 0 1 0 0 0 0 1 0.60625
0 1 0 0 0 1 1 1 1.16875 1 0 1 0 0 0 1 0 0.60000
0 1 0 0 1 0 0 0 1.16250 1 0 1 0 0 0 1 1 0.59375
0 1 0 0 1 0 0 1 1.15625 1 0 1 0 0 1 0 0 0.58750
0 1 0 0 1 0 1 0 1.15000 1 0 1 0 0 1 0 1 0.58125
0 1 0 0 1 0 1 1 1.14375 1 0 1 0 0 1 1 0 0.57500
0 1 0 0 1 1 0 0 1.13750 1 0 1 0 0 1 1 1 0.56875
0 1 0 0 1 1 0 1 1.13125 1 0 1 0 1 0 0 0 0.56250
0 1 0 0 1 1 1 0 1.12500 1 0 1 0 1 0 0 1 0.55625
VID7VID6VID5VID4VID3VID2VID1VID
0
V
CC_MAX
16 Intel® Xeon® Processor 3500 Series Datasheet Volume 1
Electrical Specifications
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Table 2-1. Voltage Identification Definition (Sheet 3 of 3)
VID7VID6VID5VID4VID3VID2VID1VID
0 1 0 0 1 1 1 1 1.11875 1 0 1 0 1 0 1 0 0.55000
0 1 0 1 0 0 0 0 1.11250 1 0 1 0 1 0 1 1 0.54375
0 1 0 1 0 0 0 1 1.10625 1 0 1 0 1 1 0 0 0.53750
0 1 0 1 0 0 1 0 1.10000 1 0 1 0 1 1 0 1 0.53125
0 1 0 1 0 0 1 1 1.09375 1 0 1 0 1 1 1 0 0.52500
0 1 0 1 0 1 0 0 1.08750 1 0 1 0 1 1 1 1 0.51875
0 1 0 1 0 1 0 1 1.08125 1 0 1 1 0 0 0 0 0.51250
0 1 0 1 0 1 1 0 1.07500 1 0 1 1 0 0 0 1 0.50625
0 1 0 1 0 1 1 1 1.06875 1 0 1 1 0 0 1 0 0.50000
010110001.06250 11111110 OFF
010110011.05625 11111111 OFF
0 1 0 1 1 0 1 0 1.05000
V
CC_MAX
0
VID7VID6VID5VID4VID3VID2VID1VID
0
V
CC_MAX
Table 2-2. Market Segment Selection Truth Table for MS_ID[2:0]
MSID2 MSID1 MSID0 Description
0 0 0 Reserved
0 0 1 Reserved
0 1 0 Reserved
0 1 1 Reserved
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Intel Xeon Processor 3500 Series
1 1 1 Reserved
otes:
1. The MSID[2:0] signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying.
1

2.6 Reserved or Unused Signals

All Reserved (RSVD) signals must remain unconnected. Connection of these signals to VCC, V result in component malfunction or incompatibility with future processors. See
Chapter 4 for a land listing of the processor and the location of all Reserved signals.
For reliable operation, always connect unused inputs or bi-directional signals to an appropriate signal level, except for unused integrated memory controller inputs, outputs, and bi-directional pins which may be left floating. Unused active high inputs should be connected through a resistor to ground (V unconnected; however, this may interfere with some Test Access Port (TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bi-directional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability.
Intel® Xeon® Processor 3500 Series Datasheet Volume 1 17
TTA
, V
TTD
, V
DDQ
, V
, VSS, or to any other signal (including each other) can
CCPLL
). Unused outputs maybe left
SS

2.7 Signal Groups

Signals are grouped by buffer type and similar characteristics as listed in Table 2-3. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals have On­Die Termination (ODT) resistors. There are some signals that do not have ODT and need to be terminated on the board. The signals that have ODT are listed in Table 2-4.
Table 2-3. Signal Groups (Sheet 1 of 2)
Signal Group Type Signals
System Reference Clock
Differential Clock Input BCLK_DP, BCLK_DN
®
Intel
QPI Signal Groups
Differential Intel QPI Input QPI_DRX_D[N/P][19:0], QPI_CLKRX_DP,
Differential Intel QPI Output QPI_DTX_D[N/P][19:0], QPI_CLKTX_DP,
DDR3 Reference Clocks
Differential
DDR3 Output DDR{0/1/2}_CLK[D/P][3:0]
Electrical Specifications
1,2
QPI_CLKRX_DN
QPI_CLKTX_DN
DDR3 Command Signals
Single ended CMOS Output DDR{0/1/2}_RAS#, DDR{0/1/2}_CAS#,
Single ended Asynchronous Output DDR{0/1/2}_RESET#
DDR3 Control Signals
Single ended CMOS Output DDR{0/1/2}_CS#[5:4], DDR{0/1/2}_CS#[1:0],
DDR3 Data Signals
Single ended CMOS Bi-directional DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_ECC[7:0]
Differential CMOS Bi-directional DDR{0/1/2}_DQS_[N/P][7:0]
TAP
Single ended TAP Input TCK, TDI, TMS, TRST#
Single ended GTL Output TDO
Control Sideband
Single ended Asynchronous GTL Output PRDY#
Single ended Asynchronous GTL Input PREQ#
Single ended GTL Bi-directional CAT_ERR#, BPM#[7:0]
Single Ended Asynchronous Bi-directional PECI
Single Ended Analog Input COMP0, QPI_CMP[0], DDR_COMP[2:0]
Single ended Asynchronous GTL Bi-
directional
Single ended Asynchronous GTL Output THERMTRIP#
Single ended CMOS Input/Output VID[7:6]
DDR{0/1/2}_WE#, DDR{0/1/2}_MA[15:0], DDR{0/1/2}_BA[2:0]
DDR{0/1/2}_ODT[3:0], DDR{0/1/2}_CKE[3:0]
PROCHOT#
VID[5:3]/CSC[2:0] VID[2:0]/MSID[2:0] VTT_VID[4:2]
18 Intel® Xeon® Processor 3500 Series Datasheet Volume 1
Electrical Specifications
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Table 2-3. Signal Groups (Sheet 2 of 2)
Signal Group Type Signals
Single ended CMOS Output VTT_VID[4:2]
Single ended Analog Input ISENSE
Reset Signal
Single ended Reset Input RESET#
PWRGOOD Signals
Single ended Asynchronous Input VCCPWRGOOD, VTTPWRGOOD, VDDPWRGOOD
Power/Other
Power VCC, VTTA, VTTD, VCCPLL, VDDQ
Asynchronous CMOS Output PSI#
Sense Points VCC_SENSE, VSS_SENSE
Other SKTOCC#, DBR#
otes:
1.
Notes:
1. Refer to Chapter 5 for signal descriptions.
2. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.
1,2
Table 2-4. Signals with ODT
• QPI_DRX_DP[19:0], QPI_DRX_DN[19:0], QPI_DTX_DP[19:0], QPI_DTX_DN[19:0], QPI_CLKRX_D[N/P], QPI_CLKTX_D[N/P]
• DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_DQS_[N/P][7:0], DDR{0/1/2}_ECC[7:0], DDR{0/1/ 2}_PAR_ERR#[0:2], VDDPWRGOOD
• BCLK_ITP_D[N/P]
•PECI
• BPM#[7:0], PREQ#, TRST#, VCCPWRGOOD, VTTPWRGOOD
Notes:
1. Unless otherwise specified, signals have ODT in the package with 50 Ω pulldown to V
2. PREQ#, BPM[7:0], TDI, TMS and BCLK_ITP_D[N/P] have ODT in package with 35 Ω pullup to V
3. VCCPWRGOOD, VDDPWRGOOD, and VTTPWRGOOD have ODT in package with a 10 kΩ to 20 kΩ pulldown to .
V
SS
4. TRST# has ODT in package with a 1 kΩ to 5 kΩ pullup to V
5. All DDR signals are terminated to VDDQ/2
6. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.
7. While TMS and TDI do not have On-Die Termination, these signals are weakly pulled up using a 1–5 kΩ
resistor to V
8. While TCK does not have On-Die Termination, this signal is weakly pulled down using a 1–5 kΩ resistor to .
V
SS
TT
.
TT
All Control Sideband Asynchronous signals are required to be asserted/deasserted for at least eight BCLKs for the processor to recognize the proper signal state. See
Section 2.11 for the DC specifications. See Chapter 6 for additional timing
requirements for entering and leaving the low power states.

2.8 Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the processor be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage. Two copies of each signal may be required with each driving a different voltage level.
.
SS
.
TT
Intel® Xeon® Processor 3500 Series Datasheet Volume 1 19
Electrical Specifications

2.9 Platform Environmental Control Interface (PECI) DC Specifications

PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature. Temperature sensors located throughout the die are implemented as analog-to-digital converters calibrated at the factory. PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control. More detailed information may be found in the Platform Environment Control Interface
(PECI) Specification.

2.9.1 DC Characteristics

The PECI interface operates at a nominal voltage set by V specifications shown in Table 2-5 is used with devices normally operating from a V interface supply. V
nominal levels will vary between processor families. All PECI
TTD
devices will operate at the V system. For specific nominal V
Table 2-5. PECI DC Electrical Limits
Symbol Definition and Conditions Min Max Units Notes
V
V
hysteresis
V
V
I
source
I
sink
I
leak+
I
leak-
C
V
noise
Notes:
1. V
2. The leakage specification applies to powered devices on the PECI bus.
Input Voltage Range -0.150 V
in
Hysteresis 0.1 * V
Negative-edge threshold voltage 0.275 * V
n
Positive-edge threshold voltage 0.550 * V
p
High level output source
= 0.75 * V
(V
OH
Low level output sink
= 0.25 * V
(V
OL
High impedance state leakage to V
= VOL)
(V
leak
High impedance leakage to GND
= VOH)
(V
leak
bus
Bus capacitance per node N/A 10 pF
Signal noise immunity above 300 MHz 0.1 * V
supplies the PECI interface. PECI behavior does not affect V
TTD
TTD
TTD
. The set of DC electrical
TTD
level determined by the processor installed in the
TTD
levels, refer to Table 2-7.
TTD
V
TTD
TTD
TTD
TTD
)
)
TTD
-6.0 N/A mA
0.5 1.0 mA
N/A 100 µA 2
N/A 100 µA 2
TTD
min/max specifications.
TTD
N/A V
0.500 * V
0.725 * V
N/A V
TTD
TTD
V
V
p-p
TTD
1
20 Intel® Xeon® Processor 3500 Series Datasheet Volume 1
Electrical Specifications

2.9.2 Input Device Hysteresis

The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 2-2 as a guide for input buffer design.
Figure 2-2. Input Device Hysteresis
V
TTD
Maximum V
Minimum V
P
P
PECI High Range
Minimum Hysteresis
Maximum V
Minimum V
N
N
PECI Low Range
PECI Ground

2.10 Absolute Maximum and Minimum Ratings

Table 2-6 specifies absolute maximum and minimum ratings, which lie outside the
functional limits of the processor. Only within specified operation limits can functionality and long-term reliability be expected.
At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits.
Valid Input Signal Range
At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function or its reliability will be severely degraded.
Although the processor contains protective circuitry to resist damage from Electro­Static Discharge (ESD), precautions should always be taken to avoid high static voltages or electric fields.
Intel® Xeon® Processor 3500 Series Datasheet Volume 1 21
.
Table 2-6. Processor Absolute Minimum and Maximum Ratings
Symbol Parameter Min Max Unit Notes
V
V
V
V
DDQ
V
CCPLL
T
CASE
T
STORAGE
Notes:
1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must
be satisfied.
2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
3. V
CC
TTA
TTD
TTA
Processor Core voltage with respect to V
Voltage for the analog portion of the integrated memory controller, Intel QPI link and Shared Cache with respect to V
Voltage for the digital portion of the integrated memory controller, Intel QPI link and Shared Cache with respect to V
Processor I/O supply voltage for DDR3 with respect to V
Processor PLL voltage with respect to V
Processor case temperature See
Storage temperature See
and V
TTD
SS
should be derived from the same VR.
SS
SS
SS
SS
-0.3 1.55 V
—1.35V3
—1.35V3
— 1.875 V
1.65 1.89 V
Chapter 6
Chapter 6
Electrical Specifications
See
Chapter 6
See
Chapter 6
°C
°C
1, 2

2.11 Processor DC Specifications

The processor DC specifications in this section are defined at the processor pads, unless noted otherwise. See Chapter 4 for the processor land listings and
Chapter 5 for signal definitions. Voltage and current specifications are detailed in Tab l e 2-7. For platform planning, refer to Table 2-8, which provides V
tolerances. This same information is presented graphically in Figure 2-3.
The DC specifications for the DDR3 signals are listed in Table 2-11. Control Sideband and Test Access Port (TAP) are listed in Table 2-12 through Table 2-15.
Table 2-7 through Table 2-15 list the DC specifications for the processor and are valid
only while meeting specifications for case temperature (T
“Thermal Specifications”), clock frequency, and input voltages. Care should be taken to
read all notes associated with each parameter.
static and transient
CC
as specified in Chapter 6,
CASE
22 Intel® Xeon® Processor 3500 Series Datasheet Volume 1
Electrical Specifications
N

2.11.1 DC Voltage and Current Specification

Table 2-7. Voltage and Current Specifications
Symbol Parameter Min Typ Max Unit Notes
VID VID range 0.8 — 1.375 V
Processor Number
W3580
V
CC
W3570
W3550
W3540 W3520
Voltage for the analog portion of the
V
TTA
integrated memory controller, Intel QPI link and Shared Cache
Voltage f or th e d ig ital portion of the
V
V
V
TTD
DDQ
CCPLL
integrated memory controller, Intel QPI link and Shared Cache
Processor I/O supply voltage for DDR3 1.425 1.5 1.575 V
PLL supply voltage (DC + AC specification)
Processor Number
W3580
I
CC
W3570
W3550
W3540 W3520
Current for the analog portion of the
I
TTA
integrated memory controller, Intel QPI link and Shared Cache
Current for the digital portion of the
I
TTD
I
DDQ
I
DDQ
I
CC_VCCPLL
integrated memory controller, Intel QPI link and Shared Cache
Processor I/O supply current for DDR3 — — 6 A
Processor I/O supply current for DDR3
S3
while in S3
PLL supply current (DC + AC specification) — — 1.1 A
otes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date
2. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Please note this differs from the VID employed by the processor during a power management event (Adaptive Thermal Monitor, Enhanced Intel SpeedStep
3. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
4. Refer to Tab le 2 - 8
The processor should not be subjected to any V a given current.
5. See Ta b l e 2 - 9 for details on VTT Voltage Identification and Tab le 2 - 9 and Figure 2-4 for details on the VTT Loadline.
6. I
7. This spec is based on a processor temperature, as reported by the DTS, of less than or equal to Tcontrol-25.
specification is based on the V
CC_MAX
V
for processor core
CC
3.33 GHz
3.20 GHz
See Ta b l e 2 - 8 and Figure 2-3 V
3.06 GHz
2.93 GHz
2.66 GHz
See Table 2-10 and Figure 2-4 V
See Ta b l e 2 - 9 and Figure 2-4 V5
1.71 1.8 1.89
for processor
I
CC
3.33 GHz
3.20 GHz
——
3.06 GHz
2.93 GHz
2.66 GHz
——5A
——23A
——1A
®
Technology, or Low Power States).
and Figure 2-3 for the minimum, typical, and maximum VCC allowed for a given current.
and ICC combination wherein VCC exceeds V
CC
loadline. Refer to Figure 2-3 for details.
CC_MAX
145
145 145
145
145
V
A
2
3,4
5
6
7
CC_MAX
1
for
Intel® Xeon® Processor 3500 Series Datasheet Volume 1 23
Table 2-8. VCC Static and Transient Tolerance
Electrical Specifications
ICC (A) V
(V) V
CC_Max
(V) V
CC_Typ
(V) Notes
CC_Min
0 VID - 0.000 VID - 0.019 VID - 0.038 1, 2, 3
5 VID - 0.004 VID - 0.023 VID - 0.042 1, 2, 3
10 VID - 0.008 VID - 0.027 VID - 0.046 1, 2, 3
15 VID - 0.012 VID - 0.031 VID - 0.050 1, 2, 3
20 VID - 0.016 VID - 0.035 VID - 0.054 1, 2, 3
25 VID - 0.020 VID - 0.039 VID - 0.058 1, 2, 3
30 VID - 0.024 VID - 0.043 VID - 0.062 1, 2, 3
35 VID - 0.028 VID - 0.047 VID - 0.066 1, 2, 3
40 VID - 0.032 VID - 0.051 VID - 0.070 1, 2, 3
45 VID - 0.036 VID - 0.055 VID - 0.074 1, 2, 3
50 VID - 0.040 VID - 0.059 VID - 0.078 1, 2, 3
55 VID - 0.044 VID - 0.063 VID - 0.082 1, 2, 3
60 VID - 0.048 VID - 0.067 VID - 0.086 1, 2, 3
65 VID - 0.052 VID - 0.071 VID - 0.090 1, 2, 3
70 VID - 0.056 VID - 0.075 VID - 0.094 1, 2, 3
75 VID - 0.060 VID - 0.079 VID - 0.098 1, 2, 3
78 VID - 0.062 VID - 0.081 VID - 0.100 1, 2, 3
85 VID - 0.068 VID - 0.087 VID - 0.106 1, 2, 3
90 VID - 0.072 VID - 0.091 VID - 0.110 1, 2, 3
95 VID - 0.076 VID - 0.095 VID - 0.114 1, 2, 3
100 VID - 0.080 VID - 0.099 VID - 0.118 1, 2, 3
105 VID - 0.084 VID - 0.103 VID - 0.122 1, 2, 3
110 VID - 0.088 VID - 0.107 VID - 0.126 1, 2, 3
115 VID - 0.092 VID - 0.111 VID - 0.130 1, 2, 3
120 VID - 0.096 VID - 0.115 VID - 0.134 1, 2, 3
125 VID - 0.100 VID - 0.119 VID - 0.138 1, 2, 3
130 VID - 0.104 VID - 0.123 VID - 0.142 1, 2, 3
135 VID - 0.108 VID - 0.127 VID - 0.146 1, 2, 3
140 VID - 0.112 VID - 0.131 VID - 0.150 1, 2, 3
Notes:
1. The V overshoot specifications.
2. This table is intended to aid in reading discrete points on Figure 2-3.
3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and VSS_SENSE lands.
CC_MIN
and V
loadlines represent static and transient limits. See Section 2.11.2 for VCC
CC_MAX
24 Intel® Xeon® Processor 3500 Series Datasheet Volume 1
Electrical Specifications
Figure 2-3. VCC Static and Transient Tolerance Load Lines
VID - 0.000
VID - 0.013
VID - 0.025
VID - 0.038
VID - 0.050
VID - 0.063
VID - 0.075
V
VID - 0.088
c c
VID - 0.100
V
VID - 0.113
VID - 0.125
VID - 0.138
VID - 0.150
VID - 0.163
VID - 0.175
0 102030405060708090100110120130140
Vcc Typical
Vcc Minimum
Table 2-9. VTT Voltage Identification (VID) Definition
VTT VR - VID Input V
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
01000010 1.220V
01000110 1.195V
01001010 1.170V
01001110 1.145V
01010010 1.120V
01010110 1.095V
01011010 1.070V
01011110 1.045V
Icc [A]
Vcc Maximum
TT_Typ
Notes:
1. This is a typical voltage, see Table 2-10 for VTT_Max and VTT_Min voltage.
Table 2-10. VTT Static and Transient Tolerance (Sheet 1 of 2)
ITT (A) V
(V) V
TT_Max
(V) V
TT_Typ
(V) Notes
TT_Min
0 VID + 0.0315 VID – 0.0000 VID – 0.0315
1 VID + 0.0255 VID – 0.0060 VID – 0.0375
2 VID + 0.0195 VID – 0.0120 VID – 0.0435
3 VID + 0.0135 VID – 0.0180 VID – 0.0495
4 VID + 0.0075 VID – 0.0240 VID – 0.0555
5 VID + 0.0015 VID – 0.0300 VID – 0.0615
Intel® Xeon® Processor 3500 Series Datasheet Volume 1 25
1
N
Table 2-10. VTT Static and Transient Tolerance (Sheet 2 of 2)
ITT (A) V
6 VID – 0.0045 VID – 0.0360 VID – 0.0675
7 VID – 0.0105 VID – 0.0420 VID – 0.0735
8 VID – 0.0165 VID – 0.0480 VID – 0.0795
9 VID – 0.0225 VID – 0.0540 VID – 0.0855
10 VID – 0.0285 VID – 0.0600 VID – 0.0915
11 VID – 0.0345 VID – 0.0660 VID – 0.0975
12 VID – 0.0405 VID – 0.0720 VID – 0.1035
13 VID – 0.0465 VID – 0.0780 VID – 0.1095
14 VID – 0.0525 VID – 0.0840 VID – 0.1155
15 VID – 0.0585 VID – 0.0900 VID – 0.1215
16 VID – 0.0645 VID – 0.0960 VID – 0.1275
17 VID – 0.0705 VID – 0.1020 VID – 0.1335
18 VID – 0.0765 VID – 0.1080 VID – 0.1395
19 VID – 0.0825 VID – 0.1140 VID – 0.1455
20 VID – 0.0885 VID – 0.1200 VID – 0.1515
21 VID – 0.0945 VID – 0.1260 VID – 0.1575
22 VID – 0.1005 VID – 0.1320 VID – 0.1635
23 VID – 0.1065 VID – 0.1380 VID – 0.1695
24 VID – 0.1125 VID – 0.1440 VID – 0.1755
25 VID – 0.1185 VID – 0.1500 VID – 0.1815
26 VID – 0.1245 VID – 0.1560 VID – 0.1875
27 VID – 0.1305 VID – 0.1620 VID – 0.1935
28 VID – 0.1365 VID – 0.1680 VID – 0.1995
otes:
1. The I
2. The loadlines specify voltage limits at the die measured at the VTT_SENSE and VSS_SENSE_VTT lands. Voltage
listed in this table is a sum of I
TT
regulation feedback for voltage regulator circuits must also be taken from processor VTT_SENSE and VSS_SENSE_VTT lands.
(V) V
TT_Max
TTA
and I
(V) V
TT_Typ
TTD
Electrical Specifications
(V) Notes
TT_Min
1
26 Intel® Xeon® Processor 3500 Series Datasheet Volume 1
Electrical Specifications
Figure 2-4. VTT Static and Transient Tolerance Load Line
Itt [A] (sum of Itta and Ittd)
0 5 10 15 20 25
0.0500
0.0375
0.0250
0.0125
0.0000
V
-0.0125
t
-0.0250
t
-0.0375
V
-0.0500
-0.0625
-0.0750
-0.0875
-0.1000
-0.1125
-0.1250
-0.1375
-0.1500
-0.1625
-0.1750
-0.1875
-0.2000
-0.2125
Vtt Typical
Vtt Minimum
Vtt Maximum
Table 2-11. DDR3 Signal Group DC Specifications
Symbol Parameter Min Typ Max Units Notes
V
Input Low Voltage — 0.43*V
IL
V
V
V
R
R
R
R
R
DDR_COMP0
DDR_COMP1
DDR_COMP2
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
3. V
Input High Voltage 0.57*V
IH
Output Low Voltage
OL
Output High Voltage
OH
DDR3 Clock Buffer On
ON
Resistance
DDR3 Command Buffer
ON
On Resistance
DDR3 Reset Buffer On
ON
Resistance
DDR3 Control Buffer On
ON
Resistance
DDR3 Data Buffer On
ON
Resistance
Input Leakage Current N/A N/A ± 1 mA
I
LI
DDQ
—
—
21 — 31 Ω
16 — 24 Ω
25 — 75 Ω
21 — 31 Ω
21 — 31 Ω
COMP Resistance 99 100 101 Ω 5
COMP Resistance 24.65 24.9 25.15 Ω 5
COMP Resistance 128.7 130 131.30 Ω 5
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
IL
value.
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
IH
value.
(V
DDQ
(R
ON+RVTT_TERM
V
– ((V
DDQ
/(RON+R
(R
ON
1
DDQ
V2,4
——V3
/ 2)* (R
ON
/ 2)*
DDQ
VTT_TERM
/
))
—V
—V 4
))
Intel® Xeon® Processor 3500 Series Datasheet Volume 1 27
4. V
and VOH may experience excursions above V
IH
signal quality specifications.
5. COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design guide for implementation details. DDR_COMP[2:0] resistors are to V
Table 2-12. RESET# Signal DC Specifications
Symbol Parameter Min Typ Max Units Notes
V
Input Low Voltage — — 0.40 * V
IL
V
Input High Voltage 0.80 * V
IH
I
Input Leakage Current — — ± 200 μA3
LI
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The V
3. For Vin between 0 V and V
4. V
referred to in these specifications refers to instantaneous V
TTA
and VOH may experience excursions above VTT.
IH
. Measured when the driver is tristated.
TTA
Table 2-13. TAP Signal Group DC Specifications
Symbol Parameter Min Typ Max Units Notes
V
Input Low Voltage — — 0.40
IL
V
Input High Voltage 0.75 * V
IH
V
Output Low Voltage
OL
V
Output High Voltage V
OH
Ron Buffer on Resistance 10 — 18 Ω
I
Input Leakage Current — — ± 200 μA3
LI
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The V
3. For Vin between 0 V and V
4. V
referred to in these specifications refers to instantaneous V
TTA
and VOH may experience excursions above VTT.
IH
. Measured when the driver is tristated.
TTA
——
TTA
Electrical Specifications
. However, input signal drivers must comply with the
DDQ
.
SS
V2
V2
V2
)
TTA
TTA
TTA
—— 2,4
.
TTA
* VTTA
—— 2,4
V
* RON /
TTA
(R
+ R
ON
sys_term
——V2,4
.
TTA
1
1
Table 2-14. PWRGOOD Signal Group DC Specifications
Symbol Parameter Min Typ Max Units Notes
Input Low Voltage for VCCPWRGOOD
V
IL
and VTTPWRGOOD Signals
Input Low Voltage for VDDPWRGOOD
V
IL
Signal
Input High Voltage for VCCPWRGOOD
V
IH
and VTTPWRGOOD Signals
Input High Voltage for VDDPWRGOOD
V
IH
Signal
— — 0.25 * V
TTA
V2,5
— — 0.29 V 6
0.75 * V
0.87
—— V2,5
TTA
——
V5
Ron Buffer on Resistance 10 — 18 Ω
I
Input Leakage Current — — ± 200 μA4
LI
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The V
3. For Vin between 0 V and V
4. V
5. This spec applies to VCCPWRGOOD and VTTPWRGOOD
6. This specification applies to VDDPWRGOOD
referred to in these specifications refers to instantaneous V
TTA
and VOH may experience excursions above VTT.
IH
. Measured when the driver is tristated.
TTA
TTA
.
28 Intel® Xeon® Processor 3500 Series Datasheet Volume 1
1
Electrical Specifications
Table 2-15. Control Sideband Signal Group DC Specifications
Symbol Parameter Min Typ Max Units Notes
V
Input Low Voltage — — 0.64
IL
V
Input High Voltage 0.76
IH
Output Low Voltage
V
OL
V
Output High Voltage V
OH
* VTTA
——
TTA
Ron Buffer on Resistance 10 — 18 Ω
Buffer on Resistance for
Ron
VID[7:0]
I
Input Leakage Current — — ± 200 μA3
LI
— 100 —
COMP0 COMP Resistance 49.4 49.9 50.40 Ω 5
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The V
3. For Vin between 0 V and V
4. V
5. COMP resistance must be provided on the system board with 1% resistors. See the applicable platform
referred to in these specifications refers to instantaneous V
TTA
and VOH may experience excursions above VTT.
IH
. Measured when the driver is tristated.
TTA
design guide for implementation details. COMP0 resistors are to V
——V2
——V2,4
V
* RON / (RON
TTA
+ R
TTA
.
SS
* VTTA
sys_term
.
1
V2
)
V2,4
Ω

2.11.2 VCC Overshoot Specification

The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high-to-low current load condition. This overshoot cannot exceed VID + V
OS_MAX
VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.
Table 2-16. VCC Overshoot Specifications
Symbol Parameter Min Max Units Figure Notes
V
OS_MAX
T
OS_MAX
Magnitude of V
CCP
Time duration of V
(V
OS_MAX
overshoot above VID — 50 mV 2-5
overshoot above VID — 25 µs 2-5
CCP
is the maximum allowable overshoot above
Intel® Xeon® Processor 3500 Series Datasheet Volume 1 29
Figure 2-5. VCC Overshoot Example Waveform
Example Overshoot Waveform
Electrical Specifications
VID + V
OS
VID
Voltage (V)
TOS: Overshoot time above VID V
: Overshoot above VID
OS

2.11.3 Die Voltage Validation

Core voltage (VCC) overshoot events at the processor must meet the specifications in
Table 2-16 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot
events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope.
V
OS
T
OS
Time
§
30 Intel® Xeon® Processor 3500 Series Datasheet Volume 1
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