The PR440FX motherboard may contain design defects or errors known as errata. Characterized errata that
may cause the PR440FX motherboard’s behavior to deviate from published specifications are documented in
the PR440FX Motherboard Specification Update.
Revision History
Revision
001
002
Revision HistoryDate
First release of the PR440FX Specification.08/96
Second release of the PR440FX Specification11/96
This product specification applies only to standard PR440FX with BIOS identifier 1.00.0x.DI0.
Changes to this specification will be published in the PR440FX Motherboard Specification Update
(Order Number: 281832) before being incorporated into a revision of this document.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
The PR440FX motherboard may contain design defects or errors known as errata. Current characterized errata are available
on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
†
Third-party brands and names are the property of their respective owners.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call in North America 1-800-879-4683, Europe 44-0-1793-431-155, France 44-0-1793-421-777,
Germany 44-0-1793-421-333, other Countries 708-296-9333.
The PR440FX motherboard is designed to fit into an ATX form factor chassis. Figure 2 illustrates
the mechanical form factor of the motherboard.
Figure 2. Motherboard Dimensions
1.3 Microprocessor
The PR440FX motherboard supports 2.1 V to 3.5 V Intel Pentium Pro processors operating at
180 MHz and 200 MHz. For motherboards with two processors installed, a voltage regulator
module (VRM) is required for the second processor.
The Pentium Pro processor integrates an internal nonblocking second-level (L2) cache and cache
controller. The motherboard supports processors with 256 KB or 512 KB L2 cache.
The Pentium Pro processor maintains full backward compatibility with the 8086, 80286,
™
Intel386
, Intel486™ and Pentium processors. It also has a numeric coprocessor that significantly
increases the speed of floating point operations and complies with ANSI/IEEE standard 754-1985.
The dual processor support for the PR440FX motherboard consists of the following:
• Two Socket 8 ZIF processor sockets
• Voltage regulator module (VRM) socket for a VRM, which provides power to the secondary
processor
• BIOS support for either MPS v1.1 or MPS v.1.4 operating systems
1.3.2 Microprocessor Upgrades
Two microprocessor upgrades are available:
• Single to dual processors
• Upgrade from 180 MHz Pentium Pro processor to 200 MHz Pentium Pro processor
CAUTION
The second processor must be the same speed and second-level cache size as the primary
processor. The second processor must also be the same stepping as, or no more than one stepping
higher than, the primary processor.
1.3.3 VRM Electrical Characteristics
Motherboards with two processors require a VRM. There are two types of VRMs: 5 V and 12 V.
The PR440FX motherboard supports 5 V modules. Table 1 shows the electrical characteristics of
the VRM.
Table 1.VRM Electrical Characteristics
ParameterValue
Input Voltage5 V ± 5%
Output Current12.4A
Efficiency>40% at low current, >80% at full current
Slew rate30 A/µS at its pins
Maximum secondary input voltage
source current
DC Output Current
ParameterValue
I
min
I
max
I
(Overshoot lasting 15 µS)13 Amps
peak
250 mA
0.3 Amps
12.4 Amps
10
Motherboard Description
Pentium Pro processor-based systems require voltage levels between the minimum and maximum
levels shown in Table 2. The voltage level required by the system depends on the speed of the
Pentium Pro processor. The Icc column represents Intel’s current requirement for a Pentium Pro
processor operating in this voltage range.
Table 2.VRM Voltage Ranges
Voltage MinimumVoltage MaximumIcc
2.4 Volts3.4 Volts12.4 Amps
1.3.4 Microprocessor Fan/Heat Sink Assembly and Clips
CAUTION
Do not use the older style of bail-wire clips for securing the fan/heat sink assembly. These clips
could damage the motherboard if installed or removed incorrectly.
In an ATX v. 1.1 compliant chassis, the chassis’s power supply provides the fan for the primary
processor; the primary processor must also have a heat sink for proper thermal dissipation. The
secondary processor must have an active fan/heat sink assembly for proper thermal dissipation.
The heat sink assembly must be securely fastened to the Socket 8 ZIF socket by clips.
1.3.4.1 Secondary Processor Fan
In dual processor systems where both processors have a fan/heat sink assembly, both tach fans
must comply with the specifications in Table 3.
Table 3.Tach Fan Specifications
ParameterValue
Operating voltage range10.2 - 13.8 VDC
Current (worst case)80 mA
Air Volume (worst case) at zero pressure9.9 CFM
Static Pressure (worst case) at zero air flow0.051 inch H2O
Noise (worst case)25 dB @ 1 m
Initial RPM (nominal)2800 ± 600
Size60 x 60 x 10 mm,
screw centers50 x 50 mm
Tachometer output2 cycles per revolution
The motherboard has four DIMM sockets. Minimum memory size is 16 MB and maximum
memory size is 512 MB. The motherboard supports the following memory types, speeds, and
module sizes:
• 168-pin 3.3 V DIMMs with gold-plated contacts
• 50 ns and 60 ns buffered asynchronous EDO memory
• Parity and ECC memory
• 2 MB x 72 (16 MB), 4 MB x 72 (32 MB), 8 MB x 72 (64 MB) and 16 MB x 72 (128 MB)
modules
NOTE
✏
Parity memory operates in ECC mode unless you disable memory error detection in the BIOS
Setup program (see section 3.14.8.4).
1.5 Chipset
The Intel 82440FX PCIset consists of the 82441FX PCI Bridge and Memory Controller (PMC)
and the 82442FX Data Bus Accelerator (DBX). The Intel 82371SB PCI ISA/IDE Xcelerator
(PIIX3) bridge provides the connection between the ISA and PCI buses.
1.5.1 82441FX PCI Bridge and Memory Controller (PMC) and 82442FX
Data Bus Accelerator (DBX)
Two devices from the Intel 82440FX chipset, the PMC and DBX, form the core of the
motherboard design. As the host bridge function between the Pentium Pro processors and PCI I/O
system, these devices maintain proper ordering of operations by trapping synchronization events
and flushing buffers. The PMC also acts as memory controller for the system with the DBX
providing the data path to memory
1.5.1.1 82441FX PCI Bridge and Memory Controller (PMC)
The 82441FX comes in a 208-pin QFP package that features:
• Processor interface control
Up to 66 MHz external bus speed
32-bit addressing
• Integrated DRAM controller
72-bit non-interleaved path to memory with ECC support
ECC is implemented as single-bit error checking and correction and multi-bit error
checking and detection
12
Motherboard Description
Support for EDO DRAM
16 MB to 512 MB main memory
• Fully synchronous PCI bus interface
PCI Rev. 2.1 V compliant
Up to 33 MHz bus speed
PCI to DRAM > 100 MBps
• Data Buffering
Processor-to-DRAM and PCI-to-DRAM write data buffering
1.5.1.2 82442FX Data Bus Accelerator (DBX)
The DBX connects to the 64-bit Pentium Pro processor data bus, the 72-bit memory data bus and
the 16-bit PMC private data bus. The DBX works in parallel with the PMC to provide a high
performance memory subsystem for Pentium Pro processor-based systems. The DBX comes in a
208-pin QFP package.
1.5.2 82371SB PCI/ISA IDE Xcelerator (PIIX3)
The PIIX3 provides the interface between the PCI and ISA buses and integrates a dual channel
enhanced IDE interface capable of supporting up to four devices. The PIIX3 comes in a 208-pin
QFP package that features:
†
• PCI-to-AT
• ISA refresh address generation
• Interface between the PCI and ISA buses
• Universal Serial Bus controller
Host/hub controller
• Integrated enhanced IDE interface
Support for up to four devices
Programmed Input/Output (PIO) Mode 4 transfers up to 16 MB/sec
Integrated 8 x 32-bit buffer for bus master PCI IDE burst transfers
Bus master mode
• PCI 2.1 compliance
• Enhanced DMA controller
• Interrupt controller and interrupt steering
• Counters/timers
• SMI (System Management Interrupt) interrupt logic and timer with fast on/off mode
• NMI logic
interrupt mapping circuitry
1.5.3 Universal Serial Bus (USB) Support
NOTE
✏
Computer systems that have an unshielded cable attached to the USB port may not meet FCC
Class B requirements even if no device or a low-speed (sub-channel) USB device is attached to the
cable. Use a shielded cable that meets the requirements for high-speed (fully rated) devices.
The motherboard has two USB ports. This permits direct connection of two USB peripherals
without an external hub. If more devices are required, an external hub can be connected to either
port. The motherboard supports the standard Universal Host Controller Interface (UHCI).
Features of the USB include:
• Hot Pluggable
• Self-identifying peripherals
• Automatic mapping of function to driver and configuration
• Support for isochronous and asynchronous transfer types over the same set of wires
• Support for up to 127 physical devices
• Guaranteed bandwidth and low latencies appropriate for telephony, audio, and other
applications
• Error handling and fault recovery mechanisms built into the protocol
1.5.4 IDE Support
The motherboard has two independent high-performance bus-mastering PCI/IDE interfaces capable
of supporting PIO Mode 3, PIO Mode 4, and ATAPI devices. The system BIOS supports Logical
Block Addressing (LBA) and Extended Cylinder Head Sector (ECHS) translation modes. The IDE
device transfer rate and translation mode capability is automatically determined by the system BIOS.
Normally, programmed I/O operations require a substantial amount of processor bandwidth. In
†
true multi-tasking operating systems like Windows NT
, the processor bandwidth freed by using
bus mastering IDE can be used to complete other tasks while disk transfers are occurring. When
used in conjunction with the appropriate driver for the operating system, the IDE interface can
operate as a PCI bus master capable of supporting PIO Mode 4 devices with transfer rates of up to
16 MB/sec.
Detailed information on the PCIset is available in the Intel 82440FX PCIset data sheet.
1.6 I/O Controller
Control for the integrated into a single component, the National Semiconductor PC87308. The
PC87308 is a Plug and Play device that features:
• Two NS16C550-compatible UARTs with send/receive 16-byte FIFO
• Multi-mode bidirectional parallel port
†
Standard mode; IBM
Enhanced Parallel Port (EPP) with BIOS/Driver support
High Speed mode; Extended Capabilities Port (ECP) compatible
• Industry standard floppy controller with 16-byte FIFO (2.88 MB floppy support)
• Integrated real-time clock with century calendar functionality
• Integrated 8042-compatible keyboard controller
and Centronics† compatible
The PC87308 is normally configured automatically by the BIOS, but configuration of these
interfaces is also possible using Setup. The serial ports can support any address configuration.
14
Motherboard Description
1.6.1 Floppy Controller
The PC87308 is software compatible with the DP8473 and 82077 floppy disk controllers. The
floppy interface can be configured in Setup for:
• 5¼ inch media
360 KB
1.2 MB
• 3½ inch media
720 KB
1.2 MB (read/write only, no format capability)
1.44 MB
2.88 MB
By default, the Floppy A interface is configured for 1.44 MB and Floppy B is disabled.
Configuring the floppy interface for 1.2 MB, 3½ inch (3-mode floppy) requires a driver.
1.6.2 Keyboard and Mouse Interface
PS/2 keyboard/mouse connectors are located on the back panel side of the motherboard. The 5 V
lines to these connectors are protected with a PolySwitch
healing fuse, re-establishing the connection after an over-current condition is removed. While this
device eliminates the possibility of having to replace a fuse, take care to turn off the system power
before installing or removing a keyboard or mouse.
The I/O controller contains the AMI Megakey keyboard/mouse controller code which, besides
providing traditional keyboard and mouse control functions, supports Power-On/Reset (POR) and
password protection. You can define the POR password with Setup. The keyboard controller also
provides for the following hot-key sequences:
• <Ctrl> <Alt> <Del>: System software reset. This sequence performs a software reset of the
system by jumping to the beginning of the BIOS code and running the POST operation.
• <Ctrl> <Alt> <defined in Setup>: Power management key sequences take advantage of the
processor’s System Management Mode (SMM) features to greatly reduce the system’s power
consumption while maintaining the responsiveness necessary to service external interrupts.
• <Ctrl> <Alt> <defined in Setup>: Keyboard secure hot keys lock the keyboard until you enter
the password.
†
circuit which acts much like a self-
1.6.3 Real Time Clock, CMOS RAM and Battery
The integrated real-time clock (RTC) is compatible with DS1287 and MC146818 components. It
provides a time of day clock, a 100-year calendar with alarm features, and a century register. You
can set RTC in Setup. The RTC also supports 256-byte battery-backed CMOS RAM in two banks
which is reserved for BIOS use. You can set the CMOS RAM to specific values or clear the
CMOS RAM to system default values using Setup. You can also clear the CMOS RAM values to
system defaults by using a configuration jumper on the motherboard.
An external coin-cell style battery provides power to the RTC and CMOS memory. The battery
has an estimated lifetime of seven years and is socketed for easy replacement. When the system is
on, the life of the battery is extended by a trickle current from the power supply.
A 25-pin D-Sub header is provided on the back panel for a multi-mode bidirectional parallel port.
The parallel port operates in standard mode, EPP version 1.7 mode (BIOS and driver support) or a
high speed ECP compatible mode. EPP Mode requires a driver provided by the peripheral
manufacturer to operate correctly.
1.7 Onboard Networking
1.7.1 EtherExpress™ PRO/100B PCI LAN Subsystem
The EtherExpress PRO/100B PCI LAN optional subsystem is a high performance Ethernet† LAN
interface that provides both 10Base-T and 100Base-TX connectivity. Features include:
• 32-bit direct bus mastering on the PCI bus
• Shared memory structure in the host memory that copies data directly to/from host memory
• 10Base-T and 100Base-TX capability using a single RJ-45 connector
• IEEE 802.3µ Auto-Negotiation for hardware selection of the highest operating speed
• Jumperless configuration; the LAN subsystem is totally software configurable
The following block diagram provides an overview of the LAN subsystem architecture.
10Mbps Xmit/Rcv
RJ-45
Connector
Common
Magnetic
Module
100Mbps Xmit/Rcv
DP8322 3
"Twister"
PCI Local Bus
DP83840
100BASE-TX
PHY
MII
Intel
82557
Figure 3. Functional Block Diagram of LAN Subsystem
1.7.2 Intel 82557 LAN Controller
This device is the heart of the LAN subsystem and provides the following functions:
• CSMA/CD Protocol Engine
• PCI bus interface
• DMA engine for movement of commands, status, and network data across the PCI bus
• Access to EEPROM
• Standard MII interface for access to IEEE 802.3µ-compliant physical layer devices
EEPRO M
OM04782
16
Motherboard Description
1.7.3 10/100 MBps Physical Layer Interface
The physical layer interface is implemented in two devices from National Semiconductor, the
DP83840 and the DP83223. The DP83840 provides:
• Complete functionality necessary for the 10Base-T interface; directly drives the cable when in
10 MBps mode
• All functionality required for the 100Base-TX interface except for the NRZ to MLT3
encoding/decoding function, which is provided by the DP83223 Twister device
• Complete set of MII management registers for control and status reporting
• 802.3µ Auto-Negotiation for automatically establishing the best possible operating mode when
connected to other 10Base-T or 100Base-TX devices, whether capable of half or full-duplex
operation
1.7.4 EtherExpress PRO/100B PCI LAN Subsystem Software
Description
The software provided with the LAN subsystem includes setup/diagnostic software (SETUP.EXE),
a readme file viewer (README.EXE) and the following drivers:
Table 4.EtherExpress PRP/100B PCI Drivers
DriverDescriptionEnvironment(s)
E100BODI.COMNovell ODINetWare† DOS Client
E100BODI.SYSNovell ODINetWare OS/2† Client
E100B.LANNovell ODINetWare 3.11 Server
NetWare 3.12 Server
NetWare 4.x Server
NetWare NT Requester
NetWare for OS/2
†
E100B.DOSNDIS 2.0.1Windows
MS-DOS
E100B.OS2NDIS 2.0.1MS OS/2 1.3
IBM OS/2 2.11
IBM OS/2 Warp
E100B.SYSNDIS 3.1Windows 95
Windows NT 3.5x
for Workgroups 3.11
†
LANMAN 2.1
1.8 SCSI Subsystem
The onboard SCSI subsystem features the Adaptec AIC-7880, which contains a double-speed SCSI
controller and a PCI bus master interface in a 160-pin PQFP. The AIC-7880 supports the
following:
• 8- or 16-bit fast SCSI providing 10 MB per second or 20 MB per second throughput, or
• Double-speed SCSI that can burst data at 20 MB per second or 40 MB per second
As a PCI bus master, the AIC-7880 supports burst data transfers on the PCI bus up to the
maximum rate of 133 MB per second using the on-chip 256-byte FIFO.
The AIC 7880 also offers active negation outputs and a disk activity output signal. Active
negation outputs reduce the chance of data errors by actively driving both polarities of the SCSI
bus, avoiding indeterminate voltage levels and common-mode noise on long cable runs. The SCSI
output drivers can directly drive a 48 mA single-ended SCSI bus with no additional drivers.
Synchronous SCSI can handle up to 15 REQ control signals simultaneously.
1.8.2 SCSI Bus
The SCSI data bus is 8- or 16-bits wide with odd ECC generated per byte. SCSI control signals
are the same for either bus width. The motherboard has an onboard SCSI connector that supports
8- or 16-bit devices. On a 16-bit wide SCSI bus, the AIC-7880 assigns the highest arbitration
priority to the low byte of the 16-bit word. This way, 16-bit targets can be mixed with 8-bit targets
if the 8-bit devices are placed on the low data byte. During chip powerdown, all inputs are
disabled to reduce power consumption.
1.8.2.1 SCSI Bus Topology
The following diagram shows how the SCSI bus is implemented.
Last
Internal
Device
Internal
SCSI
Devices
Internal
SCSI
Cable
OM05664a
External
SCSI
Cable
External
SCSI
Device
Chassis
Terminator
Card
Motherboard
Figure 4. SCSI Bus Topology
From end to end, the SCSI bus cable is routed from the last internal SCSI device to each internal
device. From the last internal device, the cable connects to the motherboard, where the SCSI
controller resides. The cable can then continue to an optional terminator card installed in an
unused I/O slot of the chassis. From the terminator card, an optional external SCSI cable can be
used to connect external SCSI devices.
18
Motherboard Description
1.8.3 SCSI Cable
For proper operation of ultra/wide SCSI devices, the overall length of the SCSI cable from the last
internal device to the last external device should not exceed three meters (within constraints as
defined by ANSI SCSI-3 Specification). The recommended length for the internal SCSI cable
(from the last internal device to the terminator card) is 42 inches. For more information, see the
ANSI SCSI-3 Specification.
1.8.4 SCSI Bus Termination
Terminate the extreme ends of the SCSI bus (cable), typically by connecting a terminated device to
the end connectors of the cable:
• On the last connector of the internal cable (farthest from the motherboard), attach either a
terminated 16-bit device or some other type of 16-bit termination (see Note).
• If the internal cable ends at the motherboard, enable motherboard termination in the SCSI
BIOS (on bootup press <Ctrl><A> to enter the SCSISelect
• If the internal cable continues from the motherboard to a termination card, disable motherboard
termination in the SCSI BIOS (using SCSISelect). The terminator card provides the end
termination, unless you attach an external cable.
• If an external SCSI cable is attached to the terminator card, its termination is disabled
automatically. On the last connector of the external cable, attach either a terminated 16-bit
device or some other type of 16-bit termination (see Note).
†
utility).
Disable termination on all other SCSI devices attached to the cable (except the devices attached to
the extreme ends).
NOTE
✏
A 68-pin connector on the motherboard supports 8-bit and wide 16-bit SCSI devices. Eight-bit
devices require a 68- to 50-pin adapter. In general, if you use an 8-bit device to terminate the
SCSI bus, you must attach it using a 68-to-50-pin SCSI adapter with high-byte termination, so that
all 16 data bits are terminated.
1.8.4.1 Using Only 16-bit SCSI Devices
• Enable termination only on the device(s) attached to the last connector (internal and/or
external).
• Remove or disable termination on all devices that are not on the last connector of the cable(s).
1.8.4.2 Mixing 8-and 16-bit SCSI Devices
• When mixing 8- and 16-bit devices, each 8-bit device must have a 68-to-50 pin adapter.
• Enable termination only on the device(s) attached to the last connector (internal and/or
external). If you use an 8-bit device to provide termination, attach it using a 68-to-50-pin SCSI
adapter with high-byte termination, so that all 16 data bits are terminated.
• Remove or disable termination on all devices that are not on the last connector of the cable(s).
• Enable termination only on the device(s) attached to the last connector (internal and/or
external). Attach the 8-bit device to provide termination using a 68-to-50-pin SCSI adapter
with high-byte termination, so that all 16 data bits are terminated.
• Remove or disable termination on all devices that are not the last device on the cable(s).
NOTE
✏
Examine the gender and polarities of connectors, adapters, and terminators to assure proper
termination and connection to the low or high byte of the bus.
1.8.5 SCSI
See Section 4.0.
Select
and SCSI Disk Utilities
1.9 Audio Subsystem
The motherboard features a 16-bit stereo audio subsystem. The audio subsystem is based upon the
Sound Blaster
audio and analog mixing functions required for playing and recording audio on personal computers
including:
• Stereo analog-to-digital and digital-to-analog converters
• Analog mixing, anti-aliasing and reconstruction filters
• Line and microphone level inputs
• Digital audio compression using selectable A-law or µlaw rules
• Full digital control of all mixer and volume control functions
With the integrated Sound Blaster OPL3 compatible FM synthesizer, the CS4236 also provides
support for four major sound standards including Adlib and Sound Blaster Pro 2.0, Windows
Sound System and MPU-401 to meet all of the requirements of today’s multimedia applications.
The CS4236 also supports full-duplex operation to support future applications such as video
conferencing.
The CS4236 includes a Plug and Play ISA interface and comprises six logical devices including:
• Synthesizer
• MIDI/Game Port
• Sound Blaster
• Microsoft
• MPU-401
• CS4236 device
†
compatible Crystal CS4236 multimedia codec. The CS4236 provides the digital
†
Sound System
Each logical device is configured into the host environment using ISA Plug and Play configuration.
The audio subsystem requires two interrupts and up to two DMA channels. The system can be
configured to use either DMA channels 0, 1, or 3. The interrupt can be mapped to interrupt 5, 7, 9,
10, 11, or 15.
20
Motherboard Description
Address (hex)
80h
85h
86h
1.10 Management Extension Hardware
The Management Extension hardware provides low-cost instrumentation capabilities. The
hardware implementation is a single-chip ASIC. Features include the following:
• An integrated temperature sensor for internal chassis temperature
• Three fan-speed sensors
• Power supply voltage monitoring to detect levels above or below acceptable values
• Registers for storing power on self test (POST) hardware test results and error codes
• Optical sensor for detection of physical intrusion (such as when the chassis lid has been
removed) even when the power is off (this feature is chassis dependent)
• Remote reset capabilities from a remote peer or server through LANDesk Client Manager,
Version 3.0 and service layers (when available)
• Hardware compatibility with Windows NT, Windows 95, and Windows† 3.1
When an out-of-range condition (temperature, fan speed, or voltage) is reached, a System
Management Interrupt (SMI) is activated. The Management Extension circuitry connects to the
ISA bus as an 8-bit I/O mapped device and uses these I/O addresses:
Description
Monitors and stores POST codes
Address and control functions
Register read/write operations
Figure 5 shows the connectors on the motherboard. Following figure 5 are the pins and signal
names for each connector. For front panel connectors, see section 1.12. For back panel
connectors, see section 1.13.
1Wave Right
2Ground
3Wave Left
4Ground
5Key
6Ground
7N/C
8MIDI-Out
1.11.3 Telephony Connector - J1F1
PinSignal Name
1Ground
2Mono Out
3Mic In
4Key
1.11.4 Power Connector - J8L1
When used with a power supply that supports Remote On/Off, the motherboard can turn off the
system power under software control. The BIOS turns the computer power off when it receives the
proper APM command from the operating system. For example, Windows 95 issues an APM
command when the user selects the Shutdown the Computer option. APM must be enabled in the
BIOS and the operating system in order for Soft Off to work correctly. APM determines the status
of the power supply system responses. For example, if the power is disconnected and computer is
switched on, the computer’s response is to either turn back on when power is reapplied or remain
off. The response is predetermined by the configuration in Setup. Also see 1.12.1.4 Remote
On/Off and Soft Power Support.
1Reset IDE2Ground
3Host Data 74Host Data 8
5Host Data 66Host Data 9
7Host Data 58Host Data 10
9Host Data 410Host Data 11
11Host Data 312Host Data 12
13Host Data 214Host Data 13
15Host Data 116Host Data 14
17Host Data 018Host Data 15
19Ground20Key
21DDRQ0 [DDRQ1]22Ground
23I/O Write#24Ground
25I/O Read#26Ground
27IOCHRDY28Vcc pull-up
29DDACK0# [DDACK1#]30Ground
31IRQ14 (IRQ15)32Reserved
continued
☛
25
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