Intel PILLAR ROCK Schematic

5

4

3

2

1

PILLAR ROCK

Table of Contents

Page Description

1

D D

C C

B B

TITLE PAGE

2

NOTES

3

Penryn (1 of 2)

4

Penryn (2 of 2)

5

CPU Thermal Sensor

6

CANTIGA (1 OF 6)

7

CANTIGA (2 OF 6)

8

CANTIGA (3 OF 6)

9

CANTIGA (4 OF 6)

10

CANTIGA (5 OF 6)

11

CANTIGA (6 OF 6)

12

CANTIGA STRAP & CAMARILLO

13

DDR2 SODIMM 0

14

DDR2 SODIMM 1

15

DDR2 TERMINATION

16

CRT

17

LVDS

18

TVO

19

PCIE GRAPHICS

20

XDP

21

ICH9M (1 of 4)

22

ICH9M (2 of 4)

23

ICH9M (3 of 4)

24

ICH9M (4 of 4)

25

PCI-E Slots (1 & 2)

26

PCI-E Slots (3,4 & 5)

27

High Definition Audio

28

HDA Power Supply

29

USB 1.1/2.0

30

SATA (1 of 3)

31

SATA (2 and 3 of 3)

32

PCI Edge Connector(Gold finger)

33

LAN Boaz

34

LAN Docking and SPI

35

CK505

36

DB800 & Buffers

37

FWH and I/O Port Expander

38

SIO

39

Legacy Support

40

H8 2116 KBC(1 of 2)

41

H8 2116 KBC(2 of 2)

42

PS2

43

LPC Slot, TPM Header,

44

DOCKING

45

TPS51120 SYSTEM POWER VR

46

DDR2 VR

47

CANTIGA VR

48

DDR VREF

49

GRAPHICS CORE VR

50

SYSTEM CHARGER VR

51

SYSTEM CHARGER BATTERY

52

IMVP-6 CONTROLLER

53

IMVP-6 DRIVERS&FETS

54

CPU Decoupling

55

DISCHARGE CIRCUITS

56

Start Up Sequence

57

Sleep control

58

POWER SEQUENCING

Montevina Mobile Platform CUSTOMER REFERENCE BOARD

Merom

Fab 3

Rev. 1.0

A A

5

4

3

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

A

TITLE PAGE

355659

2

1 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

5

4

3

2

1

MONTEVINA CUSTOMER REFERENCE PLATFORM

SCHEMATIC ANNOTATIONS AND BOARD INFORMATION

D D

2

Voltage Rails

+VBATA +VBAT +VBATS +V12S

-V12A

-V12S +V5A +V5 +V5S +V3.3A +V3.3M +V3.3M_CK505 +V3.3 +V3.3S +V1.8 +V1.5S +V1.05M +V1.05S +V0.9 +VCC_CORE +VCC_GFXCORE

VOLTAGE DESCRIPTIONACTIVE INPOWER PLANE

6V-14.1V 6V-14.1V 6V-14.1V 12V

-12V

-12V 5V 5V 5V

3.3V

1.8V

1.5V

1.05V

0.9V

0.35V-1.5V

0.7V-1.25V

S0/M0, (S3-S5)/M1, (S3-S5)/M-off S0/M0, (S3-S5)/M1, (S3-S5)/M-off S0/M0 S0/M0 S0/M0, (S3-S5)/M1, (S3-S5)/M-off S0/M0 S0/M0, (S3-S5)/M1, (S3-S5)/M-off S0/M0, S3/M1, S3/M-off S0/M0 S0/M0, (S3-S5)/M1, (S3-S5)/M-off S0/M0, (S3-S5)/M1, S3/(M-off w/WOL_EN) S0/M0, (S3-S5)/M1 S0/M0, S3/M1, S3/M-off S0/M0 S0/M0, (S3-S5)/M1, S3/M-off S0/M0 S0/M0, (S3-S5)/M1 S0/M0 S0/M0, (S3-S5)/M1, S3/M-off S0/M0 S0/M0

Battery Rail in Mobile Power Mode Battery Rail in Mobile Power Mode Battery Rail in Mobile Power Mode Only on in DT Power Mode Only on in DT Power Mode Only on in DT Power Mode

LAN Clock, MCH

DDR core

GMCH, ICH core, and FSB rail DDR command & control pull up. CPU core rail GMCH Graphics core rail

I C / SMB Addresses

Clock Generator DB800 Clock Buffer SO-DIMM0 SO-DIMM1 SO-DIMM0 Thermal Sensor SO-DIMM1 Thermal Sensor DDR Thermal Sensor I2C Bus Expander Ambient Lighr Sensor EMA Display CPU Thermal Sensor IMVP6 Amb. Temp. Sensor Battery A Battery B Board ID Port Expander Docking Port Expander Skin Temperature Sensor H8 PCI-Slot3 PCI-Gold Finger PCI-Express Slot1-5 Docking PCIe x16 Slot (PEG) TPM Header ITP-XDP

AddressDevice 1101 001x 1101 110x 1010 000x 1010 010x 0011 000x 0011 010x 0100 110x 0011 xxxx 0111 001x 0011 110x 1001 100x 1001 101x 0001 110x 0001 111x 0011 000x 0011 001x 1001 100x TBD TBD TBD TBD TBD TBD TBD TBD

BusHex PageJumper DescriptionDefault

D2

SMB_ICH_M3

DC

SMB_ICH_M3

A0

SMB_ICH_M2

A4

SMB_ICH_M2

30

SMB_ICH_M2

34

SMB_ICH_M2

4C

SMB_ICH_M2

3x

SMB_ICH

72

ALS

3C

EMA

98

SMB_THRM

9A

SMB_THRM

1C

SMB_BS

1E

SMB_BS

30

SMB_BS

32

SMB_BS

98

SMB_BS

TBD

SMB_ME

TBD

SMB_ICH_A1

TBD

SMB_ICH_A1

TBD

SMB_ICH_A1

TBD

SMB_ICH_A1

TBD

SMB_ICH_S4

TBD

SMB_ICH_S4

TBD

SMB_ICH_S4

C C

Buses labeled SMB_ICH_xx come out of ICH, via an I2C expander. The rest come out of EC.

Jumper / Switch Settings

J1G1 J1G3 J1G5 J2B2 J2G1 J2H2 J3C1 J3J2 J4H1 J4J2 J5G1 J5H2 J7A1 J7E1 J7H1 J7H2 J8B1 J8B2 J8C1 J8F2 J8G1 J8G3 J8G4 J8G5 J8G6 J8H1 J9C1 J9D1 J9F1 J9G2 J9H1 J9H2 J9H3 J9H4

BSEL2

1-2

BSEL1

1-2

BSEL0

1-2

CPU CORE VID

All OPEN

Force Shutdown

1-X

GFX CORE VID

All OPEN

CPU thermal sensor

1-2, 3-4

Power ON Latch

1-X

No ME G3 to M1 support

1-X

SATA Power Enable

1-2

SRTC RST

1-X

CMOS Clear

1-X

In-circuit SMC Programming

1-2

SIO Reset

1-2

SATA interlock switch for port0

1-2

TPM PHYSICAL PRESENCE

1-X

PM Lan enable

1-2

In-circuit SMC Programming

1-2

SELCETING SPI0 or SPI1 TO BE PROGRAMMED

1-X

BIOS recovery

1-X

SV Setup

1-X

SMC MD2

1-X

CRB/SV Detect

1-X

SMC MD1

1-2

KBC disable

1-X

Boot BIOS Strap

1-2

PROGRAMMING SPI1

1-X

PROGRAMMING SPI0

1-X

KSC Enable

1-2

Boot Block Programming

1-2

NMI

1-X

SATA interlock switch for port1

1-2

LID Position

1-X

Virtual Battery

1-X

35 35 35 52 56 49 5 56 56 31 21 21 39 38 30 23 40 39 34 23 63 40 64 40 40 31 34 34 40 42 42 31 41 41

PCI Devices

Device

LAN

IDSEL # AD18 D, C, A, BSlot 3

(AD24 internal)

REQ/GNT # 2 2

Interrupts

Net Naming Conventions

Suffix # = Active Low Signal

Prefix H = Host M = DDR Memory TP = Test Point (does not connect anywhere else)

B B

Power States

S0 (Full on)/M0

S3 (Suspend to RAM)/M1

S3 (Suspend to RAM)/Moff

S3 (Suspend to RAM)/Moff w/WOL_EN

S4 (Suspend to Disk)/M1

S5 (Soft Off)/M1

S4 (Suspend to Disk)/Moff

S5 (Soft Off)/Moff

SLP_S3# HIGH

LOW

S4_STATE# HIGH

HIGH

LOW

SLP_S4# HIGH

HIGH

LOW

SLP_S5# HIGH

HIGH

LOW

HIGH

LOW

SLP_M# HIGH

HIGH

LOW

HIGH

LOW

+V*A ON

ON

+V3.3M_WOL ON

ON

OFF

ON

OFF

+V1.05M ON

ON

OFF

ON

OFF

+V3.3M ON

ON

OFF

ON

OFF

+V1.8/+V0.9 ON

ON

OFF

+V5/+V3.3 ON

ON

OFF

+V*S ON

OFF

Clocks ON

only MCH BCLK

OFF

only MCH BCLK

OFF

Wake Events

Wake Events RI# from serial port

A A

PME# from PCI, mini PCI slot/device, LPC slot/device PCI Express, mini PCI Express, Express-card wake event Wake on LAN LID switch attached to SMC USB HDA wake on ring SmLink for AOLII Hot Key from Scan matrix keyboard PS/2 Keyboard/mouse PWRBTN# Netdetect

5

State Supported S3 S3 S3 S3/M1 S3 S3 S3 S3 S3 S3 S3 S3, S4, S5 / M1

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

4

3

Date: Sheet of

NOTES

355659

A

355659

A

355659

A

2

Changes for Pillar Rock with PM GMCH SKU

SL No NO_STUFF STUFF

U6E2, U6E3, U6E4

1

L5F1

2

3

4

5

6

R5E5, R5F9, R5T16, R5U3, R5U11, R5U14, R5U21, R6V1

C5E8, C5E9, C5E11, C5E12, C5E13, C5E14, C5E15, C5T12, C5T13, C5U1, C5U2, C5U3

FB5F1, FB5F2, FB5T1

J2G1(3 4), J2G1(5 6), J2G1(7 8)

R5E4, R5T5, R5T8, R5T9, R5T10, R5T12, R5T17

C5E8,C5E9,C5T13,C5U3 with 0 Ohm 0402 size res IPN A93549-001

J2G1(1 2), J2G1(13 14)

LEDs and Switches

LED xTA Activity VID0 VID1 VID2 VID3 VID4 VID5 VID6 Num Lock Scroll Lock Caps Lock S3 M0/M1 S4 S5 S0 System Power Good LT Status

Switch Default Description Page SW9H1

1 - 2 1 - 2 1 - 2 1 - 2

Virtual Docking Virtual Battery LID Switch Hybrid GFX switch

Power Button Reset Button Net Detect

SW9H3 SW9H2 SW7J1

SW1C1 SW1C2 SW8E1

21 39 39 39 39 39 39 39 40 40 40 57 57 57 57 57 57 64

ReferencePage CR7H1 CR1B1 CR1B2 CR1B3 CR1B4 CR1B5 CR1B6 CR1B7 CR9G1 CR9G3 CR9G2 CR5H6 CR5H3 CR5H7 CR5H5 CR5H4 CR7H3 CR8G1

PCB Footprints

1

2

SOT-23

3

As seen from top

1

2

3

2 58Tuesday, August 28, 2007

1

5

4

Intel Confidential

41 41 41 41

56 56 56

SOT23-5

1.0

5

4

+V1.05S_CPU4,20,35,39,43,52,54

3

2

1

H_A#[35:3]6

D D

H_ADSTB#06 H_REQ#[4:0]6

H_A#[35:3]6

Layout note: no stub on H_STPCLK TP. H_STPCLK# to be routed in daisy chain fashion from ICH to LPC slot and then to CPU.

C C

H_STPCLK#_R

TP2F1NO_STUFF TP2F1NO_STUFF

H_STPCLK#21,43

Layout Note: TP2F1 should be placed close to J1G7

H_ADSTB#16

H_A20M#21 H_FERR#21

H_IGNNE#21

R2U11

R2U11 0

0

H_INTR21 H_NMI21,43

.

H_SMI#21,43

CPU_RSVD06

CPU_RSVD09

TP_CPU_RSVD01 TP_CPU_RSVD02 TP_CPU_RSVD03 TP_CPU_RSVD04 TP_CPU_RSVD05

TP_CPU_RSVD07 TP_CPU_RSVD08

B B

XDP_TMS

XDP_TDI

XDP_BPM#5

XDP_TCK

XDP_TRST#

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20

W6

H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27

W2

H_A#28

W5

H_A#29 H_A#30 H_A#31 H_A#32

W3

H_A#33

AA4

H_A#34

AB2

H_A#35

AA3

D22

R2U4 54.9

R2U3 54.9

R1U6 54.9

R1T2 54.9

R1T3

1%

.

U2E1A

J4

ADDR GROUP_0 ADDR GROUP_1

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]# A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]# A[27]# A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]# A[32]#

THERMAL

A[33]# A[34]#

PROCHOT#

A[35]#

V1

ADSTB[1]#

A6

ICH

A20M#

A5

FERR#

C4

D5 C6 B4 A3

M4 N5 T2 V3 B2 D2

D3 F6

THERMTRIP#

IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]

RESERVED

Penryn_Ball-out_Rev_1p0

+V1.05S_CPU4,20,35,39,43,52,54

1%

Layout Note: Place R1U6 close to CPU with stub length <200mils.

1%

649

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDO TMS

TRST#

DBR#

XDP/ITP SIGNALS

THERMDA

THERMDC

H CLK

BCLK[0] BCLK[1]

H1 E2 G5

H5 F21 E1

F1

D20 B3

H4

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6

TDI

AB3 AB5 AB6 C20

H_PROCHOT#_D

D21 A24 B25

C7

A22 A21

H_ADS# 6 H_BNR# 6 H_BPRI# 6

H_DEFER# 6 H_DRDY# 6 H_DBSY# 6

H_BREQ# 6

H_IERR#_R

H_INIT# 21

H_LOCK# 6 H_CPURST# 6,20

H_TRDY# 6

H_HIT# 6 H_HITM# 6

XDP_BPM#1 35 XDP_BPM#2 35

XDP_BPM#3 35 XDP_BPM#4 20 XDP_BPM#5 20

XDP_TCK 20

XDP_TDI 20

XDP_TDO 20

XDP_TMS 20

XDP_TRST# 20

XDP_DBRESET# 20

H_THERMDA 5

H_THERMDC 5

PM_THRMTRIP# 7,21

CLK_CPU_BCLK 35

CLK_CPU_BCLK# 35

R2H256R2H2 56

R2H356R2H3

56

Place testpoint on H_IERR# with a GND

H_RS#[2:0] 6

Layout note: Zo=55 ohm,

0.5" max for GTLREF.

0.1" away

NO_STUFF

TP1F1

+V1.05S_CPU4,20,35,39,43,52,54

PM_THRMTRIP# should connect to ICH9 and GMCH without T-ing (No stub)

H_GTLREF

Connect H_IERR# with no stub to the connector J2H1 and then connect to the 56 ohm pull up Resistor R2H2.

H_IERR#

XDP_BPM#0 20

TP1D1

TP1D1 R1R4

R1R4 68

68

5%

NO_STUFF

.

+V1.05S_CPU4,20,35,39,43,52,54

R1R16

R1R16 1K

1K

1%

1% .

.

R1R17

R1R17 2K

2K

1%

1% .

.

Place TP1D1 close to CPU.

R1D1

R1D1 0

0

.

C1T1

0.1uF

10%

NO_STUFF

Place C1T1 close to the CPU_TEST4 pin. Make sure CPU_TEST4 routing is reference to GND and away from other noisy signals.

H_PROCHOT# 52

H_PROCHOT#_D

H_DSTBN#06 H_DSTBP#06 H_DINV#06 H_D#[63:0]6

CPU_TEST3

CPU_TEST5 CPU_TEST6 CPU_TEST7

CPU_BSEL035 CPU_BSEL135 CPU_BSEL235

H_D#[63:0]6

H_DSTBN#16 H_DSTBP#16 H_DINV#16

CPU_TEST1 CPU_TEST2

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24

H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

CPU_TEST4

NO_STUFF

R3P5 1K

U2E1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

C3

TEST7

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Penryn_Ball-out_Rev_1p0

NO_STUFF

R3P6 1K

MISC

DATA GRP 0

DATA GRP 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#

DATA GRP 2DATA GRP 3

D[41]# D[42]# D[43]# D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]#

COMP[0] COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP# DPWR#

PWRGOOD

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0

R2R3 27.4 1%R2R3 27.4 1%

COMP1

R2R2 54.9 1%R2R2 54.9 1%

COMP2

R2U1 27.4 1%R2U1 27.4 1%

COMP3

R2U2 54.9 1%R2U2 54.9 1%

H_DPRSTP# 7,21,43 H_DPSLP# 21,43

H_CPUSLP# 6,43 PSI# 52

Layout: Connect test point TP3E2 with no stub

H_D#[63:0] 6

H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 H_D#[63:0] 6

Layout note: Comp0,2 connect with Zo=27.4ohm, make trace length shorter than 0.5". Comp1,3 connect with Zo=55ohm, make trace length shorter than 0.5".

H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6

H_DPWR# 6 H_PWRGD 21,43

H_PWRGD_XDP 20

TP3E2

NO_STUFF

R1U15

R1U15 1K

1K

5%

5% .

.

Place Series Resistor on H_PWRGD_XDP Without Stub

A A

Intel Confidential

3 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

Pillar Rock

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Date: Sheet of

5

4

3

Date: Sheet of

Penryn (1 of 2)

355659

2

5

4

3

2

1

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

+VCC_CORE53,54,55

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

.

CPU_G21

NO_STUFF

TP3E1

R3T2 is for test purpose only.

R3T2

R3T2 0

0

.

H_VID0 52 H_VID1 52 H_VID2 52 H_VID3 52 H_VID4 52 H_VID5 52 H_VID6 52

C2U2

C2U2 270uF

270uF

20%

20% .

.

+V1.05S_CPU3,20,35,39,43,52,54

+VCCA_PROC

+VCC_CORE53,54,55

R1T16

R1T16 100

100

1%

1% .

.

R1T14

R1T14 100

100

1%

1% .

.

C3R3

0.01uF

10%

10% .

.

VCCSENSE 52

VSSSENSE 52

R3U2

R3U1

C3R2

Layout Note:

10uF

Place C3R3 near pin-B26

20%

20% .

.

Layout Note: Route VCCSENSE and VSSSENSE traces at

27.4 Ohms with 50 mil spacing. Place PU and PD within 1 inch of CPU.

0

R3R13 0.01

12

NO_STUFF

12

NO_STUFF

1%

+V1.05S9,10,24,47,55

+V1.5S10,11,24,28,47,55,57

U2E1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Penryn_Ball-out_Rev_1p0

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

.

+VCC_CORE53,54,55

D D

C C

U2E1C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Penryn_Ball-out_Rev_1p0

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VCCSENSE

VSSSENSE

B B

A A

Intel Confidential

4 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

Pillar Rock

Title

Size Document Number Rev

Custom

Date: Sheet of

5

4

3

Date: Sheet of

Penryn (2 of 2)

355659

2

5

4

3

2

1

CPU Thermal Sensor

C3N10

0.1uF

20%

20% .

.

U3B3

1

VDD

2

D+

3

D-

T_CRIT#4GND

LM95245C

SMBCLK

SMBDAT

OS#/A0

8

7

6

5

R3B19

R3B19 10K

10K

5%

5% .

.

0

+V3.3S7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R3N21

R3N21 10K

10K

5%

5% NO_STUFF

NO_STUFF

C3N11

ADT_THERM_DXP

ADT_THERM_DXN

1000pF

5%

ADT_THM# THRM_ALERT#

NO_STUFF

D D

C C

J3C1

1-2 3-4

1-X 3-X

Layout Note: Route H_THERMDA and H_THERMDC on same layer w/ 10 mil trace & 10 mil spacing. Route away from noise sources with ground guard tracks on each side.

H_THERMDA3 H_THERMDC3

Thermal Diode Connector

Connects the Internal CPU Thermal sensor to the ADT7461A (Default)

Connect an external Thermal sensor to the ADT7461A

J4A1

J4A1 3Pin_Recepticle

3Pin_Recepticle

GND0

3 4 5 6

GND1

J3C1

1 3

2X2HDR

12

THERMDNTHERMDP

GND2

NO_STUFF

GND3

THERM_DXP

2 4

THERM_DXN

R3N27

R3N26

.

NOTE : R3N27, R3N26, C3N11 are placeholders for the new thermal sensor (NS LM95245).

+V3.3S7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R3N22

R3N19

10K

5%

.

SMB_THRM_CLK 12,40,43

SMB_THRM_DATA 12,40,43

R3N20

R3N20 0

0

NO_STUFF

Note: No-Stuff R3N20 for normal operation, No Stuff (R9G11, Sheet 40) if R3N20 is stuffed

PM_THRM# 12,23,40,43

CPU Fan Power Control

+V5S11,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57

R2N4

R2N4 0

0

.

+V3.3S7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R2N6

R2N6 1K

1K

1%

1% .

.

CPU_TACHO_FAN 40,43

Intel Confidential

5 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

CPU Thermal Sensor & Fan

355659

A

355659

A

355659

A

2

C3N4

C3N6

0.1uF

4.7uF

10%

B B

OPA567_POSIN

R3N14

CPU_PWM_FAN40,43

R3N14 15K

15K

1%

1% .

.

10%

.

1

101112

EU3B1

V+

_

C3B5

C3B5 1uF

1uF

10%

.

_

8

OPA567

9

+

V-

456

HS

TF

EN

IF

IS

13

OPA567_ISIN_R

2

OUT

3

.

7

OPA567_NEGIN

R3N6

R3N6 20K

20K

5%

5% .

.

VOUT_OPAMP

CR2N2

CR2N2 BAT54

BAT54

R3N8

1.74K

1%

1% .

.

R3N10

3.32K

1%

1% .

.

2

CPU_TACHO_R_FAN

Note: No-Stuff R2N4 to Disable PWM control of FAN

11332

3

1

J2B3

CONN3_HDR

.

A A

5

4

3

5

D D

+VCCP_GMCH10

R4E8

R4E8 221

221

1%

1% .

.

R4E5

R4E5 100

100

1%

1% .

.

C C

R4E2

24.9

1%

1% .

.

C4F1

0.1uF

20%

20% .

.

H_RCOMP

H_SWING

B B

+VCCP_GMCH10

R4E7

R4E7 1K

1K

1%

1% .

H_AVREF

H_DVREF

.

R4E4

R4E4 2K

2K

1%

1% .

.

R4E6 0

0

.

4

U5E1A

M11

AD14

AA8

AA13

AA9 AA11 AD11 AD10 AD13 AE12

AE9

AA2

AD8

AA3

AD3

AD7 AE14

AC1

AE3

AC3 AE11

AE8

AG2

AD6

G2 H6 H2

D4 H3 M9

N12

R2 N9

M5

N2 R1 N5 N6

P13

N8

N10

M3

Y10 Y12 Y14

W2

AF3

C5

C12 E11

A11 B11

U5E1A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3 H_D#_4 H_D#_5 H_D#_6

F6

H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11

J1

H_D#_12

J2

H_D#_13 H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17 H_D#_18 H_D#_19

L6

H_D#_20 H_D#_21

J3

H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28

L7

H_D#_29 H_D#_30 H_D#_31

Y3

H_D#_32 H_D#_33

Y6

H_D#_34 H_D#_35 H_D#_36 H_D#_37

Y7

H_D#_38 H_D#_39 H_D#_40

Y9

H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING

E3

H_RCOMP

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

CANTIGA_1p2

H_D#[63:0]3

H_CPURST#3,20

H_CPUSLP#3,43

C4E12

0.1uF

10%

10%R4E6

NO_STUFF

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

3

H_A#3

A14

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS# H_ADSTB#_0 H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

HOST

H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

H_A#4

C15

H_A#5

F16

H_A#6

H13

H_A#7

C18

H_A#8

M16

H_A#9

J13

H_A#10

P16

H_A#11

R16

H_A#12

N17

H_A#13

M13

H_A#14

E17

H_A#15

P17

H_A#16

F17

H_A#17

G20

H_A#18

B19

H_A#19

J16

H_A#20

E20

H_A#21

H16

H_A#22

J20

H_A#23

L17

H_A#24

A17

H_A#25

B17

H_A#26

L16

H_A#27

C21

H_A#28

J17

H_A#29

H20

H_A#30

B18

H_A#31

K17

H_A#32

B20

H_A#33

F21

H_A#34

K21

H_A#35

L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

H_REQ#0

B15

H_REQ#1

K13

H_REQ#2

F13

H_REQ#3

B13

H_REQ#4

B14

H_RS#0

B6

H_RS#1

F12

H_RS#2

C8

2

H_A#[35:3] 3

H_DINV#0 3 H_DINV#1 3 H_DINV#2 3 H_DINV#3 3

H_DSTBN#0 3 H_DSTBN#1 3 H_DSTBN#2 3 H_DSTBN#3 3

H_DSTBP#0 3 H_DSTBP#1 3 H_DSTBP#2 3 H_DSTBP#3 3

H_ADS# 3 H_ADSTB#0 3 H_ADSTB#1 3 H_BNR# 3

H_BPRI# 3

H_BREQ# 3

H_DEFER# 3

H_DBSY# 3 CLK_MCH_BCLK 35 CLK_MCH_BCLK# 35

H_DPWR# 3

H_DRDY# 3

H_HIT# 3

H_HITM# 3

H_LOCK# 3

H_TRDY# 3

H_RS#[2:0] 3

1

H_REQ#[4:0] 3

H_VREF & H_DVREF

A A

5

Default= R4E6(STUFF) R4E3, R4F1(NO_STUFF) on Sheet # 65

H_AVREF & H_DVREF shorted togther (same voltage divider) For EV= R4E6(NO_STUFF) R4E3, R4F1 (STUFF) on Sheet # 65

H_AVREF & H_DVREF can be schoomed independently for EV (separate voltage divider)

4

Intel Confidential

6 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

3

Date: Sheet of

CANTIGA (1 OF 6)

355659

A

355659

A

355659

A

2

5

U5E1B

M36

MCH_RSVD_1 MCH_RSVD_2 MCH_RSVD_3 MCH_RSVD_4 MCH_RSVD_5 MCH_RSVD_6 MCH_RSVD_7 MCH_RSVD_8

D D

MCH_RSVD_14

MCH_RSVD_21

MCH_RSVD_24 MCH_RSVD_25

MCH_CFG_18 MCH_CFG_1912 MCH_CFG_2012,19

PM_EXTTS#0_EC40 TS#_DIMM0_113,14

R5D1

20

1%

MCH_TCK15

MCH_TDI15

MCH_TDO15

MCH_TMS15

MCH_CFG_[17:3]12

PM_SYNC#23

H_DPRSTP#3,21,43

DELAY_VR_PWRGOOD23

PM_THRMTRIP#3,21

PM_DPRSLPVR23,43,52

PLT_RST# 19,22,25,26,38,41,57

+V1.8_GMCH9,10

.

NO_STUFF

.

C C

B B

A A

MCH_BSEL035 MCH_BSEL135 MCH_BSEL235

TP5F2 NO_STUFFTP5F2 NO_STUFF

R5D4

80.6

1%

SM_RCOMP SM_RCOMP#

1%

80.6

80.6 R5D3

R5D3

TP_MCH_RSVD9

TP_MCH_RSVD15

TP_MCH_RSVD17

TP_MCH_RSVD20

TP_MCH_RSVD22 TP_MCH_RSVD23

MCH_CFG_20_R

R5F10

R5F10 0

0

.

PM_SYNC#_R

R5F13

PM_DPRSTP#_R

0

R4T2

R4T2 0

0

PM_EXTTS#1_R

R5P2

.

0

.

R4R11 100R4R11 100

.

R4T3 0

R4T3 0 R5U31 0

R5U31 0

.

. .

.

TP_MCH_NC1 TP_MCH_NC2 TP_MCH_NC3 TP_MCH_NC4 TP_MCH_NC5 TP_MCH_NC6 TP_MCH_NC7 TP_MCH_NC8 TP_MCH_NC9 TP_MCH_NC10 TP_MCH_NC11 TP_MCH_NC12 TP_MCH_NC13 TP_MCH_NC14 TP_MCH_NC15 TP_MCH_NC16 TP_MCH_NC17 TP_MCH_NC18 TP_MCH_NC19 TP_MCH_NC20 TP_MCH_NC21 TP_MCH_NC22 TP_MCH_NC23 TP_MCH_NC24 TP_MCH_NC25

MCH_CFG_3 MCH_CFG_4 MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_8 MCH_CFG_9 MCH_CFG_10 MCH_CFG_11 MCH_CFG_12 MCH_CFG_13 MCH_CFG_14 MCH_CFG_15 MCH_CFG_16 MCH_CFG_17

RST_IN#_MCH THRMTRIP#_R DPRSLPVR_R

R5R1

R5R1 20

20

NO_STUFF

NO_STUFF 1%

1%

N36 R33

T33

AH9 AH10 AH12 AH13

K12

T24

B31

M1

AY21

B2 BG23 BF23 BH18 BF18

AL34

AK34

AN35

AM35

T25 R25 P25 P20 P24 C25 N24

M24

E21 C23 C24 N21

P21

T21 R20 M20

L21 H21

P29

R28

T28

R29

B7

N33

P32

AT40 AT11

T20 R32

BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43

BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1

F1

CANTIGA_1p2

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9

RSVD14

RSVD15

RSVD17

RSVD20

RSVD21 RSVD22 RSVD23 RSVD24 RSVD25

ME_JTAG_TCK

ME_JTAG_TDI

ME_JTAG_TDO

ME_JTAG_TMS

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25

RSVD

ME JTAG

CFG

PM

NC

5

4

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

BB36

SB_CKE_1

BA17

SA_CS#_0

AY16

SA_CS#_1

AV16

SB_CS#_0

AR13

SB_CS#_1

BD17

SA_ODT_0

AY17

SA_ODT_1

BF15

SB_ODT_0

AY13

SB_ODT_1

BG22

SM_RCOMP

SM_VREF

SM_REXT

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK

HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

BH21

SM_RCOMP_VOH

BF28

SM_RCOMP_VOL

BH28

AV42 AR36 BF17 BC36

B38 A38 E41 F41

F43 E43

AE41 AE37 AE47 AH39

AE40 AE38 AE48 AH40

DMI_RXN0

AE35

DMI_RXN1

AE43

DMI_RXN2

AE46

DMI_RXN3

AH42

DMI_RXP0

AD35

DMI_RXP1

AE44

DMI_RXP2

AF46

DMI_RXP3

AH43

B33 B32 G33 F33 E33

C34

AH37 AH36 AN36 AJ35

MCH_CLVREF_R

AH34

N28 M28 G36 E36 K36 H36

B12

HDA_CODEC_BCLK

B28

HDA_CODEC_RST#

B30

HDA_SDIN

B29

HDA_CODEC_SDATAOUT

C29

HDA_CODEC_SYNC

A28

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_PWROK

SM_DRAMRST#

DPLL_REF_CLK

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

DMI

GFX_VR_EN

GRAPHICS VID

MEHDA

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

SM_RCOMP

SM_RCOMP#

SM_REXT

TP_SM_DRAMRST#

DREFCLK 35 DREFCLK# 35 DREFSSCLK 35 DREFSSCLK# 35

CLK_PCIE_3GPLL 35 CLK_PCIE_3GPLL# 35

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

NO_STUFF

R5D90

M_CLK_DDR0 13 M_CLK_DDR1 13 M_CLK_DDR3 14 M_CLK_DDR4 14

M_CLK_DDR#0 13 M_CLK_DDR#1 13 M_CLK_DDR#3 14 M_CLK_DDR#4 14

M_CKE0 13,15 M_CKE1 13,15 M_CKE3 14,15 M_CKE4 14,15

M_CS#0 13,15 M_CS#1 13,15 M_CS#2 14,15 M_CS#3 14,15

M_ODT0 13,15 M_ODT1 13,15 M_ODT2 14,15 M_ODT3 14,15

SM_PWROK 46

R4R7 499

. 1%

GFXVR_VID_0 49 GFXVR_VID_1 49 GFXVR_VID_2 49 GFXVR_VID_3 49 GFXVR_VID_4 49

GFXVR_EN 49

CL_CLK0 23 CL_DATA0 23 MPWROK 23,46

DDPC_CTRLCLK 19 DDPC_CTRLDATA 19 SDVO_CTRLCLK 19 SDVO_CTRLDATA 19 CLK_MCH_OE# 35

MCH_ICH_SYNC# 23

MCH_TSATN# 41

LVDS_VDD_EN17

LVDS_IBG

+V1.8_GMCH9,10

NO_STUFF

R5R5

R5R5 1K

1K

1%

1% NO_STUFF

NO_STUFF

DMI_TXN[3:0] 22

DMI_TXP[3:0] 22

DMI_RXN[3:0] 22

DMI_RXP[3:0] 22 PEG_TX[15:0] 19

+V1.25S_1.05M_CANTIGA9,10

CL_RST#0 23

MCH_CLVREF

IMPORTANT NOTE:

When the Resistors R8E7, R7H3 (Page-28) are mounted, then the resistors R7V4, R7V3, R7V8, R7V23, R5F9 should be NO_STUFF.

4

3

L_BKLT_CTRL17 L_BKLT_EN17

L_CTRL_CLK17,20

L_CTRL_DATA17,20

LVDS_DDC_CLK17

LVDS_DDC_DATA17

R5T11

2.37K

1%

.

R5R4

R5R4 1K

1K

1%

M_VREF_MCH 46,48

NOTE:SM_DRAMRST# Would be needed for DDR3 only

NOTE: All LVDS data signals/and its compliments SHOULD BE ROUTED DIFFERENTIALLY

TVA_DAC18 TVB_DAC18

TVC_DAC18

R5U4 150 1%R5U4 150 1% R5U7 150 1%R5U7 150 1% R5U6 150 1%R5U6 150 1%

Layout Note: Place 150 Ohm termination resistors close to GMCH

R5T4 150 1%R5T4 150 1% R5T5 150 1%R5T5 150 1% R5T6 150 1%R5T6 150 1%

CRT_DDC_CLK_MCH16

CRT_DDC_DATA_MCH16

CRT_HSYNC16

CRT_VSYNC16

R5D10

R5D10 1K

1K

1%

R5D11

R5D11 0

0

NO_STUFF

R5D12

R5D12 511

511

1%

1% .

.

NO_STUFF

C5D3

0.1uF

10%

.

3

2

U5E1C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

L_VDD_EN_R

R5U18

R5U18 0

0

NO_STUFF

TP5F1

LVDSA_CLK#17 LVDSA_CLK17 LVDSB_CLK#17 LVDSB_CLK17

LVDSA_DATA#017 LVDSA_DATA#117 LVDSA_DATA#217 LVDSA_DATA#317

LVDSA_DATA017 LVDSA_DATA117 LVDSA_DATA217 LVDSA_DATA317

LVDSB_DATA#017 LVDSB_DATA#117 LVDSB_DATA#217 LVDSB_DATA#317

LVDSB_DATA017 LVDSB_DATA117 LVDSB_DATA217 LVDSB_DATA317

R5U9 0.5%R5U9 0.5% R5U8 0.5%R5U8 0.5% R5U5 0.5%R5U5 0.5%

TV_DCONSEL0_MCH18 TV_DCONSEL1_MCH18

CRT_BLUE16

CRT_GREEN16

CRT_RED16

R5U10 30.1

R5T7 1.02k

0.5% .

R5U11 30.1

EV_VCC_V1.05_CLVREF0

****

R7V4 33 NO_STUFFR7V4 33 NO_STUFF C5R3 R7V3 33 NO_STUFFR7V3 33 NO_STUFF R7V8 33 NO_STUFFR7V8 33 NO_STUFF R7V23 33 NO_STUFFR7V23 33 NO_STUFF R5F9 0 NO_STUFFR5F9 0 NO_STUFF

LVDS_VBG

.

MCH_TVA_DAC MCH_TVB_DAC MCH_TVC_DAC

HSYNC CRTIREF

.

.R5T7 1.02k

VSYNC

.

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANTIGA_1p2

+V1.8_GMCH9,10

HDA_BIT_CLK 21,27

HDA_RST# 21,27

HDA_SYNC 21,27

HDA_SDOUT 21,27

HDA_SDIN3 21,27

CANTIGA (2 OF 6)

355659

2

LVDS

TV

PCI-EXPRESS GRAPHICS

VGA

R5D5

R5D5 1K

1K

0.10%

R5D8

3.01k

1%

R5D6

R5D6 1K

1K

0.10%

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8

PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

+V3.3S5,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

C5R2

0.01uF

10%

402

C5R1

0.01uF

10%

402

PEG_COMP

T37 T36

H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39

H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40

J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46

J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46

R5U13 10KR5U13 10K

R5U12 10KR5U12 10K

R5P5 10KR5P5 10K

SM_RCOMP_VOH

C5R4

2.2uF

10%

.

SM_RCOMP_VOL

C5R3

2.2uF

10%

.

1

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8

PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

7 58Tuesday, August 28, 2007

1

+VCC_PEG10

R5T3 49.9R5T3 49.9

PEG_RX#[15:0] 19

PEG_RX[15:0] 19

PEG_TX#[15:0] 19

CLK_MCH_OE#

PM_EXTTS#0_EC

PM_EXTTS#1_R 15

Intel Confidential

1.0

5

4

3

2

1

M_A_DQ[63:0]13 M_B_DQ[63:0]14

D D

C C

B B

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AJ38

AJ41 AN38 AM38

AJ36

AJ40

AM44 AM42

AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36

AW36

BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12

AU10

BA11

AN10

AM11

AM5

AN12

AM13

AJ11

AJ12

BB9 BA9

AV9

BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5

AJ9 AJ8

U5E1D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

CANTIGA_1p2

BD21

SA_BS_0

BG18

SA_BS_1

AT25

SA_BS_2

BB20

SA_RAS#

BD20

SA_CAS#

AY20

SA_WE#

M_A_DM0

AM37

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

DDR SYSTEM MEMORY A

AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6

M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

M_A_BS1 13,15 M_A_BS2 13,15

M_A_RAS# 13,15 M_A_CAS# 13,15 M_A_WE# 13,15

M_A_DM[7:0] 13

M_A_DQS[7:0] 13

M_A_DQS#[7:0] 13

M_A_A[14:0] 13,15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AK47 AH46 AP47 AP46

AJ46

AJ48 AM48 AP48 AU47 AU46 BA48

AY48

AT47 AR47 BA47 BC47 BC46 BC44 BG43

BF43 BE45 BC41

BF40

BF41 BG38

BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11

BG8

BH12

BF11

BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1

AH1 AM2 AM3 AH3

AL1 AL2 AJ1

AJ3

U5E1E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

CANTIGA_1p2

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

M_B_DM0

AM47

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

DDR SYSTEM MEMORY B

AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

M_B_BS0 14,15M_A_BS0 13,15 M_B_BS1 14,15 M_B_BS2 14,15

M_B_RAS# 14,15 M_B_CAS# 14,15 M_B_WE# 14,15

M_B_DM[7:0] 14

M_B_DQS[7:0] 14

M_B_DQS#[7:0] 14

M_B_A[14:0] 14,15

A A

5

4

3

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

CANTIGA (3 OF 6)

355659

A

355659

A

355659

A

2

8 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

5

4

3

2

1

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

+VGFX_CORE49

+VCCSM_LF1 +VCCSM_LF2 +VCCSM_LF3 +VCCSM_LF4 +VCCSM_LF5 +VCCSM_LF6

+VCCSM_LF7

+VCC_GFXCORE49 +V1.25S_1.05M_CANTIGA7,10

+V1.05M10,15,35,47,55

+V1.05S4,10,24,47,55

R4U5 TO BE STUFFED ONLY AS BACKUP OPTION FOR +VGFX_CORE

VCC_SM_36

C5R12

0.1uF

10%

C4R4

C4R8

0.1uF

10%

.

SMC0402

.

SMC0402

4

R3F1

NO_STUFF

R4F6

.

R3F2 0.002

1%

R4U5 0.002

1%

NO_STUFF

VCC_SM_37

VCC_SM_38

C4R10

C4R11

0.1uF

10%

Place C5C7 where LVDS and DDR2 taps.

C4R5

0.22uF

SMC0402

.

R5U3 0.002

1%

12

0.002

12

0.002

12

+

C4T7

C4T7 330uF

330uF

3

20%

smc7343_TAK

Place close to the GMCH

VCC_SM_40

VCC_SM_42

C4R12

C4R13

0.1uF

10%

NO_STUFF

+V1.8 10,13,14,46,48,55,57

R5C6 0.002

C5C7

0.1uF

10%

.

SMC0402

.

SMC0402

C4R6

C5R10

0.22uF

0.47uF

SMC0402

SMC7343

Place close to the GMCH

12

+

3

smc7343_TAK

1%

C5R7

1.0uF

20%

SMC0402

C5U4

C5U4 270uF

270uF

20%

+V1.25S_1.05M_CANTIGA

For Teenah

For Cantiga STUFF: R4F6

+VGFX_CORE49+VCC_GFXCORE49

C4T5

C4T5 330uF

330uF

20%

C5C8

C5C8 330uF

330uF

20%

SMC7343_75h

C5R8

1.0uF

20%

20% SMC0402

SMC0402

3

STUFF: R3F1 NO_STUFF: R4F6

NO_STUFF: R3F1

C4T3

0.47uF

SMC0603

C5T3

C5T3 22uF

22uF

20%

.

SMC0805

.

SMC0805

C4R9

C4R9 1uF

1uF

20%

20% .

SMC0603

.

SMC0603

Cavity Capacitors

SMC0805

PLACE ON THE EDGE

C5T1

C5R11

0.22uF

20%

SMC0603

C4T6

C4T2

22uF

10uF

20%

.

SMC0805

.

SMC0805

.

SMC0805

.

SMC0805

Cavity Capacitors

R5T1 is used for internal test purpose only

C5D2

C5D1

22uF

20%

.

SMC0805

.

SMC0805

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

CANTIGA (4 OF 6)

355659

A

355659

A

355659

A

U5E1G

D D

+V1.8_GMCH7,10

Pins BA36, BB24, BD16, BB21, AW16, AW13, AT13 could be left NC for DDR2 boards

C C

VCC_SM_36 VCC_SM_37 VCC_SM_38

VCC_SM_40

VCC_SM_42

+VGFX_CORE

B B

A A

VCC_AXG_SENSE49 VSS_AXG_SENSE49

Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially

AP33 AN33 BH32 BG32

BF32 BD32 BC32

BB32

BA32

AY32 AW32

AV32 AU32

AT32 AR32

AP32 AN32 BH31 BG31

BF31 BG30 BH29 BG29

BF29 BD29 BC29

BB29

BA29

AY29 AW29

AV29 AU29

AT29 AR29

AP29

BA36

BB24 BD16

BB21 AW16 AW13

AT13

AE25

AB25

AA25

AE24 AC24

AA24

AE23 AC23

AB23

AA23

AJ21

AG21

AE21 AC21

AA21

AH20

AF20

AE20 AC20

AB20

AA20

AM15

AL15

AE15

AJ15 AH15 AG15

AF15 AB15 AA15

AN14 AM14

AJ14 AH14

Y26

Y24

Y21

T17 T16

Y15 V15 U15

U14 T14

U5E1G

VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35

VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42

VCC_AXG_SENSE VSS_AXG_SENSE

CANTIGA_1p2

POWER

VCC SMVCC GFX

VCC GFX NCTF

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

5

C5T4

0.1uF

10%

10% .

SMC0402

.

SMC0402

C4T4

C5T2

0.1uF

10%

.

SMC0402

.

SMC0402

.

SMC0402

.

SMC0402

+V1.8_GMCH 7,10

C5R13

0.1uF

10%

NO_STUFF

2

+VCC_GMCH+V1.05M10,15,35,47,55

NO_STUFF

C5T10

1.0uF

20%

20% 402

402

R5T1

R5T1 0

0

.

+VCC_MCH_35

AG34 AC34 AB34 AA34

AM33 AK33

AJ33

AG33

AF33

AE33 AC33 AA33

W33

AH28

AF28 AC28 AA28

AJ26 AG26 AE26 AC26 AH25 AG25

AF25 AG24

AJ23 AH23

AF23

Y34 V34 U34

Y33

V33 U33

T32

U5E1F

VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34

VCC_35

CANTIGA_1p2

VCC CORE

POWER

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31

VCC NCTF

VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

9 58Tuesday, August 28, 2007

1

+VCC_GMCH

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

Intel Confidential

1.0

5

+V1.25S_1.05M_CANTIGA7,9

12

.

R5F14

0.002

L5F1 10uH

1 2

10%

201005-548

D D

L6F1 10uH

+V1.05M_MCH_PLL+V1.05M_MCH_PLL2

1 2

10%

201005-548

+V1.25S_1.05M_CANTIGA

.

12

R4D6

0.002

R4E90.R4E9

0.

C C

B B

A A

FB4E1

SMF0603

120ohm@100MHz

R4E1 0.51

+V1.05M_MPLL_RC

C4T1

C4T1 22uF

22uF

20%

.

SMC0805

.

SMC0805

+V3.3S_TVDAC

FB4F1

180ohm@100MHz

SMF0603

NOTE: CAPS USED IN +V3.3S_TVDAC should be within 250mils of edge of MCH

+V1.5S

R4U3

1 2

0.002

+V1.5S_LDO_QDAC28

12

0.002

0.002 R4U4

R4U4

+V1.5S_LDO_QDAC_R

+V1.25S_1.05M_CANTIGA

R5T8

1 2

0.002

.

+V1.05M_DPLLA

C5E8

+

C5U7

+

C5U7 220uF

220uF

0.1uF

10%

.

SMC0402

.

SMC0402

+V1.05M_DPLLB

+

C5F1

+

C5F1

C5E5

220uF

0.1uF

10%

.

SMC0402

.

SMC0402

+V1.05M_HPLL

C4E4

4.7uF

10%

.

SMC0603

.

SMC0603

+V1.05M_MPLL

1%

SMR0402

+V3.3S_A_TV_CRT_BG +V3.3S_A_TV_DAC

R4U2

R4U2 0

0

NO_STUFF

FB5U1

180ohm@100MHz

SMF0603

+V1.05M_PEGPLL_R

+V1.05M_PEGPLL_RC

C5T8

C5T8 10uF

10uF

20%

.

SMC0805

.

SMC0805

+V3.3S_A_TV_CRT_BG

1 2

+V1.5S4,11,24,28,47,55,57

R6E1

1 2

.

+V1.25S_1.05M_CANTIGA7,9

C4E3

0.1uF

10%

.

SMC0402

.

SMC0402

C4E1

0.1uF

10%

.

SMC0402

.

SMC0402

+V1.25S_1.05M_CANTIGA7,9

R4F3

1 2

0.002

R4U2 to be stuffed & R4U4 to be no_stuffed , if val needs to be done from switcher

SMF0805

220ohm_at_100MHz

R5T2

SMR0402

C5U1

0.1uF

10%

.

SMC0402

.

SMC0402

C5U3

0.1uF

10%

.

SMC0402

.

SMC0402

1 2

FB5T1

1.00

1%

R4R1

1 2

.

12

+

C4E2

C4E2 100uF

100uF

SMC7343

R4R2

0.002

.

C5T9

0.01uF

10%

10% SMC0402

SMC0402

C5U2

0.01uF

10%

10% SMC0402

SMC0402

R5F2

0.002

R5F6

0.002

+V1.05M_A_SM_R

0.002

+V1.05M_A_SM_CK_R

C5E18

0.1uF

10%

.

SMC0402

.

SMC0402

+V1.5S_TVDAC

+V1.05M_PEGPLL

10%

.

SMC0402

.

SMC0402

C5T5

0.1uF

+V3.3S_A_CRT_DAC

C5E12

0.1uF

10%

.

SMC0402

.

SMC0402

C5E13

0.1uF

10%

.

SMC0402

.

SMC0402

+V3.3S

R5D13

R5D13 0

0

NO_STUFF

C5E2

0.1uF

10%

.

SMC0402

.

SMC0402C4E4

SMR0603

C5E14

0.01uF

10%

10% SMC0402

SMC0402

+V1.5S_QDAC

R5U2

R5U2 0

0

NO_STUFF

+V1.5S4,11,24,28,47,55,57

SMR0603

+VCC_HDA

5

C5E17

0.01uF

10%

10% SMC0402

SMC0402

C5E16

0.01uF

10%

10% SMC0402

SMC0402

+VCCA_PEG_BG

R4R3

R4R3 0

0

.

R5R3

R5R3 0

0

.

R5E7

R5E7 0

0

NO_STUFF

+V1.8_LDO46

1 2

4

+V1.8_TXLVDS

+V1.05M_A_SM

C4R1

C4R1 22uF

22uF

20%

20% SMC0805

SMC0805

NO_STUFF

C4R3: Edge Cap

NO_STUFF

+V1.05M_MCH_PLL2

R5U1

0.002

4

R5E5

R5E5 0

0

NO_STUFF

+V3.3S_A_DAC_BG

R5E6

R5E6 0

0

NO_STUFF

+V1.05M_PEGPLL

C5R7:Cavity Cap

C4R2

C4R2 22uF

22uF

20%

.

SMC0805

.

SMC0805

+V1.05M_A_SM_CK

C5R6

C5R5

22uF

2.2uF

20%

10%

SMC0805

SMC0603

+V3.3S_A_TV_DAC

R5T10

R5T10 0

0

5%

+V1.5S_QDAC

C4D3

0.1uF

10%SMC0402

.

Topside Cap

R5F8

1 2

R5F5

0.002

NO_STUFF

+VCC_HDA

C5E11

0.1uF

10%

.

SMC0402

.

SMC0402

+V1.05M_DPLLA

+V1.05M_DPLLB

+V1.05M_HPLL

+V1.05M_MPLL

C5E7

C5E7 1000pF

1000pF

10%

10% .

.

SMC0402

C4R3

4.7uF

10%

.

SMC0603

.

SMC0603

.

+V1.5S_TVDAC

+V1.05M_PEGPLL

+V1.8_DLVDS+V1.89,13,14,46,48,55,57

0.002

12

C4R7

1.0uF

20%

20% SMC0402

SMC0402

C5R9

0.1uF

10%

.

SMC0402

.

SMC0402

C5T6

0.1uF

10%

.

SMC0402

.

SMC0402

R5T9

R5T9 0

0

5%

NO_STUFF

U5E1H

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

AD48

VCCA_PEG_BG

AA48

VCCA_PEG_PLL

AR20

VCCA_SM_1

AP20

VCCA_SM_2

AN20

VCCA_SM_3

AR17

VCCA_SM_4

AP17

VCCA_SM_5

AN17

VCCA_SM_6

AT16

VCCA_SM_7

AR16

VCCA_SM_8

AP16

VCCA_SM_9

AP28

VCCA_SM_CK_1

AN28

VCCA_SM_CK_2

AP25

VCCA_SM_CK_3

AN25

VCCA_SM_CK_4

AN24

VCCA_SM_CK_5

AM28

VCCA_SM_CK_NCTF_1

AM26

VCCA_SM_CK_NCTF_2

AM25

VCCA_SM_CK_NCTF_3

AL25

VCCA_SM_CK_NCTF_4

AM24

VCCA_SM_CK_NCTF_5

AL24

VCCA_SM_CK_NCTF_6

AM23

VCCA_SM_CK_NCTF_7

AL23

VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

CANTIGA_1p2

C5E9

1.0uF

20%

20% SMC0402

SMC0402

+V3.3S

3

CRTPLLA PEGA SM

A LVDS

POWER

A CK

TV

HDA

D TV/CRT

LVDS

+V1.05S4,9,24,47,55

1

CR5F1

CR5F1 BAT54

BAT54

+V1_05S_SD

3

12

R5U19

R5U19 10

10

5%

3

SM CK

DMI

R5F1

1 2

0.002

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15

VTT

VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

VCC_TX_LVDS

VCC_HV_1 VCC_HV_2 VCC_HV_3

HV

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

PEG

VCC_DMI_1

VCC_DMI_2 VCC_DMI_3 VCC_DMI_4

VTTLF1 VTTLF2 VTTLF3

VTTLF

+V3.3S_HV

C5E10

0.1uF

10%

.

SMC0402

.

SMC0402

2

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47

+V3.3S_HV

C35 B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

+VTTLF_CAP1

A8

+VTTLF_CAP2

L1

+VTTLF_CAP3

AB2

C4E5

0.47uF

SMC0402

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

C4E6

0.47uF

SMC0603

+V1.05M_AXF

C4E14

1.0uF

20%

20% SMC0402

SMC0402

+V1.8_SM_CK

C4D2

0.1uF

10%

.

SMC0402

.

SMC0402

+V1.8_TXLVDS

R5E4

R5E4 0

0

5%

5% NO_STUFF

NO_STUFF

+VCC_PEG7 +V1.05M9,15,35,47,55

+VCC_DMI

C4T8

C4E8

0.47uF

SMC0402

NO_STUFF

CANTIGA (5 OF 6)

355659

C4E9

2.2uF

10%

10% .

SMC0805

.

SMC0805

R4D2

SMR0402

C5E6

C5E6 1000pF

1000pF

10%

10% .

.

SMC0402

C5E4

4.7uF

10%

10% .

SMC0805

.

SMC0805

C5E1

0.1uF

10%

10% SMC0402

SMC0402

C4E13

0.47uF

SMC0402

NO_STUFF

1.001%

.

C4E7

4.7uF

10%

10% .

SMC0805

.

SMC0805

1 2

C4E15

C4E15 10uF

10uF

20%

20% SMC0805

SMC0805

+V1.8_SMCK_RC

C5E3

C5E3 22uF

22uF

20%

20% .

SMC0805

.

SMC0805

R5E1

1 2

0.002

+VCC_DMI

C4T9

0.47uF

NO_STUFF

+VCCP_GMCH6 +V1.05S4,9,24,47,55

C4E10

C4F2

C4F2 270uF

270uF

4.7uF

20%

10%

10% .

SMC0805

.

SMC0805

SMC7343

R4F2 0

+V1.05M_AXF_R

SMR1210

1 2

1uH

30%

30% SML0805

SML0805

C4D1

C4D1 10uF

10uF

20%

.

SMC0805

.

SMC0805

L5E1

1 2

0.10uH

20%

C5E15

C5E15 22uF

22uF

SML0805

20%

.

SMC0805

.

SMC0805

.

+

+VCC_PEG7

To use seperate filters for VCC_PEG & VCC_DMI rails No-Stuff R5E1 and stuff L5D1 ,C5C9 & R5D7

NO_STUFF

+

C5C9

+

C5C9 220uF

220uF

10%

SMC7343

L4D1

+V_TXLVDS_PM

C6E11

C6E11 220uF

220uF

10%

SMC7343

R4F5

1 2

+V1.8_SM_CK_RR

R5E3 0

1 2

SMR1210

SMR1210FB4F1

L5D1

91nH

20%

20% SML1210-STD

SML1210-STD NO_STUFF

NO_STUFF

2

0.002

R4F4

0.002

.

+V1.8_LDO46

R5F3

0.002

NO_STUFF

1 2

+V1.05M_PEG_LR

+V1.05M_DMI_LR

10 58Tuesday, August 28, 2007

1

+V1.25S_1.05M_CANTIGA7,9

R4D1

1 2

R5F4

1 2

0.002

Intel Confidential

1

+V1.8_GMCH7,9

0.002

+V1.89,13,14,46,48,55,57

R6E3

1 2

.

NO_STUFF

R6E2

1 2

0.002

R5D7

0.002

NO_STUFF

+V1.05S4,9,24,47,55

1.0

+V1.05M9,15,35,47,55

5

U5E1I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

VSS_9

AB47

BD46

BA46 AY46

AV46 AR46 AM46

BF44 AH44 AD44

AA44

M44

BC43

AV43 AU43 AM43

C43

BG42

AY42

AT42 AN42

AJ42

AE42

N42

BD41 AU41 AM41 AH41 AD41

AA41

U41

M41 G41

BG40

BB40

AV40 AN40

H40

AT39 AM39

AJ39

AE39

N39

BH38 BC38

BA38 AU38 AH38 AD38

AA38

U38

C38 BF37 BB37

AW37

AT37

AN37

AJ37

H37

C37

BG36 BD36

AK15

AU36

Y47 T47 N47 L47 G47

V46 R46 P46 H46 F46

Y44 U44 T44

F44

L42

Y41

T41

B41

E40

L39 B39

Y38

T38

F38

J43

J38

VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

CANTIGA_1p2

VSS

D D

C C

B B

A A

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23

5

4

U5E1J

BG21

AW21

AU21 AP21 AN21 AH21 AF21 AB21

BC20 BA20

AW20

AT20

AJ20

AG20

BG19

BG17

BC17

AW17

AT17

BA16

AU16 AN16

BG15

AC15

W15

BG14

AA14

BG13

BC13 BA13

AN13

AJ13

AE13

BF12 AV12 AT12

AM12

AA12

BD11 BB11 AY11 AN11 AH11

BG10

AV10 AT10

AJ10 AE10 AA10

AM9

R21 M21

G21

Y20 N20 K20 F20 C20 A20

A18

R17 M17 H17 C17

N16 K16 G16 E16

A15

C14

N13

G13 E13

A12

Y11 N11 G11 C11

M10 BF9 BC9 AN9

AD9

BH8 BB8 AV8 AT8

L12

J21

L13

J12

G9 B9

CANTIGA_1p2

VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233

VSS_235

VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252

VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273

VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296

VSS

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

VSS NCTF

VSS_NCTF_15 VSS_NCTF_16

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4

VSS_SCB_6

VSS SCB

NC

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

VSS_351 VSS_352 VSS_353 VSS_354 VSS_355

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 NC_43

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29 AJ6

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1

A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48 A47

4

MCH_VSS_351 MCH_VSS_352 MCH_VSS_353 MCH_VSS_354 MCH_VSS_355

3

R4T4 0R4T4 0 R5T12 0R5T12 0 R4T5 0R4T5 0 R5T13 0R5T13 0 R4R13 0

R4R13 0

.

23,40,43,44,46,47,49,55,57

PM_SLP_S3#

2

+V5S 5,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57

R3R9

R3R9 10K

10K

5%

U3D1 SC1563U3D1 SC1563

5

C3D2

1.0uF

10%

3

Q3D1

Q3D1 BSS138

1

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

BSS138

2

CANTIGA (6 OF 6)

355659

IN

1

SHDN

GND2ADJ

PM_SLP_S3_SHDN2

R3R11

R3R11 100

100

5%

5% NO_STUFF

NO_STUFF

2

4

OUT

3

TVDAC_ADJ2

V3.3S_TVDAC_R2

R3R7

17.8K

1%

R3R10

R3R10 10K

10K

1%

C3D1

C3D1 22uF

22uF

C3R1

0.1uF

10%

.

R3D2

0.011%

1

+V1.5S4,10,24,28,47,55,57

11 58Tuesday, August 28, 2007

1

CR3R2

CR3R2 BAT54

BAT54

NO_STUFF

3

V1_5SFOLLOW

12

R3R8

R3R8 10

10

5%

5% NO_STUFF

NO_STUFF

+V3.3S_TVDAC10,48,55

Intel Confidential

1.0

5

Layout Note: Location of all MCH_CFG strap resistors needs to be close to trace to minimize stub

MCH_CFG_57

DMI X2 Select

MCH_CFG_5

D D

Low = DMIx2 High = DMIx4 (default)

R1T11

2.21K

1%

1% NO_STUFF

NO_STUFF

4

MCH_CFG_77

MCH_CFG_7 ME TLS Confidentiality (Isolation Bypass Enable)

Low = AMT Firmware will use TLS cipher suite with no confidentiality (Isolators are bypassed] High = AMT Firmware will use TLS cipher suite with Confidentiality {Isolators are active (Default)}

R1T9

2.21K

1%

1% NO_STUFF

NO_STUFF

3

Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe

MCH_CFG_20 Low = Only Digital Display Port (SDVO/DP/iHDMI) or

PCIE or is operational (Default) High = Digital Display Port (SDVO/DP/iHDMI) and PCIE are operating simultaneously via PEG port

2

+V3.3S5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R5P7

4.02K

1%

1% NO_STUFF

NO_STUFF

MCH_CFG_207,19

1

GMCH Fan Power Control

MCH_CFG_167

FSB Dynamic ODT

MCH_CFG_16

C C

PCI Express Graphics Lane

MCH_CFG_9 Low = Reverse Lane (default)

Low = Dynamic ODT Disabled High = Dynamic ODT Enabled (default)

MCH_CFG_97

High = Normal operation

+V3.3S

R1E1

2.21K

1%

1% NO_STUFF

NO_STUFF

R1U4

2.21K

1%

1% .

.

MCH_PWM_FAN40,43

MCH_CFG_67

stuff J1C3 to enable ITPM

MCH_CFG_6 (iTPM Host Interface) Low = iTPM Host Interface is enabled High = iTPM Host Interface is Disabled (default)

R4P2

R4P2 15K

15K

1%

1% .

.

R1T7

2.21K

1%

1% .

.

MCH_CFG_6_R

12

J1C3J1C3

C3P4

0.1uF

10%

.

OPA567_POSIN_R

C4C19

C4C19 1uF

1uF

10%

+V5S5,11,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57

C3C13

4.7uF

10%

10% .

.

1

101112

EU4C1

V+

_

8

OPA567

9

+

V-

456

.

TF

IS

HS

13

2

EN

OUT

IF

3

.

7

OPA567_ISIN_MCH_R

OPA567_NEGIN_R

R4P1

R4P1 20K

20K

5%

MCH_TACHO_OP_FAN

CR3P1

CR3P1 BAT54

BAT54

R3P2

1.74K

1%

R4C25

3.32K

1%

2

11332

MCH_TACHO_R_FAN

J3C2

3

1

CONN3_HDR

R3P4

R3P4 0

0

.

+V3.3S5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R3P3

R3P3 1K

1K

1%

1% .

.

MCH_TACHO_FAN 40,43

DMI Lane Reversal

MCH_CFG_19

B B

Low = Normal (default) High = Lanes Reversed

MCH_CFG_107

MCH_CFG_127

MCH_CFG_137

MCH_CFG_197

R1T12

2.21K

1%

1% NO_STUFF

NO_STUFF

R5F11

4.02K

1%

1% NO_STUFF

NO_STUFF

R1T15

2.21K

1%

1% NO_STUFF

NO_STUFF

R1T17

2.21K

1%

1% NO_STUFF

NO_STUFF

1

2N3904

7481_D1P_Q

7481_D1N_Q

3

Q3C3

2

Place in IMVP_6 Hot Spot

Design Note: Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time

R3B16

R3B16 0

0

.

R3B18

R3B18 0

0

.

C3N9

C3N9 1000pF

1000pF

10%

+V3.3S5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

C3B7

R3B20

R3B20 10K

10K

1%

NO_STUFF

7481_D1P 7481_D1N

C3B7

0.1uF

20%

U3B2

1

VDD

2

D1+

3

D1-

ALRT#/THM2#

4

THM#

5

GND

ADT7481ARMZ-1 TEMP MON

Place ADT7481 near Air inlet not under SODIMM

SCLK

SDATA

D2+

10 9 8 7 6

D2-

7481_THRM#

A A

XOR / ALLZ / Clock Un-gating

MCH_CFG_13 MCH_CFG_12 Configuration

0 1 0 1

MCH_CFG_10 (PCIE Loopback enable) Low = Enabled High = Disabled (Default)

5

4

Reserved

0

XOR Mode Enabled

0

All-Z Mode Enabled

1

Normal Operation (Default)

1

3

IMVP6 & Amb Thermal sensors

+V3.3S5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R3B21

R3B21 10K

10K

1%

NO_STUFF

SMB_THRM_CLK 5,40,43

7481_D2P 7481_D2P_Q

7481_D2N

Title

Size Document Number Rev

Date: Sheet of

SMB_THRM_DATA 5,40,43

C3N8

C3N8 1000pF

1000pF

10%

Pillar Rock

CANTIGA STRAPPING

355659

A

355659

A

355659

A

R3B15

R3B15 0

0

.

R3B17

R3B17 0

0

.

7481_D2N_Q

2

7481_THRM2#

3

Q3B1

1

2N3904

2

Spare sensor, For Amb. temp sensor

R3N24

NO_STUFF

0

R3N23

R3N23 0

0

12 58Tuesday, August 28, 2007

1

Intel Confidential

PM_THRM# 5,23,40,43

1.0

5

4

3

2

1

D D

M_A_A[14:0]8,15

M_A_BS28,15

M_A_BS08,15 M_A_BS18,15 M_CS#07,15 M_CS#17,15

R3C6

R3C6 10K

10K

5%

5% .

.

M_CLK_DDR07 M_CLK_DDR#07 M_CLK_DDR17 M_CLK_DDR#17 M_CKE07,15 M_CKE17,15 M_A_CAS#8,15 M_A_RAS#8,15 M_A_WE#8,15

SMB_CLK_M214,15,23 SMB_DATA_M214,15,23

M_ODT07,15 M_ODT17,15 M_A_DM[7:0]8

M_A_DQS[7:0]8

M_A_DQS#[7:0]8

C C

Note: SO-DIMM0 SPD Address is 0xA0 SO-DIMM0 TS Address is 0x30

R3C5

R3C5 10K

10K

5%

5% .

.

B B

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

SA0_DIM0 SA1_DIM0

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

J5P1A CON200_DDR2-SODIMM-STANJ5P1A CON200_DDR2-SODIMM-STAN

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

110

S0#

115

S1#

30

CK0

32

CK0#

164

CK1

166

CK1#

79

CKE0

80

CKE1

113

CAS#

108

RAS#

109

WE#

198

SA0

200

SA1

197

SCL

195

SDA

114

ODT0

119

ODT1

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

11

DQS#0

29

DQS#1

49

DQS#2

68

DQS#3

129

DQS#4

146

DQS#5

167

DQS#6

186

DQS#7

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

M_A_DQ0

5

M_A_DQ1

7

M_A_DQ2

17

M_A_DQ3

19

M_A_DQ4

4

M_A_DQ5

6

M_A_DQ6

14

M_A_DQ7

16

M_A_DQ8

23

M_A_DQ9

25

M_A_DQ10

35

M_A_DQ11

37

M_A_DQ12

20

M_A_DQ13

22

M_A_DQ14

36

M_A_DQ15

38

M_A_DQ16

43

M_A_DQ17

45

M_A_DQ18

55

M_A_DQ19

57

M_A_DQ20

44

M_A_DQ21

46

M_A_DQ22

56

M_A_DQ23

58

M_A_DQ24

61

M_A_DQ25

63

M_A_DQ26

73

M_A_DQ27

75

M_A_DQ28

62

M_A_DQ29

64

M_A_DQ30

74

M_A_DQ31

76

M_A_DQ32

123

M_A_DQ33

125

M_A_DQ34

135

M_A_DQ35

137

M_A_DQ36

124

M_A_DQ37

126

M_A_DQ38

134

M_A_DQ39

136

M_A_DQ40

141

M_A_DQ41

143

M_A_DQ42

151

M_A_DQ43

153

M_A_DQ44

140

M_A_DQ45

142

M_A_DQ46

152

M_A_DQ47

154

M_A_DQ48

157

M_A_DQ49

159

M_A_DQ50

173

M_A_DQ51

175

M_A_DQ52

158

M_A_DQ53

160

M_A_DQ54

174

M_A_DQ55

176

M_A_DQ56

179

M_A_DQ57

181

M_A_DQ58

189

M_A_DQ59

191

M_A_DQ60

180

M_A_DQ61

182

M_A_DQ62

192

M_A_DQ63

194

M_A_DQ[63:0] 8

+V3.3M14,15,23,35,55,57

To connect TS on DIMM0&1 o/p to H8, stuff R5P3 and no-stuff R5P1

+V3.3S

PM_EXTTS#0_DIMM0_115,40

Layout Note: Place these Caps near SO-DIMM0.

+V1.89,10,14,46,48,55,57

R5C3 0.002

R4C1 0.022R4C1 0.022

TS#_DIMM0_17,14

R5P1 10KR5P1 10K

M_VREF_DIMM048

+V1.8_DIMM0

C4C8

0.1uF

10%

.

Layout Note: Place these Caps near SO-DIMM0.

1%

C5C1

C5C1 330uF

330uF

20%

2.5V

C4C9

0.1uF

10%

.

C4C13

2.2uF

10%

.

C4C10

0.1uF

10%

.

+V3.3M_DIMM0

C3C7

0.1uF

10%

.

C6P2

0.1uF

10%

.

C5C5

0.1uF

10%

.

C5C3

2.2uF

10%

.

R5P3

0NO_STUFF

C4C12

2.2uF

10%

.

C4C7

2.2uF

10%

10% .

.

C6P1

2.2uF

10%

10% .

.

C5C4

2.2uF

10%

.

+V1.8_DIMM0

C4C11

2.2uF

10%

.

J5P1B CON200_DDR2-SODIMM-STANJ5P1B CON200_DDR2-SODIMM-STAN

112

VDD1

111

VDD2

117

VDD3

96

VDD4

95

VDD5

118

VDD6

81

VDD7

82

VDD8

87

VDD9

103

VDD10

88

VDD11

104

VDD12

199

VDDSPD

83

NC1

120

NC2

50

EVENT#

69

NC4

163

NCTEST

1

VREF

201

GND0

202

GND1

47

VSS1

133

VSS2

183

VSS3

77

VSS4

12

VSS5

48

VSS6

184

VSS7

78

VSS8

71

VSS9

72

VSS10

121

VSS11

122

VSS12

196

VSS13

193

VSS14

8

VSS15

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162

A A

5

4

3

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

DDR2 SODIMM 0

355659

A

355659

A

355659

A

2

13 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

5

4

3

2

1

D D

M_B_A[14:0]8,15

M_B_BS28,15

M_B_BS08,15 M_B_BS18,15 M_CS#27,15

M_CS#37,15 M_CLK_DDR37 M_CLK_DDR#37

R4B24

R4B24 10K

10K

5%

5% .

.

M_CLK_DDR47 M_CLK_DDR#47 M_CKE37,15 M_CKE47,15 M_B_CAS#8,15 M_B_RAS#8,15 M_B_WE#8,15

SMB_CLK_M213,15,23 SMB_DATA_M213,15,23

M_ODT27,15 M_ODT37,15 M_B_DM[7:0]8

M_B_DQS[7:0]8

M_B_DQS#[7:0]8

C C

Note: SO-DIMM1 SPD Address is 0xA4 SO-DIMM1 TS Address is 0x34

+V3.3M13,15,23,35,55,57

R3B23

R3B23 10K.5%

10K.5%

B B

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

SA0_DIM1 SA1_DIM1

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

J5N1A CON200_DDR2-SODIMM-REVJ5N1A CON200_DDR2-SODIMM-REV

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

110

S0#

115

S1#

30

CK0

32

CK0#

164

CK1

166

CK1#

79

CKE0

80

CKE1

113

CAS#

108

RAS#

109

WE#

198

SA0

200

SA1

197

SCL

195

SDA

114

ODT0

119

ODT1

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

11

DQS#0

29

DQS#1

49

DQS#2

68

DQS#3

129

DQS#4

146

DQS#5

167

DQS#6

186

DQS#7

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

M_B_DQ0

5

M_B_DQ1

7

M_B_DQ2

17

M_B_DQ3

19

M_B_DQ4

4

M_B_DQ5

6

M_B_DQ6

14

M_B_DQ7

16

M_B_DQ8

23

M_B_DQ9

25

M_B_DQ10

35

M_B_DQ11

37

M_B_DQ12

20

M_B_DQ13

22

M_B_DQ14

36

M_B_DQ15

38

M_B_DQ16

43

M_B_DQ17

45

M_B_DQ18

55

M_B_DQ19

57

M_B_DQ20

44

M_B_DQ21

46

M_B_DQ22

56

M_B_DQ23

58

M_B_DQ24

61

M_B_DQ25

63

M_B_DQ26

73

M_B_DQ27

75

M_B_DQ28

62

M_B_DQ29

64

M_B_DQ30

74

M_B_DQ31

76

M_B_DQ32

123

M_B_DQ33

125

M_B_DQ34

135

M_B_DQ35

137

M_B_DQ36

124

M_B_DQ37

126

M_B_DQ38

134

M_B_DQ39

136

M_B_DQ40

141

M_B_DQ41

143

M_B_DQ42

151

M_B_DQ43

153

M_B_DQ44

140

M_B_DQ45

142

M_B_DQ46

152

M_B_DQ47

154

M_B_DQ48

157

M_B_DQ49

159

M_B_DQ50

173

M_B_DQ51

175

M_B_DQ52

158

M_B_DQ53

160

M_B_DQ54

174

M_B_DQ55

176

M_B_DQ56

179

M_B_DQ57

181

M_B_DQ58

189

M_B_DQ59

191

M_B_DQ60

180

M_B_DQ61

182

M_B_DQ62

192

M_B_DQ63

194

M_B_DQ[63:0] 8

+V1.8_DIMM1

C4B20

C4B22

0.1uF

10%

.

Layout Note: Place these Caps near SO-DIMM1.

+V1.8_DIMM1

C5B4

2.2uF

10%

.

Layout Note: Place these Caps near SO-DIMM1.

C4B21

2.2uF

10%

.

0.1uF

10%

.

C4B18

2.2uF

10%

.

C4B19

0.1uF

10%

.

C5B6

2.2uF

10%

.

C4B23

0.1uF

10%

.

C4B17

2.2uF

10%

.

C5B5

C5B5 330uF

330uF

20%

+V3.3M13,15,23,35,55,57

R4B23 0.022R4B23 0.022

TS#_DIMM0_17,13

M_VREF_DIMM148

R5B6 0.002

1%

+V3.3M_DIMM1

C6N10

0.1uF

10%

.

+V1.89,10,13,46,48,55,57

C3B8

0.1uF

10%

.

C6N11

2.2uF

10%

.

+V1.8_DIMM1

C3B9

2.2uF

10%

.

J5N1B CON200_DDR2-SODIMM-REVJ5N1B CON200_DDR2-SODIMM-REV

112

VDD1

111

VDD2

117

VDD3

96

VDD4

95

VDD5

118

VDD6

81

VDD7

82

VDD8

87

VDD9

103

VDD10

88

VDD11

104

VDD12

199

VDDSPD

83

NC1

120

NC2

50

EVENT#

69

NC4

163

NCTEST

1

VREF

201

GND0

202

GND1

47

VSS1

133

VSS2

183

VSS3

77

VSS4

12

VSS5

48

VSS6

184

VSS7

78

VSS8

71

VSS9

72

VSS10

121

VSS11

122

VSS12

196

VSS13

193

VSS14

8

VSS15

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162

SO-DIMM1 is placed farther from the GMCH than SO-DIMM0

A A

5

4

3

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

DDR2 SODIMM 1

355659

A

355659

A

355659

A

2

14 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

5

4

3

2

1

Layout Note: Place Q5N2 under DIMM0

DDR_THERM1

2

Q5N2

1

2N3904

D D

2N3904

3

PM_EXTTS#1_R7

On Board DDR2 Thermal Sensor

+V3.3M 13,14,23,35,55,57

U5P1

1

DDR_THERM2

PM_EXTTS#1_D

R5P4

R5P4 0

0

.

VDD

2

D+

3

D-

THERM#4GND

ADM1032AR

Layout Note: Place U5P1 under DIMM1

SCLK

SDATA

ALERT#

8

7

PM_EXTTS#0_D

6

5

+V0.9 46,55

C4C3

0.1uF

10%

.

C5C6

0.1uF

10%

.

R5P6

R5P6 0

0

NO_STUFF

C4C15

0.1uF

10%

.

C4B29

0.1uF

10%

.

SMB_CLK_M2 13,14,23

SMB_DATA_M2 13,14,23

PM_EXTTS#0_DIMM0_1 13,40

Layout note: Place one cap close to every 2 pullup resistors terminated to +V0.9

C4B25

C4C5

0.1uF

10%

.

C4B15

0.1uF

10%

.

C4B25

0.1uF

10%

.

C4B28

0.1uF

10%

.

C4B16

0.1uF

10%

.

C4C18

0.1uF

10%

.

C4B12

0.1uF

10%

.

C4C17

0.1uF

10%

.

C4B26

0.1uF

10%

.

C4C16

0.1uF

10%

.

C4B27

0.1uF

10%

.

C5B3

0.1uF

10%

.

C4C1

0.1uF

10%

10% .

.

C4B24

0.1uF

10%

10% .

.

C4B14

0.1uF

10%

.

C4C2

0.1uF

10%

.

C4C6

0.1uF

10%

.

C5C2

0.1uF

10%

.

C4C4

0.1uF

10%

.

C4B9

0.1uF

10%

.

C4B11

0.1uF

10%

.

C4B10

0.1uF

10%

.

C4C14

0.1uF

10%

10% .

.

C C

Voltage Buffer Translator for MCH ME JTAG

+V3.3M13,14,23,35,55,57

R6M7

R6M4

1K

.

R6A2

GTL2005_JTAG_REF

.

MCH_TDI_R MCH_TCK_R

MCH_TMS_R

R6M4

2.37K

1%

.

R6A3

R6A3 806

806

1%

C6A1

0.1uF

20%

TP_GTL2005_JTAG_A3

GTL2005_JTAG_DIR1 ME_JTAG_TCK_BUFFER

NO_STUFF

U6M1

1

DIR

2

A0

3

A1

4

GTLREF

5

A2

6

A3 GND17GND2

GTL2005

+V3.3M13,14,23,35,55,57

+V1.05M9,10,35,47,55

MCH_RSVD_10 JTAG_TCK MCH_RSVD_11 JTAG_TDI MCH_RSVD_12 JTAG_TDO MCH_RSVD_13 JTAG_TMS

MCH_TDI7 MCH_TCK7

MCH_TMS7

B B

R6M8 100R6M8 100 R6M6 100R6M6 100

R6M2 100R6M2 100

1K

.

R6A6

R6A5

10K

.

R6A4

R6A4 10K

10K

VCC

GND3

B0 B1

B2 B3

+V3.3M13,14,23,35,55,57

C6M7

0.1uF

20%

14 13 12 11 10 9 8

10K

R6M9

R6M5

GTL2005_JTAG_B3

R6A19

R6A18

10K

10K NO_STUFF

5%

10K

NO_STUFF

R6M3

ME_JTAG_TDI_BUFFER ME_JTAG_TCK_BUFFER

ME_JTAG_TMS_BUFFER

R6A17

10K

5%

R6M1

R6M1 1K

1K

5%

5% .

.

ME_JTAG_TMS_BUFFER

ME_JTAG_TDI_BUFFER

ME_JTAG_TDO_BUFFER

J5A2

1 2 3 4 5 6

RJ-11_JACK_Vertical-Mount

.

+V0.9 46,55

R5C1 56R5C1 56 R5C4 56R5C4 56 R5B4 56R5B4 56 R5B7 56R5B7 56

R4C22 56R4C22 56 R4C12 56R4C12 56 R4B34 56R4B34 56 R4B22 56R4B22 56

R4C13 56R4C13 56 R4C20 56R4C20 56 R5C2 56R5C2 56

R4C9 56R4C9 56 R4C10 56R4C10 56 R4C21 56R4C21 56

R4B14 56R4B14 56 R4B31 56R4B31 56 R5B5 56R5B5 56

R4B15 56R4B15 56 R4B21 56R4B21 56 R4B32 56R4B32 56

R4C23 56R4C23 56 R4C11 56R4C11 56 R4B33 56R4B33 56 R4B16 56R4B16 56

R4C19 56R4C19 56 R4C7 56R4C7 56 R4C18 56R4C18 56 R4C6 56R4C6 56 R4C17 56R4C17 56 R4C4 56R4C4 56 R4C16 56R4C16 56 R4C15 56R4C15 56 R4C5 56R4C5 56 R4C2 56R4C2 56 R4C8 56R4C8 56 R4C14 56R4C14 56 R4C3 56R4C3 56 R4C24 56R4C24 56 R5C5 56R5C5 56

R4B30 56R4B30 56 R4B13 56R4B13 56 R4B28 56R4B28 56 R4B19 56R4B19 56 R4B29 56R4B29 56 R4B11 56R4B11 56 R4B27 56R4B27 56 R4B26 56R4B26 56 R4B12 56R4B12 56 R4B17 56R4B17 56 R4B20 56R4B20 56 R4B25 56R4B25 56 R4B18 56R4B18 56 R4B35 56R4B35 56 R5B8 56R5B8 56

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

M_A_A14

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11

M_B_A12 M_B_A13 M_B_A14

M_CKE0 7,13 M_CKE1 7,13 M_CKE3 7,14 M_CKE4 7,14

M_ODT0 7,13 M_ODT1 7,13 M_ODT2 7,14 M_ODT3 7,14

M_A_BS0 8,13 M_A_BS1 8,13 M_A_BS2 8,13

M_A_WE# 8,13 M_A_CAS# 8,13 M_A_RAS# 8,13

M_B_BS0 8,14 M_B_BS1 8,14 M_B_BS2 8,14

M_B_WE# 8,14 M_B_CAS# 8,14 M_B_RAS# 8,14

M_CS#0 7,13 M_CS#1 7,13 M_CS#2 7,14 M_CS#3 7,14

M_A_A[14:0] 8,13

M_B_A[14:0] 8,14

VCC

GND3

B0 B1

B2 B3

+V3.3M13,14,23,35,55,57

C6M2

0.1uF

20%

14

ME_JTAG_TDO_BUFFER_R

13

TP_GTL2005_JTAG_B1

12 11

TP_GTL2005_JTAG_B2

10

TP_GTL2005_JTAG_B3

9 8

R6M11 22R6M11 22

3

R6M12

R6M12 10K

10K

NO_STUFF

ME_JTAG_TDO_BUFFER

C6M6

C6M6 220PF

220PF

Intel Confidential

15 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

DDR2 TERMINATION, THERMAL SENSOR AND ME JTAG

355659

A

355659

A

355659

A

2

R6A13

R6A13 10K

5%

.

R6A11 1K

R6A9 1K

10K

NO_STUFF

GTL2005_JTAG_DIR2

R6A12

R6A12 10K

10K

.

GTL2005_JTAG_A2

GTL2005_JTAG_A3

5%

.

R6A7 1K

U6M2

1

DIR

2

A0

3

A1

4

GTLREF

5

A2

6

A3 GND17GND2

GTL2005

4

R6A8

3.24K

1%

1% .

.

GTL2005_JTAG_REF2

R6M10

C6M5

1K

0.1uF

5%

5% .

.

MCH_TDO7

GTL2005_JTAG_A1

A A

R6A10 22.1KR6A10 22.1K

5

+V3.3S

4

+V3.3S5,7,10,12,13,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

U2M2

8

VP

C2N3

0.1uF

20%

3

2

1

R6T5

R6T5 10K

+V3.3S

1 4 9 19

24 22 18 17 14

CRT_Q_RED

23

CRT_Q_GREEN

21

CRT_Q_BLUE

16

CRT_Q_VSYNC

15

CRT_Q_HSYNC

13

10K

NO_STUFF

R6T4

R6T4 1K

1K

NO_STUFF

D D

DOCK_CRT_EN#_R

R6T3

C6T6

0.1uF

20%

R6T3 0

0

.

12

11

10 20

C6T7

0.1uF

20%

2 5 6 8

3 7

U6E4

SEL

Y_A Y_B Y_C Y_D Y_E

GND1 GND2 GND3 GND4

PI3V512QE

VDD1 VDD2 VDD3 VDD4

I_A0 I_B0 I_C0 I_D0 I_E0

I_A1 I_B1 I_C1 I_D1 I_E1

DOCK_CRT_EN#41

DOCK_CRT_EN#_R

C C

CRT_RED7 CRT_GREEN7 CRT_BLUE7 CRT_VSYNC7 CRT_HSYNC7

+V3.3S

C6T5

C6E9

0.1uF

20%

B B

DOCK_CRT_EN#_R CRT_EN#

+V3.3S

R6T1

2.2K

CRT_DDC_DATA_MCH7

CRT_DDC_DATA_DOCK44

+V3.3S

A A

CRT_DDC_CLK_MCH7

CRT_DDC_CLK_DOCK44

R6T2

2.2K

5

CRT_L2_RED CRT_L2_BLUE CRT_L2_GREEN CRT_Q_HSYNC

CRT_RED_DOCK 44 CRT_GRN_DOCK 44 CRT_BLUE_DOCK 44 CRT_VSYNC_DOCK 44 CRT_HSYNC_DOCK 44

5

U6T1

2 4

INVERTER

3

U6E1

1

1OE#

VCC

2

1A

2OE#

3

1B

2B

4

GND

2A

SN74CBTD3306C

U6E3

1

1OE#

VCC

2

1A

2OE#

3

1B

2B

4

GND

2A

SN74CBTD3306C

4

1 2 3 4

+V3.3S5,7,10,12,13,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

8 7 6 5

I/O1 I/O2 I/O3 I/O4

ESD DIODE ARRAY

C6T3

0.1uF

20%

CRT_DDC_DATA_ISO

CRT_DDC_CLK_ISO

10

I/O8

9

I/O7

7

I/O6 I/O5

VN

5

Note: For video bandwidths > 200MHz: C3B1, C3A4, C2B1, C2A5, C2B2, C2N1 = 3.3pF C3M3, C2A4, C2A6 = No_Stuff FB3A1, FB2A4, FB2B1 = Short

+V5S5,11,12,17,18,24,28,30,31,32,39,48,49,52,55,56,57

C6T2

0.1uF

20%

+V5S5,11,12,17,18,24,28,30,31,32,39,48,49,52,55,56,57

C6T4

0.1uF

20%

3

6

CRT_Q_VSYNC

+V5S5,11,12,17,18,24,28,30,31,32,39,48,49,52,55,56,57

+VBATS19,27,30,31,55,57 +V5S_F_DAC

R2N11KR2N1 1K

DDC_GATE

R2N2

R2N2 100K

100K

.

CRT_DDC_DATA_ISO

CRT_DDC_CLK_ISO

FB3B1

CRT_Q_RED

R3B1

R3B1 150

150

1%

CRT_Q_GREEN CRT_L2_GREEN

CRT_Q_BLUE

CRT_Q_VSYNC

CRT_Q_HSYNC

R3B2

R3B2 150

150

1%

R2B1

R2B1 150

150

1%

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

CRT

355659

A

355659

A

355659

A

C3B1

C3B1 10pF

10pF

5%

5% .

.

C2B1

C2B1 10pF

10pF

5%

5% .

.

C2B2

C2B2 10pF

10pF

5%

5% .

.

FB3B1

47ohm@100MHz

FB3B2

47ohm@100MHz

FB2B2

47ohm@100MHz

2

CRT_L_RED

CRT_L_GREEN

CRT_L_BLUE

C3A4

C3A4 22pF

22pF

5%

5% .

.

C2A5

C2A5 22pF

22pF

5%

5% .

.

C2N1

C2N1 22pF

22pF

5%

5% .

.

C3M4

C3M4 33pF

33pF

5%

5% NO_STUFF

NO_STUFF

2

1

3

DDC_SRC

R2M3

2.2K

FB3A1

47ohm@100MHz

FB2A4

47ohm@100MHz

FB2B1

47ohm@100MHz

C3M5

C3M5 33pF

33pF

5%

5% NO_STUFF

NO_STUFF

+

1 2

Q2A1

Q2A1 BSS138

BSS138

R2M4

2.2K

.

C3M3

C3M3 10pF

10pF

5%

5% .

.

C2A4

C2A4 10pF

10pF

5%

5% .

.

C2A6

C2A6 10pF

10pF

5%

5% .

.

F2A1

1.1A

CRT_L2_BLUE

CRT_L2_RED

FB2M1

FB2M1 50OHM

50OHM

+V5S_L_DAC

CR2N1

Clamping-Diode

GND1

GND1 RED

RED GND2

GND2 GRN

GRN GND3

GND3 BLU

BLU VCC

VCC NC1

NC1 GND4

GND4 GND5 CLK

GND5 CLK

Intel Confidential

16 58Tuesday, August 28, 2007

1

2 1

J2A2B

19 14 18 13 17 12 16 11 15 10 20

2IN1

CR2M1

2 1

Clamping-Diode

NC2

24

DATA

23

HSYNC

22

VSYNC

21

1.0

5

4

3

+V3.3S5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

2

1

+V5S5,11,12,16,18,24,28,30,31,32,39,48,49,52,55,56,57

R6U19

0.002

R6U20

0.002

1%

+V5S_LVDS_BKLT

0.002

1%

+VBAT49,53,55,56,57

R6F15

0.002

1%

+VCC_LVDS_BKLT+V3.3S_LVDS_DDC

D D

C6F6

C6U2

0.1uF

20%

C6F6

0.1uF

10%

+V5S_LVDS_BKLT

DBL_CLK

R6U18

R6U18 100K

100K

+VCC_LVDS_BKLT

17 58Tuesday, August 28, 2007

1

J6F1

1

VDD_BLI

2

VSS_BLI

3

VSS_DBC

4

VDD_DBC

5

DBL_CLK

6

DBL_DATA

7

ENA_BL

8

NC1

9

VDD_ALS

10

VSS_ALS

11

ALS_CLK

12

ALS_DATA

13

ALS_INTR

14

NC2

15

VSS_VDL

16

VDD_VDL1

17

VDD_VDL2

18

VDD_VCL

19

RSVD

20

VCL_CLK

21

VCL_DATA

22

A0M

23

A0P

24

VSS_SHIELD1

25

A1M

26

A1P

27

VSS_SHIELD2

28

A2M

29

A2P

30

VSS_SHIELD3

31

A3M

32

A3P

33

VSS_SHIELD4

34

VDL_CLKAM

35

VDL_CLKAP

36

VSS

37

B0M

38

B0P

39

VSS_SHIELD5

40

B1M

41

B1P

42

VSS_SHIELD6

43

B2M

44

B2P

45

VSS_SHIELD7

46

B3M

47

B3P

48

VSS_SHIELD8

49

VDL_CLKBM

50

VDL_CLKBP

LVDS,CONN50

Intel Confidential

1.0

C6U9

C6U10

0.1uF

20%

+V3.3S5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V5S5,11,12,16,18,24,28,30,31,32,39,48,49,52,55,56,57

C7T19

0.1uF

20%

U7E6

R6U26

0.002

U7E6

1

OE1#

2

1A

3

1B GND42A

74CBT3306

L_BRIGHTNESS

NO_STUFF

1 2

R6U281MR6U28 1M

R6U23 100KR6U23 100K

L_VDDEN#

3

Q6F2

Q6F2 BSS138

BSS138

2

0.002

VCC

OE2#

R6V4

8 7 6

2B

5

C6V1

C6V1 1000pF

1000pF

10%

LVDS Panel Backlight

C C

BIOS Note: Disable both BKLTSEL lines before enabling one.

For 2.5V panel support, connect an external source to net TP_+V2.5.

B B

+V3.3S

+VDD_VDL

+V3.3S (DEFAULT)

+V5S STUFF R6U26

TP_+V2.5 STUFF R6V4

A A

STRAPPING

STUFF R6V2 NO_STUFF R6U26, R6V4

NO_STUFF R6V2, R6V4

NO_STUFF R6V2, R6U26

LVDS_VDD_EN7

5

L_BKLTSEL0#38 L_BKLT_CTRL7

GMCH_PWM Support

R6V2 0.002

1%

+V5S5,11,12,16,18,24,28,30,31,32,39,48,49,52,55,56,57

12

NO_STUFF

+VDD_VDL

1

R6V1

R6V1 100K

100K

4

20%

L_BKLTSEL1# 38

GM_Data_D Support

LVDS_DDC_CLK7 LVDS_DDC_DATA7

TP_+V2.5

L_VDDEN_D#

TP6G1 NO_STUFFTP6G1 NO_STUFF

R7U2

R7U2 10K

10K

5%

L_CTRL_DATA 7,20

+V3.3S5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R6U25

2.2K

5%

Q6U3

SI2307DS

32

C6F5

C6F5 22UF

22UF

1

C6U1

0.1uF

20%

R6U24

2.2K

5%

L_CTRL_CLK7,20

+VDD_VDL_L

3

+V3.3S

R6U15

R6U15 10K

10K

5%

GM_CLK_D Support

+V3.3S5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

LVDS

355659

A

355659

A

355659

A

C6U9

0.1uF

20%

L_BKLTSEL1#

L_BKLT_EN7

ALS_CLK40 ALS_DATA40 ALS_INTR#40

LVDSA_DATA#07 LVDSA_DATA07

LVDSA_DATA#17 LVDSA_DATA17

LVDSA_DATA#27 LVDSA_DATA27

LVDSA_DATA#37 LVDSA_DATA37

LVDSA_CLK#7 LVDSA_CLK7

LVDSB_DATA#07 LVDSB_DATA07

LVDSB_DATA#17 LVDSB_DATA17

LVDSB_DATA#27 LVDSB_DATA27

LVDSB_DATA#37 LVDSB_DATA37

LVDSB_CLK#7 LVDSB_CLK7

2

U6F1

1

OE#

VCC

2

A

GND3Y

74CBTLV1G125

+V3.3S_LVDS_DDC

+V3.3S5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

5

4

+VDD_VDL_L

5

D D

+V3.3S5,7,10,12,13,16,17,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

U6B1

DOCK_TV_EN#41

TVA_DAC7

TVB_DAC7

TVC_DAC7

12

2 5 6 8

11

3

7 10 20

SEL

Y_A Y_B Y_C Y_D Y_E

GND1 GND2 GND3 GND4

PI3V512QE

VDD1 VDD2 VDD3 VDD4

I_A0 I_B0 I_C0 I_D0 I_E0

I_A1 I_B1 I_C1 I_D1 I_E1

1 4 9 19

24 22 18 17 14

DACA

23 21 16 15

DACC

13

4

TV_DACA_OUT_DOCK 44

TV_DACB_OUT_DOCK 44

TV_DACC_OUT_DOCK 44

DACA

3

Layout Note: Place 150 Ohm termination resistors, ferrite beads and capicators close to connector

FB2A2

12

150ohm@100MHz

C1A3

R1M2

5.6pF

150

8.9%

1%

.

FB2A1

DACBDACB

R2M2

R2M2 150

150

1%

12

C2A3

5.6pF

8.9%

.

FB2A1

150ohm@100MHz

DACA_L

12

C1A1

5.6pF

8.9%

8.9% .

.

DACB_L

12

C2A1

5.6pF

8.9%

8.9% .

.

DACA_L DACB_L DACC_L

2

U2M1

1

I/O1

2

I/O2

3

I/O3

4

I/O4

ESD DIODE ARRAY

Port Value

IO2 IO1 IO0

0 0 0b

0 0 Xb 0 1 0b 0 1 1b 0 1 Xb X 1 0b X 1 1b 1 0 0b 1 0 1b 1 1 0b 1 1 1b

Aspect Ratio

Format 525i (480) 525i (480)0 0 1b 525i (480) 525p (480) 525p (480) 525p (480) 750p (720) 0V 750p (720) 1125i (1080) 1125i (1080) 1125p (1080) 1125p (1080)

+V3.3S5,7,10,12,13,16,17,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

8

VP

VN

5

C2M1

0.1uF

20%

4:3

Letterbox

4:3 4:3 16:9 4:3

Letterbox 2.2V 4:3 16:9 4:3 16:9 4:3 16:9

10

I/O8

9

I/O7

7

I/O6

6

I/O5

1

Voltage

Line3

Line2

Line1

0V

0V 0V16:9 0V 0V 0V 0V

2.2V

2.2V 5V 5V 5V 5V

Note: ESD Diode Array for the TV DAC A, DAC B, DAC C signals located on CRT page.

0V

5V

2.2V

0V

5V

5V 5V 5V

5V

5V 0V

0V

5V 0V

5V 5V

5V

+V3.3S

C C

C6N8

0.1uF

20%

B B

A A

C6N6

0.1uF

20%

C6N4

C6N5

0.1uF

20%

TV_DCONSEL1_LVL TV_DCONSEL0_LVL

+V3.3S

R6D7

2.2K

5%

TV_DCONSEL1_MCH7

TV_DCONSEL1_DOCK44

+V3.3S

R6D5

2.2K

5%

TV_DCONSEL0_MCH7

TV_DCONSEL0_DOCK44

5

DOCK_TV_EN#

4

I2C_RST#

+V3.3S5,7,10,12,13,16,17,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

5

2 4

3

U6D2

1

1OE#

2

1A

3

1B

4

GND

SN74CBTD3306C

U6D1

1

1OE#

2

1A

3

1B

4

GND

SN74CBTD3306C

2OE#

DACC DACC_L

R1M1

R1M1 150

150

1%

+V5S5,11,12,16,17,24,28,30,31,32,39,48,49,52,55,56,57

C2A2

1.0uF

R2A6

R2A6 10K

10K

1%

U6R1

INVERTER

VCC

2B 2A

VCC

2OE#

2B 2A

1.0uF

10%

U2A1

10

9 8 7 6

C6T1

0.1uF

20%

8 7 6 5

VDD SDA SCL INT# RESET#

I2C - PCA9537

TV_EN#

IO_0 IO_1 IO_2 IO_3

VSS

.

R6D6

2.2K

5%

TV_DCONSEL1_LVL

.

R6D4

2.2K

5%

TV_DCONSEL0_LVL

12

C1A4

5.6pF

8.9%

.

1 2 3 4 5

+V5S

FB1A1

150ohm@100MHz

12

DLINE3_IO DLINE2_IO DLINE1_IO

C6R1

0.1uF

20%

C6D8

0.1uF

20%

3

C1A2

5.6pF

8.9%

8.9% .

.

R2A1

5.90K

J2A1

1 2 3 4 5 6 7

CON14_DCONN-CP4120

R2A7

5.90K

CON14_DCONN-CP4120

R2A5

R2A3

4.7K

+V5S5,11,12,16,17,24,28,30,31,32,39,48,49,52,55,56,57

8 9 10 11 12 13 14

R2A2 10KR2A2 10K R2A4 10KR2A4 10K R2M1 10KR2M1 10K

DLINE3 DLINE2 DLINE1

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

TV

355659

Note: Pins 12 & 14 are shorted inside D-Connector plug.

+V5S5,11,12,16,17,24,28,30,31,32,39,48,49,52,55,56,57

U2A2

1

I/O1

2

I/O2

3

I/O3

4

I/O4

ESD DIODE ARRAY

TV-OUT DAC Channel Definition

Channel A (DACA) Channel B(DACB) Luminance (Y) Channel C (DACC)

Composite Video S-Video Component Video CVBS Signal

X

Chrominance (C)

2

C2M2

0.1uF

20%

8

VP

10

I/O8

9

I/O7

7

I/O6

6

I/O5

VN

5

X

Chrominance (Pb) Luminance (Y)X Chrominance (Pr)

18 58Tuesday, August 28, 2007

1

Intel Confidential

DLINE1_IO DLINE2_IO DLINE3_IO

1.0

Intel PILLAR ROCK Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual