Intel PILLAR ROCK Schematic

5

4

3

2

1

PILLAR ROCK

Table of Contents

Page Description

1

D D

C C

B B

TITLE PAGE

2

NOTES

3

Penryn (1 of 2)

4

Penryn (2 of 2)

5

CPU Thermal Sensor

6

CANTIGA (1 OF 6)

7

CANTIGA (2 OF 6)

8

CANTIGA (3 OF 6)

9

CANTIGA (4 OF 6)

10

CANTIGA (5 OF 6)

11

CANTIGA (6 OF 6)

12

CANTIGA STRAP & CAMARILLO

13

DDR2 SODIMM 0

14

DDR2 SODIMM 1

15

DDR2 TERMINATION

16

CRT

17

LVDS

18

TVO

19

PCIE GRAPHICS

20

XDP

21

ICH9M (1 of 4)

22

ICH9M (2 of 4)

23

ICH9M (3 of 4)

24

ICH9M (4 of 4)

25

PCI-E Slots (1 & 2)

26

PCI-E Slots (3,4 & 5)

27

High Definition Audio

28

HDA Power Supply

29

USB 1.1/2.0

30

SATA (1 of 3)

31

SATA (2 and 3 of 3)

32

PCI Edge Connector(Gold finger)

33

LAN Boaz

34

LAN Docking and SPI

35

CK505

36

DB800 & Buffers

37

FWH and I/O Port Expander

38

SIO

39

Legacy Support

40

H8 2116 KBC(1 of 2)

41

H8 2116 KBC(2 of 2)

42

PS2

43

LPC Slot, TPM Header,

44

DOCKING

45

TPS51120 SYSTEM POWER VR

46

DDR2 VR

47

CANTIGA VR

48

DDR VREF

49

GRAPHICS CORE VR

50

SYSTEM CHARGER VR

51

SYSTEM CHARGER BATTERY

52

IMVP-6 CONTROLLER

53

IMVP-6 DRIVERS&FETS

54

CPU Decoupling

55

DISCHARGE CIRCUITS

56

Start Up Sequence

57

Sleep control

58

POWER SEQUENCING

Montevina Mobile Platform CUSTOMER REFERENCE BOARD

Merom

Fab 3

Rev. 1.0

A A

5

4

3

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

A

TITLE PAGE

355659

2

1 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

5

4

3

2

1

MONTEVINA CUSTOMER REFERENCE PLATFORM

SCHEMATIC ANNOTATIONS AND BOARD INFORMATION

D D

2

Voltage Rails

+VBATA +VBAT +VBATS +V12S

-V12A

-V12S +V5A +V5 +V5S +V3.3A +V3.3M +V3.3M_CK505 +V3.3 +V3.3S +V1.8 +V1.5S +V1.05M +V1.05S +V0.9 +VCC_CORE +VCC_GFXCORE

VOLTAGE DESCRIPTIONACTIVE INPOWER PLANE

6V-14.1V 6V-14.1V 6V-14.1V 12V

-12V

-12V 5V 5V 5V

3.3V

1.8V

1.5V

1.05V

0.9V

0.35V-1.5V

0.7V-1.25V

S0/M0, (S3-S5)/M1, (S3-S5)/M-off S0/M0, (S3-S5)/M1, (S3-S5)/M-off S0/M0 S0/M0 S0/M0, (S3-S5)/M1, (S3-S5)/M-off S0/M0 S0/M0, (S3-S5)/M1, (S3-S5)/M-off S0/M0, S3/M1, S3/M-off S0/M0 S0/M0, (S3-S5)/M1, (S3-S5)/M-off S0/M0, (S3-S5)/M1, S3/(M-off w/WOL_EN) S0/M0, (S3-S5)/M1 S0/M0, S3/M1, S3/M-off S0/M0 S0/M0, (S3-S5)/M1, S3/M-off S0/M0 S0/M0, (S3-S5)/M1 S0/M0 S0/M0, (S3-S5)/M1, S3/M-off S0/M0 S0/M0

Battery Rail in Mobile Power Mode Battery Rail in Mobile Power Mode Battery Rail in Mobile Power Mode Only on in DT Power Mode Only on in DT Power Mode Only on in DT Power Mode

LAN Clock, MCH

DDR core

GMCH, ICH core, and FSB rail DDR command & control pull up. CPU core rail GMCH Graphics core rail

I C / SMB Addresses

Clock Generator DB800 Clock Buffer SO-DIMM0 SO-DIMM1 SO-DIMM0 Thermal Sensor SO-DIMM1 Thermal Sensor DDR Thermal Sensor I2C Bus Expander Ambient Lighr Sensor EMA Display CPU Thermal Sensor IMVP6 Amb. Temp. Sensor Battery A Battery B Board ID Port Expander Docking Port Expander Skin Temperature Sensor H8 PCI-Slot3 PCI-Gold Finger PCI-Express Slot1-5 Docking PCIe x16 Slot (PEG) TPM Header ITP-XDP

AddressDevice 1101 001x 1101 110x 1010 000x 1010 010x 0011 000x 0011 010x 0100 110x 0011 xxxx 0111 001x 0011 110x 1001 100x 1001 101x 0001 110x 0001 111x 0011 000x 0011 001x 1001 100x TBD TBD TBD TBD TBD TBD TBD TBD

BusHex PageJumper DescriptionDefault

D2

SMB_ICH_M3

DC

SMB_ICH_M3

A0

SMB_ICH_M2

A4

SMB_ICH_M2

30

SMB_ICH_M2

34

SMB_ICH_M2

4C

SMB_ICH_M2

3x

SMB_ICH

72

ALS

3C

EMA

98

SMB_THRM

9A

SMB_THRM

1C

SMB_BS

1E

SMB_BS

30

SMB_BS

32

SMB_BS

98

SMB_BS

TBD

SMB_ME

TBD

SMB_ICH_A1

TBD

SMB_ICH_A1

TBD

SMB_ICH_A1

TBD

SMB_ICH_A1

TBD

SMB_ICH_S4

TBD

SMB_ICH_S4

TBD

SMB_ICH_S4

C C

Buses labeled SMB_ICH_xx come out of ICH, via an I2C expander. The rest come out of EC.

Jumper / Switch Settings

J1G1 J1G3 J1G5 J2B2 J2G1 J2H2 J3C1 J3J2 J4H1 J4J2 J5G1 J5H2 J7A1 J7E1 J7H1 J7H2 J8B1 J8B2 J8C1 J8F2 J8G1 J8G3 J8G4 J8G5 J8G6 J8H1 J9C1 J9D1 J9F1 J9G2 J9H1 J9H2 J9H3 J9H4

BSEL2

1-2

BSEL1

1-2

BSEL0

1-2

CPU CORE VID

All OPEN

Force Shutdown

1-X

GFX CORE VID

All OPEN

CPU thermal sensor

1-2, 3-4

Power ON Latch

1-X

No ME G3 to M1 support

1-X

SATA Power Enable

1-2

SRTC RST

1-X

CMOS Clear

1-X

In-circuit SMC Programming

1-2

SIO Reset

1-2

SATA interlock switch for port0

1-2

TPM PHYSICAL PRESENCE

1-X

PM Lan enable

1-2

In-circuit SMC Programming

1-2

SELCETING SPI0 or SPI1 TO BE PROGRAMMED

1-X

BIOS recovery

1-X

SV Setup

1-X

SMC MD2

1-X

CRB/SV Detect

1-X

SMC MD1

1-2

KBC disable

1-X

Boot BIOS Strap

1-2

PROGRAMMING SPI1

1-X

PROGRAMMING SPI0

1-X

KSC Enable

1-2

Boot Block Programming

1-2

NMI

1-X

SATA interlock switch for port1

1-2

LID Position

1-X

Virtual Battery

1-X

35 35 35 52 56 49 5 56 56 31 21 21 39 38 30 23 40 39 34 23 63 40 64 40 40 31 34 34 40 42 42 31 41 41

PCI Devices

Device

LAN

IDSEL # AD18 D, C, A, BSlot 3

(AD24 internal)

REQ/GNT # 2 2

Interrupts

Net Naming Conventions

Suffix # = Active Low Signal

Prefix H = Host M = DDR Memory TP = Test Point (does not connect anywhere else)

B B

Power States

S0 (Full on)/M0

S3 (Suspend to RAM)/M1

S3 (Suspend to RAM)/Moff

S3 (Suspend to RAM)/Moff w/WOL_EN

S4 (Suspend to Disk)/M1

S5 (Soft Off)/M1

S4 (Suspend to Disk)/Moff

S5 (Soft Off)/Moff

SLP_S3# HIGH

LOW

S4_STATE# HIGH

HIGH

LOW

SLP_S4# HIGH

HIGH

LOW

SLP_S5# HIGH

HIGH

LOW

HIGH

LOW

SLP_M# HIGH

HIGH

LOW

HIGH

LOW

+V*A ON

ON

+V3.3M_WOL ON

ON

OFF

ON

OFF

+V1.05M ON

ON

OFF

ON

OFF

+V3.3M ON

ON

OFF

ON

OFF

+V1.8/+V0.9 ON

ON

OFF

+V5/+V3.3 ON

ON

OFF

+V*S ON

OFF

Clocks ON

only MCH BCLK

OFF

only MCH BCLK

OFF

Wake Events

Wake Events RI# from serial port

A A

PME# from PCI, mini PCI slot/device, LPC slot/device PCI Express, mini PCI Express, Express-card wake event Wake on LAN LID switch attached to SMC USB HDA wake on ring SmLink for AOLII Hot Key from Scan matrix keyboard PS/2 Keyboard/mouse PWRBTN# Netdetect

5

State Supported S3 S3 S3 S3/M1 S3 S3 S3 S3 S3 S3 S3 S3, S4, S5 / M1

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

4

3

Date: Sheet of

NOTES

355659

A

355659

A

355659

A

2

Changes for Pillar Rock with PM GMCH SKU

SL No NO_STUFF STUFF

U6E2, U6E3, U6E4

1

L5F1

2

3

4

5

6

R5E5, R5F9, R5T16, R5U3, R5U11, R5U14, R5U21, R6V1

C5E8, C5E9, C5E11, C5E12, C5E13, C5E14, C5E15, C5T12, C5T13, C5U1, C5U2, C5U3

FB5F1, FB5F2, FB5T1

J2G1(3 4), J2G1(5 6), J2G1(7 8)

R5E4, R5T5, R5T8, R5T9, R5T10, R5T12, R5T17

C5E8,C5E9,C5T13,C5U3 with 0 Ohm 0402 size res IPN A93549-001

J2G1(1 2), J2G1(13 14)

LEDs and Switches

LED xTA Activity VID0 VID1 VID2 VID3 VID4 VID5 VID6 Num Lock Scroll Lock Caps Lock S3 M0/M1 S4 S5 S0 System Power Good LT Status

Switch Default Description Page SW9H1

1 - 2 1 - 2 1 - 2 1 - 2

Virtual Docking Virtual Battery LID Switch Hybrid GFX switch

Power Button Reset Button Net Detect

SW9H3 SW9H2 SW7J1

SW1C1 SW1C2 SW8E1

21 39 39 39 39 39 39 39 40 40 40 57 57 57 57 57 57 64

ReferencePage CR7H1 CR1B1 CR1B2 CR1B3 CR1B4 CR1B5 CR1B6 CR1B7 CR9G1 CR9G3 CR9G2 CR5H6 CR5H3 CR5H7 CR5H5 CR5H4 CR7H3 CR8G1

PCB Footprints

1

2

SOT-23

3

As seen from top

1

2

3

2 58Tuesday, August 28, 2007

1

5

4

Intel Confidential

41 41 41 41

56 56 56

SOT23-5

1.0

5

4

+V1.05S_CPU4,20,35,39,43,52,54

3

2

1

H_A#[35:3]6

D D

H_ADSTB#06 H_REQ#[4:0]6

H_A#[35:3]6

Layout note: no stub on H_STPCLK TP. H_STPCLK# to be routed in daisy chain fashion from ICH to LPC slot and then to CPU.

C C

H_STPCLK#_R

TP2F1NO_STUFF TP2F1NO_STUFF

H_STPCLK#21,43

Layout Note: TP2F1 should be placed close to J1G7

H_ADSTB#16

H_A20M#21 H_FERR#21

H_IGNNE#21

R2U11

R2U11 0

0

H_INTR21 H_NMI21,43

.

H_SMI#21,43

CPU_RSVD06

CPU_RSVD09

TP_CPU_RSVD01 TP_CPU_RSVD02 TP_CPU_RSVD03 TP_CPU_RSVD04 TP_CPU_RSVD05

TP_CPU_RSVD07 TP_CPU_RSVD08

B B

XDP_TMS

XDP_TDI

XDP_BPM#5

XDP_TCK

XDP_TRST#

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20

W6

H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27

W2

H_A#28

W5

H_A#29 H_A#30 H_A#31 H_A#32

W3

H_A#33

AA4

H_A#34

AB2

H_A#35

AA3

D22

R2U4 54.9

R2U3 54.9

R1U6 54.9

R1T2 54.9

R1T3

1%

.

U2E1A

J4

ADDR GROUP_0 ADDR GROUP_1

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]# A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]# A[27]# A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]# A[32]#

THERMAL

A[33]# A[34]#

PROCHOT#

A[35]#

V1

ADSTB[1]#

A6

ICH

A20M#

A5

FERR#

C4

D5 C6 B4 A3

M4 N5 T2 V3 B2 D2

D3 F6

THERMTRIP#

IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]

RESERVED

Penryn_Ball-out_Rev_1p0

+V1.05S_CPU4,20,35,39,43,52,54

1%

Layout Note: Place R1U6 close to CPU with stub length <200mils.

1%

649

ADS# BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HIT#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TCK

TDO TMS

TRST#

DBR#

XDP/ITP SIGNALS

THERMDA

THERMDC

H CLK

BCLK[0] BCLK[1]

H1 E2 G5

H5 F21 E1

F1

D20 B3

H4

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3 G2

G6 E4

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6

TDI

AB3 AB5 AB6 C20

H_PROCHOT#_D

D21 A24 B25

C7

A22 A21

H_ADS# 6 H_BNR# 6 H_BPRI# 6

H_DEFER# 6 H_DRDY# 6 H_DBSY# 6

H_BREQ# 6

H_IERR#_R

H_INIT# 21

H_LOCK# 6 H_CPURST# 6,20

H_TRDY# 6

H_HIT# 6 H_HITM# 6

XDP_BPM#1 35 XDP_BPM#2 35

XDP_BPM#3 35 XDP_BPM#4 20 XDP_BPM#5 20

XDP_TCK 20

XDP_TDI 20

XDP_TDO 20

XDP_TMS 20

XDP_TRST# 20

XDP_DBRESET# 20

H_THERMDA 5

H_THERMDC 5

PM_THRMTRIP# 7,21

CLK_CPU_BCLK 35

CLK_CPU_BCLK# 35

R2H256R2H2 56

R2H356R2H3

56

Place testpoint on H_IERR# with a GND

H_RS#[2:0] 6

Layout note: Zo=55 ohm,

0.5" max for GTLREF.

0.1" away

NO_STUFF

TP1F1

+V1.05S_CPU4,20,35,39,43,52,54

PM_THRMTRIP# should connect to ICH9 and GMCH without T-ing (No stub)

H_GTLREF

Connect H_IERR# with no stub to the connector J2H1 and then connect to the 56 ohm pull up Resistor R2H2.

H_IERR#

XDP_BPM#0 20

TP1D1

TP1D1 R1R4

R1R4 68

68

5%

NO_STUFF

.

+V1.05S_CPU4,20,35,39,43,52,54

R1R16

R1R16 1K

1K

1%

1% .

.

R1R17

R1R17 2K

2K

1%

1% .

.

Place TP1D1 close to CPU.

R1D1

R1D1 0

0

.

C1T1

0.1uF

10%

NO_STUFF

Place C1T1 close to the CPU_TEST4 pin. Make sure CPU_TEST4 routing is reference to GND and away from other noisy signals.

H_PROCHOT# 52

H_PROCHOT#_D

H_DSTBN#06 H_DSTBP#06 H_DINV#06 H_D#[63:0]6

CPU_TEST3

CPU_TEST5 CPU_TEST6 CPU_TEST7

CPU_BSEL035 CPU_BSEL135 CPU_BSEL235

H_D#[63:0]6

H_DSTBN#16 H_DSTBP#16 H_DINV#16

CPU_TEST1 CPU_TEST2

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24

H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

CPU_TEST4

NO_STUFF

R3P5 1K

U2E1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

C3

TEST7

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Penryn_Ball-out_Rev_1p0

NO_STUFF

R3P6 1K

MISC

DATA GRP 0

DATA GRP 1

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]#

DATA GRP 2DATA GRP 3

D[41]# D[42]# D[43]# D[44]# D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]#

COMP[0] COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP# DPWR#

PWRGOOD

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0

R2R3 27.4 1%R2R3 27.4 1%

COMP1

R2R2 54.9 1%R2R2 54.9 1%

COMP2

R2U1 27.4 1%R2U1 27.4 1%

COMP3

R2U2 54.9 1%R2U2 54.9 1%

H_DPRSTP# 7,21,43 H_DPSLP# 21,43

H_CPUSLP# 6,43 PSI# 52

Layout: Connect test point TP3E2 with no stub

H_D#[63:0] 6

H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 H_D#[63:0] 6

Layout note: Comp0,2 connect with Zo=27.4ohm, make trace length shorter than 0.5". Comp1,3 connect with Zo=55ohm, make trace length shorter than 0.5".

H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6

H_DPWR# 6 H_PWRGD 21,43

H_PWRGD_XDP 20

TP3E2

NO_STUFF

R1U15

R1U15 1K

1K

5%

5% .

.

Place Series Resistor on H_PWRGD_XDP Without Stub

A A

Intel Confidential

3 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

Pillar Rock

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Date: Sheet of

5

4

3

Date: Sheet of

Penryn (1 of 2)

355659

2

5

4

3

2

1

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

+VCC_CORE53,54,55

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

.

CPU_G21

NO_STUFF

TP3E1

R3T2 is for test purpose only.

R3T2

R3T2 0

0

.

H_VID0 52 H_VID1 52 H_VID2 52 H_VID3 52 H_VID4 52 H_VID5 52 H_VID6 52

C2U2

C2U2 270uF

270uF

20%

20% .

.

+V1.05S_CPU3,20,35,39,43,52,54

+VCCA_PROC

+VCC_CORE53,54,55

R1T16

R1T16 100

100

1%

1% .

.

R1T14

R1T14 100

100

1%

1% .

.

C3R3

0.01uF

10%

10% .

.

VCCSENSE 52

VSSSENSE 52

R3U2

R3U1

C3R2

Layout Note:

10uF

Place C3R3 near pin-B26

20%

20% .

.

Layout Note: Route VCCSENSE and VSSSENSE traces at

27.4 Ohms with 50 mil spacing. Place PU and PD within 1 inch of CPU.

0

R3R13 0.01

12

NO_STUFF

12

NO_STUFF

1%

+V1.05S9,10,24,47,55

+V1.5S10,11,24,28,47,55,57

U2E1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080] VSS[081]P3VSS[162]

Penryn_Ball-out_Rev_1p0

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]

VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

.

+VCC_CORE53,54,55

D D

C C

U2E1C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Penryn_Ball-out_Rev_1p0

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VCCSENSE

VSSSENSE

B B

A A

Intel Confidential

4 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

Pillar Rock

Title

Size Document Number Rev

Custom

Date: Sheet of

5

4

3

Date: Sheet of

Penryn (2 of 2)

355659

2

5

4

3

2

1

CPU Thermal Sensor

C3N10

0.1uF

20%

20% .

.

U3B3

1

VDD

2

D+

3

D-

T_CRIT#4GND

LM95245C

SMBCLK

SMBDAT

OS#/A0

8

7

6

5

R3B19

R3B19 10K

10K

5%

5% .

.

0

+V3.3S7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R3N21

R3N21 10K

10K

5%

5% NO_STUFF

NO_STUFF

C3N11

ADT_THERM_DXP

ADT_THERM_DXN

1000pF

5%

ADT_THM# THRM_ALERT#

NO_STUFF

D D

C C

J3C1

1-2 3-4

1-X 3-X

Layout Note: Route H_THERMDA and H_THERMDC on same layer w/ 10 mil trace & 10 mil spacing. Route away from noise sources with ground guard tracks on each side.

H_THERMDA3 H_THERMDC3

Thermal Diode Connector

Connects the Internal CPU Thermal sensor to the ADT7461A (Default)

Connect an external Thermal sensor to the ADT7461A

J4A1

J4A1 3Pin_Recepticle

3Pin_Recepticle

GND0

3 4 5 6

GND1

J3C1

1 3

2X2HDR

12

THERMDNTHERMDP

GND2

NO_STUFF

GND3

THERM_DXP

2 4

THERM_DXN

R3N27

R3N26

.

NOTE : R3N27, R3N26, C3N11 are placeholders for the new thermal sensor (NS LM95245).

+V3.3S7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R3N22

R3N19

10K

5%

.

SMB_THRM_CLK 12,40,43

SMB_THRM_DATA 12,40,43

R3N20

R3N20 0

0

NO_STUFF

Note: No-Stuff R3N20 for normal operation, No Stuff (R9G11, Sheet 40) if R3N20 is stuffed

PM_THRM# 12,23,40,43

CPU Fan Power Control

+V5S11,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57

R2N4

R2N4 0

0

.

+V3.3S7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R2N6

R2N6 1K

1K

1%

1% .

.

CPU_TACHO_FAN 40,43

Intel Confidential

5 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

CPU Thermal Sensor & Fan

355659

A

355659

A

355659

A

2

C3N4

C3N6

0.1uF

4.7uF

10%

B B

OPA567_POSIN

R3N14

CPU_PWM_FAN40,43

R3N14 15K

15K

1%

1% .

.

10%

.

1

101112

EU3B1

V+

_

C3B5

C3B5 1uF

1uF

10%

.

_

8

OPA567

9

+

V-

456

HS

TF

EN

IF

IS

13

OPA567_ISIN_R

2

OUT

3

.

7

OPA567_NEGIN

R3N6

R3N6 20K

20K

5%

5% .

.

VOUT_OPAMP

CR2N2

CR2N2 BAT54

BAT54

R3N8

1.74K

1%

1% .

.

R3N10

3.32K

1%

1% .

.

2

CPU_TACHO_R_FAN

Note: No-Stuff R2N4 to Disable PWM control of FAN

11332

3

1

J2B3

CONN3_HDR

.

A A

5

4

3

5

D D

+VCCP_GMCH10

R4E8

R4E8 221

221

1%

1% .

.

R4E5

R4E5 100

100

1%

1% .

.

C C

R4E2

24.9

1%

1% .

.

C4F1

0.1uF

20%

20% .

.

H_RCOMP

H_SWING

B B

+VCCP_GMCH10

R4E7

R4E7 1K

1K

1%

1% .

H_AVREF

H_DVREF

.

R4E4

R4E4 2K

2K

1%

1% .

.

R4E6 0

0

.

4

U5E1A

M11

AD14

AA8

AA13

AA9 AA11 AD11 AD10 AD13 AE12

AE9

AA2

AD8

AA3

AD3

AD7 AE14

AC1

AE3

AC3 AE11

AE8

AG2

AD6

G2 H6 H2

D4 H3 M9

N12

R2 N9

M5

N2 R1 N5 N6

P13

N8

N10

M3

Y10 Y12 Y14

W2

AF3

C5

C12 E11

A11 B11

U5E1A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3 H_D#_4 H_D#_5 H_D#_6

F6

H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11

J1

H_D#_12

J2

H_D#_13 H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17 H_D#_18 H_D#_19

L6

H_D#_20 H_D#_21

J3

H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28

L7

H_D#_29 H_D#_30 H_D#_31

Y3

H_D#_32 H_D#_33

Y6

H_D#_34 H_D#_35 H_D#_36 H_D#_37

Y7

H_D#_38 H_D#_39 H_D#_40

Y9

H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING

E3

H_RCOMP

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

CANTIGA_1p2

H_D#[63:0]3

H_CPURST#3,20

H_CPUSLP#3,43

C4E12

0.1uF

10%

10%R4E6

NO_STUFF

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

3

H_A#3

A14

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS# H_ADSTB#_0 H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

HOST

H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

H_A#4

C15

H_A#5

F16

H_A#6

H13

H_A#7

C18

H_A#8

M16

H_A#9

J13

H_A#10

P16

H_A#11

R16

H_A#12

N17

H_A#13

M13

H_A#14

E17

H_A#15

P17

H_A#16

F17

H_A#17

G20

H_A#18

B19

H_A#19

J16

H_A#20

E20

H_A#21

H16

H_A#22

J20

H_A#23

L17

H_A#24

A17

H_A#25

B17

H_A#26

L16

H_A#27

C21

H_A#28

J17

H_A#29

H20

H_A#30

B18

H_A#31

K17

H_A#32

B20

H_A#33

F21

H_A#34

K21

H_A#35

L20

H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9

J8 L3 Y13 Y1

L10 M7 AA5 AE6

L9 M8 AA6 AE5

H_REQ#0

B15

H_REQ#1

K13

H_REQ#2

F13

H_REQ#3

B13

H_REQ#4

B14

H_RS#0

B6

H_RS#1

F12

H_RS#2

C8

2

H_A#[35:3] 3

H_DINV#0 3 H_DINV#1 3 H_DINV#2 3 H_DINV#3 3

H_DSTBN#0 3 H_DSTBN#1 3 H_DSTBN#2 3 H_DSTBN#3 3

H_DSTBP#0 3 H_DSTBP#1 3 H_DSTBP#2 3 H_DSTBP#3 3

H_ADS# 3 H_ADSTB#0 3 H_ADSTB#1 3 H_BNR# 3

H_BPRI# 3

H_BREQ# 3

H_DEFER# 3

H_DBSY# 3 CLK_MCH_BCLK 35 CLK_MCH_BCLK# 35

H_DPWR# 3

H_DRDY# 3

H_HIT# 3

H_HITM# 3

H_LOCK# 3

H_TRDY# 3

H_RS#[2:0] 3

1

H_REQ#[4:0] 3

H_VREF & H_DVREF

A A

5

Default= R4E6(STUFF) R4E3, R4F1(NO_STUFF) on Sheet # 65

H_AVREF & H_DVREF shorted togther (same voltage divider) For EV= R4E6(NO_STUFF) R4E3, R4F1 (STUFF) on Sheet # 65

H_AVREF & H_DVREF can be schoomed independently for EV (separate voltage divider)

4

Intel Confidential

6 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

3

Date: Sheet of

CANTIGA (1 OF 6)

355659

A

355659

A

355659

A

2

5

U5E1B

M36

MCH_RSVD_1 MCH_RSVD_2 MCH_RSVD_3 MCH_RSVD_4 MCH_RSVD_5 MCH_RSVD_6 MCH_RSVD_7 MCH_RSVD_8

D D

MCH_RSVD_14

MCH_RSVD_21

MCH_RSVD_24 MCH_RSVD_25

MCH_CFG_18 MCH_CFG_1912 MCH_CFG_2012,19

PM_EXTTS#0_EC40 TS#_DIMM0_113,14

R5D1

20

1%

MCH_TCK15

MCH_TDI15

MCH_TDO15

MCH_TMS15

MCH_CFG_[17:3]12

PM_SYNC#23

H_DPRSTP#3,21,43

DELAY_VR_PWRGOOD23

PM_THRMTRIP#3,21

PM_DPRSLPVR23,43,52

PLT_RST# 19,22,25,26,38,41,57

+V1.8_GMCH9,10

.

NO_STUFF

.

C C

B B

A A

MCH_BSEL035 MCH_BSEL135 MCH_BSEL235

TP5F2 NO_STUFFTP5F2 NO_STUFF

R5D4

80.6

1%

SM_RCOMP SM_RCOMP#

1%

80.6

80.6 R5D3

R5D3

TP_MCH_RSVD9

TP_MCH_RSVD15

TP_MCH_RSVD17

TP_MCH_RSVD20

TP_MCH_RSVD22 TP_MCH_RSVD23

MCH_CFG_20_R

R5F10

R5F10 0

0

.

PM_SYNC#_R

R5F13

PM_DPRSTP#_R

0

R4T2

R4T2 0

0

PM_EXTTS#1_R

R5P2

.

0

.

R4R11 100R4R11 100

.

R4T3 0

R4T3 0 R5U31 0

R5U31 0

.

. .

.

TP_MCH_NC1 TP_MCH_NC2 TP_MCH_NC3 TP_MCH_NC4 TP_MCH_NC5 TP_MCH_NC6 TP_MCH_NC7 TP_MCH_NC8 TP_MCH_NC9 TP_MCH_NC10 TP_MCH_NC11 TP_MCH_NC12 TP_MCH_NC13 TP_MCH_NC14 TP_MCH_NC15 TP_MCH_NC16 TP_MCH_NC17 TP_MCH_NC18 TP_MCH_NC19 TP_MCH_NC20 TP_MCH_NC21 TP_MCH_NC22 TP_MCH_NC23 TP_MCH_NC24 TP_MCH_NC25

MCH_CFG_3 MCH_CFG_4 MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_8 MCH_CFG_9 MCH_CFG_10 MCH_CFG_11 MCH_CFG_12 MCH_CFG_13 MCH_CFG_14 MCH_CFG_15 MCH_CFG_16 MCH_CFG_17

RST_IN#_MCH THRMTRIP#_R DPRSLPVR_R

R5R1

R5R1 20

20

NO_STUFF

NO_STUFF 1%

1%

N36 R33

T33

AH9 AH10 AH12 AH13

K12

T24

B31

M1

AY21

B2 BG23 BF23 BH18 BF18

AL34

AK34

AN35

AM35

T25 R25 P25 P20 P24 C25 N24

M24

E21 C23 C24 N21

P21

T21 R20 M20

L21 H21

P29

R28

T28

R29

B7

N33

P32

AT40 AT11

T20 R32

BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43

BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1

F1

CANTIGA_1p2

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9

RSVD14

RSVD15

RSVD17

RSVD20

RSVD21 RSVD22 RSVD23 RSVD24 RSVD25

ME_JTAG_TCK

ME_JTAG_TDI

ME_JTAG_TDO

ME_JTAG_TMS

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25

RSVD

ME JTAG

CFG

PM

NC

5

4

AP24

SA_CK_0

AT21

SA_CK_1

AV24

SB_CK_0

AU20

SB_CK_1

AR24

SA_CK#_0

AR21

SA_CK#_1

AU24

SB_CK#_0

AV20

SB_CK#_1

BC28

SA_CKE_0

AY28

SA_CKE_1

AY36

SB_CKE_0

BB36

SB_CKE_1

BA17

SA_CS#_0

AY16

SA_CS#_1

AV16

SB_CS#_0

AR13

SB_CS#_1

BD17

SA_ODT_0

AY17

SA_ODT_1

BF15

SB_ODT_0

AY13

SB_ODT_1

BG22

SM_RCOMP

SM_VREF

SM_REXT

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK

HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

BH21

SM_RCOMP_VOH

BF28

SM_RCOMP_VOL

BH28

AV42 AR36 BF17 BC36

B38 A38 E41 F41

F43 E43

AE41 AE37 AE47 AH39

AE40 AE38 AE48 AH40

DMI_RXN0

AE35

DMI_RXN1

AE43

DMI_RXN2

AE46

DMI_RXN3

AH42

DMI_RXP0

AD35

DMI_RXP1

AE44

DMI_RXP2

AF46

DMI_RXP3

AH43

B33 B32 G33 F33 E33

C34

AH37 AH36 AN36 AJ35

MCH_CLVREF_R

AH34

N28 M28 G36 E36 K36 H36

B12

HDA_CODEC_BCLK

B28

HDA_CODEC_RST#

B30

HDA_SDIN

B29

HDA_CODEC_SDATAOUT

C29

HDA_CODEC_SYNC

A28

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_PWROK

SM_DRAMRST#

DPLL_REF_CLK

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

DMI

GFX_VR_EN

GRAPHICS VID

MEHDA

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

MISC

SM_RCOMP

SM_RCOMP#

SM_REXT

TP_SM_DRAMRST#

DREFCLK 35 DREFCLK# 35 DREFSSCLK 35 DREFSSCLK# 35

CLK_PCIE_3GPLL 35 CLK_PCIE_3GPLL# 35

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

NO_STUFF

R5D90

M_CLK_DDR0 13 M_CLK_DDR1 13 M_CLK_DDR3 14 M_CLK_DDR4 14

M_CLK_DDR#0 13 M_CLK_DDR#1 13 M_CLK_DDR#3 14 M_CLK_DDR#4 14

M_CKE0 13,15 M_CKE1 13,15 M_CKE3 14,15 M_CKE4 14,15

M_CS#0 13,15 M_CS#1 13,15 M_CS#2 14,15 M_CS#3 14,15

M_ODT0 13,15 M_ODT1 13,15 M_ODT2 14,15 M_ODT3 14,15

SM_PWROK 46

R4R7 499

. 1%

GFXVR_VID_0 49 GFXVR_VID_1 49 GFXVR_VID_2 49 GFXVR_VID_3 49 GFXVR_VID_4 49

GFXVR_EN 49

CL_CLK0 23 CL_DATA0 23 MPWROK 23,46

DDPC_CTRLCLK 19 DDPC_CTRLDATA 19 SDVO_CTRLCLK 19 SDVO_CTRLDATA 19 CLK_MCH_OE# 35

MCH_ICH_SYNC# 23

MCH_TSATN# 41

LVDS_VDD_EN17

LVDS_IBG

+V1.8_GMCH9,10

NO_STUFF

R5R5

R5R5 1K

1K

1%

1% NO_STUFF

NO_STUFF

DMI_TXN[3:0] 22

DMI_TXP[3:0] 22

DMI_RXN[3:0] 22

DMI_RXP[3:0] 22 PEG_TX[15:0] 19

+V1.25S_1.05M_CANTIGA9,10

CL_RST#0 23

MCH_CLVREF

IMPORTANT NOTE:

When the Resistors R8E7, R7H3 (Page-28) are mounted, then the resistors R7V4, R7V3, R7V8, R7V23, R5F9 should be NO_STUFF.

4

3

L_BKLT_CTRL17 L_BKLT_EN17

L_CTRL_CLK17,20

L_CTRL_DATA17,20

LVDS_DDC_CLK17

LVDS_DDC_DATA17

R5T11

2.37K

1%

.

R5R4

R5R4 1K

1K

1%

M_VREF_MCH 46,48

NOTE:SM_DRAMRST# Would be needed for DDR3 only

NOTE: All LVDS data signals/and its compliments SHOULD BE ROUTED DIFFERENTIALLY

TVA_DAC18 TVB_DAC18

TVC_DAC18

R5U4 150 1%R5U4 150 1% R5U7 150 1%R5U7 150 1% R5U6 150 1%R5U6 150 1%

Layout Note: Place 150 Ohm termination resistors close to GMCH

R5T4 150 1%R5T4 150 1% R5T5 150 1%R5T5 150 1% R5T6 150 1%R5T6 150 1%

CRT_DDC_CLK_MCH16

CRT_DDC_DATA_MCH16

CRT_HSYNC16

CRT_VSYNC16

R5D10

R5D10 1K

1K

1%

R5D11

R5D11 0

0

NO_STUFF

R5D12

R5D12 511

511

1%

1% .

.

NO_STUFF

C5D3

0.1uF

10%

.

3

2

U5E1C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

L_VDD_EN_R

R5U18

R5U18 0

0

NO_STUFF

TP5F1

LVDSA_CLK#17 LVDSA_CLK17 LVDSB_CLK#17 LVDSB_CLK17

LVDSA_DATA#017 LVDSA_DATA#117 LVDSA_DATA#217 LVDSA_DATA#317

LVDSA_DATA017 LVDSA_DATA117 LVDSA_DATA217 LVDSA_DATA317

LVDSB_DATA#017 LVDSB_DATA#117 LVDSB_DATA#217 LVDSB_DATA#317

LVDSB_DATA017 LVDSB_DATA117 LVDSB_DATA217 LVDSB_DATA317

R5U9 0.5%R5U9 0.5% R5U8 0.5%R5U8 0.5% R5U5 0.5%R5U5 0.5%

TV_DCONSEL0_MCH18 TV_DCONSEL1_MCH18

CRT_BLUE16

CRT_GREEN16

CRT_RED16

R5U10 30.1

R5T7 1.02k

0.5% .

R5U11 30.1

EV_VCC_V1.05_CLVREF0

****

R7V4 33 NO_STUFFR7V4 33 NO_STUFF C5R3 R7V3 33 NO_STUFFR7V3 33 NO_STUFF R7V8 33 NO_STUFFR7V8 33 NO_STUFF R7V23 33 NO_STUFFR7V23 33 NO_STUFF R5F9 0 NO_STUFFR5F9 0 NO_STUFF

LVDS_VBG

.

MCH_TVA_DAC MCH_TVB_DAC MCH_TVC_DAC

HSYNC CRTIREF

.

.R5T7 1.02k

VSYNC

.

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANTIGA_1p2

+V1.8_GMCH9,10

HDA_BIT_CLK 21,27

HDA_RST# 21,27

HDA_SYNC 21,27

HDA_SDOUT 21,27

HDA_SDIN3 21,27

CANTIGA (2 OF 6)

355659

2

LVDS

TV

PCI-EXPRESS GRAPHICS

VGA

R5D5

R5D5 1K

1K

0.10%

R5D8

3.01k

1%

R5D6

R5D6 1K

1K

0.10%

PEG_COMPI

PEG_COMPO

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8

PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8

PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

+V3.3S5,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

C5R2

0.01uF

10%

402

C5R1

0.01uF

10%

402

PEG_COMP

T37 T36

H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39

H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40

J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46

J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46

R5U13 10KR5U13 10K

R5U12 10KR5U12 10K

R5P5 10KR5P5 10K

SM_RCOMP_VOH

C5R4

2.2uF

10%

.

SM_RCOMP_VOL

C5R3

2.2uF

10%

.

1

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8

PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

7 58Tuesday, August 28, 2007

1

+VCC_PEG10

R5T3 49.9R5T3 49.9

PEG_RX#[15:0] 19

PEG_RX[15:0] 19

PEG_TX#[15:0] 19

CLK_MCH_OE#

PM_EXTTS#0_EC

PM_EXTTS#1_R 15

Intel Confidential

1.0

5

4

3

2

1

M_A_DQ[63:0]13 M_B_DQ[63:0]14

D D

C C

B B

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AJ38

AJ41 AN38 AM38

AJ36

AJ40

AM44 AM42

AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36

AW36

BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12

AU10

BA11

AN10

AM11

AM5

AN12

AM13

AJ11

AJ12

BB9 BA9

AV9

BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5

AJ9 AJ8

U5E1D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

CANTIGA_1p2

BD21

SA_BS_0

BG18

SA_BS_1

AT25

SA_BS_2

BB20

SA_RAS#

BD20

SA_CAS#

AY20

SA_WE#

M_A_DM0

AM37

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

DDR SYSTEM MEMORY A

AT41 AY41 AU39 BB12 AY6 AT7 AJ5

AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8

BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25

M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6

M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

M_A_BS1 13,15 M_A_BS2 13,15

M_A_RAS# 13,15 M_A_CAS# 13,15 M_A_WE# 13,15

M_A_DM[7:0] 13

M_A_DQS[7:0] 13

M_A_DQS#[7:0] 13

M_A_A[14:0] 13,15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AK47 AH46 AP47 AP46

AJ46

AJ48 AM48 AP48 AU47 AU46 BA48

AY48

AT47 AR47 BA47 BC47 BC46 BC44 BG43

BF43 BE45 BC41

BF40

BF41 BG38

BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11

BG8

BH12

BF11

BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1

AH1 AM2 AM3 AH3

AL1 AL2 AJ1

AJ3

U5E1E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

CANTIGA_1p2

BC16

SB_BS_0

BB17

SB_BS_1

BB33

SB_BS_2

AU17

SB_RAS#

BG16

SB_CAS#

BF14

SB_WE#

M_B_DM0

AM47

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

DDR SYSTEM MEMORY B

AY47 BD40 BF35 BG11 BA3 AP1 AK2

AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5

AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33

M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

M_B_BS0 14,15M_A_BS0 13,15 M_B_BS1 14,15 M_B_BS2 14,15

M_B_RAS# 14,15 M_B_CAS# 14,15 M_B_WE# 14,15

M_B_DM[7:0] 14

M_B_DQS[7:0] 14

M_B_DQS#[7:0] 14

M_B_A[14:0] 14,15

A A

5

4

3

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

CANTIGA (3 OF 6)

355659

A

355659

A

355659

A

2

8 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

5

4

3

2

1

W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16

AV44 BA37 AM40 AV21 AY5 AM10 BB13

+VGFX_CORE49

+VCCSM_LF1 +VCCSM_LF2 +VCCSM_LF3 +VCCSM_LF4 +VCCSM_LF5 +VCCSM_LF6

+VCCSM_LF7

+VCC_GFXCORE49 +V1.25S_1.05M_CANTIGA7,10

+V1.05M10,15,35,47,55

+V1.05S4,10,24,47,55

R4U5 TO BE STUFFED ONLY AS BACKUP OPTION FOR +VGFX_CORE

VCC_SM_36

C5R12

0.1uF

10%

C4R4

C4R8

0.1uF

10%

.

SMC0402

.

SMC0402

4

R3F1

NO_STUFF

R4F6

.

R3F2 0.002

1%

R4U5 0.002

1%

NO_STUFF

VCC_SM_37

VCC_SM_38

C4R10

C4R11

0.1uF

10%

Place C5C7 where LVDS and DDR2 taps.

C4R5

0.22uF

SMC0402

.

R5U3 0.002

1%

12

0.002

12

0.002

12

+

C4T7

C4T7 330uF

330uF

3

20%

smc7343_TAK

Place close to the GMCH

VCC_SM_40

VCC_SM_42

C4R12

C4R13

0.1uF

10%

NO_STUFF

+V1.8 10,13,14,46,48,55,57

R5C6 0.002

C5C7

0.1uF

10%

.

SMC0402

.

SMC0402

C4R6

C5R10

0.22uF

0.47uF

SMC0402

SMC7343

Place close to the GMCH

12

+

3

smc7343_TAK

1%

C5R7

1.0uF

20%

SMC0402

C5U4

C5U4 270uF

270uF

20%

+V1.25S_1.05M_CANTIGA

For Teenah

For Cantiga STUFF: R4F6

+VGFX_CORE49+VCC_GFXCORE49

C4T5

C4T5 330uF

330uF

20%

C5C8

C5C8 330uF

330uF

20%

SMC7343_75h

C5R8

1.0uF

20%

20% SMC0402

SMC0402

3

STUFF: R3F1 NO_STUFF: R4F6

NO_STUFF: R3F1

C4T3

0.47uF

SMC0603

C5T3

C5T3 22uF

22uF

20%

.

SMC0805

.

SMC0805

C4R9

C4R9 1uF

1uF

20%

20% .

SMC0603

.

SMC0603

Cavity Capacitors

SMC0805

PLACE ON THE EDGE

C5T1

C5R11

0.22uF

20%

SMC0603

C4T6

C4T2

22uF

10uF

20%

.

SMC0805

.

SMC0805

.

SMC0805

.

SMC0805

Cavity Capacitors

R5T1 is used for internal test purpose only

C5D2

C5D1

22uF

20%

.

SMC0805

.

SMC0805

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

CANTIGA (4 OF 6)

355659

A

355659

A

355659

A

U5E1G

D D

+V1.8_GMCH7,10

Pins BA36, BB24, BD16, BB21, AW16, AW13, AT13 could be left NC for DDR2 boards

C C

VCC_SM_36 VCC_SM_37 VCC_SM_38

VCC_SM_40

VCC_SM_42

+VGFX_CORE

B B

A A

VCC_AXG_SENSE49 VSS_AXG_SENSE49

Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially

AP33 AN33 BH32 BG32

BF32 BD32 BC32

BB32

BA32

AY32 AW32

AV32 AU32

AT32 AR32

AP32 AN32 BH31 BG31

BF31 BG30 BH29 BG29

BF29 BD29 BC29

BB29

BA29

AY29 AW29

AV29 AU29

AT29 AR29

AP29

BA36

BB24 BD16

BB21 AW16 AW13

AT13

AE25

AB25

AA25

AE24 AC24

AA24

AE23 AC23

AB23

AA23

AJ21

AG21

AE21 AC21

AA21

AH20

AF20

AE20 AC20

AB20

AA20

AM15

AL15

AE15

AJ15 AH15 AG15

AF15 AB15 AA15

AN14 AM14

AJ14 AH14

Y26

Y24

Y21

T17 T16

Y15 V15 U15

U14 T14

U5E1G

VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35

VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42

VCC_AXG_SENSE VSS_AXG_SENSE

CANTIGA_1p2

POWER

VCC SMVCC GFX

VCC GFX NCTF

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

5

C5T4

0.1uF

10%

10% .

SMC0402

.

SMC0402

C4T4

C5T2

0.1uF

10%

.

SMC0402

.

SMC0402

.

SMC0402

.

SMC0402

+V1.8_GMCH 7,10

C5R13

0.1uF

10%

NO_STUFF

2

+VCC_GMCH+V1.05M10,15,35,47,55

NO_STUFF

C5T10

1.0uF

20%

20% 402

402

R5T1

R5T1 0

0

.

+VCC_MCH_35

AG34 AC34 AB34 AA34

AM33 AK33

AJ33

AG33

AF33

AE33 AC33 AA33

W33

AH28

AF28 AC28 AA28

AJ26 AG26 AE26 AC26 AH25 AG25

AF25 AG24

AJ23 AH23

AF23

Y34 V34 U34

Y33

V33 U33

T32

U5E1F

VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34

VCC_35

CANTIGA_1p2

VCC CORE

POWER

VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31

VCC NCTF

VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44

9 58Tuesday, August 28, 2007

1

+VCC_GMCH

AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23

Intel Confidential

1.0

5

+V1.25S_1.05M_CANTIGA7,9

12

.

R5F14

0.002

L5F1 10uH

1 2

10%

201005-548

D D

L6F1 10uH

+V1.05M_MCH_PLL+V1.05M_MCH_PLL2

1 2

10%

201005-548

+V1.25S_1.05M_CANTIGA

.

12

R4D6

0.002

R4E90.R4E9

0.

C C

B B

A A

FB4E1

SMF0603

120ohm@100MHz

R4E1 0.51

+V1.05M_MPLL_RC

C4T1

C4T1 22uF

22uF

20%

.

SMC0805

.

SMC0805

+V3.3S_TVDAC

FB4F1

180ohm@100MHz

SMF0603

NOTE: CAPS USED IN +V3.3S_TVDAC should be within 250mils of edge of MCH

+V1.5S

R4U3

1 2

0.002

+V1.5S_LDO_QDAC28

12

0.002

0.002 R4U4

R4U4

+V1.5S_LDO_QDAC_R

+V1.25S_1.05M_CANTIGA

R5T8

1 2

0.002

.

+V1.05M_DPLLA

C5E8

+

C5U7

+

C5U7 220uF

220uF

0.1uF

10%

.

SMC0402

.

SMC0402

+V1.05M_DPLLB

+

C5F1

+

C5F1

C5E5

220uF

0.1uF

10%

.

SMC0402

.

SMC0402

+V1.05M_HPLL

C4E4

4.7uF

10%

.

SMC0603

.

SMC0603

+V1.05M_MPLL

1%

SMR0402

+V3.3S_A_TV_CRT_BG +V3.3S_A_TV_DAC

R4U2

R4U2 0

0

NO_STUFF

FB5U1

180ohm@100MHz

SMF0603

+V1.05M_PEGPLL_R

+V1.05M_PEGPLL_RC

C5T8

C5T8 10uF

10uF

20%

.

SMC0805

.

SMC0805

+V3.3S_A_TV_CRT_BG

1 2

+V1.5S4,11,24,28,47,55,57

R6E1

1 2

.

+V1.25S_1.05M_CANTIGA7,9

C4E3

0.1uF

10%

.

SMC0402

.

SMC0402

C4E1

0.1uF

10%

.

SMC0402

.

SMC0402

+V1.25S_1.05M_CANTIGA7,9

R4F3

1 2

0.002

R4U2 to be stuffed & R4U4 to be no_stuffed , if val needs to be done from switcher

SMF0805

220ohm_at_100MHz

R5T2

SMR0402

C5U1

0.1uF

10%

.

SMC0402

.

SMC0402

C5U3

0.1uF

10%

.

SMC0402

.

SMC0402

1 2

FB5T1

1.00

1%

R4R1

1 2

.

12

+

C4E2

C4E2 100uF

100uF

SMC7343

R4R2

0.002

.

C5T9

0.01uF

10%

10% SMC0402

SMC0402

C5U2

0.01uF

10%

10% SMC0402

SMC0402

R5F2

0.002

R5F6

0.002

+V1.05M_A_SM_R

0.002

+V1.05M_A_SM_CK_R

C5E18

0.1uF

10%

.

SMC0402

.

SMC0402

+V1.5S_TVDAC

+V1.05M_PEGPLL

10%

.

SMC0402

.

SMC0402

C5T5

0.1uF

+V3.3S_A_CRT_DAC

C5E12

0.1uF

10%

.

SMC0402

.

SMC0402

C5E13

0.1uF

10%

.

SMC0402

.

SMC0402

+V3.3S

R5D13

R5D13 0

0

NO_STUFF

C5E2

0.1uF

10%

.

SMC0402

.

SMC0402C4E4

SMR0603

C5E14

0.01uF

10%

10% SMC0402

SMC0402

+V1.5S_QDAC

R5U2

R5U2 0

0

NO_STUFF

+V1.5S4,11,24,28,47,55,57

SMR0603

+VCC_HDA

5

C5E17

0.01uF

10%

10% SMC0402

SMC0402

C5E16

0.01uF

10%

10% SMC0402

SMC0402

+VCCA_PEG_BG

R4R3

R4R3 0

0

.

R5R3

R5R3 0

0

.

R5E7

R5E7 0

0

NO_STUFF

+V1.8_LDO46

1 2

4

+V1.8_TXLVDS

+V1.05M_A_SM

C4R1

C4R1 22uF

22uF

20%

20% SMC0805

SMC0805

NO_STUFF

C4R3: Edge Cap

NO_STUFF

+V1.05M_MCH_PLL2

R5U1

0.002

4

R5E5

R5E5 0

0

NO_STUFF

+V3.3S_A_DAC_BG

R5E6

R5E6 0

0

NO_STUFF

+V1.05M_PEGPLL

C5R7:Cavity Cap

C4R2

C4R2 22uF

22uF

20%

.

SMC0805

.

SMC0805

+V1.05M_A_SM_CK

C5R6

C5R5

22uF

2.2uF

20%

10%

SMC0805

SMC0603

+V3.3S_A_TV_DAC

R5T10

R5T10 0

0

5%

+V1.5S_QDAC

C4D3

0.1uF

10%SMC0402

.

Topside Cap

R5F8

1 2

R5F5

0.002

NO_STUFF

+VCC_HDA

C5E11

0.1uF

10%

.

SMC0402

.

SMC0402

+V1.05M_DPLLA

+V1.05M_DPLLB

+V1.05M_HPLL

+V1.05M_MPLL

C5E7

C5E7 1000pF

1000pF

10%

10% .

.

SMC0402

C4R3

4.7uF

10%

.

SMC0603

.

SMC0603

.

+V1.5S_TVDAC

+V1.05M_PEGPLL

+V1.8_DLVDS+V1.89,13,14,46,48,55,57

0.002

12

C4R7

1.0uF

20%

20% SMC0402

SMC0402

C5R9

0.1uF

10%

.

SMC0402

.

SMC0402

C5T6

0.1uF

10%

.

SMC0402

.

SMC0402

R5T9

R5T9 0

0

5%

NO_STUFF

U5E1H

B27

VCCA_CRT_DAC_1

A26

VCCA_CRT_DAC_2

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

J48

VCCA_LVDS

J47

VSSA_LVDS

AD48

VCCA_PEG_BG

AA48

VCCA_PEG_PLL

AR20

VCCA_SM_1

AP20

VCCA_SM_2

AN20

VCCA_SM_3

AR17

VCCA_SM_4

AP17

VCCA_SM_5

AN17

VCCA_SM_6

AT16

VCCA_SM_7

AR16

VCCA_SM_8

AP16

VCCA_SM_9

AP28

VCCA_SM_CK_1

AN28

VCCA_SM_CK_2

AP25

VCCA_SM_CK_3

AN25

VCCA_SM_CK_4

AN24

VCCA_SM_CK_5

AM28

VCCA_SM_CK_NCTF_1

AM26

VCCA_SM_CK_NCTF_2

AM25

VCCA_SM_CK_NCTF_3

AL25

VCCA_SM_CK_NCTF_4

AM24

VCCA_SM_CK_NCTF_5

AL24

VCCA_SM_CK_NCTF_6

AM23

VCCA_SM_CK_NCTF_7

AL23

VCCA_SM_CK_NCTF_8

B24

VCCA_TV_DAC_1

A24

VCCA_TV_DAC_2

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS_1

L37

VCCD_LVDS_2

CANTIGA_1p2

C5E9

1.0uF

20%

20% SMC0402

SMC0402

+V3.3S

3

CRTPLLA PEGA SM

A LVDS

POWER

A CK

TV

HDA

D TV/CRT

LVDS

+V1.05S4,9,24,47,55

1

CR5F1

CR5F1 BAT54

BAT54

+V1_05S_SD

3

12

R5U19

R5U19 10

10

5%

3

SM CK

DMI

R5F1

1 2

0.002

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15

VTT

VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

VCC_TX_LVDS

VCC_HV_1 VCC_HV_2 VCC_HV_3

HV

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

PEG

VCC_DMI_1

VCC_DMI_2 VCC_DMI_3 VCC_DMI_4

VTTLF1 VTTLF2 VTTLF3

VTTLF

+V3.3S_HV

C5E10

0.1uF

10%

.

SMC0402

.

SMC0402

2

U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1

B22 B21 A21

BF21 BH20 BG20 BF20

K47

+V3.3S_HV

C35 B35 A35

V48 U48 V47 U47 U46

AH48 AF48 AH47 AG47

+VTTLF_CAP1

A8

+VTTLF_CAP2

L1

+VTTLF_CAP3

AB2

C4E5

0.47uF

SMC0402

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

C4E6

0.47uF

SMC0603

+V1.05M_AXF

C4E14

1.0uF

20%

20% SMC0402

SMC0402

+V1.8_SM_CK

C4D2

0.1uF

10%

.

SMC0402

.

SMC0402

+V1.8_TXLVDS

R5E4

R5E4 0

0

5%

5% NO_STUFF

NO_STUFF

+VCC_PEG7 +V1.05M9,15,35,47,55

+VCC_DMI

C4T8

C4E8

0.47uF

SMC0402

NO_STUFF

CANTIGA (5 OF 6)

355659

C4E9

2.2uF

10%

10% .

SMC0805

.

SMC0805

R4D2

SMR0402

C5E6

C5E6 1000pF

1000pF

10%

10% .

.

SMC0402

C5E4

4.7uF

10%

10% .

SMC0805

.

SMC0805

C5E1

0.1uF

10%

10% SMC0402

SMC0402

C4E13

0.47uF

SMC0402

NO_STUFF

1.001%

.

C4E7

4.7uF

10%

10% .

SMC0805

.

SMC0805

1 2

C4E15

C4E15 10uF

10uF

20%

20% SMC0805

SMC0805

+V1.8_SMCK_RC

C5E3

C5E3 22uF

22uF

20%

20% .

SMC0805

.

SMC0805

R5E1

1 2

0.002

+VCC_DMI

C4T9

0.47uF

NO_STUFF

+VCCP_GMCH6 +V1.05S4,9,24,47,55

C4E10

C4F2

C4F2 270uF

270uF

4.7uF

20%

10%

10% .

SMC0805

.

SMC0805

SMC7343

R4F2 0

+V1.05M_AXF_R

SMR1210

1 2

1uH

30%

30% SML0805

SML0805

C4D1

C4D1 10uF

10uF

20%

.

SMC0805

.

SMC0805

L5E1

1 2

0.10uH

20%

C5E15

C5E15 22uF

22uF

SML0805

20%

.

SMC0805

.

SMC0805

.

+

+VCC_PEG7

To use seperate filters for VCC_PEG & VCC_DMI rails No-Stuff R5E1 and stuff L5D1 ,C5C9 & R5D7

NO_STUFF

+

C5C9

+

C5C9 220uF

220uF

10%

SMC7343

L4D1

+V_TXLVDS_PM

C6E11

C6E11 220uF

220uF

10%

SMC7343

R4F5

1 2

+V1.8_SM_CK_RR

R5E3 0

1 2

SMR1210

SMR1210FB4F1

L5D1

91nH

20%

20% SML1210-STD

SML1210-STD NO_STUFF

NO_STUFF

2

0.002

R4F4

0.002

.

+V1.8_LDO46

R5F3

0.002

NO_STUFF

1 2

+V1.05M_PEG_LR

+V1.05M_DMI_LR

10 58Tuesday, August 28, 2007

1

+V1.25S_1.05M_CANTIGA7,9

R4D1

1 2

R5F4

1 2

0.002

Intel Confidential

1

+V1.8_GMCH7,9

0.002

+V1.89,13,14,46,48,55,57

R6E3

1 2

.

NO_STUFF

R6E2

1 2

0.002

R5D7

0.002

NO_STUFF

+V1.05S4,9,24,47,55

1.0

+V1.05M9,15,35,47,55

5

U5E1I

AU48

VSS_1

AR48

VSS_2

AL48

VSS_3

BB47

VSS_4

AW47

VSS_5

AN47

VSS_6

AJ47

VSS_7

AF47

VSS_8

AD47

VSS_9

AB47

BD46

BA46 AY46

AV46 AR46 AM46

BF44 AH44 AD44

AA44

M44

BC43

AV43 AU43 AM43

C43

BG42

AY42

AT42 AN42

AJ42

AE42

N42

BD41 AU41 AM41 AH41 AD41

AA41

U41

M41 G41

BG40

BB40

AV40 AN40

H40

AT39 AM39

AJ39

AE39

N39

BH38 BC38

BA38 AU38 AH38 AD38

AA38

U38

C38 BF37 BB37

AW37

AT37

AN37

AJ37

H37

C37

BG36 BD36

AK15

AU36

Y47 T47 N47 L47 G47

V46 R46 P46 H46 F46

Y44 U44 T44

F44

L42

Y41

T41

B41

E40

L39 B39

Y38

T38

F38

J43

J38

VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

CANTIGA_1p2

VSS

D D

C C

B B

A A

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23

5

4

U5E1J

BG21

AW21

AU21 AP21 AN21 AH21 AF21 AB21

BC20 BA20

AW20

AT20

AJ20

AG20

BG19

BG17

BC17

AW17

AT17

BA16

AU16 AN16

BG15

AC15

W15

BG14

AA14

BG13

BC13 BA13

AN13

AJ13

AE13

BF12 AV12 AT12

AM12

AA12

BD11 BB11 AY11 AN11 AH11

BG10

AV10 AT10

AJ10 AE10 AA10

AM9

R21 M21

G21

Y20 N20 K20 F20 C20 A20

A18

R17 M17 H17 C17

N16 K16 G16 E16

A15

C14

N13

G13 E13

A12

Y11 N11 G11 C11

M10 BF9 BC9 AN9

AD9

BH8 BB8 AV8 AT8

L12

J21

L13

J12

G9 B9

CANTIGA_1p2

VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233

VSS_235

VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252

VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273

VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296

VSS

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

VSS NCTF

VSS_NCTF_15 VSS_NCTF_16

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4

VSS_SCB_6

VSS SCB

NC

VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325

VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350

VSS_351 VSS_352 VSS_353 VSS_354 VSS_355

NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 NC_43

AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4

BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1

U24 U28 U25 U29 AJ6

AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17

BH48 BH1 A48 C1

A3

E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48 A47

4

MCH_VSS_351 MCH_VSS_352 MCH_VSS_353 MCH_VSS_354 MCH_VSS_355

3

R4T4 0R4T4 0 R5T12 0R5T12 0 R4T5 0R4T5 0 R5T13 0R5T13 0 R4R13 0

R4R13 0

.

23,40,43,44,46,47,49,55,57

PM_SLP_S3#

2

+V5S 5,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57

R3R9

R3R9 10K

10K

5%

U3D1 SC1563U3D1 SC1563

5

C3D2

1.0uF

10%

3

Q3D1

Q3D1 BSS138

1

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

BSS138

2

CANTIGA (6 OF 6)

355659

IN

1

SHDN

GND2ADJ

PM_SLP_S3_SHDN2

R3R11

R3R11 100

100

5%

5% NO_STUFF

NO_STUFF

2

4

OUT

3

TVDAC_ADJ2

V3.3S_TVDAC_R2

R3R7

17.8K

1%

R3R10

R3R10 10K

10K

1%

C3D1

C3D1 22uF

22uF

C3R1

0.1uF

10%

.

R3D2

0.011%

1

+V1.5S4,10,24,28,47,55,57

11 58Tuesday, August 28, 2007

1

CR3R2

CR3R2 BAT54

BAT54

NO_STUFF

3

V1_5SFOLLOW

12

R3R8

R3R8 10

10

5%

5% NO_STUFF

NO_STUFF

+V3.3S_TVDAC10,48,55

Intel Confidential

1.0

5

Layout Note: Location of all MCH_CFG strap resistors needs to be close to trace to minimize stub

MCH_CFG_57

DMI X2 Select

MCH_CFG_5

D D

Low = DMIx2 High = DMIx4 (default)

R1T11

2.21K

1%

1% NO_STUFF

NO_STUFF

4

MCH_CFG_77

MCH_CFG_7 ME TLS Confidentiality (Isolation Bypass Enable)

Low = AMT Firmware will use TLS cipher suite with no confidentiality (Isolators are bypassed] High = AMT Firmware will use TLS cipher suite with Confidentiality {Isolators are active (Default)}

R1T9

2.21K

1%

1% NO_STUFF

NO_STUFF

3

Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe

MCH_CFG_20 Low = Only Digital Display Port (SDVO/DP/iHDMI) or

PCIE or is operational (Default) High = Digital Display Port (SDVO/DP/iHDMI) and PCIE are operating simultaneously via PEG port

2

+V3.3S5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R5P7

4.02K

1%

1% NO_STUFF

NO_STUFF

MCH_CFG_207,19

1

GMCH Fan Power Control

MCH_CFG_167

FSB Dynamic ODT

MCH_CFG_16

C C

PCI Express Graphics Lane

MCH_CFG_9 Low = Reverse Lane (default)

Low = Dynamic ODT Disabled High = Dynamic ODT Enabled (default)

MCH_CFG_97

High = Normal operation

+V3.3S

R1E1

2.21K

1%

1% NO_STUFF

NO_STUFF

R1U4

2.21K

1%

1% .

.

MCH_PWM_FAN40,43

MCH_CFG_67

stuff J1C3 to enable ITPM

MCH_CFG_6 (iTPM Host Interface) Low = iTPM Host Interface is enabled High = iTPM Host Interface is Disabled (default)

R4P2

R4P2 15K

15K

1%

1% .

.

R1T7

2.21K

1%

1% .

.

MCH_CFG_6_R

12

J1C3J1C3

C3P4

0.1uF

10%

.

OPA567_POSIN_R

C4C19

C4C19 1uF

1uF

10%

+V5S5,11,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57

C3C13

4.7uF

10%

10% .

.

1

101112

EU4C1

V+

_

8

OPA567

9

+

V-

456

.

TF

IS

HS

13

2

EN

OUT

IF

3

.

7

OPA567_ISIN_MCH_R

OPA567_NEGIN_R

R4P1

R4P1 20K

20K

5%

MCH_TACHO_OP_FAN

CR3P1

CR3P1 BAT54

BAT54

R3P2

1.74K

1%

R4C25

3.32K

1%

2

11332

MCH_TACHO_R_FAN

J3C2

3

1

CONN3_HDR

R3P4

R3P4 0

0

.

+V3.3S5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R3P3

R3P3 1K

1K

1%

1% .

.

MCH_TACHO_FAN 40,43

DMI Lane Reversal

MCH_CFG_19

B B

Low = Normal (default) High = Lanes Reversed

MCH_CFG_107

MCH_CFG_127

MCH_CFG_137

MCH_CFG_197

R1T12

2.21K

1%

1% NO_STUFF

NO_STUFF

R5F11

4.02K

1%

1% NO_STUFF

NO_STUFF

R1T15

2.21K

1%

1% NO_STUFF

NO_STUFF

R1T17

2.21K

1%

1% NO_STUFF

NO_STUFF

1

2N3904

7481_D1P_Q

7481_D1N_Q

3

Q3C3

2

Place in IMVP_6 Hot Spot

Design Note: Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time

R3B16

R3B16 0

0

.

R3B18

R3B18 0

0

.

C3N9

C3N9 1000pF

1000pF

10%

+V3.3S5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

C3B7

R3B20

R3B20 10K

10K

1%

NO_STUFF

7481_D1P 7481_D1N

C3B7

0.1uF

20%

U3B2

1

VDD

2

D1+

3

D1-

ALRT#/THM2#

4

THM#

5

GND

ADT7481ARMZ-1 TEMP MON

Place ADT7481 near Air inlet not under SODIMM

SCLK

SDATA

D2+

10 9 8 7 6

D2-

7481_THRM#

A A

XOR / ALLZ / Clock Un-gating

MCH_CFG_13 MCH_CFG_12 Configuration

0 1 0 1

MCH_CFG_10 (PCIE Loopback enable) Low = Enabled High = Disabled (Default)

5

4

Reserved

0

XOR Mode Enabled

0

All-Z Mode Enabled

1

Normal Operation (Default)

1

3

IMVP6 & Amb Thermal sensors

+V3.3S5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R3B21

R3B21 10K

10K

1%

NO_STUFF

SMB_THRM_CLK 5,40,43

7481_D2P 7481_D2P_Q

7481_D2N

Title

Size Document Number Rev

Date: Sheet of

SMB_THRM_DATA 5,40,43

C3N8

C3N8 1000pF

1000pF

10%

Pillar Rock

CANTIGA STRAPPING

355659

A

355659

A

355659

A

R3B15

R3B15 0

0

.

R3B17

R3B17 0

0

.

7481_D2N_Q

2

7481_THRM2#

3

Q3B1

1

2N3904

2

Spare sensor, For Amb. temp sensor

R3N24

NO_STUFF

0

R3N23

R3N23 0

0

12 58Tuesday, August 28, 2007

1

Intel Confidential

PM_THRM# 5,23,40,43

1.0

5

4

3

2

1

D D

M_A_A[14:0]8,15

M_A_BS28,15

M_A_BS08,15 M_A_BS18,15 M_CS#07,15 M_CS#17,15

R3C6

R3C6 10K

10K

5%

5% .

.

M_CLK_DDR07 M_CLK_DDR#07 M_CLK_DDR17 M_CLK_DDR#17 M_CKE07,15 M_CKE17,15 M_A_CAS#8,15 M_A_RAS#8,15 M_A_WE#8,15

SMB_CLK_M214,15,23 SMB_DATA_M214,15,23

M_ODT07,15 M_ODT17,15 M_A_DM[7:0]8

M_A_DQS[7:0]8

M_A_DQS#[7:0]8

C C

Note: SO-DIMM0 SPD Address is 0xA0 SO-DIMM0 TS Address is 0x30

R3C5

R3C5 10K

10K

5%

5% .

.

B B

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

SA0_DIM0 SA1_DIM0

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

J5P1A CON200_DDR2-SODIMM-STANJ5P1A CON200_DDR2-SODIMM-STAN

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

110

S0#

115

S1#

30

CK0

32

CK0#

164

CK1

166

CK1#

79

CKE0

80

CKE1

113

CAS#

108

RAS#

109

WE#

198

SA0

200

SA1

197

SCL

195

SDA

114

ODT0

119

ODT1

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

11

DQS#0

29

DQS#1

49

DQS#2

68

DQS#3

129

DQS#4

146

DQS#5

167

DQS#6

186

DQS#7

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

M_A_DQ0

5

M_A_DQ1

7

M_A_DQ2

17

M_A_DQ3

19

M_A_DQ4

4

M_A_DQ5

6

M_A_DQ6

14

M_A_DQ7

16

M_A_DQ8

23

M_A_DQ9

25

M_A_DQ10

35

M_A_DQ11

37

M_A_DQ12

20

M_A_DQ13

22

M_A_DQ14

36

M_A_DQ15

38

M_A_DQ16

43

M_A_DQ17

45

M_A_DQ18

55

M_A_DQ19

57

M_A_DQ20

44

M_A_DQ21

46

M_A_DQ22

56

M_A_DQ23

58

M_A_DQ24

61

M_A_DQ25

63

M_A_DQ26

73

M_A_DQ27

75

M_A_DQ28

62

M_A_DQ29

64

M_A_DQ30

74

M_A_DQ31

76

M_A_DQ32

123

M_A_DQ33

125

M_A_DQ34

135

M_A_DQ35

137

M_A_DQ36

124

M_A_DQ37

126

M_A_DQ38

134

M_A_DQ39

136

M_A_DQ40

141

M_A_DQ41

143

M_A_DQ42

151

M_A_DQ43

153

M_A_DQ44

140

M_A_DQ45

142

M_A_DQ46

152

M_A_DQ47

154

M_A_DQ48

157

M_A_DQ49

159

M_A_DQ50

173

M_A_DQ51

175

M_A_DQ52

158

M_A_DQ53

160

M_A_DQ54

174

M_A_DQ55

176

M_A_DQ56

179

M_A_DQ57

181

M_A_DQ58

189

M_A_DQ59

191

M_A_DQ60

180

M_A_DQ61

182

M_A_DQ62

192

M_A_DQ63

194

M_A_DQ[63:0] 8

+V3.3M14,15,23,35,55,57

To connect TS on DIMM0&1 o/p to H8, stuff R5P3 and no-stuff R5P1

+V3.3S

PM_EXTTS#0_DIMM0_115,40

Layout Note: Place these Caps near SO-DIMM0.

+V1.89,10,14,46,48,55,57

R5C3 0.002

R4C1 0.022R4C1 0.022

TS#_DIMM0_17,14

R5P1 10KR5P1 10K

M_VREF_DIMM048

+V1.8_DIMM0

C4C8

0.1uF

10%

.

Layout Note: Place these Caps near SO-DIMM0.

1%

C5C1

C5C1 330uF

330uF

20%

2.5V

C4C9

0.1uF

10%

.

C4C13

2.2uF

10%

.

C4C10

0.1uF

10%

.

+V3.3M_DIMM0

C3C7

0.1uF

10%

.

C6P2

0.1uF

10%

.

C5C5

0.1uF

10%

.

C5C3

2.2uF

10%

.

R5P3

0NO_STUFF

C4C12

2.2uF

10%

.

C4C7

2.2uF

10%

10% .

.

C6P1

2.2uF

10%

10% .

.

C5C4

2.2uF

10%

.

+V1.8_DIMM0

C4C11

2.2uF

10%

.

J5P1B CON200_DDR2-SODIMM-STANJ5P1B CON200_DDR2-SODIMM-STAN

112

VDD1

111

VDD2

117

VDD3

96

VDD4

95

VDD5

118

VDD6

81

VDD7

82

VDD8

87

VDD9

103

VDD10

88

VDD11

104

VDD12

199

VDDSPD

83

NC1

120

NC2

50

EVENT#

69

NC4

163

NCTEST

1

VREF

201

GND0

202

GND1

47

VSS1

133

VSS2

183

VSS3

77

VSS4

12

VSS5

48

VSS6

184

VSS7

78

VSS8

71

VSS9

72

VSS10

121

VSS11

122

VSS12

196

VSS13

193

VSS14

8

VSS15

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162

A A

5

4

3

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

DDR2 SODIMM 0

355659

A

355659

A

355659

A

2

13 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

5

4

3

2

1

D D

M_B_A[14:0]8,15

M_B_BS28,15

M_B_BS08,15 M_B_BS18,15 M_CS#27,15

M_CS#37,15 M_CLK_DDR37 M_CLK_DDR#37

R4B24

R4B24 10K

10K

5%

5% .

.

M_CLK_DDR47 M_CLK_DDR#47 M_CKE37,15 M_CKE47,15 M_B_CAS#8,15 M_B_RAS#8,15 M_B_WE#8,15

SMB_CLK_M213,15,23 SMB_DATA_M213,15,23

M_ODT27,15 M_ODT37,15 M_B_DM[7:0]8

M_B_DQS[7:0]8

M_B_DQS#[7:0]8

C C

Note: SO-DIMM1 SPD Address is 0xA4 SO-DIMM1 TS Address is 0x34

+V3.3M13,15,23,35,55,57

R3B23

R3B23 10K.5%

10K.5%

B B

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

SA0_DIM1 SA1_DIM1

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

J5N1A CON200_DDR2-SODIMM-REVJ5N1A CON200_DDR2-SODIMM-REV

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

110

S0#

115

S1#

30

CK0

32

CK0#

164

CK1

166

CK1#

79

CKE0

80

CKE1

113

CAS#

108

RAS#

109

WE#

198

SA0

200

SA1

197

SCL

195

SDA

114

ODT0

119

ODT1

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

11

DQS#0

29

DQS#1

49

DQS#2

68

DQS#3

129

DQS#4

146

DQS#5

167

DQS#6

186

DQS#7

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

M_B_DQ0

5

M_B_DQ1

7

M_B_DQ2

17

M_B_DQ3

19

M_B_DQ4

4

M_B_DQ5

6

M_B_DQ6

14

M_B_DQ7

16

M_B_DQ8

23

M_B_DQ9

25

M_B_DQ10

35

M_B_DQ11

37

M_B_DQ12

20

M_B_DQ13

22

M_B_DQ14

36

M_B_DQ15

38

M_B_DQ16

43

M_B_DQ17

45

M_B_DQ18

55

M_B_DQ19

57

M_B_DQ20

44

M_B_DQ21

46

M_B_DQ22

56

M_B_DQ23

58

M_B_DQ24

61

M_B_DQ25

63

M_B_DQ26

73

M_B_DQ27

75

M_B_DQ28

62

M_B_DQ29

64

M_B_DQ30

74

M_B_DQ31

76

M_B_DQ32

123

M_B_DQ33

125

M_B_DQ34

135

M_B_DQ35

137

M_B_DQ36

124

M_B_DQ37

126

M_B_DQ38

134

M_B_DQ39

136

M_B_DQ40

141

M_B_DQ41

143

M_B_DQ42

151

M_B_DQ43

153

M_B_DQ44

140

M_B_DQ45

142

M_B_DQ46

152

M_B_DQ47

154

M_B_DQ48

157

M_B_DQ49

159

M_B_DQ50

173

M_B_DQ51

175

M_B_DQ52

158

M_B_DQ53

160

M_B_DQ54

174

M_B_DQ55

176

M_B_DQ56

179

M_B_DQ57

181

M_B_DQ58

189

M_B_DQ59

191

M_B_DQ60

180

M_B_DQ61

182

M_B_DQ62

192

M_B_DQ63

194

M_B_DQ[63:0] 8

+V1.8_DIMM1

C4B20

C4B22

0.1uF

10%

.

Layout Note: Place these Caps near SO-DIMM1.

+V1.8_DIMM1

C5B4

2.2uF

10%

.

Layout Note: Place these Caps near SO-DIMM1.

C4B21

2.2uF

10%

.

0.1uF

10%

.

C4B18

2.2uF

10%

.

C4B19

0.1uF

10%

.

C5B6

2.2uF

10%

.

C4B23

0.1uF

10%

.

C4B17

2.2uF

10%

.

C5B5

C5B5 330uF

330uF

20%

+V3.3M13,15,23,35,55,57

R4B23 0.022R4B23 0.022

TS#_DIMM0_17,13

M_VREF_DIMM148

R5B6 0.002

1%

+V3.3M_DIMM1

C6N10

0.1uF

10%

.

+V1.89,10,13,46,48,55,57

C3B8

0.1uF

10%

.

C6N11

2.2uF

10%

.

+V1.8_DIMM1

C3B9

2.2uF

10%

.

J5N1B CON200_DDR2-SODIMM-REVJ5N1B CON200_DDR2-SODIMM-REV

112

VDD1

111

VDD2

117

VDD3

96

VDD4

95

VDD5

118

VDD6

81

VDD7

82

VDD8

87

VDD9

103

VDD10

88

VDD11

104

VDD12

199

VDDSPD

83

NC1

120

NC2

50

EVENT#

69

NC4

163

NCTEST

1

VREF

201

GND0

202

GND1

47

VSS1

133

VSS2

183

VSS3

77

VSS4

12

VSS5

48

VSS6

184

VSS7

78

VSS8

71

VSS9

72

VSS10

121

VSS11

122

VSS12

196

VSS13

193

VSS14

8

VSS15

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57

18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162

SO-DIMM1 is placed farther from the GMCH than SO-DIMM0

A A

5

4

3

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

DDR2 SODIMM 1

355659

A

355659

A

355659

A

2

14 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

5

4

3

2

1

Layout Note: Place Q5N2 under DIMM0

DDR_THERM1

2

Q5N2

1

2N3904

D D

2N3904

3

PM_EXTTS#1_R7

On Board DDR2 Thermal Sensor

+V3.3M 13,14,23,35,55,57

U5P1

1

DDR_THERM2

PM_EXTTS#1_D

R5P4

R5P4 0

0

.

VDD

2

D+

3

D-

THERM#4GND

ADM1032AR

Layout Note: Place U5P1 under DIMM1

SCLK

SDATA

ALERT#

8

7

PM_EXTTS#0_D

6

5

+V0.9 46,55

C4C3

0.1uF

10%

.

C5C6

0.1uF

10%

.

R5P6

R5P6 0

0

NO_STUFF

C4C15

0.1uF

10%

.

C4B29

0.1uF

10%

.

SMB_CLK_M2 13,14,23

SMB_DATA_M2 13,14,23

PM_EXTTS#0_DIMM0_1 13,40

Layout note: Place one cap close to every 2 pullup resistors terminated to +V0.9

C4B25

C4C5

0.1uF

10%

.

C4B15

0.1uF

10%

.

C4B25

0.1uF

10%

.

C4B28

0.1uF

10%

.

C4B16

0.1uF

10%

.

C4C18

0.1uF

10%

.

C4B12

0.1uF

10%

.

C4C17

0.1uF

10%

.

C4B26

0.1uF

10%

.

C4C16

0.1uF

10%

.

C4B27

0.1uF

10%

.

C5B3

0.1uF

10%

.

C4C1

0.1uF

10%

10% .

.

C4B24

0.1uF

10%

10% .

.

C4B14

0.1uF

10%

.

C4C2

0.1uF

10%

.

C4C6

0.1uF

10%

.

C5C2

0.1uF

10%

.

C4C4

0.1uF

10%

.

C4B9

0.1uF

10%

.

C4B11

0.1uF

10%

.

C4B10

0.1uF

10%

.

C4C14

0.1uF

10%

10% .

.

C C

Voltage Buffer Translator for MCH ME JTAG

+V3.3M13,14,23,35,55,57

R6M7

R6M4

1K

.

R6A2

GTL2005_JTAG_REF

.

MCH_TDI_R MCH_TCK_R

MCH_TMS_R

R6M4

2.37K

1%

.

R6A3

R6A3 806

806

1%

C6A1

0.1uF

20%

TP_GTL2005_JTAG_A3

GTL2005_JTAG_DIR1 ME_JTAG_TCK_BUFFER

NO_STUFF

U6M1

1

DIR

2

A0

3

A1

4

GTLREF

5

A2

6

A3 GND17GND2

GTL2005

+V3.3M13,14,23,35,55,57

+V1.05M9,10,35,47,55

MCH_RSVD_10 JTAG_TCK MCH_RSVD_11 JTAG_TDI MCH_RSVD_12 JTAG_TDO MCH_RSVD_13 JTAG_TMS

MCH_TDI7 MCH_TCK7

MCH_TMS7

B B

R6M8 100R6M8 100 R6M6 100R6M6 100

R6M2 100R6M2 100

1K

.

R6A6

R6A5

10K

.

R6A4

R6A4 10K

10K

VCC

GND3

B0 B1

B2 B3

+V3.3M13,14,23,35,55,57

C6M7

0.1uF

20%

14 13 12 11 10 9 8

10K

R6M9

R6M5

GTL2005_JTAG_B3

R6A19

R6A18

10K

10K NO_STUFF

5%

10K

NO_STUFF

R6M3

ME_JTAG_TDI_BUFFER ME_JTAG_TCK_BUFFER

ME_JTAG_TMS_BUFFER

R6A17

10K

5%

R6M1

R6M1 1K

1K

5%

5% .

.

ME_JTAG_TMS_BUFFER

ME_JTAG_TDI_BUFFER

ME_JTAG_TDO_BUFFER

J5A2

1 2 3 4 5 6

RJ-11_JACK_Vertical-Mount

.

+V0.9 46,55

R5C1 56R5C1 56 R5C4 56R5C4 56 R5B4 56R5B4 56 R5B7 56R5B7 56

R4C22 56R4C22 56 R4C12 56R4C12 56 R4B34 56R4B34 56 R4B22 56R4B22 56

R4C13 56R4C13 56 R4C20 56R4C20 56 R5C2 56R5C2 56

R4C9 56R4C9 56 R4C10 56R4C10 56 R4C21 56R4C21 56

R4B14 56R4B14 56 R4B31 56R4B31 56 R5B5 56R5B5 56

R4B15 56R4B15 56 R4B21 56R4B21 56 R4B32 56R4B32 56

R4C23 56R4C23 56 R4C11 56R4C11 56 R4B33 56R4B33 56 R4B16 56R4B16 56

R4C19 56R4C19 56 R4C7 56R4C7 56 R4C18 56R4C18 56 R4C6 56R4C6 56 R4C17 56R4C17 56 R4C4 56R4C4 56 R4C16 56R4C16 56 R4C15 56R4C15 56 R4C5 56R4C5 56 R4C2 56R4C2 56 R4C8 56R4C8 56 R4C14 56R4C14 56 R4C3 56R4C3 56 R4C24 56R4C24 56 R5C5 56R5C5 56

R4B30 56R4B30 56 R4B13 56R4B13 56 R4B28 56R4B28 56 R4B19 56R4B19 56 R4B29 56R4B29 56 R4B11 56R4B11 56 R4B27 56R4B27 56 R4B26 56R4B26 56 R4B12 56R4B12 56 R4B17 56R4B17 56 R4B20 56R4B20 56 R4B25 56R4B25 56 R4B18 56R4B18 56 R4B35 56R4B35 56 R5B8 56R5B8 56

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

M_A_A14

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11

M_B_A12 M_B_A13 M_B_A14

M_CKE0 7,13 M_CKE1 7,13 M_CKE3 7,14 M_CKE4 7,14

M_ODT0 7,13 M_ODT1 7,13 M_ODT2 7,14 M_ODT3 7,14

M_A_BS0 8,13 M_A_BS1 8,13 M_A_BS2 8,13

M_A_WE# 8,13 M_A_CAS# 8,13 M_A_RAS# 8,13

M_B_BS0 8,14 M_B_BS1 8,14 M_B_BS2 8,14

M_B_WE# 8,14 M_B_CAS# 8,14 M_B_RAS# 8,14

M_CS#0 7,13 M_CS#1 7,13 M_CS#2 7,14 M_CS#3 7,14

M_A_A[14:0] 8,13

M_B_A[14:0] 8,14

VCC

GND3

B0 B1

B2 B3

+V3.3M13,14,23,35,55,57

C6M2

0.1uF

20%

14

ME_JTAG_TDO_BUFFER_R

13

TP_GTL2005_JTAG_B1

12 11

TP_GTL2005_JTAG_B2

10

TP_GTL2005_JTAG_B3

9 8

R6M11 22R6M11 22

3

R6M12

R6M12 10K

10K

NO_STUFF

ME_JTAG_TDO_BUFFER

C6M6

C6M6 220PF

220PF

Intel Confidential

15 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

DDR2 TERMINATION, THERMAL SENSOR AND ME JTAG

355659

A

355659

A

355659

A

2

R6A13

R6A13 10K

5%

.

R6A11 1K

R6A9 1K

10K

NO_STUFF

GTL2005_JTAG_DIR2

R6A12

R6A12 10K

10K

.

GTL2005_JTAG_A2

GTL2005_JTAG_A3

5%

.

R6A7 1K

U6M2

1

DIR

2

A0

3

A1

4

GTLREF

5

A2

6

A3 GND17GND2

GTL2005

4

R6A8

3.24K

1%

1% .

.

GTL2005_JTAG_REF2

R6M10

C6M5

1K

0.1uF

5%

5% .

.

MCH_TDO7

GTL2005_JTAG_A1

A A

R6A10 22.1KR6A10 22.1K

5

+V3.3S

4

+V3.3S5,7,10,12,13,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

U2M2

8

VP

C2N3

0.1uF

20%

3

2

1

R6T5

R6T5 10K

+V3.3S

1 4 9 19

24 22 18 17 14

CRT_Q_RED

23

CRT_Q_GREEN

21

CRT_Q_BLUE

16

CRT_Q_VSYNC

15

CRT_Q_HSYNC

13

10K

NO_STUFF

R6T4

R6T4 1K

1K

NO_STUFF

D D

DOCK_CRT_EN#_R

R6T3

C6T6

0.1uF

20%

R6T3 0

0

.

12

11

10 20

C6T7

0.1uF

20%

2 5 6 8

3 7

U6E4

SEL

Y_A Y_B Y_C Y_D Y_E

GND1 GND2 GND3 GND4

PI3V512QE

VDD1 VDD2 VDD3 VDD4

I_A0 I_B0 I_C0 I_D0 I_E0

I_A1 I_B1 I_C1 I_D1 I_E1

DOCK_CRT_EN#41

DOCK_CRT_EN#_R

C C

CRT_RED7 CRT_GREEN7 CRT_BLUE7 CRT_VSYNC7 CRT_HSYNC7

+V3.3S

C6T5

C6E9

0.1uF

20%

B B

DOCK_CRT_EN#_R CRT_EN#

+V3.3S

R6T1

2.2K

CRT_DDC_DATA_MCH7

CRT_DDC_DATA_DOCK44

+V3.3S

A A

CRT_DDC_CLK_MCH7

CRT_DDC_CLK_DOCK44

R6T2

2.2K

5

CRT_L2_RED CRT_L2_BLUE CRT_L2_GREEN CRT_Q_HSYNC

CRT_RED_DOCK 44 CRT_GRN_DOCK 44 CRT_BLUE_DOCK 44 CRT_VSYNC_DOCK 44 CRT_HSYNC_DOCK 44

5

U6T1

2 4

INVERTER

3

U6E1

1

1OE#

VCC

2

1A

2OE#

3

1B

2B

4

GND

2A

SN74CBTD3306C

U6E3

1

1OE#

VCC

2

1A

2OE#

3

1B

2B

4

GND

2A

SN74CBTD3306C

4

1 2 3 4

+V3.3S5,7,10,12,13,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

8 7 6 5

I/O1 I/O2 I/O3 I/O4

ESD DIODE ARRAY

C6T3

0.1uF

20%

CRT_DDC_DATA_ISO

CRT_DDC_CLK_ISO

10

I/O8

9

I/O7

7

I/O6 I/O5

VN

5

Note: For video bandwidths > 200MHz: C3B1, C3A4, C2B1, C2A5, C2B2, C2N1 = 3.3pF C3M3, C2A4, C2A6 = No_Stuff FB3A1, FB2A4, FB2B1 = Short

+V5S5,11,12,17,18,24,28,30,31,32,39,48,49,52,55,56,57

C6T2

0.1uF

20%

+V5S5,11,12,17,18,24,28,30,31,32,39,48,49,52,55,56,57

C6T4

0.1uF

20%

3

6

CRT_Q_VSYNC

+V5S5,11,12,17,18,24,28,30,31,32,39,48,49,52,55,56,57

+VBATS19,27,30,31,55,57 +V5S_F_DAC

R2N11KR2N1 1K

DDC_GATE

R2N2

R2N2 100K

100K

.

CRT_DDC_DATA_ISO

CRT_DDC_CLK_ISO

FB3B1

CRT_Q_RED

R3B1

R3B1 150

150

1%

CRT_Q_GREEN CRT_L2_GREEN

CRT_Q_BLUE

CRT_Q_VSYNC

CRT_Q_HSYNC

R3B2

R3B2 150

150

1%

R2B1

R2B1 150

150

1%

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

CRT

355659

A

355659

A

355659

A

C3B1

C3B1 10pF

10pF

5%

5% .

.

C2B1

C2B1 10pF

10pF

5%

5% .

.

C2B2

C2B2 10pF

10pF

5%

5% .

.

FB3B1

47ohm@100MHz

FB3B2

47ohm@100MHz

FB2B2

47ohm@100MHz

2

CRT_L_RED

CRT_L_GREEN

CRT_L_BLUE

C3A4

C3A4 22pF

22pF

5%

5% .

.

C2A5

C2A5 22pF

22pF

5%

5% .

.

C2N1

C2N1 22pF

22pF

5%

5% .

.

C3M4

C3M4 33pF

33pF

5%

5% NO_STUFF

NO_STUFF

2

1

3

DDC_SRC

R2M3

2.2K

FB3A1

47ohm@100MHz

FB2A4

47ohm@100MHz

FB2B1

47ohm@100MHz

C3M5

C3M5 33pF

33pF

5%

5% NO_STUFF

NO_STUFF

+

1 2

Q2A1

Q2A1 BSS138

BSS138

R2M4

2.2K

.

C3M3

C3M3 10pF

10pF

5%

5% .

.

C2A4

C2A4 10pF

10pF

5%

5% .

.

C2A6

C2A6 10pF

10pF

5%

5% .

.

F2A1

1.1A

CRT_L2_BLUE

CRT_L2_RED

FB2M1

FB2M1 50OHM

50OHM

+V5S_L_DAC

CR2N1

Clamping-Diode

GND1

GND1 RED

RED GND2

GND2 GRN

GRN GND3

GND3 BLU

BLU VCC

VCC NC1

NC1 GND4

GND4 GND5 CLK

GND5 CLK

Intel Confidential

16 58Tuesday, August 28, 2007

1

2 1

J2A2B

19 14 18 13 17 12 16 11 15 10 20

2IN1

CR2M1

2 1

Clamping-Diode

NC2

24

DATA

23

HSYNC

22

VSYNC

21

1.0

5

4

3

+V3.3S5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

2

1

+V5S5,11,12,16,18,24,28,30,31,32,39,48,49,52,55,56,57

R6U19

0.002

R6U20

0.002

1%

+V5S_LVDS_BKLT

0.002

1%

+VBAT49,53,55,56,57

R6F15

0.002

1%

+VCC_LVDS_BKLT+V3.3S_LVDS_DDC

D D

C6F6

C6U2

0.1uF

20%

C6F6

0.1uF

10%

+V5S_LVDS_BKLT

DBL_CLK

R6U18

R6U18 100K

100K

+VCC_LVDS_BKLT

17 58Tuesday, August 28, 2007

1

J6F1

1

VDD_BLI

2

VSS_BLI

3

VSS_DBC

4

VDD_DBC

5

DBL_CLK

6

DBL_DATA

7

ENA_BL

8

NC1

9

VDD_ALS

10

VSS_ALS

11

ALS_CLK

12

ALS_DATA

13

ALS_INTR

14

NC2

15

VSS_VDL

16

VDD_VDL1

17

VDD_VDL2

18

VDD_VCL

19

RSVD

20

VCL_CLK

21

VCL_DATA

22

A0M

23

A0P

24

VSS_SHIELD1

25

A1M

26

A1P

27

VSS_SHIELD2

28

A2M

29

A2P

30

VSS_SHIELD3

31

A3M

32

A3P

33

VSS_SHIELD4

34

VDL_CLKAM

35

VDL_CLKAP

36

VSS

37

B0M

38

B0P

39

VSS_SHIELD5

40

B1M

41

B1P

42

VSS_SHIELD6

43

B2M

44

B2P

45

VSS_SHIELD7

46

B3M

47

B3P

48

VSS_SHIELD8

49

VDL_CLKBM

50

VDL_CLKBP

LVDS,CONN50

Intel Confidential

1.0

C6U9

C6U10

0.1uF

20%

+V3.3S5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V5S5,11,12,16,18,24,28,30,31,32,39,48,49,52,55,56,57

C7T19

0.1uF

20%

U7E6

R6U26

0.002

U7E6

1

OE1#

2

1A

3

1B GND42A

74CBT3306

L_BRIGHTNESS

NO_STUFF

1 2

R6U281MR6U28 1M

R6U23 100KR6U23 100K

L_VDDEN#

3

Q6F2

Q6F2 BSS138

BSS138

2

0.002

VCC

OE2#

R6V4

8 7 6

2B

5

C6V1

C6V1 1000pF

1000pF

10%

LVDS Panel Backlight

C C

BIOS Note: Disable both BKLTSEL lines before enabling one.

For 2.5V panel support, connect an external source to net TP_+V2.5.

B B

+V3.3S

+VDD_VDL

+V3.3S (DEFAULT)

+V5S STUFF R6U26

TP_+V2.5 STUFF R6V4

A A

STRAPPING

STUFF R6V2 NO_STUFF R6U26, R6V4

NO_STUFF R6V2, R6V4

NO_STUFF R6V2, R6U26

LVDS_VDD_EN7

5

L_BKLTSEL0#38 L_BKLT_CTRL7

GMCH_PWM Support

R6V2 0.002

1%

+V5S5,11,12,16,18,24,28,30,31,32,39,48,49,52,55,56,57

12

NO_STUFF

+VDD_VDL

1

R6V1

R6V1 100K

100K

4

20%

L_BKLTSEL1# 38

GM_Data_D Support

LVDS_DDC_CLK7 LVDS_DDC_DATA7

TP_+V2.5

L_VDDEN_D#

TP6G1 NO_STUFFTP6G1 NO_STUFF

R7U2

R7U2 10K

10K

5%

L_CTRL_DATA 7,20

+V3.3S5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R6U25

2.2K

5%

Q6U3

SI2307DS

32

C6F5

C6F5 22UF

22UF

1

C6U1

0.1uF

20%

R6U24

2.2K

5%

L_CTRL_CLK7,20

+VDD_VDL_L

3

+V3.3S

R6U15

R6U15 10K

10K

5%

GM_CLK_D Support

+V3.3S5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

LVDS

355659

A

355659

A

355659

A

C6U9

0.1uF

20%

L_BKLTSEL1#

L_BKLT_EN7

ALS_CLK40 ALS_DATA40 ALS_INTR#40

LVDSA_DATA#07 LVDSA_DATA07

LVDSA_DATA#17 LVDSA_DATA17

LVDSA_DATA#27 LVDSA_DATA27

LVDSA_DATA#37 LVDSA_DATA37

LVDSA_CLK#7 LVDSA_CLK7

LVDSB_DATA#07 LVDSB_DATA07

LVDSB_DATA#17 LVDSB_DATA17

LVDSB_DATA#27 LVDSB_DATA27

LVDSB_DATA#37 LVDSB_DATA37

LVDSB_CLK#7 LVDSB_CLK7

2

U6F1

1

OE#

VCC

2

A

GND3Y

74CBTLV1G125

+V3.3S_LVDS_DDC

+V3.3S5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

5

4

+VDD_VDL_L

5

D D

+V3.3S5,7,10,12,13,16,17,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

U6B1

DOCK_TV_EN#41

TVA_DAC7

TVB_DAC7

TVC_DAC7

12

2 5 6 8

11

3

7 10 20

SEL

Y_A Y_B Y_C Y_D Y_E

GND1 GND2 GND3 GND4

PI3V512QE

VDD1 VDD2 VDD3 VDD4

I_A0 I_B0 I_C0 I_D0 I_E0

I_A1 I_B1 I_C1 I_D1 I_E1

1 4 9 19

24 22 18 17 14

DACA

23 21 16 15

DACC

13

4

TV_DACA_OUT_DOCK 44

TV_DACB_OUT_DOCK 44

TV_DACC_OUT_DOCK 44

DACA

3

Layout Note: Place 150 Ohm termination resistors, ferrite beads and capicators close to connector

FB2A2

12

150ohm@100MHz

C1A3

R1M2

5.6pF

150

8.9%

1%

.

FB2A1

DACBDACB

R2M2

R2M2 150

150

1%

12

C2A3

5.6pF

8.9%

.

FB2A1

150ohm@100MHz

DACA_L

12

C1A1

5.6pF

8.9%

8.9% .

.

DACB_L

12

C2A1

5.6pF

8.9%

8.9% .

.

DACA_L DACB_L DACC_L

2

U2M1

1

I/O1

2

I/O2

3

I/O3

4

I/O4

ESD DIODE ARRAY

Port Value

IO2 IO1 IO0

0 0 0b

0 0 Xb 0 1 0b 0 1 1b 0 1 Xb X 1 0b X 1 1b 1 0 0b 1 0 1b 1 1 0b 1 1 1b

Aspect Ratio

Format 525i (480) 525i (480)0 0 1b 525i (480) 525p (480) 525p (480) 525p (480) 750p (720) 0V 750p (720) 1125i (1080) 1125i (1080) 1125p (1080) 1125p (1080)

+V3.3S5,7,10,12,13,16,17,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

8

VP

VN

5

C2M1

0.1uF

20%

4:3

Letterbox

4:3 4:3 16:9 4:3

Letterbox 2.2V 4:3 16:9 4:3 16:9 4:3 16:9

10

I/O8

9

I/O7

7

I/O6

6

I/O5

1

Voltage

Line3

Line2

Line1

0V

0V 0V16:9 0V 0V 0V 0V

2.2V

2.2V 5V 5V 5V 5V

Note: ESD Diode Array for the TV DAC A, DAC B, DAC C signals located on CRT page.

0V

5V

2.2V

0V

5V

5V 5V 5V

5V

5V 0V

0V

5V 0V

5V 5V

5V

+V3.3S

C C

C6N8

0.1uF

20%

B B

A A

C6N6

0.1uF

20%

C6N4

C6N5

0.1uF

20%

TV_DCONSEL1_LVL TV_DCONSEL0_LVL

+V3.3S

R6D7

2.2K

5%

TV_DCONSEL1_MCH7

TV_DCONSEL1_DOCK44

+V3.3S

R6D5

2.2K

5%

TV_DCONSEL0_MCH7

TV_DCONSEL0_DOCK44

5

DOCK_TV_EN#

4

I2C_RST#

+V3.3S5,7,10,12,13,16,17,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

5

2 4

3

U6D2

1

1OE#

2

1A

3

1B

4

GND

SN74CBTD3306C

U6D1

1

1OE#

2

1A

3

1B

4

GND

SN74CBTD3306C

2OE#

DACC DACC_L

R1M1

R1M1 150

150

1%

+V5S5,11,12,16,17,24,28,30,31,32,39,48,49,52,55,56,57

C2A2

1.0uF

R2A6

R2A6 10K

10K

1%

U6R1

INVERTER

VCC

2B 2A

VCC

2OE#

2B 2A

1.0uF

10%

U2A1

10

9 8 7 6

C6T1

0.1uF

20%

8 7 6 5

VDD SDA SCL INT# RESET#

I2C - PCA9537

TV_EN#

IO_0 IO_1 IO_2 IO_3

VSS

.

R6D6

2.2K

5%

TV_DCONSEL1_LVL

.

R6D4

2.2K

5%

TV_DCONSEL0_LVL

12

C1A4

5.6pF

8.9%

.

1 2 3 4 5

+V5S

FB1A1

150ohm@100MHz

12

DLINE3_IO DLINE2_IO DLINE1_IO

C6R1

0.1uF

20%

C6D8

0.1uF

20%

3

C1A2

5.6pF

8.9%

8.9% .

.

R2A1

5.90K

J2A1

1 2 3 4 5 6 7

CON14_DCONN-CP4120

R2A7

5.90K

CON14_DCONN-CP4120

R2A5

R2A3

4.7K

+V5S5,11,12,16,17,24,28,30,31,32,39,48,49,52,55,56,57

8 9 10 11 12 13 14

R2A2 10KR2A2 10K R2A4 10KR2A4 10K R2M1 10KR2M1 10K

DLINE3 DLINE2 DLINE1

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

TV

355659

Note: Pins 12 & 14 are shorted inside D-Connector plug.

+V5S5,11,12,16,17,24,28,30,31,32,39,48,49,52,55,56,57

U2A2

1

I/O1

2

I/O2

3

I/O3

4

I/O4

ESD DIODE ARRAY

TV-OUT DAC Channel Definition

Channel A (DACA) Channel B(DACB) Luminance (Y) Channel C (DACC)

Composite Video S-Video Component Video CVBS Signal

X

Chrominance (C)

2

C2M2

0.1uF

20%

8

VP

10

I/O8

9

I/O7

7

I/O6

6

I/O5

VN

5

X

Chrominance (Pb) Luminance (Y)X Chrominance (Pr)

18 58Tuesday, August 28, 2007

1

Intel Confidential

DLINE1_IO DLINE2_IO DLINE3_IO

1.0

5

4

3

2

1

PRSNT1#

+12V4 +12V5

GND6 JTAG2 JTAG3 JTAG4 JTAG5 +3.3V2 +3.3V3

PWRGD

GND7

REFCLK+

REFCLK-

GND8

HSIP_0 HSIN_0

GND9

RSVD5

GND16 HSIP_1 HSIN_1

GND17

GND18 HSIP_2 HSIN_2

GND19

GND20 HSIP_3 HSIN_3

GND21 RSVD6 RSVD7

GND30 HSIP_4 HSIN_4

GND31

GND32 HSIP_5 HSIN_5

GND33

GND34 HSIP_6 HSIN_6

GND35

GND36 HSIP_7 HSIN_7

GND37 RSVD8

GND54 HSIP_8 HSIN_8

GND55

GND56 HSIP_9 HSIN_9

GND57

GND58

HSIP_10 HSIN_10

GND59

GND60

HSIP_11 HSIN_11

GND61

GND62

HSIP_12 HSIN_12

GND63

GND64

HSIP_13 HSIN_13

GND65

GND66

HSIP_14 HSIN_14

GND67

GND68

HSIP_15 HSIN_15

GND69

+VBATS_PEG

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

+V3.3S_PEG 23

PEG_RX15 PEG_RX#15

PEG_RX14 PEG_RX#14

PEG_RX13 PEG_RX#13

PEG_RX12 PEG_RX#12

PEG_RX11 PEG_RX#11

PEG_RX10 PEG_RX#10

PEG_RX9 PEG_RX#9

PEG_RX8 PEG_RX#8

PEG_RX7 PEG_RX#7

PEG_RX6 PEG_RX#6

PEG_RX5 PEG_RX#5

PEG_RX4 PEG_RX#4

PEG_RX3 PEG_RX#3

PEG_RX2 PEG_RX#2

PEG_RX1 PEG_RX#1

PEG_RX0 PEG_RX#0

DDPC_CTRLCLK 7

PEG_SLT_RST#

CLK_PCIE_PEG 35PEG_TX[15:0]7

PEG_RX[15:0] 7 PEG_RX#[15:0] 7

PEG_RSVD5

For D3 HOT/ D3 ON: Stuff R6N5, R6P2, and R6N7, unstuff R6N9, R6C1 and R6N6.

R6N8

R6N8 0

0

NO_STUFF

R6N7

R6N7 0

0

.

+VBATS_PEG

C6B6

C6B6 22UF

22UF

+V3.3S_PEG23

PLT_GATED_RST# 41

PLT_RST# 7,22,25,26,38,41,57

PEG_SLT_RST#

C6A4

C6B1

22UF

12

+

C6B9

0.1uF

C6B11

10%

100uF

.

C6B8

0.1uF

10%

.

+VBAT_S455,57

+VBATS16,27,30,31,55,57

R6N9

R6N6

0.002

1%

1% NO_STUFF

NO_STUFF

C6B5

C6N9

0.1uF

C6B3

C6B3 22UF

22UF

+V3.3S5,7,10,12,13,16,17,18,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

12

R6C1

0.002

.

+V3.327,32,39,41,42,43,55,57

10%

10% .

.

R6P2

0.002

1%

1% NO_STUFF

NO_STUFF

+V3.3A21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

C6C1

C6C1 22uF

22uF

0.1uF

10%

10% .

.

C6B12

0.1uF

10%

10% .

.

+VBATS_PEG

D D

SMB_CLK_S423,43 SMB_DATA_S423,43

PCIE_WAKE#23,25,26,44

PEG_RSVD2

PEG_TX#[15:0]7 CLK_PCIE_PEG# 35

SDVO_CTRLCLK7

C C

PEG_RSVD3

SDVO_CTRLDATA7

MCH_CFG_207,12

B B

DDPC_CTRLDATA7

PEG_RSVD4

PEG_TX15 PEG_TX#15

PEG_TX14 PEG_TX#14

PEG_TX13 PEG_TX#13

PEG_TX12 PEG_TX#12

PEG_TX11 PEG_TX#11

PEG_TX10 PEG_TX#10

PEG_TX9 PEG_TX#9

PEG_TX8 PEG_TX#8

PEG_TX7 PEG_TX#7

PEG_TX6 PEG_TX#6

PEG_TX5 PEG_TX#5

PEG_TX4 PEG_TX#4

PEG_TX3 PEG_TX#3

PEG_TX2 PEG_TX#2

PEG_TX1 PEG_TX#1

PEG_TX0 PEG_TX#0

C6C3

0.1uF

10%

.

C6C5

0.1uF

10%

.

C6C7

0.1uF

10%

.

C6C9

0.1uF

10%

.

C6C11

0.1uF

10%

.

C6C14

0.1uF

10%

.

C6D2

0.1uF

10%

.

C6D5

0.1uF

10%

.

C6D7

0.1uF

10%

.

C6D10

0.1uF

10%

.

C6D11

0.1uF

10%

.

C6D14

0.1uF

10%

.

C6E2

0.1uF

10%

.

C6E4

0.1uF

10%

.

C6E6

0.1uF

10%

.

C6E7

0.1uF

10%

.

C6C2

0.1uF

10%

.

C6C4

0.1uF

10%

.

C6C6

0.1uF

10%

.

C6C8

0.1uF

10%

.

C6C10

0.1uF

10%

.

C6C13

0.1uF

10%

.

C6D1

0.1uF

10%

.

C6D4

0.1uF

10%

.

C6D6

0.1uF

10%

.

C6D9

0.1uF

10%

.

C6D12

0.1uF

10%

.

C6D13

0.1uF

10%

.

C6E1

0.1uF

10%

.

C6E3

0.1uF

10%

.

C6E5

0.1uF

10%

.

C6E8

0.1uF

10%

.

+V3.3S_PEG23

+V3.3A21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

PEG_C_TX15 PEG_C_TX#15

PEG_C_TX14 PEG_C_TX#14

PEG_C_TX13 PEG_C_TX#13

PEG_C_TX12 PEG_C_TX#12

PEG_C_TX11 PEG_C_TX#11

PEG_C_TX10 PEG_C_TX#10

PEG_C_TX9 PEG_C_TX#9

PEG_C_TX8 PEG_C_TX#8

PEG_C_TX7 PEG_C_TX#7

PEG_C_TX6 PEG_C_TX#6

PEG_C_TX5 PEG_C_TX#5

PEG_C_TX4 PEG_C_TX#4

PEG_C_TX3 PEG_C_TX#3

PEG_C_TX2 PEG_C_TX#2

PEG_C_TX1 PEG_C_TX#1

PEG_C_TX0 PEG_C_TX#0

B10 B11

B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82

B1 B2 B3 B4 B5 B6 B7 B8 B9

J6B2

+12V1 +12V2 +12V3 GND1 SMCLK SMDAT GND2 +3.3V1 JTAG1

3.3VAUX WAKE#

RSVD2 GND3 HSOP_0 HSON_0 GND4 PRSNT2# GND5 HSOP_1 HSON_1 GND10 GND11 HSOP_2 HSON_2 GND12 GND13 HSOP_3 HSON_3 GND14 RSVD3 PRSNT2#1 GND15 HSOP_4 HSON_4 GND22 GND23 HSOP_5 HSON_5 GND24 GND25 HSOP_6 HSON_6 GND26 GND27 HSOP_7 HSON_7 GND28 PRSNT2#2 GND29 HSOP_8 HSON_8 GND38 GND39 HSOP_9 HSON_9 GND40 GND41 HSOP_10 HSON_10 GND42 GND43 HSOP_11 HSON_11 GND44 GND45 HSOP_12 HSON_12 GND46 GND47 HSOP_13 HSON_13 GND48 GND49 HSOP_14 HSON_14 GND50 GND51 HSOP_15 HSON_15 GND52 PRSNT2#3 RSVD4

Key

PCIE_X16

A A

5

4

3

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

A

PCIE GRAPHICS

355659

2

19 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

5

4

3

2

1

D D

C C

XDP_OBS035 XDP_OBS135

XDP_OBS235 XDP_OBS3

+V1.05S_CPU3,4,35,39,43,52,54

C1T3

0.1uF

10%

.

XDP_BPM#03

XDP_OBS20 CLK_XDP# 35

B B

XDP_BPM#53

XDP_BPM#43

XDP_OBS3_R

R1U1

R1U1 0

0

R1U2

R1U2 0

0

NO_STUFF

.

XDP_OBS5

R1T1

54.9

XDP_OBS6

1%

XDP_OBS7

H_PWRGD_XDP3

CLK_PCIE_XDP_3GPLL35

CLK_PCIE_XDP_3GPLL#35

L_CTRL_DATA7,17 L_CTRL_CLK7,17

XDP_TCK3

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

XDP

J1F1

GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16

CONN60_ITP-XDP

CAD NOTE: Place the XDP connector on the primary side of the CRB and place all components near the connector.

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

GND11 OBSDATA_D2 OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRSTN

GND17

GND1

GND3

GND5

GND7

GND9

TDO

TMS

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56

TDI

58 60

RST_SNS1

XDP_OBS8 XDP_OBS9

XDP_OBS10 XDP_OBS11

XDP_OBS12 XDP_OBS13

XDP_OBS14XDP_OBS4 XDP_OBS15

XDP_OBS16 XDP_OBS17

CLK_XDP 35

5%

5%C1T3

.

XDP_TRST# 3 XDP_TDI 3 XDP_TMS 3

R2U5

Layout note: R2U5 should connect to H_CPURST# with no stub.

+V1.05S_CPU3,4,35,39,43,52,54 +V3.3S

C1T4

0.1uF

10%

.

100

H_CPURST# 3,6

R1T4

54.9

1%

R1T5

1K

5%

.

XDP_DBRESET# 3

XDP_TDO 3

A A

5

4

3

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

XDP

355659

A

355659

A

355659

A

2

20 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

5

+V3.3A

CR5H1

1 3

BAT54

CR5H2

BAT_D

1 3

BAT54

R5W51KR5W5 1K

D D

BAT

132

BT5H1

BT5H1 Battery_Holder

Battery_Holder

SATA_LED#56

C C

CR7H1

CR7H1 GREEN

GREEN

R5W31MR5W3 1M

RTC Circuitry

R5G10 20KR5G10 20K

TPM Settings Clear ME RTC registers Keep ME RTC registers

R7H7

R7H7 330

330

LED_R

1 2

4

NO_STUFF R7H8

NO_STUFF

+V3.3S

SATA_RXN030 SATA_RXP030

SATA_TXN030 SATA_TXP030

SATA_RXN131 SATA_RXP131

SATA_TXN131 SATA_TXP131

53

0

+V3.3A_RTC24

R5W4 20KR5W4 20K

C5G6

C5G6 1uF

1uF

C7H3

0.1uF

10%

10% .

.

1

2

.

74AHC1G08

74AHC1G08 U7H1

U7H1

R7H8

C5W2

C5W2 1uF

1uF

CMOS Settings J5H2

80%

Clear CMOS Keep CMOS

J5G1J5G1

1 2

J5G1 Shunt Open

SMC0402

C7V17 0.01uF

C7V17 0.01uF C7V18 0.01uF

C7V18 0.01uF C7V16 0.01uF

C7V16 0.01uF C7V15 0.01uFC7V15 0.01uF

C7V22 0.01uF

C7V22 0.01uF C7V21 0.01uF

C7V21 0.01uF C7V19 0.01uF

C7V19 0.01uF C7V20 0.01uFC7V20 0.01uF

Shunt Open

J5H2J5H2

C5H3

C5H3 1uF

1uF

1 2

R7H14

R7H14 10K

10K

.

ICH_SATA_LED#

.

Distance between the ICH9-M and cap on the "P" signal should be identical distance between the ICH9-M and cap on the "N" signal for same pair.

B B

+V3.3A19,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3A_RTC24

R7U8

R7U8 332K

332K

1%

A A

ICH_INTVRMEN

1%

5

4

RTC_RST# 41

C7F2

C7F2 10pF

10pF

Y7F1

32.7680KHZ

Cap values depend on Xtal

C7F1

C7F1 10pF

10pF

LAN_RSTSYNC33

+V1.5S_PCIE_ICH22,24

R6F10

24.9

1%

1% .

.

HDA_DOCK_EN#27,41 HDA_DOCK_RST#27,44

.

R8U1

R8U1 10K

10K

5%

Internal VRM enabled for VccSus1_05, VccSus1_5, VccCL1_5, VccLAN1_05 and VccCL1_05

GLAN_CLK33

LAN_RXD033 LAN_RXD133 LAN_RXD233

LAN_TXD033 LAN_TXD133 LAN_TXD233

GLAN_COMP

HDA_BIT_CLK7,27

HDA_SYNC7,27

HDA_RST#7,27

HDA_SDIN027 HDA_SDIN127 HDA_SDIN227 HDA_SDIN37,27

HDA_SDOUT7,27

4 1

RTC_RST#

SRTC_RST#

SM_INTRUDER#

ICH_GPIO56

ICH_INTVRMEN

4

R7U4

R7U4 10M

10M

RTC_X1 RTC_X2

ICH_GPIO56

ICH_SATA_LED#

SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C

SATA_RXN1_C SATA_RXP1_C SATA_TXN1_C SATA_TXP1_C

U7F1A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD0

D12

LAN_TXD1

E13

LAN_TXD2

B10

GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOUT

AG7

HDA_DOCK_EN#/GPIO33

AE8

HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9M REV 1.0

3

SATA_RXN5_C SATA_RXP5_C SATA_TXN5_C SATA_TXP5_C

3

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME#

RTCLAN / GLANIHDASATA

LPCCPU

RTCLAN / GLANIHDASATA

LPCCPU

LDRQ1#/GPIO23

A20GATE

DPRSTP#

CPUPWRGD

STPCLK#

THRMTRIP#

SATA4RXN SATA4RXP

SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATA_CLKN SATA_CLKP

SATARBIAS#

SATARBIAS

C7H12 0.01uF

.

C7H13 0.01uF

C7H13 0.01uF C7H11 0.01uF

C7H11 0.01uF

.

C7H10 0.01uFC7H10 0.01uF

.

LDRQ0#

A20M#

DPSLP#

FERR#

IGNNE#

INIT# INTR

RCIN#

NMI

SMI#

TP12

2

K5 K4 L6 K2

K3

J3 J1

N7 AJ27

H_DPRSTP#_R

AJ25

H_DPSLP#_R

AE23

AJ26

AD22

AF25

AE22 AG25 L3

AF23

H_SMI#_R

AF24

AH27

H_THERMTRIP_R

AG26

AG27

SATA_RXN4_C

AH11

SATA_RXP4_C

AJ11

SATA_TXN4_C

AG12

SATA_TXP4_C

AF12

SATA_RXN5_C

AH9

SATA_RXP5_C

AJ9

SATA_TXN5_C

AE10

SATA_TXP5_C

AF10

AH18 AJ18

SATA_RBIAS_PN

AJ7 AH7

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

LPC_AD0 38,40,43 LPC_AD1 38,40,43 LPC_AD2 38,40,43 LPC_AD3 38,40,43

LPC_FRAME# 38,40,43

ICH_DRQ#0 38 ICH_DRQ#1 38

H_A20GATE 40,43 H_A20M# 3

R7V10 0

R7V10 0 R6V6 0

R6V6 0

.

. .

.

H_PWRGD 3,43

H_IGNNE# 3

H_INTR 3 H_RCIN# 40,43

H_NMI 3,43

H_STPCLK# 3,43

C7H1 0.01uF

C7H1 0.01uF C7H2 0.01uF

C7H2 0.01uF C7G9 0.01uF

C7G9 0.01uF C7G8 0.01uFC7G8 0.01uF

CLK_PCIE_SATA# 35 CLK_PCIE_SATA 35

Layout Note: Short pins AJ7, AH7 and place

R7G8

R7G1 within 500 mils from them.

24.9

1%

1% .

.

SATA_RXN5 30 SATA_RXP5 30 SATA_TXN5 30 SATA_TXP5 30

ICH9M (1 of 4)

355659 1.0

+V1.05S_ICH_IO24

NO_STUFF

H_FERR#_R

R6V9

R6V9 0

0

.

ICH_TP8

.

C7W2 0.01uF NO_STUFFC7W2 0.01uF NO_STUFF C7W3 0.01uF NO_STUFFC7W3 0.01uF NO_STUFF C7V13 0.01uF NO_STUFFC7V13 0.01uF NO_STUFF C7V14 0.01uF NO_STUFFC7V14 0.01uF NO_STUFF

R6V5

R6V5 56

56

H_INIT# 3

H_SMI# 3,43

R6V8 54.9

.

SATA_RXN4 31 SATA_RXP4 31 SATA_TXN4 31 SATA_TXP4 31

+V3.3S_1.5S_HDA_IO24,27,28

R7G13

R7G13 1K

1K

NO_STUFF

HDA_SDOUT

R7H18

R7H18 1K

1K

NO_STUFF

R7V18

R7V18 56

56

NO_STUFF

R7V9 56R7V9 56

1%

ICH_TP3 23

H_DPRSTP# 3,7,43 H_DPSLP# 3,43

+V1.05S_ICH_IO24

R6V756R6V7 56

Layout note: R6V7 needs to placed within 2" of ICH9-M, R6V8 must be placed within 2" of R6V7 w/o stub.

SATA_RXN4_DOCK 44 SATA_RXP4_DOCK 44 SATA_TXN4_DOCK 44 SATA_TXP4_DOCK 44

XOR Chain Entrance Strap - to be updated

ICH_TP3

0 0 1 1

2

1

+V1.05S_ICH_IO24

R7V1556R7V15 56

H_RCIN#

HDA_SDOUT

Description RSVD0

1 Enter XOR Chain

Normal Operation (Default)

0

Set PCIE port config bit 1

1

Intel Confidential

21 58Tuesday, August 28, 2007

1

H_FERR# 3

PM_THRMTRIP# 3,7

R8U6 10KR8U6 10K

+V3.3S5,7,10,12,13,16,17,18,19,20,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

5

PCIE_RXN1_DOCK44

PCIE_RXP1_DOCK44 PCIE_TXN1_DOCK44 PCIE_TXP1_DOCK44

PCIE_RXN2_DOCK44 PCIE_RXP2_DOCK44

PCIE_TXN2_DOCK44

R9D9 1K.R9D9 1K

.

SPI_SI34 SPI_SO34

PCI

SPI_MOSI_R_3.2V

+V3.3S

53

74AHC1G08

REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55

PIRQE#/GPIO2

PIRQF#/GPIO3

PIRQG#/GPIO4

PCIE_TXP2_DOCK44

PCIE_RXN1_SLOT125

PCIE_RXP1_SLOT125 PCIE_TXN1_SLOT125 PCIE_TXP1_SLOT125

PCIE_RXN2_SLOT225 PCIE_RXP2_SLOT225 PCIE_TXN2_SLOT225 PCIE_TXP2_SLOT225

1

2

.

REQ0# GNT0#

C/BE0#

C/BE1#

C/BE2#

C/BE3#

IRDY#

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR# STOP# TRDY#

FRAME#

PLTRST#

PCICLK

PAR

PME#

F1 G4 B6 A7 F13 F12 E6 F6

D8 B4 D6 A5

D3 E3 R1 C6 E4 C2 J4 A4 F5 D7

C14 D4 R2

H4 K6 F2 G2

1 2

PLT_RST#

J9D2J9D2

R7U11 15R7U11 15

GLAN_TXP &TXN towards GLAN Device

D D

PCI_E_SLOT6_TXN_C &TXPC (from ICH)

PCI_E_SLOT5_TXN_C &TXPC (towards PCIe slot5)

PCI_E_SLOT5_TXN_C &TXPC (from ICH)

PCIe LANE 6 SELECTION

Lane 6 can be connected to LAN or Slot 5 depending on the stuffing option described below. Placed the components such that CAP1 (0603)Pad2 & CAP2 Pad1 are next to each other as shown above. The Placement is such that a 0603 Capacitor can be placed there . Similar placement followed for CAP3 and CAP4. This approach is same for RX Path also.

+V3.3M_WOL24,33,34,44,48,55,57

C C

Layout Note: R7U11,R7F7,R7F8,R7F9 to be placed within 600mils of U7F1

Buffer to reduce loading on PLT_RST#.

BUF_PLT_RST#40,43

PCI_AD[31:0]32

B B

A A

INT_PIRQC#32

PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

INT_PIRQA# INT_PIRQB#

INT_PIRQD#

5

C7T4

0.1uF

20%

20% .

.

4

R8T6

R8T6 100K

100K

U7F1B

D11

AD0

C8

AD1

D9

AD2

E12

AD3

E9

AD4

C9

AD5

E10

AD6

B7

AD7

C7

AD8

C5

AD9

G11

AD10

F8

AD11

F11

AD12

E7

AD13

A3

AD14

D2

AD15

F10

AD16

D5

AD17

D10

AD18

B3

AD19

F7

AD20

C3

AD21

F3

AD22

F4

AD23

C1

AD24

G7

AD25

H7

AD26

D1

AD27

G5

AD28

H6

AD29

G1

AD30

H3

AD31

Interrupt I/F

J5

PIRQA#

E1

PIRQB#

J6

PIRQC# PIRQD#C4PIRQH#/GPIO5

ICH9M REV 1.0

U8E2

4

R6U29 0

R6U29 0 R6U27 0R6U27 0 C6F11 0.1uFC6F11 0.1uF C6F10 0.1uFC6F10 0.1uF

R6U22 0R6U22 0 R6U21 0R6U21 0 C6U8 0.1uFC6U8 0.1uF C6U7 0.1uFC6U7 0.1uF

R6F19 0

R6F19 0 R6F18 0

R6F18 0 C6U12 0.1uF

C6U12 0.1uF C6U11 0.1uF

C6U11 0.1uF

R6F17 0

R6F17 0 R6F16 0

R6F16 0 C6F9 0.1uFC6F9 0.1uF C6F8 0.1uF

C6F8 0.1uF

PCIE_RXN3_SLOT326 PCIE_RXP3_SLOT326 PCIE_TXN3_SLOT326 PCIE_TXP3_SLOT326

PCIE_RXN4_SLOT426 PCIE_RXP4_SLOT426 PCIE_TXN4_SLOT426 PCIE_TXP4_SLOT426

PCIE_RXN5_SLOT526 PCIE_RXP5_SLOT526 PCIE_TXN5_SLOT526 PCIE_TXP5_SLOT526

SPI_MOSI_R

USB_OC#029 USB_OC#129 USB_OC#229 USB_OC#329 USB_OC#429 USB_OC#529 USB_OC#629 USB_OC#729 USB_OC#829 USB_OC#929 USB_OC#1029 USB_OC#1129

USB_OC#0_R USB_OC#1_R USB_OC#2_R USB_OC#3_R USB_OC#4_R USB_OC#5_R USB_OC#6_R USB_OC#7_R USB_OC#8_R USB_OC#9_R

PCI_CBE#0 32 PCI_CBE#1 32 PCI_CBE#2 32 PCI_CBE#3 32

PCI_IRDY# 32 PCI_PAR 32 PCI_RST# 32,41 PCI_DEVSEL# 32 PCI_PERR# 32 PCI_LOCK# 32 PCI_SERR# 32 PCI_STOP# 32 PCI_TRDY# 32 PCI_FRAME# 32

PLT_RST# 7,19,25,26,38,41,57 CLK_PCIF_ICH 36 PCI_PME# 32,43

INT_PIRQE# 32 INT_PIRQF# 32 INT_PIRQG# 32 INT_PIRQH# 32

4

.

. .

.

GLAN_RXN33 GLAN_RXP33 GLAN_TXN33 GLAN_TXP33

SPI_CLK34 SPI_CS#034 SPI_CS#134

R8F17 0R8F17 0 R8G1 0R8G1 0 R8F19 0R8F19 0 R8G2 0R8G2 0 R8F12 0R8F12 0 R8F18 0R8F18 0 R8U7 0R8U7 0 R8F16 0R8F16 0 R8U9 0R8U9 0 R7H6 0R7H6 0

PCI_REQ#0 32 PCI_GNT#0 32 PCI_REQ#1 32 PCI_GNT#1 32

ICH_GPIO52 ICH_GPIO53 PCI_REQ#3 32 PCI_GNT#3 32

NO_STUFF

C6U6 0.1uFC6U6 0.1uF C6U4 0.1uFC6U4 0.1uF

C6U5 0.1uFC6U5 0.1uF C6U3 0.1uFC6U3 0.1uF

R6F14 0

R6F14 0 R6F11 0

R6F11 0 C6F4 0.1uF

C6F4 0.1uF C6F2 0.1uF

C6F2 0.1uF

.

. .

.

R6F12 0

R6F12 0 R6F13 0

R6F13 0 C6F3 0.1uF

C6F3 0.1uF C6F1 0.1uF

C6F1 0.1uF

.

. .

.

R7F8 15R7F8 15 R7F9 15R7F9 15 R7F7 15R7F7 15

PCIE_RXN1_R PCIE_RXP1_R PCIE_TXN1_C PCIE_TXP1_C

PCIE_RXN2_R PCIE_RXP2_R PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN3_C PCIE_TXP3_C

PCIE_TXN4_C PCIE_TXP4_C

PCIE_RXN5_SLOT5_R PCIE_RXP5_SLOT5_R PCIE_TXN5_C PCIE_TXP5_C

GLAN_RXN_R GLAN_RXP_R PCIE_TXN6_C PCIE_TXP6_C

SPI_CLK_R SPI_CS#0_R SPI_CS#1_R

USBRBIAS_PN

R7G5

22.6

1%

ICH9M Pullups

3

U7F1D

N29

PERN1

N28

PERP1

P27

PETN1

P26

PETP1

L29

PERN2

L28

PERP2

M27

PETN2

M26

PETP2

J29

PERN3

J28

PERP3

K27

PETN3

K26

PETP3

G29

PERN4

G28

PERP4

H27

PETN4

H26

PETP4

E29

PERN5

E28

PERP5

F27

PETN5

F26

PETP5

C29

PERN6/GLAN_RXN

C28

PERP6/GLAN_RXP

D27

PETN6/GLAN_TXN

D26

PETP6/GLAN_TXP

D23

SPI_CLK

D24

SPI_CS0#

F23

SPI_CS1#/GPIO58/CLGPIO6

D25

SPI_MOSI

E23

SPI_MISO

N4

OC0#/GPIO59

N5

OC1#/GPIO40

N6

OC2#/GPIO41

P6

OC3#/GPIO42

M1

OC4#/GPIO43

N2

OC5#/GPIO29

M4

OC6#/GPIO30

M3

OC7#/GPIO31

N3

OC8#/GPIO44

N1

OC9#/GPIO45

P5

OC10#/GPIO46

P3

OC11#/GPIO47

AG2

USBRBIAS

AG1

USBRBIAS#

ICH9M REV 1.0

PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_SERR# PCI_DEVSEL# PCI_PERR# PCI_LOCK# PCI_REQ#0 PCI_REQ#1 ICH_GPIO52 PCI_REQ#3

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#

3

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

DMI1RXN DMI1RXP DMI1TXN DMI1TXP

DMI2RXN DMI2RXP DMI2TXN DMI2TXP

DMI3RXN DMI3RXP DMI3TXN DMI3TXP

DMI_CLKN

PCI-Express

DMI_CLKP

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N

SPI

USBP5P USBP6N

USB

USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P

RP8C1A 8.2KRP8C1A 8.2K

1 8

RP8C1B 8.2KRP8C1B 8.2K

2 7

RP8C1C 8.2KRP8C1C 8.2K

3 6

RP9D1A 8.2KRP9D1A 8.2K

1 8

RP9D1D 8.2KRP9D1D 8.2K

4 5

RP8C1D 8.2KRP8C1D 8.2K

4 5

RP9D1C 8.2KRP9D1C 8.2K

3 6

RP9D1B 8.2KRP9D1B 8.2K

2 7

RP9B1A 8.2KRP9B1A 8.2K

1 8

RP9C1B 8.2KRP9C1B 8.2K

2 7

RP9C1D 8.2KRP9C1D 8.2K

4 5

RP9C1C 8.2KRP9C1C 8.2K

3 6

RP9C1A 8.2KRP9C1A 8.2K

1 8

RP9B1D 8.2KRP9B1D 8.2K

4 5

RP9B2A 8.2KRP9B2A 8.2K

1 8

RP9B1C 8.2KRP9B1C 8.2K

3 6

RP9B2B 8.2KRP9B2B 8.2K

2 7

RP9B2C 8.2KRP9B2C 8.2K

3 6

RP9B2D 8.2KRP9B2D 8.2K

4 5

RP9B1B 8.2KRP9B1B 8.2K

2 7

2

DMI_RXN0_R

V27

DMI_RXP0_R

V26

DMI_TXN0_R

U29

DMI_TXP0_R

U28

DMI_RXN1_R

Y27

DMI_RXP1_R

Y26

DMI_TXN1_R

W29

DMI_TXP1_R

W28

DMI_RXN2_R

AB27

DMI_RXP2_R

AB26

DMI_TXN2_R

AA29

DMI_TXP2_R

AA28

DMI_RXN3_R

AD27

DMI_RXP3_R

AD26

DMI_TXN3_R

AC29

DMI_TXP3_R

AC28

T26 T25

AF29 AF28

AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2

+V3.3S

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

R6F5 0

R6F5 0 R6F6 0

R6F6 0 R6U2 0

R6U2 0

.

R6U1 0

.

. .

.

R6F3 0

.

R6F4 0

R6F4 0 R6U4 0

R6U4 0

.

R6U3 0

.

. .

.

R6F7 0

.

R6F8 0

R6F8 0 R6U6 0

R6U6 0

.

R6U5 0

.

. .

.

R6F1 0

.

R6F2 0

R6F2 0 R6U8 0

R6U8 0

.

R6U7 0

.

. .

.

CLK_PCIE_ICH# 35

CLK_PCIE_ICH 35

DMI_IRCOMP_R

USB_PN0 29 USB_PP0 29 USB_PN1 29 USB_PP1 29 USB_PN2 29 USB_PP2 29 USB_PN3 29 USB_PP3 29 USB_PN4 29 USB_PP4 29 USB_PN5 29 USB_PP5 29 USB_PN6 29 USB_PP6 29 USB_PN7 29 USB_PP7 29 USB_PN8 29 USB_PP8 29

USB_PN10 29 USB_PP10 29 USB_PN11 29 USB_PP11 29

ICH9M (2 of 4)

355659

2

DMI_RXN0 7 DMI_RXP0 7 DMI_TXN0 7 DMI_TXP0 7

DMI_RXN1 7 DMI_RXP1 7 DMI_TXN1 7 DMI_TXP1 7

DMI_RXN2 7 DMI_RXP2 7 DMI_TXN2 7 DMI_TXP2 7

DMI_RXN3 7 DMI_RXP3 7 DMI_TXN3 7 DMI_TXP3 7

USB_PN9 USB_PP9

A16 swap override Strap/Top-Block Swap Override jumper

PCI_GNT#3 Low = A16 swap override/Top-Block

GNT#0 and SPI_CS#1 have a weak internal pull up

Boot BIOS Strap

1 1

R8G4

R8G4 0

0

R8G6

R8G6 0

0 R8V4

R8V4

.

0

.

R8V3

R8V3 0

0

NO_STUFF

Swap Override enabled High = Default (Jumper 1-X)

PCI_GNT#0

SPI_CS#1

Boot BIOS LocationPCI_GNT#0 SPI(Default)0

1

PCI

0

LPC

1

+V1.5S_PCIE_ICH 21,24

R6G5

24.9

1%

1% .

.

USB_PN9_R 44 USB_PP9_R 44

USB_PP9_R_FPIO 29

USB_PN9_R_FPIO 29

PCI_GNT#3

R8F10 1K

5%

R7F3

R7F3 1K

1K

NO_STUFF

22 58Tuesday, August 28, 2007

1

J8G7J8G7

1 2

PCI_GNT#0_R

1

J8H1J8H1

1 2

Default : 1-2

Intel Confidential

1.0

5

+V3.3M13,14,15,35,55,57

ICH_GPIO6034

R6H1

R6H1 10K

10K

NO_STUFF

D D

PM_STPPCI#35,43 PM_STPCPU#35,43

VR_PWRGD_CLKEN#

TPM PHYSICAL PRESENCE J7H2 1-X default

C C

MCH_ICH_SYNC#7

MCH_ICH_SYNC_R#

+V3.3S

R8F8

R8F8 10K

10K

J8F2 Default is 1-X for BIOS recovery 1-2

B B

A A

PM_ICH_PWROK

J8F2J8F2

1 2

TXT Status LED

ICH_GPIO38 is used for TXT status indication

R8C4

R8C4 10K

10K

5%

NO_STUFF

+V3.3S

C7W1

0.1uF

10%

5

.

2 4

3

ICH_GPIO37_R

ICH_GPIO38

+V3.3A 19,21,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

C8C1

0.1uF

10%

.

53

U8C2

4

74AHC1G08

5

+V3.3A

SMB_CLK

R7U14 10K

.

R6H4

R6H4 10K

10K

NO_STUFF

R7U25

R7U25 0

0

.

U6H1

INVERTER

R7H13

R7H13 100K

100K

5%

R7G15

R7G15 0

0

.

R7H4

R7H4 100K

100K

5%

+V3.3A

R7H12

R7H12 10K

10K

ICH_GPIO57_J

J7H2J7H2

1 2

+V3.3S_PEG19

R6C3

10K

.

R6C5

0

.

BIOS_REC 41

+V3.3S

1

R8V10

R8V10 10K

10K

5%

5% .

.

+V3.3S 5,7,10,12,13,16,17,18,19,20,21,22,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R7P3

R7P3 2K

2K

1%

1

2

SMB_DATA

SMB_CLK_ME40,43 SMB_DATA_ME40,43

PM_RI#38,43

PM_SUS_STAT#38,40,43

PM_SYSRST#56

PM_SYNC#7

PM_CLKRUN#32,38,40,43

PCIE_WAKE#19,25,26,44

INT_SERIRQ38,40,43

PM_THRM#5,12,40,43

ICH_TP7

SMC_RUNTIME_SCI#40,43

ICH_GPIO13

ICH_GPIO18 ICH_GPIO20 BIOS_REC41

CLK_SATA_OE#35

MFG_MODE

CRB_SV_DET_R

ICH_GPIO57

HDA_SPKR27,44

ICH_TP321

ICH_GPIO37

R8G11

R8G11 240

240

TXT_STATUS

CR8G1

CR8G1 GREEN

GREEN

3

TXT_STATUS_R

1 2

Q8G1

.

BSS138

.

2

GPIO49 has a weak internal pull-up

ALL_SYS_PWRGD 40,43,47

DELAY_VR_PWRGOOD 7

4

SMB_ALERT#

PM_STPPCI_ICH#

R7U15

PM_STPCPU_ICH#

0

.

VR_PWRGD_CLKEN

SMC_EXTSMI#38,40,43,44

ICH_GPIO6

SMC_WAKE_SCI#_R

ICH_GPIO12_R

SATA_PWR_EN#0_R SATA_PWR_EN#1_R

ICH_GPIO38

DMI_TERM_SEL

ICH_GPIO12_R

R7V16 is used for testing purposes only

SATA_PWR_EN#1_R

4

TP_ICH_PWM0 TP_ICH_PWM1 TP_ICH_PWM2

0

.

R8H9

R8H9 0

0

.

R8F20

DMI_TERM_SEL

G16

G19

AJ23

AG19 AH21 AG21

AE18

AJ22

AE19 AG22 AF21 AH24

AJ24

AH20

AJ20 AJ21

A13

E17 C17 B18

F19

R4

M6

A17

A14 E19

L4

E20

M5

D21

A20

A21 C12 C21

K1

AF8

A9

D19

L1

A8

M7

B21

U7F1C

SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1

RI#

SUS_STAT#/LPCPD# SYS_RESET#

PMSYNC#/GPIO0

SMBALERT#/GPIO11

STP_PCI# STP_CPU#

CLKRUN#

WAKE# SERIRQ THRM#

VRMPWRGD

TP11

GPIO1 GPIO6 GPIO7 GPIO8 GPIO12 GPIO13 GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 GPIO27 GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5

SPKR MCH_SYNC# TP3 TP8 TP9 TP10

ICH9M REV 1.0

ICH_GPIO12_R

ICH_GPIO12 57

+V3.3S

+V3.3M13,14,15,35,55,57

SMB_CLK SMB_DATA

NO_STUFF

R7V16

R7V16 1K

1K

SATA

GPIO

SATA

GPIO

SMBSYS GPIO

Clocks

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

Power MGTController Link

GPIO

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

MISC

+V3.3M 13,14,15,35,55,57

+V3.3A

R7R2 10KR7R2 10K R7R4 10KR7R4 10K R7R5 10KR7R5 10K R7R3 10KR7R3 10K

R7R8 10KR7R8 10K R7R11 10KR7R11 10K R7R9 10KR7R9 10K R7R7 10KR7R7 10K

SMC_WAKE_SCI#_R

SATA_PWR_EN#0_R

3

SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37

CLK14 CLK48

SUSCLK

SLP_S3# SLP_S4# SLP_S5#

PWROK

BATLOW#

PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0 CL_CLK1

CL_DATA0 CL_DATA1

CL_VREF0 CL_VREF1

CL_RST0# CL_RST1#

MEM_LED/GPIO24

WOL_EN/GPIO9

R416 10K

NO_STUFF

R7D3 10KR7D3 10K R7D1 10KR7D1 10K

R7R10 10KR7R10 10K R7R12 10KR7R12 10K

+V3.3S

R9A4 10KR9A4 10K R9A5 10KR9A5 10K

I2C_EN1 I2C_EN2 I2C_EN3 I2C_EN4

R8W3

R8W3 0

0

.

R8W6

R8W6 0

0

.

3

AH23 AF19 AE21 AD20

H1 AF3

P1

SLP_S3#_R

C16

SLP_S4#_R

E16 G17

PM_S4_STATE#_R

C10

PM_ICH_PWROK

G20

PM_DPRSLPVR_R

M2

PM_BATLOW#_R

B13

R3

D20

PM_RSMRST#_R

D22

R5

R6

PM_SLP_M#_R

B16

F24 B19

F22 C19

CL_VREF0_ICH_R

C25

CL_VREF1_ICH_R

A19

F21 D18

A16 C18 C11 C20

SMB_CLK_M3 SMB_DATA_M3

SMB_CLK_M2 SMB_DATA_M2

U7D1

CL1

1

EXPSCL1

CL2

2

EXPSCL2

DA1

18

EXPSDA1

DA2

19

EXPSDA2

3

SCL0

4

SDA0

7

EN1

11

EN2

14

EN3

17

EN4

10

VSS

SMC_WAKE_SCI#_R SMC_WAKE_SCI# 40,43

SATA_PWR_EN#0_RSATA_PWR_EN#1_R SATA_PWR_EN#0 30SATA_PWR_EN#1 31

PM_SLP_S5#_R

R7U27 0. 5%R7U27 0. 5%

+V3.3A

R7U22

R7U22 10K

10K

SMB_CLK_S4 SMB_DATA_S4

EXP. 5-CH-I2C HUB

2

5,7,10,12,13,16,17,18,19,20,21,22,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

ICH_GPIO19_R

R7V20

R7V20 0

0

.

CLK_REF_ICH 35 CLK_USB48 35

SUS_CLK 43

R7U24 0R7U24 0

R7U23 0R7U23 0

R7V1 0R7V1 0

R8U2 0

.

R8F13 0

R8F4

R8F4 0

0

.

R7U19 0

CLK_PWRGD 35,36

.

MPWROK 7,46

PM_SLP_M# 40,43,44,47,55,57

CL_CLK0 7SV_SET_UP CL_CLK1 26

CL_DATA0 7 CL_DATA1 26

CL_RST#0 7 CL_RST#1 26

SUS_PWR_ACK 40,43

AC_PRESENT 40,43,56

CL_VREF1_ICH

LAN_WOL_EN 40,43,55,57

+V3.3A

R8C5 10KR8C5 10K R8D1 10KR8D1 10K

+V3.3S

R7V12 10KR7V12 10K

20

VCC

5

SCL1

6

SDA1

8

SCL2

9

SDA2

12

SCL3

13

SDA3

15

SCL4

16

SDA4

Title

Size Document Number Rev

Date: Sheet of

SMB_CLK_A1 25,26,32,44 SMB_DATA_A1 25,26,32,44

SMB_CLK_M2 13,14,15 SMB_DATA_M2 13,14,15

SMB_CLK_M3 35,36 SMB_DATA_M3 35,36

SMB_CLK_S4 19,43 SMB_DATA_S4 19,43

Pillar Rock

ICH9M (3 of 4)

355659

A

355659

A

355659

A

SATA_DET#0 30 SATA_DET#1 31

ICH_GPIO36

ICH_GPIO37_R

R7V22 10K

NO_STUFF

PM_SLP_S3# 11,40,43,44,46,47,49,55,57 PM_SLP_S4# 46,55 PM_SLP_S5# 57

PM_S4_STATE# 32,40,43,44,55,57

PM_DPRSLPVR 7,43,52

PM_BATLOW# 40,43

PM_PWRBTN# 40,43

PM_LAN_ENABLE 33,40,43

PM_RSMRST# 40,43,56

C7U2

0.1uF

10%

.

R6U12 0

NO_STUFF

ICH_GPIO24 34

C7U3

C7R2

0.1uF

20%

20% .

.

C7U3

0.1uF

10%

.

R7U17 0

NO_STUFF

SMB_CLK_A1 SMB_DATA_A1

ICH_GPIO36

+V3.3A19,21,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

2

No Reboot Strap

HDA_SPKR

+V3.3M13,14,15,35,55,57

R7U13

3.24K

1%

R6U11

R6U11 0

0

NO_STUFF

EV_V3.3_ICH_CLVREF0

CL_VREF0_ICH

R3J3

R3J3 0

0

NO_STUFF

12

R7U18

R7U18 453_1%

453_1%

+V3.3A 19,21,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

R7U6

3.24K

1%

12

R7U20

R7U20 453_1%

453_1%

ICH9M Pullups

ICH_GPIO13

PM_RI#

SMB_CLK_ME SMB_DATA_ME

SMB_CLK SMB_DATA

SMB_ALERT#

PCIE_WAKE#

PM_BATLOW#_R

ICH_GPIO12

CLK_SATA_OE#

PM_THRM#

INT_SERIRQ

PM_CLKRUN#

ICH_GPIO6

ALL_SYS_PWRGD PM_RSMRST#

1

Low = Default High = No Reboot

HDA_SPKR

EV_V3.3_ICH_CLVREF1

R7T20 10KR7T20 10K

R7U21 10KR7U21 10K R7U12 10KR7U12 10K

R7D10 2.2KR7D10 2.2K R7D11 2.2KR7D11 2.2K

R7U9 10KR7U9 10K

R7U1 1KR7U1 1K

R8U4 8.2KR8U4 8.2K

R8F5 10KR8F5 10K

R7F10 10KR7F10 10K

R7G7 8.2KR7G7 8.2K

R7T16 10KR7T16 10K

R8F9 8.2KR8F9 8.2K

R7G6 10KR7G6 10K

R8G5 10KR8G5 10K R9G17 10KR9G17 10K

Intel Confidential

23 58Tuesday, August 28, 2007

1

10K.5%

+V3.3S

R7T22

R8F14

R8F14 1K

1K

NO_STUFF

+V3.3A

+V3.3S

1.0

5

+V5S 5,11,12,16,17,18,28,30,31,32,39,48,49,52,55,56,57

+V3.3A_RTC21

R7U16

R7U16 10

10

5%

+V3.3S

D D

+V1.5S 4,10,11,28,47,55,57

R6G3 0.002R6G3 0.002

+V5A

R8V5

R8V5 10

10

5%

+V1.5S_PCIE_R

+V3.3A

1

CR8V1

CR8V1 BAT54

BAT54

3

C7V9

0.1uF

10%

.

SMC0402

.

SMC0402

FB6G1

330ohm@100MHz

1

CR7U1

CR7U1 BAT54

BAT54

+V5S_ICH_VCC5REF

3

+V1.5S_PCIE_ICH21,22

C6G2

C6G2 220uF

220uF

C7U5

0.1uF

10%

.

SMC0402

.

SMC0402

+V5A_ICH_V5REF_SUS

C7U8

0.1uF

10%

.

SMC0402

.

SMC0402

C6G3

C6G3 22uF

22uF

.

C7U4

0.1uF

10%

10% SMC0402

SMC0402

C6G1

C6G1 22uF

22uF

.

C C

+V1.5S 4,10,11,28,47,55,57

R7G16 0.002R7G16 0.002

B B

R7H1 0.002R7H1 0.002

+V3.3M_WOL22,33,34,44,48,55,57

R7F2 0.002R7F2 0.002

+V1.5S 4,10,11,28,47,55,57

A A

R7F1

R7F1 0

0

.

+V1.5S_SATA_ICH

+V3.3M_VCCPAUX VCCLAN1_05_INT_ICH

C7U9

0.1uF

10%

.

SMC0402

.

SMC0402

+V1.5S_ICH_GLANPLL_R

+V1.5S_SATA_ICH

+V1.5S_USB_ICH

1 2

1uH

+V1.5S_PCIE_ICH21,22

+V3.3S

L7G1

10uH

C7V7

0.1uF

10%

.

SMC0402

.

SMC0402

C7U6

0.1uF

10%

.

SMC0402

.

SMC0402

L7F1

R6U9 0.002R6U9 0.002

+V1.5S_APLL_ICH

C7G7

C7G7 10uF

10uF

20%

.

SMC0805

.

SMC0805

C7V10

0.1uF

10%

.

SMC0402

.

SMC0402

+V1.5S_ICH_GLANPLL_R_L

C7F3

C7F4

10uF

2.2uF

20%

SMC0603

.

C6F7

4.7uF

10%

.

+V3.3S_GLAN_ICH

5

C7U17

2.2uF

SMC0603

.

C7G6

1.0uF

402

402 .

.

C7G5

1.0uF

402

402 .

.

C7G3

1.0uF

402

402 .

.

4

AA24 AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE25 AE26 AE27 AE28 AE29

M24 M25

W24 W25

AJ19

AC16 AD15 AD16 AE15 AF15 AG15 AH15

AJ15

AC11 AD11 AE11 AF11 AG10 AG11 AH10

AJ10

AC9

AC18 AC19

AC21

AC12 AC13 AC14

AC6 AC7

A23

A6

AE1

F25 G25 H24 H25

J24

J25 K24 K25

L23

L24

L25

N23 N24 N25 P24 P25 R24 R25 R26 R27

T24

T27

T28

T29 U24 U25 V24 V25 U23

K23

Y24

Y25

G10

G9

AJ5

AA7 AB6 AB7

A10 A11

A12 B12

A27

D28 D29 E26 E27

A26

U7F1F

VCCRTC

V5REF

V5REF_SUS

VCC1_5_B[1] VCC1_5_B[2] VCC1_5_B[3] VCC1_5_B[4] VCC1_5_B[5] VCC1_5_B[6] VCC1_5_B[7] VCC1_5_B[8] VCC1_5_B[9] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] VCC1_5_B[47] VCC1_5_B[48] VCC1_5_B[49]

VCCSATAPLL

VCC1_5_A[1] VCC1_5_A[2] VCC1_5_A[3] VCC1_5_A[4] VCC1_5_A[5] VCC1_5_A[6] VCC1_5_A[7] VCC1_5_A[8]

VCC1_5_A[9] VCC1_5_A[10] VCC1_5_A[11] VCC1_5_A[12] VCC1_5_A[13] VCC1_5_A[14] VCC1_5_A[15] VCC1_5_A[16]

VCC1_5_A[17]

VCC1_5_A[18] VCC1_5_A[19]

VCC1_5_A[20]

VCC1_5_A[21] VCC1_5_A[22]

VCC1_5_A[23] VCC1_5_A[24] VCC1_5_A[25]

VCCUSBPLL

VCC1_5_A[26] VCC1_5_A[27] VCC1_5_A[28] VCC1_5_A[29] VCC1_5_A[30]

VCCLAN1_05[1] VCCLAN1_05[2]

VCCLAN3_3[1] VCCLAN3_3[2]

VCCGLANPLL

VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4]

VCCGLAN3_3

ICH9M REV 1.0

CORE

VCCA3GP ATXARX USB CORE

VCCPSUSVCCPUSB

GLAN POWER

VCC1_05[1] VCC1_05[2] VCC1_05[3] VCC1_05[4] VCC1_05[5] VCC1_05[6] VCC1_05[7] VCC1_05[8]

VCC1_05[9] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26]

VCCDMIPLL

VCC_DMI[1] VCC_DMI[2]

V_CPU_IO[1] V_CPU_IO[2]

VCC3_3[1]

VCC3_3[2]

VCC3_3[7]

VCC3_3[3] VCC3_3[4] VCC3_3[5] VCC3_3[6]

VCCP_CORE

VCC3_3[8]

VCC3_3[9] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13]

PCI

VCC3_3[14]

VCCHDA

VCCSUSHDA

VCCSUS1_05[1] VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]

VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4]

VCCSUS3_3[5]

VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8]

VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20]

VCCCL1_05

VCCCL1_5

VCCCL3_3[1] VCCCL3_3[2]

A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18

R29

+V1.05S_ICH_DMI

W23 Y23

AB23 AC23

AG29

AJ6

AC10

AD19 AF20 AG24 AC20

B9 F9 G3 G6 J2 J7 K7

AJ4

AJ3

TP_VCCSUS1_05_ICH_1

AC8

TP_VCCSUS1_05_ICH_2

F17

TP_VCCSUS1_5_ICH_1

AD8

VCCSUS1_5_INT_ICH

F18

A18 D16 D17 E22

AF1

T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7

VCCCL1_05_INT_ICH

G22

VCCCL1_5_INT_ICH

G23

A24 B24

3

C7U16

0.1uF

10%

.

SMC0402

.

SMC0402

+V1.5S_ICH_VCCDMIPLL

C7V8

0.1uF

10%

.

SMC0402

.

SMC0402

+V3.3A_ICH

+V3.3A_USB_ICH

C7V1

0.022uF

10%

10% 402

402

.

C7U14

C7U14 1UF

1UF

NO_STUFF

+V3.3M_ICH

R7U7 0.002R7U7 0.002

3

C7V2

0.1uF

10%

.

SMC0402

.

SMC0402

C6F13

0.01uF

10%

10% .402

.402

C7V3

4.7uF

10%

.

C7G4

0.1uF

10%

.

SMC0402

.

SMC0402

C7U15

0.1uF

10%

.

SMC0402

.

SMC0402

+V3.3S_1.5S_HDA_IO_ICH

C7U11

0.1uF

10% SMC0402

.

C7G1

0.022uF

10%

10% 402

402

.

C7U13

0.1uF

10%

NO_STUFF

SMC0402

+V3.3M_WOL22,33,34,44,48,55,57

1 2

C6F12

C6F12 10uF

10uF

20%

.

FB7V1

5ohm@100MHz

C7V5

0.1uF

10%

.

SMC0402

.

SMC0402

C7U7

0.1uF

10%

NO_STUFF

SMC0402

+V3.3A_1.5A_HDA_IO27,28,44

C7V12

0.1uF

10%

.

SMC0402

.

SMC0402

C7G2

0.1uF

10%

.

SMC0402

.

SMC0402

2

U7F1E

+V1.05S_ICH41

R7F5 0.002R7F5 0.002

L6G1

+V1.5S_ICH_VCCDMIPLL_R

1uH

+V1.05S_ICH41

+V1.05S_ICH_IO21

C7V6

0.1uF

10%

.

SMC0402

.

SMC0402

C6V5

0.1uF

10%

.

SMC0402

.

SMC0402

C7U10

0.1uF

10%

NO_STUFF

SMC0402

R6F9 0.002R6F9 0.002

R7G1 0.002R7G1 0.002

C7U12

0.1uF

10%

.

SMC0402

.

SMC0402

Title

Size Document Number Rev

Date: Sheet of

R6V10 0.002R6V10 0.002

C7V4

4.7uF

10%

.

+V3.3S_DMI_ICH

+V3.3S_SATA_ICH

+V3.3S_VCCPCORE_ICH

+V3.3S_PCI_ICH

R7V17 0.022R7V17 0.022

C7V11

0.1uF

10% SMC0402

.

+V3.3A

Pillar Rock

ICH9M (4 of 4)

355659

A

355659

A

355659

A

+V1.05S4,9,10,47,55

R6G2

R6G2 0

0

.

+V1.05S4,9,10,47,55

R6G6 0.002R6G6 0.002

R7G9 0.002R7G9 0.002

R7G14 0.002R7G14 0.002

R7F4 0.002R7F4 0.002

+V3.3S_1.5S_HDA_IO21,27,28

+V1.5S4,10,11,28,47,55,57

+V3.3S

AA26 AA27

AA23 AB28 AB29

AC17 AC26 AC27

AD10 AD12 AD13 AD14 AD17 AD18 AD21 AD28 AD29

AE12 AE13 AE14 AE16 AE17

AE20 AE24

AF13 AF16 AF18 AF22 AH26 AF26 AF27

AG13 AG16 AG18 AG20 AG23

AH12 AH14 AH17 AH19

AH22 AH25 AH28

AJ12 AJ14 AJ17

AA3 AA6 AB1

AB4 AB5

AC3 AD1

AD4 AD5 AD6 AD7 AD9

AE2

AE3 AE4 AE6 AE9

AF5 AF7 AF9

AG3 AG6 AG9

AH2

AH5 AH8

B11 B14 B17

B20 B23

C26 C27 E11 E14 E18

E21 E24

G12 G14 G18 G21 G24 G26 G27

H23 H28 H29

AJ8

B2

B5 B8

E2

E5

E8 F16 F28 F29

G8 H2

U7F1E

VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106]

ICH9M REV 1.0

2

VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198]

VSS_NCTF[1] VSS_NCTF[2] VSS_NCTF[3] VSS_NCTF[4] VSS_NCTF[5] VSS_NCTF[6] VSS_NCTF[7] VSS_NCTF[8]

VSS_NCTF[9] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]

24 58Tuesday, August 28, 2007

1

H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25

A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29

Intel Confidential

1

1.0

5

4

3

2

1

D D

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3A19,21,23,24,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

C7B14

0.1uF

C7B16

C7B16 22uF

22uF

10%

.

+V12S26,30,31,32,43,55,57

+12V3 +12V4

GND6 JTAG2 JTAG3 JTAG4 JTAG5 +3.3V2 +3.3V3

GND7

GND8

HSLP_0 HSLN_0

GND9

+V12S_PCIESLOT1

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

+V3.3S_PCIESLOT1

PCIESLOT1_PRSNT#1

R6B2

R6B2 0

0

.

PLT_RST# 7,19,22,26,38,41,57

CLK_PCIE_SLOT1 36 CLK_PCIE_SLOT1# 36

PCIE_RXP1_SLOT1 22 PCIE_RXN1_SLOT1 22

+V3.3S_PCIESLOT1

C6B10

C6B10 22uF

22uF

+V12S_PCIESLOT1

C7B8

C7B8 22uF

22uF

C6B13

0.1uF

10%

.

C7B6

0.1uF

10%

10% .

.

C7B10

0.1uF

10%

.

C6B4

0.1uF

10%

10% .

.

R7N5

0.002

1%

1%C6B13 .

.

R7N6

0.002

1%

1% .

.

+V12S_PCIESLOT1

+V3.3S_PCIESLOT1

+V3.3A19,21,23,24,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

SMB_CLK_A123,26,32,44 SMB_DATA_A123,26,32,44

+V3.3S_PCIESLOT1

PCIE_WAKE#19,23,26,44

R7C3

R7C3 10K

10K

5%

5% .

C C

CLK_SLOT1_OE#36

.

PCIE_TXP1_SLOT122 PCIE_TXN1_SLOT122

J6B1

B1

+12V1 +12V2 RSVD1 GND1 SMCLK SMDAT GND2 +3.3V1 JTAG

3.3VAUX WAKE#

RSVD2 GND3 HSOP_0 HSON_0 GND4 PRSNT2# GND5

PCIE_X1

Key

PRSNT1#

PWRGD

REFCLK+ REFCLK-

B2 B3 B4 B5 B6 B7 B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18

SLOT 1

NOTE: SLOTS 1 AND 2 ARE PHYSICALY IN-LINE

R7R1

0.002

1%

1% .

.

R7C20

0.002

1%

1% .

.

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3A19,21,23,24,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

C7D3

0.1uF

C7D4

C7D4 22uF

22uF

10%

.

+V12S26,30,31,32,43,55,57

+V12S_PCIESLOT2

+V3.3S_PCIESLOT2

+V3.3A19,21,23,24,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

SMB_CLK_A1 SMB_DATA_A1

B B

CLK_SLOT2_OE#36

+V3.3S_PCIESLOT2

R7D14

R7D14 10K

10K

5%

5% .

.

PCIE_WAKE# PLT_RST#

PCIE_TXP2_SLOT222 PCIE_TXN2_SLOT222

J6D1

B1

+12V1 +12V2 RSVD1 GND1 SMCLK SMDAT GND2 +3.3V1 JTAG

3.3VAUX WAKE#

RSVD2 GND3 HSOP_0 HSON_0 GND4 PRSNT2# GND5

PCIE_X1

Key

PRSNT1#

PWRGD

REFCLK+ REFCLK-

B2

B3

B4

B5

B6

B7

B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18

+12V3 +12V4

GND6 JTAG2 JTAG3 JTAG4 JTAG5

+3.3V2 +3.3V3

GND7

GND8

HSLP_0 HSLN_0

GND9

+V12S_PCIESLOT2

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

+V3.3S_PCIESLOT2

PCIESLOT2_PRSNT#1

R7R6

R7R6 0

0

.

CLK_PCIE_SLOT2 36 CLK_PCIE_SLOT2# 36

PCIE_RXP2_SLOT2 22 PCIE_RXN2_SLOT2 22

+V3.3S_PCIESLOT2

C7D1

C7D1 22uF

22uF

+V12S_PCIESLOT2

C7C1

C7C1 22uF

22uF

C7D2

0.1uF

10%

.

C6C12

0.1uF

10%

10% .

.

C6D3

0.1uF

10%

.

C7C3

0.1uF

10%

10% .

.

SLOT 2

A A

5

4

3

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

PCI-E Slots (1 & 2)

355659

2

25 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

5

4

3

2

1

PCIe Slot3 VAUX Control

R8B2

0.002

1%

1% .

.

+V3.3S

R7C1

0.002

1%

1% .

.

+V12S25,30,31,32,43,55,57

+V3.3_PCIESLOT3

+V3.3_PCIE_VAUX_SLOT3

D D

CLK_SLOT3_OE#

36

SMB_CLK_A123,25,32,44 SMB_DATA_A123,25,32,44

+V3.3_PCIESLOT3

R8C1

R8C1 10K

10K

5%

.

NOTE: SLOTS 3 AND 4 ARE PHYSICALY IN-LINE

PCIE_WAKE#19,23,25,44

PCIE_TXP3_SLOT322 PCIE_TXN3_SLOT322

+V12S_PCIESLOT3

B1

+12V1

B2

+12V2

B3

RSVD1

B4

GND1

B5

SMCLK

B6

SMDAT

B7

GND2

B8

+3.3V1

B9

JTAG

B10

3.3VAUX

B11

WAKE#

B12

RSVD2

B13

GND3

B14

HSOP_0

B15

HSON_0

B16

GND4

B17

PRSNT2#

B18

GND5

J8B3

Key

PCIE_X1

SLOT 3

PRSNT1#

REFCLK+

REFCLK-

+12V3 +12V4

GND6 JTAG2 JTAG3 JTAG4 JTAG5 +3.3V2 +3.3V3

PWRGD

GND7

GND8

HSLP_0 HSLN_0

GND9

+V12S_PCIESLOT3

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

+V3.3_PCIESLOT3

PCIESLOT3_PRSNT1#

PCIE_RSVD_1#

PLT_RST# 7,19,22,25,38,41,57

R8B4

R8B4 0

0

.

CLK_PCIE_SLOT3 36 CLK_PCIE_SLOT3# 36

PCIE_RXP3_SLOT3 22 PCIE_RXN3_SLOT3 22

+V3.3_PCIESLOT3

C8B7

C8B6

0.1uF

C7B17

C7B17 22uF

22uF

Upham 4 Support: STUFF R8B5 and NO_STUFF R7C1 Upham 3 and Conventional PCIe card support(Default): STUFF R7C1 and NO_STUFF R8B5

+V12S_PCIESLOT3

C8B4

C8B4 22uF

22uF

10%

.

C8B5

0.1uF

10%

10% .

.

10%

.

C8B3

0.1uF

10%

10% .

.

+V3.3_PCIE_VAUX_SLOT3

R8B5

0.002

1%

1% NO_STUFF

NO_STUFF

C8N4

C8N4 22uF

22uF

+V3.3A

783 6 5

VAUX3_G_SWITCH

3

Q8N1

Q8N1 BSS138

BSS138

.

2

R8B6

R8B6 100K

100K

+VBATA45,46,47,56,57

R8B8

R8B8 100K

100K

R8B7

R8B7 100K

100K

VAUX3_OK#

1

3

Q8N2

Q8N2 BSS138

BSS138

1

.

2

C8B9

0.1uF

10%

.

+V3.3A

EC_PCIE_SLOT3_VAUX_ON41

+V3.3_PCIE_VAUX_SLOT3

Q8B1

Q8B1 IRF7822

IRF7822

2

.

1

4

C8B8

0.01UF

.

. 10%

10%

+V3.3S

+12V3 +12V4

GND6 JTAG2 JTAG3 JTAG4 JTAG5 +3.3V2 +3.3V3

PWRGD

GND7

GND8

HSLP_0 HSLN_0

GND9

+V12S_PCIESLOT4

+V3.3_PCIESLOT4

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

PCIESLOT4_PRSNT1#

PCIESLOT4_A6

PCIESLOT4_A8

PLT_RST#

R7P13

R7P13 0

0

.

PCIE_RSVD_2#

CLK_PCIE_SLOT4 36 CLK_PCIE_SLOT4# 36

PCIE_RXP4_SLOT4 22 PCIE_RXN4_SLOT4 22

R8D2

0.002

1%

R8C3

0.002

1%

1% .

.

1% .

.

+V12S25,30,31,32,43,55,57

+V3.3_PCIESLOT4

C8D3

C8D2

0.1uF

C8D1

C8D1 22uF

22uF

Upham 4 Support: STUFF R8D3 and NO_STUFF R8D2 Upham 3 and Conventional PCIe card support(Default): STUFF R8D2 and NO_STUFF R8D3

+V12S_PCIESLOT4

C8C2

C8C2 22uF

22uF

0.1uF

10%

.

C8C4

C8C3

0.1uF

10%

.

+V12S_PCIESLOT4

C C

+V3.3_PCIE_VAUX_SLOT4

SMB_CLK_A1 PCIESLOT4_A5

+V3.3_PCIESLOT4

R8D5

R8D5 10K

10K

5%

CLK_SLOT4_OE#36

SMB_DATA_A1

PCIE_TXP4_SLOT422

.

PCIE_TXN4_SLOT422

+V3.3_PCIESLOT4

PCIE_WAKE#

J8D1

B1

+12V1 +12V2 RSVD1 GND1 SMCLK SMDAT GND2 +3.3V1 JTAG

3.3VAUX WAKE#

RSVD2 GND3 HSOP_0 HSON_0 GND4 PRSNT2# GND5

PCIE_X1

Key

PRSNT1#

REFCLK+

REFCLK-

B2 B3 B4 B5 B6 B7 B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18

SLOT 4

B B

R7N4

0.002

1%

1% .

.

R7N2

0.002

1%

1% .

.

C7B11

0.1uF

10%

.

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V12S25,30,31,32,43,55,57

+V12S_PCIESLOT5+V12S_PCIESLOT5

+V3.3S_PCIESLOT5

+V3.3A

SMB_CLK_A1 SMB_DATA_A1

+V3.3S_PCIESLOT5

R7C2

R7C2 10K

10K

5%

.

PCIE_TXP5_SLOT522

CLK_SLOT5_OE#36 PCIE_RXN5_SLOT5 22

PCIE_TXN5_SLOT522

PCIE_WAKE#

A A

J7B1

B1

+12V1 +12V2 RSVD1 GND1 SMCLK SMDAT GND2 +3.3V1 JTAG

3.3VAUX WAKE#

RSVD2 GND3 HSOP_0 HSON_0 GND4 PRSNT2# GND5

PCIE_X1

Key

PRSNT1#

+12V3 +12V4

GND6 JTAG2 JTAG3 JTAG4 JTAG5

+3.3V2 +3.3V3

PWRGD

GND7

REFCLK+

REFCLK-

GND8

HSLP_0 HSLN_0

GND9

B2 B3 B4 B5 B6 B7 B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

+V3.3S_PCIESLOT5

PCIESLOT5_PRSNT1#

PLT_RST#

CLK_PCIE_SLOT5 36 CLK_PCIE_SLOT5# 36

PCIE_RXP5_SLOT5 22

SLOT 5

5

4

R7N3

R7N3 0

0

.

+V3.3S_PCIESLOT5

C7B15

C7B15 22uF

22uF

+V12S_PCIESLOT5

C7B4

C7B4 22uF

22uF

C7B12

0.1uF

10%

.

C7B5

0.1uF

10%

10% .

.

C7B9

0.1uF

10%

.

C7B7

0.1uF

10%

10% .

.

+V3.3A19,21,23,24,25,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

C7B13

C7B13 22uF

22uF

3

+V3.3_PCIE_VAUX_SLOT4

R8D3

0.002

1%

1% NO_STUFF

NO_STUFF

C8D5

C8D5 22uF

22uF

C8D4

0.1uF

10%

.

PCIe Slot4 VAUX Control

+V3.3A19,21,23,24,25,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+VBATA45,46,47,56,57

VAUX4_G_SWITCH

R7P6

R7P6 100K

+V3.3A19,21,23,24,25,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

VAUX4_OK#

R7P4

R7P4 100K

100K

3

EC_PCIE_SLOT4_VAUX_ON40

NOTE: Remove Resistors in case a JTAG-capable PCIE card is to be inserted in Slot 4

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

PCI-E Slots (3,4 & 5)

355659

2

1

PCIESLOT4_A6 PCIESLOT4_A8 PCIESLOT4_A5

2

R7P5

R7P5 100K

100K

Q7P2

Q7P2 BSS138

BSS138

.

100K

1

R7D20

R7D20 R7D12

R7D12

0

0 0

0

R7D13

R7D13 0

0

.

. .

.

26 58Tuesday, August 28, 2007

783 6 5

3

Q7P1

Q7P1 BSS138

BSS138

.

2

Intel Confidential

1

+V3.3_PCIE_VAUX_SLOT4

4

Q7R1

Q7R1 IRF7822

IRF7822

2

.

1

C7R1

0.01UF

.

. 10%

10%

CL_RST#1 23 CL_DATA1 23 CL_CLK1 23

1.0

5

4

3

2

1

Layout Toplogy for HDA Clk,Sync,RST,SDout,Enable

HDA_BIT_CLK7,21

HDA_RST#7,21

D D

HDA_SYNC7,21

HDA_SDOUT7,21

R7G3 33R7G3 33

R7G2 33R7G2 33

R7V7 33R7V7 33

R7G11 33R7G11 33

*

HDA_CODEC_0_1_2_CLK

R7G4

R7G4 0

0

.

HDA_CODEC_0_1_2_RST#

R7V2

R7V2 0

0

.

HDA_CODEC_0_1_2_SYNC

R7V6

R7V6 0

0

.

HDA_CODEC_0_1_2_SDATAOUT

R7G10

R7G10 0

0

.

HDA_SDIN2

HDA_CODEC_3_CLK

HDA_CODEC_3_RST#

HDA_CODEC_3_SYNC

HDA_CODEC_3_SDATAOUT

R9N2

R9N2 0

0

NO_STUFF

HDA_DOCK_SDATAIN

ICH

13x2 HeaderDocking Connector

***

Note: Place the resistors "*" as

**

Marked in the Diagram

* *

8x2 Header

GMCH

HDA Header for MDC Interposer

+V3.3A19,21,23,24,25,26,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

C C

HDA_CODEC_0_1_2_CLK HDA_MDC_BITCLK

HDA_CODEC_0_1_2_SYNC

HDA_SDIN021 HDA_SDIN121 HDA_SDIN37,21

HDA_SDIN221

HDA_DOCK_RST#21,44

**

R9D3 33R9D3 33 R9E6 33R9E6 33 R9D7 33R9D7 33 R9E2 33R9E2 33

R9E9

0

R9E12

0

R9E8

.

0NO_STUFF

.

R9E11

0

.

HDA_MDC_RST#HDA_CODEC_0_1_2_RST#

HDA_MDC_SYNC

HDA_MDC_SDOHDA_CODEC_0_1_2_SDATAOUT

HDA_MDC_SDATAIN1 HDA_MDC_SDATAIN3 HDA_MDC_SDATAIN2

HDA_AUDIO_PWRDN_NET

R9E16

R9E16 10K

10K

5%

5% .

.

B B

HDA_DOCK_EN#

+V3.3S_1.5S_HDA_IO21,24,28

C9D3

0.1uF

HDA_BCLK_R

0.1uF

20%

HDA_CODEC_0_1_2_SYNC HDA_CODEC_0_1_2_SDATAOUT

HDA_BCLK_DOCK 44

HDA_CODEC_0_1_2_CLK

U9D1

1

OE#

2

A

GND3Y

NC7SV125L

VCC

6

5

NC

R9D4 33R9D4 33

4

A A

R9D6

R9D6 20K

20K

5

2X8_HDR_KEY12

J9E2

15

16

13

14

11

12

9

10

8

7 6 4

3 2

1

1 2 3 4 5 6 7 8

J9E4

8Pin HDR

Layout Note: Place both headers in-line and exactly 200 mils from each other, pin-to-pin. Draw one silkscreen box around both parts.

U9D2

1

OE#

VCC

2

A

GND3Y

NC7SV125L

4

+V5 32,42,43,48,52,55,56,57

+V3.319,32,39,41,42,43,55,57

+V3.3A_1.5A_HDA_IO24,28,44

+VBATS_HDA_R1

HDA_SPKR_R

HDA_DOCK_EN#_J

R9E15

R9E15 0

0

R9E17

.

0

.

HDA_SPKR 23,44

HDA_DOCK_EN# 21,41

HDA Docking Circuit

+V3.3S_1.5S_HDA_IO21,24,28 +V3.3S_1.5S_HDA_IO21,24,28

C9D4

0.1uF

20%

6

5

NC

R9D8 33R9D8 33

4

HDA_SYNC_R

R9E1

R9E1 20K

20K

20%

+VBATS16,19,30,31,55,57

U9E1

1

2

NC7SV125L

3

R9E7

R9E7 0

0

.

OE#

VCC

A

GND3Y

HDA Header for External HDMI Support

+V3.319,32,39,41,42,43,55,57

J6C2

HDA_CODEC_3_CLK HDA_CODEC_3_RST# HDA_CODEC_3_SYNC HDA_CODEC_3_SDATAOUT

These Resistors need to be Mounted appropriately when SDIN2 & SDIN3 need to get tested using the MDC.

To use iHDMI, Must STUFF: R7V23, R7V8, R7V3, R7V4, R5F9. Must NO_STUFF: R7G3, R7G2, R7V7, R7G11, R9E13, R9E10, R9E14, R9E12, R9E8,

To use eHDMI (on SDIN3) Must NO_STUFF: R7V23, R7V8, R7V3, R7V4, R5F9, R9E14, R9E12, R9E8, Must STUFF: R7G3, R7G2, R7V7, R7G11, ONE of R9E13 OR R9E10 depending on the add-in-card.

C9E1

0.1uF

20%

6

5

NC

4

20%

R9E3 33R9E3 33

HDA_SDO_R

R9E4

R9E4 20K

20K

HDA_SDO_DOCK 44HDA_SYNC_DOCK 44

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

High Definition Audio

355659

A

355659

A

355659

A

HDA_SDIN2_RHDA_SDIN2

R9E14

0NO_STUFF

HDA_SDIN3_R1HDA_SDIN3

R9E13

0NO_STUFF

HDA_SDIN3_R2

R9E10

0NO_STUFF

HDA_DOCK_EN#

HDA_DOCK_SDATAIN

2

J6C2

16 14 12 10

8 6 4 2

2X8_HDR_KEY12

15 13 11 9 7

3 1

1 2 3

U9B2

OE1# 1A 1B GND42A

74CBT3306

VCC

OE2#

2B

+V3.3A_1.5A_HDA_IO24,28,44

+VBATS_HDA_R2

R9N3

R9N3 20K

20K

+V5 32,42,43,48,52,55,56,57

C9B3

0.1uF

20%

8 7 6 5

20%

27 58Tuesday, August 28, 2007

+VBATS16,19,30,31,55,57

R6C2

R6C2 0

0

.

HDA_SDATAIN_DOCK 44

Intel Confidential

1

1.0

5

4

3

2

1

D D

Power Supply for High Definiton Audio

+V3.3A19,21,23,24,25,26,27,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

R8T2

R8T2 10K

10K

5%

C8T1

1.0uF

10%

5% .

.

U8E1 SC1563U8E1 SC1563

5

IN

1

SHDN

SC1563_SHDN

R8T5

R8T5 100

100

OUT

GND2ADJ

3

HDA_IO_ADJ

+V1.5A_HDA_IO

4

R8T1

2.55K

1%

1% .

.

R8T4

R8T4 10K

10K

1%

C8T2

C8T2 22uF

22uF

C8E1

0.1uF

10%

10% .

.

+V5S

SI3442BDV

6 5 2 1

C8D6

0.01UF

.

. 10%

10%

Q8D1

4

3

+V1.5S_LDO_QDAC10

+V3.3A19,21,23,24,25,26,27,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

3

Q8T1

C C

VR_ALW_ENABLE45,56

1

Q8T1 BSS138

BSS138

2

Selection of I/O Voltage for the High Definition Audio

+V1.5S4,10,11,24,47,55,57

B B

+V3.3A +V1.5A_HDA_IO

Layout Notes:Place the Two Resistors Next to each Other

NO_STUFF

R8E8 0.002

R8E7 0.002

1%

+V3.3A_1.5A_HDA_IO24,27,44

A A

5

4

3

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3S_1.5S_HDA_IO21,24,27

NO_STUFF

R7H2 0.002

R7H3 0.002

Layout Notes:Place the Two Resistors Next to each Other

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

HDA Power Supply

355659

A

355659

A

355659

A

2

1%

Intel Confidential

28 58Tuesday, August 28, 2007

1

1.0

5

8 7 6 5

+V3.3A

8 7 6 5

+V3.3A19,21,23,24,25,26,27,28,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

18

RP3B1A

RP3B1A 10K

10K

+V3.3A19,21,23,24,25,26,27,28,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

36

RP3B1C

RP3B1C 10K

10K

+V5A_USBPWR_PN4

+V5A_USBPWR_PN6

RP3B1D

RP3B1D 10K

10K

4 5

+V3.3A19,21,23,24,25,26,27,28,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

R4A3

R4A2

10K

5%

U5B1

B1

ESD_CH2

A1

V-

CM1230_02

U5A1

B1

ESD_CH2

A1

V-

CM1230_02

+V5A 24,34,38,44,46,47,50,51,56,57

R3B3

0.002

1%

+V5A_USBPWR_IN3

R3B8

C3B4

0.1uF

20%

C3B3

0.1uF

20%

R3B8 R3B7

R3B7

R3B10

R3B10 R3B9

R3B9

1K

1K 1K

1K

.

. .

.

USB_PN022

USB_PP022

USB_PN222

USB_PP222

USB_PN422

USB_PP422

USB_PN622

USB_PP622

EN1_B

1K

EN2_B

1K

.

. .

.

D D

C C

+V5A_USBPWR_IN3

B B

+V5A_USBPWR_IN3

C4M5

0.1uF

20%

R4M6

R4M6 R4M5

R4M5

USB_PN822

USB_PP822

EN1_E +V5A_USBPWR_PN10

1K

EN2_E

1K

.

. .

.

A A

USB_PN1022

USB_PP1022

EN1_A EN2_A

U3N2

1

GND

2

IN

3

EN1 EN24OC2#

TPS2052B

U3N1

1

GND

2

IN

3

EN1 EN24OC2#

TPS2052B

USB_OC#622

U4A2

1

GND

2

IN

3

EN1 EN24OC2#

TPS2052B

L5B2

1 4

2 3

90@100MHz

L5B1

1 4

2 3

90@100MHz

OC1# OUT1 OUT2

L3B4

1 4

2 3

90@100MHz

L3B3

1 4

2 3

90@100MHz

L3B2

1 4

2 3

90@100MHz

L3B1

1 4

2 3

90@100MHz

OC1# OUT1 OUT2

5

27

RP3B1B

RP3B1B 10K

10K

+V5A_USBPWR_PN0 +V5A_USBPWR_PN2

U3A4

B1

ESD_CH2

A1

V-

CM1230_02

U3A3

B1

ESD_CH2

A1

V-

CM1230_02

U3A2

B1

ESD_CH2

A1

V-

CM1230_02

U3A1

B1

ESD_CH2

A1

V-

CM1230_02

FB3N1

50OHM

FB3N2

50OHM

USB_OC#8 22

+V5A_USBPWR_PN8

USB_OC#10 22

ESD_CH1

V+

ESD_CH1

V+

4

USB_OC#0 22

FB3N3 50OHMFB3N3 50OHM FB3M1 50OHMFB3M1 50OHM

USB_OC#2 22

USBAUSBA+

ESD_CH1

USBCUSBC+

ESD_CH1

USB_OC#4 22

+V5A_L_USBPWR_PN4

+V5A24,34,38,44,46,47,50,51,56,57

A2

B2

+V5A24,34,38,44,46,47,50,51,56,57

A2

B2

4

A2

B2

V+

A2

B2

V+

A2

B2

V+

A2

B2

V+

C3A1

+

220uF

20%

20% .

.

+V5A_L_USBPWR_PN6

C3A2

+

220uF

20%

20% .

.

FB4M1

50OHM

FB4M2

50OHM

+V5A_L_USBPWR_PN0 +V5A_L_USBPWR_PN2

+

C3A3

+

C3A3 220uF

220uF

20%

20% .

.

+V5A24,34,38,44,46,47,50,51,56,57

USBBUSBB+

+V5A24,34,38,44,46,47,50,51,56,57

+V5A_L_USBPWR_PN8

+

C4A3

+

C4A3 220uF

220uF

20%

20% .

.

+V5A_L_USBPWR_PN10

+

C3M6

C3M6 470PF

470PF

C4A6

C4A6 220uF

220uF

20%

.

C3M2

470PF

+

USBFUSBF+

C3B2

C3B2 220uF

220uF

20%

.

C3N1

C3N1 470PF

470PF

C3M1

C4M7

C4M7 470PF

470PF

C4M3

C4M3 470PF

470PF

USBDUSBD+

USBE-

USBE+

3

Quadraple USB Connector Ports 0,2,4,6

J3A1

41

VCC1

TOP

42

P#0

PORT

43

P0

44

GND1

31

VCC2

32

P#1

UPPERMIDDLE

33

P1

PORT

34

GND2

21

VCC3

LOWERMIDDLE

22

P#2

PORT

23

P2

24

GND3

11

VCC4

BOTTOM

12

P#3

PORT

13

P3

14

GND4

QUAD_stack_USB

Layout Note: Place ESD diodes as close to the connector as possible.

RJ45 1000 with Dual USB Connector

J5A1B

1

VCC1

2

P0#

3

P0

4

GND1

5

VCC2

6

P1#

7

P1

8

GND2

RJ45 1000 WITH DUAL USB

1

GND5

2

GND6

3

GND7

4

GND8

5

GND9

6

GND10

+V5A 24,34,38,44,46,47,50,51,56,57

R7H15

0.002

1%

C7H9

0.1uF

10%

10% .

.

Ports 8,10

USB FPIO Header to PCIe connector mapping USB Header USB Port PCIESlot

Header-1 Port 1 & Port 3 Slot 1 & Slot 2 Header-2 Port 5 & Port 7 Slot 3 & Slot 4 Header-3 Port 9 & Port 11

3

USB_PN122 USB_PP122

+V5A 24,34,38,44,46,47,50,51,56,57

R5W15

0.002

1%

C5W9

0.1uF

10%

10% .

.

+V5A 24,34,38,44,46,47,50,51,56,57

R7H5

0.002

1%

R6W2

R6W2 R6W3

R6W3

C7H5

0.1uF

10%

10% .

.

USB_PN9_R_FPIO22

USB_PP9_R_FPIO22

+V5A_USBPWR_IN4

R7W6

1K

1K R7W5

R7W5

1K

.

USB Port Routing Locations USB Port Location

EHCI

USB Port 0 USB Port 1 USB Port 2 USB Port 3 USB Port 4

0

USB Port 5 USB Port 6 USB Port 7 USB Port 8 USB Port 9 USB Port 10

1

USB Port 11

+V5A_USBPWR_IN1 +V5A_USBPWR_PN1_PN3 +V5A_L_USBPWR_PN1_PN3

R5W18

1K

1K R5W19

R5W19

1K

.

USB_PN522 USB_PP522

+V5A_USBPWR_IN2

1K

1K 1K

1K

.

. .

.

EN1_F EN2_F

Back of Chassis FPIO/Duckbay Back of Chassis FPIO/Duckbay Back of Chassis FPIO/Duckbay Back of Chassis FPIO/Duckbay Back of Chassis Docking/FPIO/Duckbay Back of Chassis FPIO/Duckbay

2

1

Header-1: FPIO - Port 1, 3

+V5A_L_USBPWR_PN1_PN3

J6H4

1

2

EN1_C EN2_C

3 4 5 7108

USB_2X5-Header

Header-1

U5H4

1

GND

2

IN

3

EN1 EN24OC2#

TPS2052B

6

OC1# OUT1 OUT2

8 7 6 5

USB_PN3 22 USB_PP3 22

18

RP5W1A

RP5W1A 10K

10K

+V3.3A

27

RP5W1B

RP5W1B 10K

10K

USB_OC#3 22

USB_OC#1 22

FB6H2

50OHM

+

C6H2

+

C6H2 220uF

220uF

20%

20% .

.

C6H3

C6H3 470PF

470PF

Header-2: FPIO - Port 5, 7

+V5A_L_USBPWR_PN5_PN7

J6H2

1

2 3 4 5

6 7108

USB_2X5-Header

Header-2

U6H2

1

GND

EN1_D EN2_D

2 3

Header-3: FPIO - Port 9, 11

U7H2

1

GND

2

IN

3

EN1 EN24OC2#

TPS2052B

LAYOUT NOTE FOR ESD DIODE: CM1230

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

USB 1.1/2.0

355659

OC1#

IN

OUT1

EN1

OUT2

EN24OC2#

TPS2052B

+V5A_L_USBPWR_PN9_PN11

J6J1

1

2 3 4 5

6 7108

USB_2X5-Header

Header-3

USB_OC#9_R_2052

8

OC1#

7

OUT1

6

OUT2

5

Need to have minimum of 150mil clearance step down stencil definition around the ESD diodes CM1230 in layout too. Step down stencil area can accomodate other components. If needed, area for step down stencil definition can even be extended to cover other nearby components to avoid step down area covering the components half way, meaning, if extended step down area should cover other nearby coponents fullly.

2

USB_PN7 22 USB_PP7 22

+V3.3A

45

36

RP5W1D

RP5W1C

10K

USB_OC#5 22

FB6H1

+V3.3A

FB7H1

50OHM

R7W2

R7W2 10K

10K

5%

FB6H1

50OHM

29 58Tuesday, August 28, 2007

+V5A_L_USBPWR_PN9_PN11+V5A_USBPWR_PN9_PN11

+

C7J1

+

C7J1 220uF

220uF

20%

20% .

.

C6H1

+

220uF

20%

20% .

.

USB_OC#9 22

C6J1

C6J1 470PF

470PF

Intel Confidential

8 7 6 5

+V5A_USBPWR_PN5_PN7 +V5A_L_USBPWR_PN5_PN7

USB_OC#7 22

USB_PN11 22

USB_PP11 22

+V3.3A

R7W4

R7W4 10K

10K

5%

R7W1

R7W1 0

0

5%

NO_STUFF

USB_OC#11 22

1

1.0

C6W7

C6W7 470PF

470PF

5

+VBATS16,19,27,31,55,57

R8H131MR8H13 1M

R8H10

D D

SATA_PWR_EN#0_5V

1

R8H10

1M

.

R8W12

R8W12 1M

1M

.

SATA_5V_EN0_1 SATA_5V_EN0_2

3

Q7H2

Q7H2 BSS138

BSS138

2

C C

3

Q8J1

Q8J1 BSS138

BSS138

R8J1

R8J1 10K

10K

1%

1

2

SATA_PWR_EN#0_5V

SATA_PWR_EN#023

4

SATA Port-0,Direct Connect

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

765

Q9Y1

IRF7835

4

5 6

123 8

+V5S5,11,12,16,17,18,24,28,31,32,39,48,49,52,55,56,57

3

SI4925BDY

SI4925BDY Q8H4B

Q8H4B

+V12S25,26,31,32,43,55,57

R9H201MR9H20 1M

R8H11 1MR8H11 1M

IRF7835

2

R8W11

1M

.

SATA_3.3_EN0

C9Y1

C9Y1 1000pF

1000pF

10%

C8W4

C8W4 1000pF

1000pF

10%

4

3

Q9H2

Q9H2 2N7002

2N7002

1

2

1

7 8

SI4925BDY

SI4925BDY Q8H4A

Q8H4A

+V5_SATA_EN0_3

SATA_12V_EN0_2SATA_12V_EN0_1

3

R8Y1 0.002

+V3.3_SATA_EN0_4

R8H12 0.002

C9H5

C9H5 1000pF

1000pF

10%

1

+V3.3S_SATA_P0

1%

Q9H3

SI2307DS

3 2

+V12_SATA_EN0_3 +V12S_SATA_P0

C8J2

C8J2 22uF

22uF

+V5S_SATA_P0

12

+

C8J1

C8J1 100uF

100uF

C8J3

0.1uF

10%

.

SATA_TXP021 SATA_TXN021

SATA_RXN021 SATA_RXP021

NO_STUFF

C8Y1

C8Y1 22uF

22uF

R8W14 0.002

R8J2 4.3R8J2 4.3

R8Y2 1R8Y2 1

TP_SATA_RESEV

TP9H1

C8J4

0.1uF

10%

.

1%

1% C9J2

C8J5

0.1uF

10%

.

+

2

Interlock Switch to SATA port 0

SATA Device Status J7H1

Presence Shunt (Default) Removed No Shunt

J8J1

2

3

5

6

8

9

V_3.3_3_PC

10

V_5.0_7_PC

14 15 16 18

V_12_13_PC

20

C9J2

0.1uF

20%

21 22

Serial ATA Recepticle

C9J3

0.1uF

20%

C9J1

C9J1 15uF

15uF

20%

R9Y1

5.1

This jumper simulates the drive status. For proper function of the hot plug, this jumper must be "No Shunt" when drive is removed and "Shunt" after the drive is plugged in.

SATA Port 0, Direct Connect

TX TX# RX# RX

V_3.3_1 V_3.3_2 V_3.3_3_PC

V_5.0_7_PC V_5.0_8 V_5.0_9 P_RESERVE_11

V_12_13_PC V_12_14 V_12_15

Layout Note: Place this connector on the edge of CRB

GND_2M_P_10

GND_1M_P_12

GND_2M_S_1 GND_2M_S_4 GND_2M_S_7

GND_1M_P_4 GND_2M_P_5 GND_2M_P_6

1 4 7

11 12 13

17

19

SATA_DET#023

1

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57

R7H9

R7H9 43K

43K

J7H1J7H1

1 2

+V12S is only for desktop type SATA devices

B B

SATA Port-5, eSATA

J7J1

SATA_TXP521 SATA_TXN521

SATA_RXN521 SATA_RXP521

2 3

5 6

eSATA_Signal_Plug

A A

5

1

TX

GND1

4

TX#

GND4

7

RX#

GND7

RX

Intel Confidential

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

4

3

Date: Sheet of

SATA (1 of 3)

355659

2

Intel Confidential

30 58Tuesday, August 28, 2007

1

1.0

5

4

3

2

1

SATA Port-1 and Port-2, Cable Connect

SATA Power Connector

D D

+VBATS16,19,27,30,55,57

R6J21MR6J2

3

1

2

SATA_PWR_EN#1_5V

1M

SATA_PWR_EN#1_5V

Q4J3

Q4J3 BSS138

BSS138

1

R6J11MR6J1 1M

1

+V12S25,26,30,32,43,55,57

R4J41MR4J4 1M

3

2

SATA_3.3V_EN1_1

R4J5

R4J5 1M

1M

5%

5% .

.

3

Q4J5

Q4J5 BSS138

BSS138

2

SATA_12V_EN1_1

Q4J2

Q4J2 2N7002

2N7002

C6J2

C6J2 1000pF

1000pF

10%

SATA_5V_EN1_1

+V3.3S

R9H15

R9H15 43K

43K

SATA_DET#123

Interlock Switch to SATA port 1

SATA Device Status J9H2

Presence Shunt (Default)

C C

Removed No Shunt

This jumper simulates the drive status. For proper function of the hot plug, this jumper must be "No Shunt" when drive is removed and "Shunt" after the drive is plugged in.

SATA_PWR_EN#123

SATA Port-2 SATA Port-1 Jumper (J4J2)

Device not connected thru cable

Device connected thru cable

Hot plug/removal supported

Hot plug/removal not supported

Shunt (Default)

No Shunt

J9H2J9H2

1 2

J4J2J4J2

SATA_PWR_EN#1_J

12

R4J2

R4J2 10K

10K

1%

B B

4

SATA_12V_EN1_2

R4J31MR4J3 1M

567

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,32,35,36,38,39,40,41,43,48,49,52,55,56,57

+V3.3_SATA_EN1_3

8

Q6Y1

Q6Y1 IRF7822

IRF7822

.

312

+V5S5,11,12,16,17,18,24,28,30,32,39,48,49,52,55,56,57

C4Y4

C4Y4 1000pF

R4J6 1M

1M

1000pF

10%

1238

765

+V12_SATA_EN1_3

SATA_5V_EN1_2

Q4J4

SI4835BDY

5%R4J6

5%

.

C4Y3

C4Y3 1000pF

1000pF

10%

4

1238

4

R4Y3 0.002

1%

Q4Y1

SI4835BDY

765

+

C5J7

C5J7 15uF

15uF

20%

C5J3

0.1uF

20%

R6J3 0.002

1%

R4Y4 0.002

C5J2

0.1uF

20%

C5J4

0.1uF

C6J3

C6J3 22uF

22uF

10%

.

J5J1

C5J5

0.1uF

10%

.

J5J1

1

V_3.3_1

2

3 4

5

GND_1

V_3.3_2

GND_2

V_5_1

GND_3

V_5_2

GND_4

V_12_1

GND_5

SATA_POWER_CONNECTOR

6 7

8 9

10

+V3.3S_SATA_P1

1%

+V5S_SATA_P1+V5_SATA_EN1_3

12

+

C5J8

C5J8 100uF

100uF

C5J1

C5J1 22uF

22uF

+V12S_SATA_P1

C5J6

0.1uF

10%

.

SATA Signal Connectors

SATA Port-1

J6J3

SATA_TXP121 SATA_TXN121

SATA_RXN121 SATA_RXP121

2 3

5 6

SATA_Signal_Plug

1

TX

GND1

4

TX#

GND4

7

RX#

GND7

RX

SATA_TXP421 SATA_TXN421

SATA_RXN421 SATA_RXP421

A A

Notes:

-- Both SATA Port-1 and SATA Port-2 share the same power connector, J5J1

-- Use Y-Cable available with Kit to feed the power from J5J1 to SATA device on port-1 and SATA device on Port-2.

-- Connect Power cable first before connecting SATA signal cable.

5

4

SATA Port-4

J6J2

2

TX

3

TX#

5

RX#

6

RX

SATA_Signal_Plug

GND1 GND4

GND7

1 4

7

Intel Confidential

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

3

Date: Sheet of

SATA (2 and 3 of 3)

355659

2

Intel Confidential

31 58Tuesday, August 28, 2007

1

1.0

5

4

3

2

1

D D

C C

B B

Place close to PCI Edge Connector

NO_STUFF

TP8D2TP8D2

TP9D2TP9D2

TP9D1TP9D1

TP8D1TP8D1

C8B2

C8B2 10uF

10uF

1%

C9B1

0.1uF

20%

+V5_PCI

+V12S_PCI

C9B2

0.1uF

20%

+V5 27,42,43,48,52,55,56,57

R8B3 0.002

NO_STUFF

+V12S25,26,30,31,43,55,57

R8B1 0.002

+V3.3S

-V12S57

+V5_PCI +V12S_PCI

+V5S_PCI

+V3.3S_PCI

PCI_REQ#022

INT_PIRQE#22 INT_PIRQF#22

PCI_REQ#122

PCI_GNT#122

CLK_PCI_PCIGOLDF36

PCI_REQ#322

PCI_AD3122 PCI_AD2922

PCI_AD2722 PCI_AD2522

PCI_CBE#322 PCI_AD2322

PCI_AD2122 PCI_AD1922

PCI_AD1722 PCI_CBE#222

PCI_IRDY#22

PCI_DEVSEL#22

PCI_LOCK#22 PCI_PERR#22

PCI_SERR#22

PCI_CBE#122 PCI_AD1422

PCI_AD1222 PCI_AD1022

PCI_AD822 PCI_AD722

PCI_AD522 PCI_AD322

PCI_AD122

S9B1

B1

-12V

B2

GND(TCK)

B3

GND1

B4

REQ#0(TDO)

B5

+5V_1

B6

+5V_2

B7

INTB#

B8

INTD#

B9

REQ#1(PRSNT1#)

B10

RSV1

B11

GNT#1(PRSNT2#)

B12

GND2

B13

GND3

B14

+3.3V(RSV2)

B15

GND4

B16

CLK

B17

GND5

B18

REQ#5(REQ#)

B19

+5V(+V_I/O1)

B20

AD31

B21

AD29

B22

GND6

B23

AD27

B24

AD25

B25

+3.3V_2

B26

C/BE3#

B27

AD23

B28

GND7

B29

AD21

B30

AD19

B31

+3.3V_3

B32

AD17

B33

C/BE2#

B34

GND8

B35

IRDY#

B36

+3.3V_4

B37

DEVSEL#

B38

GND9

B39

LOCK#

B40

PERR#

B41

+3.3V_5

B42

SERR#

B43

+3.3V_6

B44

C/BE1#

B45

AD14

B46

GND10

B47

AD12

B48

AD10

B49

GND11

B52

AD08

B53

AD07

B54

+3.3V_7

B55

AD05

B56

AD03

B57

GND12

B58

AD01

B59

+5V(+V_I/O2)

B60

+5V(ACK64#)

B61

+5V_3

B62

+5V_4

PCI_EXTENSION_GOLDFINGERS_5V

NO_STUFF

5V KEY

GND(TRST#)

INT#(TMS)

GNT#0(TDI)

+5V(+V_I/O3)

+5V(RSV4)

+5V(+V_I/O4)

GNT#5(GNT#)

+3.3V(IDSEL)

+5V(+V_I/O5) +5V(REQ64#)

+12V

+5V_5 INTA# INTC# +5V_6

RSV3

GND13 GND14

3.3VAUX RST#

GND15

PME#

AD30

+3.3V_11

AD28 AD26

GND16

AD24

+3.3V_12

AD22 AD20

GND17

AD18 AD16

+3.3V_13

FRAME#

GND18 TRDY# GND19 STOP#

+3.3V_14

SMBCLK SMBDAT

GND20

AD15

+3.3V_15

AD13 AD11

GND21

AD09

C/BE0#

+3.3V_16

AD06 AD04

GND22

AD02 AD00

+5V (7) +5V (8)

PAR

+V3.3A

+V5S_PCI

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62

+V3.3S_PCI

PM_SLP_S4#_R

PCI_RST#_R

PCI_GNT3

INT_PIRQH# 22 PCI_GNT#0 22

INT_PIRQC# 22 INT_PIRQG# 22

PM_CLKRUN# 23,38,40,43

PCI_PME# 22,43

PCI_AD30 22

PCI_AD28 22 PCI_AD26 22

PCI_AD24 22

PCI_AD22 22 PCI_AD20 22

PCI_AD18 22 PCI_AD16 22

PCI_FRAME# 22

PCI_TRDY# 22

PCI_STOP# 22

SMB_CLK_A1 23,25,26,44 SMB_DATA_A1 23,25,26,44

PCI_PAR 22 PCI_AD15 22

PCI_AD13 22 PCI_AD11 22

PCI_AD9 22

PCI_CBE#0 22

PCI_AD6 22 PCI_AD4 22

PCI_AD2 22 PCI_AD0 22

R9B1

R9B1 0

0 R9B3

R9B3 0NO_STUFF

0NO_STUFF

.

PCI - EDGE CONNECTOR

(GOLDFINGER)

Default is to use pin A11 as a +V5S power pin (R9N2 stuffed)

Stuff R9N3 and unstuff R9N2 if using ATX power supply directly on extension board.

DO NOT STUFF BOTH R9N3 AND R9N2 AT THE SAME TIME

+V5S5,11,12,16,17,18,24,28,30,31,39,48,49,52,55,56,57

PM_S4_STATE# 23,40,43,44,55,57

R9P1

R8P21KR8P2

R9P1 0

0 R9P2

R9P2 0 NO_STUFF

0 NO_STUFF

.

+V3.3S

LVL_PCIRST#

1K

1

3

Q8P1

Q8P1 2N3904

2N3904

2

PCI_RST# 22,41

PCI_GATED_RST# 41

+V3.3S_PCI

R8P3

R8P3 10K

10K

.

PCI_GNT#3 22

+V5

NO_STUFF

+V3.3 19,27,39,41,42,43,55,57

NO_STUFF

+V5S

R9N1

0.002

1%

+V3.3S

R9D5

0.002

1%

R9D2

0.002

1%

C9D5

C9D5 22uF

22uF

Place close to PCI Edge Connector

R9B2

0.002

1%

C9E2

C9E2 22uF

22uF

Place close to PCI Edge Connector

+V5S_PCI

C9C3

C9C2

0.1uF

20%

+V3.3S_PCI

C9C4

C9D2

0.1uF

20%

C9C1

0.1uF

C9E3

0.1uF

20%

A A

Intel Confidential

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

5

4

3

Date: Sheet of

PCI Edge Connector (Goldfinger)

355659

2

Intel Confidential

32 58Tuesday, August 28, 2007

1

1.0

5

C8B1

C8B1 27pF

27pF

5%

5% .

.

41

Y8A1

Y8A1 25MHZ

25MHZ

C8A8

C8A8 27pF

27pF

5%

5% .

.

D D

R8A12 4.99K

.

Place C8M15 & C8M16 close to LAN Controller

LAN_MDI0P34 LAN_MDI0N34

LAN_MDI1P34 LAN_MDI1N34

LAN_MDI2P34 LAN_MDI2N34

LAN_MDI3P34

C C

LAN_MDI3N34

R8A4

R8A4 10K

10K

5%

5% .

.

+V3.3M_LAN

GLAN_CLK21

1%

GLAN_RXP22 GLAN_RXN22

R8M10

R8M10 0

0

NO_STUFF

Layout Note: Keep this resistor on top side and route differentially

R8A5

R9A2

200

5%

NO_STUFF

LAN_RSTSYNC21

LAN_TXD221 LAN_TXD121 LAN_TXD021

LAN_RXD221 LAN_RXD121 LAN_RXD021

GLAN_TXP22 GLAN_TXN22

C8M16 0.1uF

LAN_ATEST_N LAN_ATEST_P

LAN_JTAG_TDO

LAN_JTAG_TMS

LAN_JTAG_TDI

LAN_JTAG_TCK

LAN_XTAL1

10%

10% .

.

LAN_JTAG_TRST

LAN_XTAL2

+V3.3M_LAN+V3.3M_LAN

Place GLAN_CLK series resistor close to LAN Controller

C8M15

0.1uF

10%

10% .

.

GLAN_CLK_R

GLAN_RXP_C GLAN_RXN_C

LAN_TEST_EN

R8M6 33R8M6 33

RES_COMP

R9A1

R9A1 200

200

5%

5% NO_STUFF

NO_STUFF

Place crystal less than

0.75 (~1.9 cm) inches from LAN Controller

EU8A1

10

XTAL1

9

XTAL2

45

JKCLK

50

JRSTSYNC

44

JTXD2

43

JTXD1

42

JTXD0

49

JRXD2

48

JRXD1

47

JRXD0

15

RSET

55

GLAN_RXP

56

GLAN_RXN

52

GLAN_TXP

53

GLAN_TXN

27

MDI_PLUS[0]

26

MDI_MINUS[0]

23

MDI_PLUS[1]

22

MDI_MINUS[1]

21

MDI_PLUS[2]

20

MDI_MINUS[2]

17

MDI_PLUS[3]

16

MDI_MINUS[3]

51

NC

36

TEST_EN

13

IEEE_TEST_N

12

IEEE_TEST_P

40

JTAG_TCK

7

JTAG_TDI

6

JTAG_TDO

39

JTAG_TMS

35

JTAG_TRST

IC,BOAZ,56QFN,11-28-06,LAN,R0p7

B B

TP9A1

TP9A3

NO_STUFF

TP9A1

TP9A4

NO_STUFF

R8A1

R8A1 1K

1K

NO_STUFF

TP9A5

TP9A6

4

+V3.3M_LAN

3

VCC3P3[1]

46

VCC3P3[2]

28

VCC3P3[3]

5

VCC1P0[1]

8

VCC1P0[2]

LCI

GLCI MDI JTAG

VCC1P0[3] VCC1P0[4]

VCC1P8[1] VCC1P8[2] VCC1P8[3] VCC1P8[4] VCC1P8[5] VCC1P8[6] VCC1P8[7] VCC1P8[8] VCC1P8[9]

VCC1P8[10]

DIS_REG1P0

CTRL10

CTRL18

LAN_DIS#

LED0 LED1 LED2

VSS

33 38

11 14 18 19 24 25 30 32 54 41

34

31

CTRL_18

29

LAN_DIS

37

4 2 1

57

3

+V3.3M_WOL22,24,34,44,48,55,57 +V3.3M_LAN +V1.8_LAN_M34+V1.8_LAN

R7A2

1 2

C8A2

1 2

CTRL_10CTRL_10_R

R8M3, R8M1, Q9A1 (Default)

C8A2

4.7uF

10%

R8A3

0.002

+V3.3M_LAN

R8A6

R8A6 10K

10K

5%

5% .

.

R8M2

+V1.0_LAN_M

+V1.8_LAN_M34

C8M11

0.1uF

10%

+V1.0_LAN_M_IN

DIS_REG1P0

R8M3

R8M3 0

0

5%

5% .

.

LAN_LED_LNK#_ACT 34

LAN_LED_1000# 34

LAN_LED_100# 34

1V Source Stuff No_Stuff

IVRi

IVRd

0.002

+V3.3M_LAN

R8M11KR8M1 1K

R8M2

R8M2 1K

1K

NO_STUFF

R8A2

0

NO_STUFF

R8M3, R8M1, Q9A1

R8M2

PM_LAN_ENABLE 23,40,43

CTRL_18

Place C8M14 close to PNP Collector (pin4)

CTRL_10

2

R8A11

1 2

0.002

+V3.3M_LAN

C9M3

R9A7 5.1K

5%

5% .

.

R9A8 5.1K

5%

5% .

.

1

C8M14

C8M14 10uF

10uF

20%

3

2 4

+V1.8_LAN

1

Q9A2

Q9A2 BCP69

BCP69

+V1.8_LAN_M34

2 4

C9M3

0.1uF

10%

3

+V1.8_LAN

C9M2

0.1uF

10%

Q9A1

Q9A1 BCP69

BCP69

C8A5

C8A5 10uF

10uF

80%

C9M4

C9M4 10uF

10uF

20%

.

C8M2

0.1uF

10%

1

Place C9M3 & C9M4 close to pin3

+V1.8_LAN_M

C8M9

C8M3

C8M12

0.1uF

10%

Place C8A5, C8M2, C8M12, C8M3, C8M9, C8M8 & C8M7 close to LAN Controller (EU8A1)

C9M1

Place C9M1 & C9M2

10uF

close to pin3

20%

.

+V1.0_LAN_M

0.1uF

10%

0.1uF

10%

C8M8

0.1uF

10%

C8M7

0.1uF

10%

+V1.0_LAN_M

Place C8M6 close to PNP Collector (pin4)

A A

5

4

3

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

A

LAN Boazman

355659

2

C8M6

C8M6 10uF

10uF

20%

C8A1

C8A1 10uF

10uF

80%

+V1.0_LAN_M_IN

C8M13

C8M4

C8M5

0.1uF

10%

33 58Tuesday, August 28, 2007

C8M4

0.1uF

10%

Place C8A1, C8M5, C8M13 & C8M4 close to LAN Controller (EU8A1)

Intel Confidential

1

1.0

5

+V3.3M_WOL22,24,33,44,48,55,57

EU7A1

LAN_DOCK_EN#_R

LAN_MDI0P33

D D

C C

LAN_MDI0N33 LAN_MDI1P33 LAN_MDI1N33 LAN_MDI2P33 LAN_MDI2N33 LAN_MDI3P33 LAN_MDI3N33

LAN_LED_LNK#_ACT33

Layout Note: This is thermal PAD of IC (at bottom) and to be shorted to GND

DOCK_LAN_EN#41

LAN_LED_1000#33 LAN_LED_100#33

+V3.3M_WOL22,24,33,44,48,55,57

NO_STUFF

R7A4

R7A4 0

0

.

NO_STUFF

17

2 3 7

8 11 12 14 15

19 20 54

57

R7A3

R7A3 10K

10K

5%

LAN_DOCK_EN#_R

R7M8

R7M8 1K

1K

5%

EU7A1

SEL

A0 A1 A2 A3 A4 A5 A6 A7

LED0 LED1 LED2

THRM

56

VDD438VDD327VDD218VDD110VDD0

VDD550VDD6

PI3L500 LAN Switch

GND01GND16GND29GND313GND416GND521GND624GND728GND833GND939GND1044GND1149GND1253GND13

+V3.3M_WOL22,24,33,44,48,55,57

C7M1

C7M4

0.1uF

10%

.

4

5

4

NC

55

LAN_MDI0P_Q LAN_MDI0N_Q LAN_MDI1P_Q LAN_MDI1N_Q

0LED1 1LED1 2LED1

0LED2 1LED2 2LED2

0B1 1B1 2B1 3B1 4B1 5B1 6B1 7B1

0B2 1B2 2B2 3B2 4B2 5B2 6B2 7B2

48 47 43 42 37 36 32 31

22 23 52

46 45 41 40 35 34 30 29

LAN_LED_LNK#_ACT_Q

25

LAN_LED_1000#_Q

26

LAN_LED_100#_Q

51

U5M1

1

I/O1

2

I/O2

3

I/O3

4

I/O4

ESD DIODE ARRAY

NO_STUFF

LAN_MDI0P_Q_DOCK 44 LAN_MDI0N_Q_DOCK 44 LAN_MDI1P_Q_DOCK 44 LAN_MDI1N_Q_DOCK 44 LAN_MDI2P_Q_DOCK 44 LAN_MDI2N_Q_DOCK 44 LAN_MDI3P_Q_DOCK 44 LAN_MDI3N_Q_DOCK 44

LAN_MDI0P_Q LAN_MDI0N_Q LAN_MDI1P_Q

LAN_MDI1N_Q LAN_MDI2P_Q LAN_MDI2N_Q LAN_MDI3P_Q LAN_MDI3N_Q

8

5

VP

VN

3

LAN_LED_LINK#_DOCK 44 LAN_LED_1000#_DOCK 44 LAN_LED_100#_DOCK 44

+V3.3M_WOL22,24,33,44,48,55,57

LAN_LED_LNK#_ACT_Q

LAN_LED_100#_Q LAN_LED_1000#_Q

LAN_MDI2P_Q

10

I/O8

LAN_MDI2N_Q

9

I/O7

LAN_MDI3P_Q

7

I/O6

LAN_MDI3N_Q

6

I/O5

+V1.8_LAN_M33

R5B1

R5B1 0

0

.

LAN_RJ45_VCT

C5N1

0.01uF

10%

10% .402

.402

9

10 11 12 13 14 15 16 17

19 20 21 22

18

+V1.8_LAN_M33

R9C4

R9C4 0

0

.

Place C5A1 & C5N1 close

C5A1

to RJ45

0.01uF

10%

10% .402

.402

J5A1A

VCC0

0+ 01+ 12+ 23+ 3-

LED_LINK# LED_ACT LED_100# LED_1000#

GND0

RJ45 1000 WITH DUAL USB

2

+V1.8_VCT_LAN_DOCK44

C9C5

0.01uF

10%

.402

ACTIVITY LED Green = LINK UP BLINKING = TX/RX ACTIVITY

SPEED LED Off = Link 10 Mbps Green = Link 100 Mbps Orange = Link 1000 Mbps

Place C9C5 & C9C6 close

C9C6

to docking connector

0.01uF

10%

10% .402

.402

1

VCC

SPI Interface

LAYOUT NOTE:

At any time either U8B2/U8C3 or U8C1/U8C3 can be stuffed.

U8B2/U8C3

B B

A A

1

HOLD#

VCC

2

NC

3

NC

4

U8C1/U8C4

NC

5

NC NC

CS#

DO WP#

SPI_CS#0_CON

SPI0_SI_R

SPI0_WP#

SPI0_HOLD#

+V3.3M_SPI_CON +V3.3M_SPI_CON

1 2 3 4

6

7

8 9

U8B2

7

CS#

15

DI

9

WP#

1

HOLD#

2

VCC

3

NC1

4

NC2

5

NC3

6

NC4

32Mb SPI FLASH

NO_STUFF

5678

GND

CLK

NC5 NC6 NC7 NC8

CLK

16

DI

15

NC

14

NC

13

NC

12

11

VSS

10

16

8

DO

11 12 13 14

10

SPI0_CLK_R

SPI0_SO_R

+V3.3M_SPI_CON

C8N2

0.1uF

10%

.

5

GND

CS

CLK

MISO

MOSI

SPI ISP Conn pinout

+V3.3M_SPI

1 2

C9P1

0.1uF

10%

.

SPI_CS#1_CON

SPI1_SI_R

SPI1_WP#

SPI1_HOLD#

R7T21

5%

5% NO_STUFF

NO_STUFF

R8R1

0.002

+V3.3M_SPI_CON

ICH_GPIO60_SPI ICH_GPIO24_SPI

0

+V3.3M_WOL22,24,33,44,48,55,57

U8C3

7

CS#

15

DI

9

WP#

1

HOLD#

2

VCC

3

NC1

4

NC2

5

NC3

6

NC4

32Mb SPI FLASH

NO_STUFF

SPI_CS# SPI_SO_SW

NC5 NC6 NC7 NC8

GND

CLK

DO

J8D2

1 2 3 4 5 6 7 8

8Pin HDR

+V3.3M_SPI_CON

SPI1_CLK_R

16

SPI1_SO_R

8

11 12 13 14

10

SPI_CLK_SW

+V3.3M_SPI_CON

+V3.3M_SPI

4

SPI_SI_SW

5%

5% NO_STUFF

NO_STUFF

R8P1

R8P7

R7F11

0

SPI_CS0#_PULLUP

3.3K

SPI_CS1#_PULLUP

3.3K

+V5A24,29,38,44,46,47,50,51,56,57

SPI_SO22

C8R1

0.1uF

10%

.

ICH_GPIO24 23ICH_GPIO6023

OE#1

Mode J9D1 J8C1 J9C1

Normal Operation

Programing SPI0

Programing SPI1

1 2

SPI_CS#022

U8D1

1

1OE#

2

SPI_SO_SW

1A

3

1B

4

2OE#

5

2A

6

2B

7

GND

1-X 1-XAll

1-2 1-21-2

1-2 1-2

J9D1.J9D1

.

J9C1.J9C1

.

OE#1

SPI_CS#0_CON

74CBT3125

Open

3-X

1-X 2-3

SPI_CS#0_CON

SPI_CS#1_CON

14

VCC

13

4OE#

12

4A

11

4B

10

3OE#

9

3A

8

3B

3

1 2 3 4

+V5A24,29,38,44,46,47,50,51,56,57

+V3.3M_SPI_CON

C8P1

0.1uF

10%

.

J8C1

1

2

3

CON3_HDR

U8R1

1OE#

VCC

1A

2OE#

1B

2B

GND

2A

SN74CBTD3306

SPI_SI_SW

SPI_CLK_SW

SPI_CS#

8 7 6 5

OE#1

.

+V3.3M_SPI_CON

C8N3

0.1uF

0.1uF R8P5

R8P5

10%

.

SPI_CS#1_CON

SPI_SI 22

SPI_CLK 22

+V5A24,29,38,44,46,47,50,51,56,57

C8R2

0.1uF

10%

.

3.3K

R8P4

3.3K

OE#1

+V5A24,29,38,44,46,47,50,51,56,57

OE#1

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

U8C4

8

VDD

SPI1_WP# SPI1_CLK_R

3

WP#

SPI1_HOLD#

7

HOLD#

SST SPI FLASH

R8R2

R8R2 100

100

.

SPI_CS#1 22

LAN Docking and SPI

355659

SI

SO CE# SCK

VSS

SPI1_SI_R

SPI0_SI_R

SPI0_SO_R

SPI1_SO_R

SPI0_CLK_R

SPI1_CLK_R

SPI1_SI_R

5

SPI1_SO_R

2

SPI_CS#1_CON

1 6

4

R8P8 15 1%R8P8 15 1%

+V3.3M_SPI_CON

R8N6 47R8N6 47

R8N2 47R8N2 47

R8N3 47R8N3 47

R8N5 47R8N5 47

R8N7

R8N4

SPI_SO_R

.

8

SPI0_WP#

3

3.3K

SPI0_HOLD#

7

3.3K

R8N8 15 1%R8N8 15 1%

R8P6

R8P6 0

0

5%

5% .

.

U8C1

VDD

WP#

HOLD#

SST SPI FLASH

34 58Tuesday, August 28, 2007

2

SPI0_SI_R

5

SI

SPI0_SO_R

2

SO

SPI_CS#0_CON

1

CE#

SPI0_CLK_R

6

SCK

4

VSS

SPI_SI_SW

SPI_SO_SW

SPI_CLK_SW

Intel Confidential

1

1.0

5

4

3

2

1

+V1.05M9,10,15,47,55

+V3.3M 13,14,15,23,55,57

1%

CLK_PCI36

CLK_PCIF36

R5W8

49.9

1%

NO_STUFF

5

VDD_CK505

C5W1

4.7uF

10%

.

XTAL_OUT XTAL_IN

C5W4

C5W4 33pF

33pF

5%

5% .

.

J1G5 -> 1-2 J1G3 -> 1-2 J1G1 -> 1-2

J1G5 -> Open J1G3 -> 2-3 J1G1 -> 2-3

J1G5 -> Open J1G3 -> Open J1G1 -> 2-3

J1G5 -> 2-3 J1G3 -> Open J1G1 -> 2-3

R5W2

R5W2 0

0

R5W6

NO_STUFF

0

NO_STUFF

+V3.3S

R5G12

R5G12 10K

10K

5%

(Default

Setting)

R5V9

R5V9 10K

10K

5%

C6V8

0.1uF

10%

.

C6V13

0.1uF

10%

.

C6V11

4.7uF

10%

.

C5H1

0.1uF

10%

C6W6

0.1uF

10%

10% .

.

XTAL_OUT

C6W3

0.1uF

10%

10% .

.

C6V6

0.1uF

10%

10% .

.

R5G13 22R5G13 22

R5G11 22R5G11 22

CLK_USB4823

CLK_BSEL0

CLK_BSEL1

CLK_REF_ICH23

CLK_REF_SIO38

CLK_REF_LPC43

CPU_BSEL03

CPU_BSEL13

CPU_BSEL23

PCI1

+V1.05S_CPU3,4,20,39,43,52,54

R1G456R1G4 56

BSEL0_PULLUP

1

3

CON3_HDR

1

3

CON3_HDR

1

3

CON3_HDR

J1G5

J1G3

J1G1

SMB_CLK_M323,36

SMB_DATA_M323,36

2

4

R5G9 33R5G9 33

R5G8 2.2KR5G8 2.2K

R5H2

10K

R5W9 33R5W9 33

.

R5H3 33R5H3 33

R5H4 33R5H4 33

R5G14

475

475 .1%

+V1.05S_CPU3,4,20,39,43,52,54

R1F21KR1F2 1K

CLK_MCH_R_OE#

R5G15

R1G11KR1G1 1K

CLK_BSEL0

R1G61KR1G6 1K

CLK_BSEL1

CLK_BSEL2

PCI1_R

XDP_OBS020

XDP_OBS120

XDP_OBS220

+VDDIO_CLK

PCI4_SRC5_EN

PCIF5_ITP_EN

FSA

FSCCLK_BSEL2

R5V8 0.002

RP1F1B

RP1U1B0RP1U1B

RP1F1C

RP1U1C0RP1U1C

R5V12 0.002

D D

Y5H1

2 1

14.318MHZ

C C

B B

NO_STUFF

C5W3

C5W3 33pF

33pF

5%

5% .

.

J5H1

XTAL_IN_D XTAL_IN

35 412

5Pin_JACK

FSB Frequency Select:

CPU Driven

1067

FSB Speed (MT/s)

800

667

A A

1%

EU6H1

56

VDD_CPU_I/O

33

VDD_SRC0_I/O

43

VDD_SRC1_I/O

52

VDD_SRC2_I/O

19

VDD_I/O

27

VDD_PLL3_I/O

23

VDD_PLL3

62

VDD_CPU

9

VDD_PCI

4

VDD_REF

46

VDD_SRC

16

VDD_48

2

XTAL_OUT

3

XTAL_IN

17

USB/FS_A

64

FSB/TEST_MODE

5

REF/FSC/TEST_SEL

8

PCI0/CLKREQ_A#

10

PCI1/CLKREQ_B#

11

PCI2

12

PCI3

13

PCI4/SEL_LCDCLK#

14

PCIF5/ITP_EN

7

SCL

6

SDA

15

VSS_PCI

18

VSS_48

22

VSS_I/O

26

VSS_PLL3

30

VSS_SRC0

36

VSS_SRC1

59

VSS_CPU

49

VSS_SRC2

1

VSS_REF

65

THERM

SLG8SP533

SPARE

RP1F1D

RP1U1D0RP1U1D

R1G5 1KR1G5 1K

RP1F1A

RP1U1A0RP1U1A

R1G3 1KR1G3 1K

R1F1 1KR1F1 1K

+VDDIO_CLK

C6W4

0.1uF

10%

.

CK505D QFN-64

45

0NO_STUFF

45

0

18

0NO_STUFF

18

0

27

0NO_STUFF

27

0

36

0NO_STUFF

36

0

3

C6W5

0.1uF

10%

.

SRC11#/CLKREQ_G#

C6V10

C6W1

0.1uF

10%

.

Place each 0.1uF cap as close as possible to each VDD_IO pin. Place the 10uF cap on the VDD_IO plane.

45

PCI_STOP#

44

CPU_STOP#

58

CPU1_MCH

57

CPU1_MCH#

61

CPU0

60

CPU0#

SRC2#

SRC2

SRC4#

SRC4

SRC9#

SRC9

SRC10#

SRC10

SRC6#

SRC6

LCDCLK/27M

SRC0/DOT_96

MCH_BSEL0 7

XDP_BPM#3 3

MCH_BSEL1 7

XDP_BPM#2 3

MCH_BSEL2 7

XDP_BPM#1 3

54 53

29 28

51 50

40 39

35 34

32 31

38 37

42 41

47 48

24 25

21 20

63

55

NC

SRC8/CPU_ITP

SRC8#/CPU_ITP#

SRC7/CLKREQ_F#

SRC7#/CLKREQ_E#

SRC11/CLKREQ_H#

SRC3#/CLKREQ_D#

SRC3/CLKREQ_C#

LCDCLK#/27M_SS

SRC0#/DOT_96#

CKPWRGD/PD#

C5V7

0.1uF

10%

.

CLK_CPU1 CLK_CPU#1

CLK_CPU0 CLK_CPU#0

CLK_SRC8_ITP CLK_SRC#8_ITP#

CLK_SRC2# CLK_SRC2

PCI0_OE#_R

CLK_SRC7 CLK_SRC#7

CLK_SRC#4 CLK_SRC4

CLK_SRC#3 CLK_SRC3

CLK_SRC#9 CLK_SRC9

CLK_SRC#10 CLK_SRC10

CLK_SRC#6 CLK_SRC6

CLK_SS_CLK CLK_SS_CLK#

CLK_DOT96# CLK_DOT96

C6V9

C6V7

0.1uF

C6V12

C6W2

10%

.

PM_STPPCI# 23,43 PM_STPCPU# 23,43

R6H11 0

R6H11 0 R6H10 0

R6H10 0

R6H13 0

R6H13 0 R6H12 0

R6H12 0

R6H9 0

R6H9 0 R6H8 0

R6H8 0

R6G9 0

R6G9 0 R6G10 0

R6G10 0

R6H14 475R6H14 475

R6H2 0

R6H2 0 R6G19 0

R6G19 0

R6G16 0

R6G16 0 R6G15 0

R6G15 0

R6G7 0

R6G7 0 R6G8 0

R6G8 0

R6G18 0

R6G18 0 R6G17 0

R6G17 0

R6H5 0

R6H5 0 R6H3 0

R6H3 0

R6H6 0

R6H6 0 R6H7 0

R6H7 0

R6G12 0

R6G12 0 R6G11 0

R6G11 0

R6G13 0

R6G13 0 R6G14 0

R6G14 0

R6W1 0

Title

Size Document Number Rev

Custom

Date: Sheet of

C6W2

10uF

20%

.

. .

.

. .

.

. .

.

. .

.

. .

.

. .

.

. .

.

. .

.

. .

.

. .

.

. .

.

. .

.

Pillar Rock

CK505

355659

C5V6

C5V5

10uF

20%

.

CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6

CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3

CLK_XDP 20 CLK_XDP# 20

CLK_PCIE_3GPLL# 7 CLK_PCIE_3GPLL 7

CLK_SATA_OE# 23

CLK_SRC_DB800 36 CLK_SRC_DB800# 36

CLK_PCIE_PEG# 19 CLK_PCIE_PEG 19

CLK_PCIE_XDP_3GPLL# 20 CLK_PCIE_XDP_3GPLL 20

CLK_PCIE_DMI_LAI# CLK_PCIE_DMI_LAI

CLK_PCIE_ICH# 22CLK_MCH_OE#7 CLK_PCIE_ICH 22

CLK_PCIE_SATA# 21 CLK_PCIE_SATA 21

DREFSSCLK 7 DREFSSCLK# 7

DREFCLK# 7 DREFCLK 7

CLK_PWRGD 23,36

CLK_PWRGD_R

2

CPU,MCH and XDP BCLK FREQUENCY SELECTION TABLE

FSB

BSEL1

0

1

0

1

FSA

Host Clock frequency MHz

BSEL0

1

0

1

35 58Tuesday, August 28, 2007

100

133

166

200

266

333

400

Reserved

Intel Confidential

FSC

BSEL2

1

0

1

1.0

5

+V3.3S +V3.3S_DB800

C7P4

0.1uF

10%

.

D D

CLK_PWRGD23,35

.

5

2 4

3

U7C1

INVERTER

R7C9

0.002

1%

1% .

.

R7P8

R7P8 10K

10K

5%

5% .

.

R7P9

R7P9 10K

10K

5%

5% NO_STUFF

NO_STUFF

R7C15

R7C15 10K

10K

5%

5% .

.

C7C2

C7C2 22uF

22uF

+V3.3S_DB800

C7P3

0.1uF

10%

.

R7C111R7C11 1

R7D2

R7D2 10K

10K

5%

5% .

.

R7P14

R7P14 10K

10K

5%

5% NO_STUFF

NO_STUFF

4

C7P5

0.1uF

10%

.

AGND_DB800

C7P1

0.1uF

10%

.

R7P10

R7P10 10K

10K

5%

5% NO_STUFF

NO_STUFF

R7P12

R7P12 10K

10K

5%

5% .

.

C7P2

0.1uF

10%

.

3

C7P7

C7P6

0.1uF

10%

R7P11

.

DB800_PD DB800_SRC_STOP

DB800_HIGH_BW# DB800_SRC_DIV#

DB800_BYPASS#_PLL

DB800_IREF

R7C12

R7C12 475

475

R7P11 10K

10K

5%

5% .

.

DB800_OEINV

R7P7

R7P7 0

0

.

CLK_SRC_DB80035 CLK_SRC_DB800#35

SMB_CLK_M323,35 SMB_DATA_M323,35

AGND_DB800

U7C2

2 11 19 31 39 48 40

4

5

23 24

26 27

45 28

1

22

46

3 10 18 25 32 47

DB800

VDD1 VDD2 VDD3 VDD4 VDD5 VDDA OE_INV

SRC_IN SRC_IN#

SCLK SDATA

PWRDWN SRC_STOP

LOCK HIGH_BW# SRC_DIV#

BYPASS#/PLL

IREF

GND1 GND2 GND3 GND4 GND5 GNDA

DIF0

DIF#0

OE0#

DIF1

DIF#1

OE1#

DIF2

DIF#2

OE2#

DIF3

DIF#3

OE3#

DIF4

DIF#4

OE4#

DIF5

DIF#5

OE5#

DIF6

DIF#6

OE6#

DIF7

DIF#7

OE7#

DIF0 DIF#0

DIF1 DIF#1+V3.3S_DB800_VDDA

DIF2 DIF#2

DIF3 DIF#3

DIF4 DIF#4

DB800_OE5#

DB800_OE6#

DIF7 DIF7#

R7C21 33R7C21 33 R7C22 33R7C22 33

R7C23 33R7C23 33 R7C24 33R7C24 33

R7C16 33R7C16 33 R7C17 33R7C17 33

R7C25 33R7C25 33 R7C26 33R7C26 33

R7P2 33R7P2 33 R7P1 33R7P1 33

R7C14 10KR7C14 10K

R7C13 10KR7C13 10K

R7C18 33R7C18 33 R7C19 33R7C19 33

8 9 6

12 13 14

16 17 15

20 21 7

30 29 43

34 33 35

38 37 36

42 41 44

2

CLK_PCIE_SLOT1 25 CLK_PCIE_SLOT1# 25

CLK_SLOT1_OE# 25

CLK_PCIE_SLOT2 25 CLK_PCIE_SLOT2# 25

CLK_SLOT2_OE# 25

CLK_PCIE_SLOT3 26 CLK_PCIE_SLOT3# 26

CLK_SLOT3_OE# 26

CLK_PCIE_SLOT4 26 CLK_PCIE_SLOT4# 26

CLK_SLOT4_OE# 26

CLK_PCIE_SLOT5 26 CLK_PCIE_SLOT5# 26

CLK_SLOT5_OE# 26

CLK_PCIE_DOCK 44 CLK_PCIE_DOCK# 44 CLK_REQ#_DOCK 44

+V3.3S_DB800

CLK_PCIE_SLOT1 CLK_PCIE_SLOT1# CLK_PCIE_SLOT2 CLK_PCIE_SLOT2# CLK_PCIE_SLOT3 CLK_PCIE_SLOT3# CLK_PCIE_SLOT4 CLK_PCIE_SLOT4# CLK_PCIE_SLOT5 CLK_PCIE_SLOT5# CLK_PCIE_DOCK CLK_PCIE_DOCK#

1

R7D4 49.9R7D4 49.9 R7D5 49.9R7D5 49.9 R7D6 49.9R7D6 49.9 R7D7 49.9R7D7 49.9 R7C6 49.9R7C6 49.9C7P5 R7C7 49.9R7C7 49.9 R7D8 49.9R7D8 49.9 R7D9 49.9R7D9 49.9 R7C10 49.9R7C10 49.9 R7C8 49.9R7C8 49.9 R7C4 49.9R7C4 49.9 R7C5 49.9R7C5 49.9

C C

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,38,39,40,41,43,48,49,52,55,56,57

U7E4

14

15

5

6

23

24

9

10

19

20

1

28

4

U7E4

OE

VDD

VDDA1

VDDA2

VDDB1

VDDB2

GND1

GND2

GND3

GND4

INA

INB

MK74CB218B

QA7

QA6

QA5

QA4

QA3

QA2

QA1

QA0

QB7

QB6

QB5

QB4

QB3

QB2

QB1

QB0

PCIF_QA7

13

12

11

8

7

4

3

2

16

17

18

21

22

25

26

27

PCI_QB7

PCI_QB6

PCI_QB5

PCI_QB4

PCI_QB3

PCI_QB2

PCI_QB1

R7T6 33

.

R7T9 15

R7T10 33

R7T11 33

R7T15 33

R7T7 33

R7T19 33

.

R7T18 33

.

CLK_PCIF_ICH 22

CLK_PCIF_2Y2

Layout Note: Series termination resistors should be placed as close to the device as possible. Place the 0.01uF decoupling capacitors closest.

.

3

CLK_PCI_SIODOCK 38

CLK_PCI_PCIGOLDF 32

CLK_PCI_XDP

CLK_PCI_SIO 38

CLK_PCI_TPM 43

CLK_PCI_LPC 43

CLK_PCI_KBC 40

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

A

DB800 & Buffers

355659

2

TP_OE

B B

CLK_PCIF35

CLK_PCI35

A A

5

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,38,39,40,41,43,48,49,52,55,56,57

C7T12

.

C7T16

0.01UF

.

C7T13

0.01UF

36 58Tuesday, August 28, 2007

C7T12

0.01UF

.

Intel Confidential

1.0

1

5

BOARD REVISION

+V3.3A19,21,23,24,25,26,27,28,29,32,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

R9V4

R9V5

R9V5 10K

10K

NO_STUFF

D D

R9V7

R9V7 10K

10K

.

R9V4 10K

10K

NO_STUFF

R9V6

R9V6 10K

10K

.

R9G22

R9G22 10K

10K

NO_STUFF

R9G19

R9G19 10K

10K

.

FAB REVISION

+V3.3A19,21,23,24,25,26,27,28,29,32,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

R9G8

R9G12

R9G7

C C

R9G7 10K

10K

5%

5% NO_STUFF

NO_STUFF

R9G13

R9G13 10K

10K

5%

5% .

.

R9G12 10K

10K

5%

5% NO_STUFF

NO_STUFF

R9G20

R9G20 10K

10K

5%

5% .

.

R9G8 10K

10K

5%

5% .

.

R9G14

R9G14 10K

10K

5%

NO_STUFF

R9G9

R9G9 10K

10K

5%

5% NO_STUFF

NO_STUFF

R9G15

R9G15 10K

10K

5%

5% .

.

R9G21

R9G21 10K

10K

NO_STUFF

BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3

R9G18

R9G18 10K

10K

.

REV_FAB_ID0 REV_FAB_ID1 REV_FAB_ID2 REV_FAB_ID3

4

SMB_BS_CLK40,43,51,52

SMB_BS_DATA40,43,51,52

3

+V3.3A19,21,23,24,25,26,27,28,29,32,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

C9G2

0.1uF

20%

R9V8

R9V8 R9V10

R9V10 R9V9

R9V9

20%

0

0 0

0

.

. .

.

A0_R A1_R A2_R

16

8

1 2

3 4 5

U9G1

VDD VSS

SCLK SDATA

A0 A1 A2

PCA9557PW

RESET#

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

8-bit I/O Port Expander

slave address

0 0 1 1 A2 A1 A0 R/W

fixed

programmable

PCA9557 Address

15

6 7 9 10 11 12 13 14

PCA9557_RST#

BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 REV_FAB_ID0 REV_FAB_ID1 REV_FAB_ID2 REV_FAB_ID3

2

FAB ID Strapping Table

FAB_REV

3

0 0

+V3.3A19,21,23,24,25,26,27,28,29,32,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

R9G4

R9G4 1K

1K

5%

5% .

.

0 0

0 0 0 0

1 1 1 1

1

2

0

0 0

0 1

0 0 4

1

0 0

1 180 1

1

0

0 0

0

1

0

1

0

1

0 0

1

0 1

1 1

1

BOARD FAB

0

1

0

2

0

3

1

5 6

1 0

7

1

0

9

1

10

0

11 12

1

13 14

1

15

0 1

16

1

BOARD REVISION Strapping Table

BOARD REVISION

3

2

0

0 0

0

0 0

0

1

0

1

0

1 1

0

1

0

1

0 0

1

0

1

1 1

1

0 0 1 1

0 0 1 111

0 0 1 1

0

0 1 0 1

0 1 0

0 1 0 1

BOARD ID

Pillar Rock Silver Cascade Fern Hill STHI CPV-MCH DDR2

STHI CPV-MCH DDR3 STHI CPV-ICH DDR2 STHI PPV-PGA DDR2 Sundial

TBD TBD TBD TBD

B B

A A

5

4

3

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

I/O Port Expander

355659

A

355659

A

355659

A

2

37 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

5

+V3.3S_SIO

+V3.3A

D D

C7T6

0.1uF

20%

LPCD_OPNREQ_OUT#

R7E2

R7E2 10K

10K

R7E1

NO_STUFF

10K

NO_STUFF

20%

TP_SIO_GPIO13

LPCD_RI#

TP_GPIO32 TP_GPIO33 LPCD_LPCPD# LPCD_LPCRST# LPCD_PWREN#

Base Address:

00 = 0x002E 01 = 0x004E 10 = 0x162E 11 = 0x164E

Default:

11= 0x164E

R7T14

8.2K

RS232_EN39

IRDA_CIR_SLT39

SMC_EXTSMI#23,40,43,44

RS232_RI#39

LPCD_PWRGD

C C

+V3.3S_SIO

SER_RTSA#

R7E4

R7E4 10K

10K

SER_DTRA#

R7E3

.

10K

.

R7T13

R7T13 100K

100K

5%

LPCS_PME#43

L_BKLTSEL1#17

L_BKLTSEL0#17

IR_TXD39 IR_RXD39

IR_MODE39

SMSC PORT-SWITCH

U7E3

5

VCC1

17

VCC2

31

VCC3

42

VCC4

60

VCC5

48

VTR

8

VSS1

20

VSS2

29

VSS3

37

VSS4

45

VSS5

62

VSS6

27

GPIO10

28

GPIO11

30

GPIO12/IO_SMI#

32

GPIO13/IRQIN1

33

GPIO14/IRQIN2

34

GPIO15

35

GPIO16

36

GPIO17

38

GPIO30

39

GPIO31

40

GPIO32

41

GPIO33

43

GPIO34

44

GPIO35

46

GPIO36

61

GPIO37

49

IRTX2

50

IRRX2

51

IRMODE/IRRX3

SIO1007-JV

4

64

LAD0

2

LAD1

POWER & GROUND

LPC_CLK_33

LPC INTERFACE

GENERAL PURPOSE I/O

DLPC_CLK_33

DOCKING LPC INTERFACE

UART2

IR

UART2

IR

UART1

RTS1#/SYSOPT0 DTR1#/SYSOPT1

LAD2 LAD3

LFRAME

LDRQ0 LDRQ1

PCI_RESET

LPCPD

CLKRUN

SER_IRQ

IO_PME

PCI_CLK

SIO_14M

DLAD(0) DLAD(1) DLAD(2) DLAD(3)

DLFRAME

DLDRQ1

DCLKRUN

DSER_IRQ

DSIO_14M

RXD1

TXD1

DSR1

CTS1

DCD1

4 7 14

SIO_DRQ#0

24

SIO_DRQ#1

12

SIO_RST#

22 25 16 19

PM_RI_SIO

47 21 10 23

D_LAD_0

63

D_LAD_1

1

D_LAD_2

3

D_LAD_3

6

D_LFRAME#

13

D_LDRQ1

11

D_CLKRUN

15

D_SER_IRQ

18

D_CLK_33

9

D_CLK_14

26

52 53 54 56 58

RI1

59 55 57

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,39,40,41,43,48,49,52,55,56,57

R9F8

R9F8 100K

100K

5%

1

2

SER_DTRA# SER_RTSA#

U9F1

VCC

GND

OUT

IN

MAX6816

LPC_AD0 21,40,43 LPC_AD1 21,40,43 LPC_AD2 21,40,43 LPC_AD3 21,40,43

LPC_FRAME# 21,40,43

R7T8

R7T8 0

0

.

SER_SINA 39 SER_SOUTA 39 SER_DSRA# 39 SER_CTSA# 39 SER_RIA# 39 SER_DCDA# 39 SER_RTSA# 39 SER_DTRA# 39

4

3

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,39,40,41,43,48,49,52,55,56,57

PM_SUS_STAT# 23,40,43

PM_CLKRUN# 23,32,40,43

INT_SERIRQ 23,40,43 PM_RI# 23,43 CLK_PCI_SIO 36

CLK_PCI_SIODOCK 36

CLK_REF_SIO 35

C9F1 0.1uFC9F1 0.1uF

LPCD_OPNREQ_OUT#LPCD_OPNREQ#

R8T8

R8T8 10K

10K

5%

R8E6

R8E6 10K

10K

5%

2

+V3.3S

C7T11

0.1uF

R8T7

R8T7 10K

10K

20%

5%

TPM_DRQ#043

53

U8E4

1

2

KSC_LPC_DOCK#40

4

74AHC1G08

LPC_DRQ#143

+V3.3A19,21,23,24,25,26,27,28,29,32,37,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,39,40,41,43,48,49,52,55,56,57

R9F11

R9F11 100K

100K

5%

LPC_DRQ#043

AND_DRQ#0

R8E5

R8E5 10K

10K

5%

D_LAD_0 D_LAD_2 D_LAD_1 LPCD_PWRGD

D_LFRAME#

LPCD_SMC_EXTSMI#

D_CLKRUN

D_CLK_33

R7T2 0.002

1%

R7T17

R7T17 10K

10K

5%

+V3.3S

C7T7

0.1uF

20%

U8E3

1

2

LPC HOT DOCKING

J9E3

1

2 3 4 5

6 798

10

11

12

13

14

15

16

17

18

19

20

21

22

23 24

2X12-HDR_SHRD

+V3.3S_SIO

C7T15

C7T1

0.1uF

22UF

20%

+V3.3S

C7T17

0.1uF

20%

U8E5

1

2

53

74AHC1G08

D_LAD_3

LPCD_PWREN#

LPCD_PCI_PME#

D_LDRQ1 LPCD_PD# D_SER_IRQ LPCD_RST#

LPCD_OPNREQ#

D_CLK_14

C7T14

0.1uF

20%

4

1

53

74AHC1G08

C7T8

0.1uF

20%

4

ICH_DRQ#0 21

ICH_DRQ#1 21

C7T10

0.1uF

20%

C7T5

0.1uF

20%

B B

LPC DOCKING

+V3.3S

53

U7E1

LPCD_LPCPD#

PM_SUS_STAT#

A A

LPCD_LPCRST#

PLT_RST#

U7E1

1

2

+V3.3S

53

U7E2

1

2

74AHC1G08

5

4

74AHC1G08

4

C7T3

0.1uF

20%

C7T2

0.1uF

20%

LPCD_PD#

R7T3

R7T3 0

0

NO_STUFF

LPCD_PWRGD

LPCD_RST#

4

+V3.3A19,21,23,24,25,26,27,28,29,32,37,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57

R8E9

R8E9 10K

10K

5%

5% .

.

LPCD_QSEN#

3

Q8E5

Q8E5 BSS138

BSS138

1

2

LPCD_PCI_PME#

LPCD_RI# SMC_EXTSMI#

U7E5

1

OE1#

2

1A

3

1B GND42A

74CBT3306

3

VCC

OE2#

2B

+V5A24,29,34,44,46,47,50,51,56,57

C7T18

0.1uF

20%

8 7 6

LPCD_SMC_EXTSMI#

5

Default: 1 - 2

J7E1

PLT_RST#7,19,22,25,26,41,57

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

SIO

355659

A

355659

A

355659

A

2

RST_PD

R7E5

R7E5 10K

10K

5%

1

3

CON3_HDR

SIO_RST#

2

38 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

5

RS-232 TRANSCEIVER

U6A1

SERBUF_C1+

C6M8

0.1uF

SERBUF_C1-

10%

D D

RS232_RI#38

+V3.319,27,32,41,42,43,55,57

RS232_EN38

Q7M1

BSS138

R7M6

R7M6 1K

1K

5%

R7M12

R7M12 1K

1K

5%

3

2

10%

.

SERBUF_C2+

C6M4

0.1uF

SERBUF_C2-

10%

.

1

SER_RIA

SER_CTSA#38

SER_RIA#38

SER_SINA38 SER_DSRA#38 SER_DCDA#38

SER_DTRA#38 SER_SOUTA38 SER_RTSA#38

SER_ON

28

24

1

2

20 19 18 17 16 15

14 13 12

23 22 21

U6A1

MAX3243

C C

SIO VID VOLTAGE TRANSLATION

4

+V3.3 19,27,32,41,42,43,55,57

C7M6

0.1uF

20%

26

VCC

C1+

C1-

C2+

C2-

R2OUTB R1OUT R2OUT R3OUT R4OUT R5OUT

T1IN T2IN T3IN

FORCEON FORCEOFF# INVALID#

R1IN R2IN R3IN R4IN R5IN

T1OUT T2OUT T3OUT

GND

V+

V-

27

3

4 5 6 7 8

9 10 11

25

Spare

C6A2

C6A2 22UF

22UF

SERBUF_V+

SERBUF_V-

SERBUF_CTSA SERBUF_RIA SERBUF_SINA# SERBUF_DSRA SERBUF_DCDA

SERBUF_DTRA SERBUF_SOUTA# SERBUF_RTSA

C6M3

0.1uF

10%

.

R1P1

R1P1 10K

10K

.

C7M5

0.1uF

10%

.

KBC_PROG_RX#40

EC_SCIF_RXD_TRANSC40

KBC_PROG_TX#40

EC_SCIF_TXD_TRANSC40

U1C1D_SPARE

3

+V3.3A

R7M11

R7M11 10K

10K

5%

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

3

U1B3D

11

+

10

13

-

LM339

12

+V3.3A

C7B2 0.1uF

.

R7M10

R7M10 10K

10K

5%

5% .

.

R7A5

R7A5 10K

10K

5%

5% .

.

C7B2 0.1uF

C1-3

R7M9

C7B3 0.1uF

10K

10%

5%

C2-5

.

C4A2,C4A5 Should be near U4A1.

10%

.

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,40,41,43,48,49,52,55,56,57

C1+1

.

C2+4

12

11

R4M3

0.002

1%

R4A1 4.7R4A1 4.7

U7B1

1

C1+

3

C1-

4

C2+

5

C2-

R1OUT R2OUT9R2IN T1IN T2IN10T2OUT

MAX3232_RS232_TRNCVR

+V3.3S_IR

C4M1

0.1uF

10%

.

T1OUT

C4A2

0.1uF

10%

.

2

+V3.3A

C7M7

0.1uF

C7N2

C7N2 22UF

22UF

20%

16

VCC

V_C_2

C7N1 0.1uF

2

V+

V_C_6

6

V-

SER_KBCPROG_RX_IN SER_KBCPROG_RX_IN

13

R1IN

SER_EC_SCIF_RXD

8 14

SER_EC_SCIF_TXD

7 15

GND

C7B1 0.1uF

SER_TX_OUT

10%

.

10%

.

In Ckt H8 Programming J7A1 and J8B2

Disable 1-2 (Default) Enable 2-3 (In Ckt Programming)

J7A2

1

2

3

CON3_HDR

SERIAL PORT CONNECTOR

SERBUF_RIA SERBUF_DTRA SERBUF_CTSA TX_OUT SERBUF_RTSA RX_IN SERBUF_DSRA SERBUF_DCDA

C4A4

+

C4A1

6.8uF

0.1uF

10%

.

C4A5

+

6.8uF

10%

FB2A3A 60OHM-100MHZFB2A3A 60OHM-100MHZ FB2A3B 60OHM-100MHZFB2A3B 60OHM-100MHZ FB2A3C 60OHM-100MHZFB2A3C 60OHM-100MHZ FB2A3D 60OHM-100MHZFB2A3D 60OHM-100MHZ FB2A5A 60OHM-100MHZFB2A5A 60OHM-100MHZ FB2A5B 60OHM-100MHZFB2A5B 60OHM-100MHZ FB2A5C 60OHM-100MHZFB2A5C 60OHM-100MHZ FB2A5D 60OHM-100MHZFB2A5D 60OHM-100MHZ

VCC_HSDL

1 8 2 7 3 6 4 5 1 8 2 7 3 6 4 5

R4M4 3.9R4M4 3.9

IR_RXD38

IR_MODE38

R4M2

R4M2 10K

10K

R4M1

R4M1 10K

10K

CIR_TXD

1

SERBUF_SOUTA#

SER_TX_OUT

SERBUF_SINA#

SERPRT_RIA SERPRT_DTRA SERPRT_CTSA SERPRT_TX_OUT SERPRT_RTSA SERPRT_RX_IN SERPRT_DSRA SERPRT_DCDA

LED_A

IRDA_TXD

IR

U4A1

1

LED_A

2

IO_VCC

3

TXD_IR

4

RXD

5

SD

6

VCC

7

TXD_RC

8

GND

HSDL-3021_021

J8B2

1

3

CON3_HDR

J7A1

1

3

CON3_HDR

GND

GND RI

RI DTR

DTR CTS

CTS TXD

TXD RTS

RTS RXD

RXD DSR

DSR DCD

DCD

SHLD

TX_OUT

2

RX_IN

2

J2A2A

5 9 4 8 3 7 2 6 1

2IN1

9

U4M1

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

3

U1B1A

VID_COMP

VR_VID052

R1N17 1KR1N17 1K

VID_0_D

B B

VID_COMP

VR_VID152

VR_VID252

+V5S 5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

R1N21 1KR1N21 1K

R1N26 1KR1N26 1K

A A

C1N5

C1N2

0.1uF

20%

CAD NOTE:

Place near U1B1 & U1B3

VID_1_D

VID_COMP

VID_2_D

+V1.05S_CPU3,4,20,35,43,52,54

R1N41

R1N41 1K

1K

1%

1% .

.

5

4

7

6

9

8

C1N8

0.1uF

20%

U1B1A

+

-

LM339

12

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

3

U1B1B

+

-

LM339

12

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

3

U1B1C

+

-

LM339

12

R1P2

R1P2 1K

1K

1%

1% .

.

SIO_VID0

2

SIO_VID1

1

SIO_VID2

14

VID_COMP

VR_VID352

VR_VID452

VR_VID552

VR_VID652

R1N18 1KR1N18 1K

R1N38 1KR1N38 1K

4

R1P4 1KR1P4 1K

R1P3 1KR1P3 1K

VID_COMP

VID_3_D

VID_COMP

VID_4_D

VID_COMP

VID_5_D

VID_COMP

VID_6_D

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

3

U1B1D

11

+

10

-

LM339

12

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

3

U1B3A

5

+

4

-

LM339

12

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

3

U1B3B

7

+

6

-

LM339

12

+V5S5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57

3

U1B3C

9

+

8

-

LM339

12

SIO_VID3

13

SIO_VID4

2

SIO_VID5

1

SIO_VID6

14

IRDA_CIR_SLT =0, then Y0=A, IRDA_CIR_SLT=1,then Y1=A.

SIO_VID0

SIO_VID1

SIO_VID2

SIO_VID3

SIO_VID4

SIO_VID5

SIO_VID6

3

IRDA_CIR_SLT38

IR_TXD38

R1N23 10KR1N23 10K

R1N29 10KR1N29 10K

R1N13 10KR1N13 10K

Title

Size Document Number Rev

Date: Sheet of

R1N33 10KR1N33 10K

R1N16 10KR1N16 10K

Pillar Rock

A

R1N37 10KR1N37 10K

Legacy Support

355659

U4M1

1 2

NON-INV DMUX

R1N12

R1N12 330

330

LED_VID0

R1N44 10KR1N44 10K

1 2

2

S GND

VCC

A3Y1

CR1B1

CR1B1 GREEN

GREEN

6

Y0

5 4

C4M2

0.1uF

10%

.

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,40,41,43,48,49,52,55,56,57

R1N22

CR1B2

CR1B2 GREEN

GREEN

R1N22 330

330

LED_VID2

1 2

R1N15

R1N15 330

330

LED_VID1

1 2

CR1B3

CR1B3 GREEN

GREEN

R1N28

R1N28 330

330

LED_VID3

1 2

CR1B4

CR1B4 GREEN

GREEN

R1N32

R1N32 330

330

LED_VID4

1 2

CR1B5

CR1B5 GREEN

GREEN

39 58Tuesday, August 28, 2007

1

R1N36

R1N36 330

330

LED_VID5

1 2

Intel Confidential

CR1B6

CR1B6 GREEN

GREEN

R1N43

R1N43 330

330

LED_VID6

CR1B7

CR1B7 GREEN

GREEN

1 2

1.0

5

Y9G1

21

10MHZ

C9G4

C9G4 18PF

18PF

D D

SMC_RST#42

PSYS50

IMVP_VR_ON43

PM_THRM#5,12,23,43

J9F1

1-2 (Default)

PBATT50

SMC/KSC

Enable Disable 2-3

EC_BRK_CURRENT51

C C

B B

SUS_PWR_ACK23,43

+V3.3S

R9W6 10KR9W6 10K R9W3 10KR9W3 10K R9G29 4.7K 5%R9G29 4.7K 5% R9G28 4.7K 5%R9G28 4.7K 5%

+V3.3A

R9V12 8.2KR9V12 8.2K

R9V15 8.2KR9V15 8.2K

R9G24 10K

R9H12 10K

A A

R8M8 10KR8M8 10K

R9W1 10KR9W1 10K

R9V14 4.7KR9V14 4.7K

R9V13 4.7KR9V13 4.7K

R9V16 10KR9V16 10K

.

DOCK_SYS_PWRGD#

R9G2510K R9G2510K

J9F1

1

2

3

CON3_HDR

TP9G1

H_A20GATE21,43

EC_PCIE_SLOT4_VAUX_ON26

SMC_EXTSMI#

SMC_RUNTIME_SCI#

ALS_DATA ALS_CLK

H8_P91_IRQ1#

ALS_INTR#

PBATT_R

PM_LAN_ENABLE

SMC_WAKE_SCI#

SMB_BS_DATA

SMB_BS_CLK

NMI_GATE

AC_PRESENT

C9G3

C9G3 18PF

18PF

H8_P91_IRQ1#

NO_STUFF

R9H130NO_STUFFR9H130NO_STUFF

R9H11

R9H11 0

0 R9H70NO_STUFFR9H70NO_STUFF

.

R9G11

R9G11 0

0

.

+V3.3A

+V3.3S

RSMRST#_PWRGD41,43

R9V11

R9V11 0

0

.

H8S_I2C_CLK41 H8S_I2C_DATA41

R9G27

R9G27 10K

10K

5%

5% .

.

SMC_XTAL SMC_EXTAL

EC_BRK_CURRENT_R

IMVP_VR_ON_R

PM_THERM#_R

R9H2

8.2K

R9H1

R9H1 0

0

.

ALS_CLK17 ALS_DATA17

PM_SLP_M#23,43,44,47,55,57

PM_EXTTS#0_EC7

PM_EXTTS#0_DIMM0_113,15

ALS_INTR#17 SMC_INITCLK42

EC_SCIF_RXD_TRANSC39 EC_SCIF_TXD_TRANSC39

SMB_BS_DATA37,43,51,52

SMB_BS_ALRT#43,51

SMC_ONOFF#43,56

GFX_PWRMN_EC41

CPU_VCC_R_EC41

PM_S4_STATE#23,32,43,44,55,57

VBRK_MON41 ATX_DETECT#43,56

PBATT_R

PM_LAN_ENABLE_H8

SMC_RUNTIME_SCI#23,43

NETDETECT#43,56

DOCK_PE_DET#44

DOCK_SYS_PWRGD#44

SMB_BS_CLK37,43,51,52

BC_ACOK43,50

CPU_PWM_FAN5,43

MCH_PWM_FAN12,43

SMC_RSTGATE#41,43

SMB_THRM_CLK5,12,43 SMB_THRM_DATA5,12,43

SMC_WAKE_SCI#23,43

KBC_PROG_TX#39

CPU_TACHO_FAN5,43

MCH_TACHO_FAN12,43

PM_RSMRST#23,43,56

SMC_EXTSMI#23,38,43,44

PM_BATLOW#23,43

AC_PRESENT23,43,56

PE_OPNREQ#44

PM_SLP_S3#11,23,43,44,46,47,49,55,57

R9G16 100R9G16 100

CPU_ICC_R_EC41

H_RCIN#21,43

BS_DISA#43,51

LIBP_BAT_SEL43,51

LIBP_CHG_EN_A43,51

ICHRM50

VCHRM50

CPU Thermal Monitor Strap

EC_THERM_STRAP

5

4

U9G2A

MD1 MD2

SMC_RES#

NMI_R

EC_THERM_STRAP

H_A20GATE_R

+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,41,43,44,45,46,47,48,50,51,52,55,56,57

R9G26

R9G26 100K

100K

NO_STUFF

R9G23

100K

Pullup = Disable Pull down = Enable

U9G2A

E2

MD1

K1

MD2

E1

PH0/ExIRQ6#/TDPCYI2

C4

PH3

D4

PH4

A2

XTAL

B2

EXTAL

E3

RES#

F3

PH1/ExIRQ7#/TDPCKI2/TDPMCI2

F4

NMI

G4

P51/FRxD

G1

P50/FTxD

F2

P52/SCL0

G2

P97/SDA0/IRQ15#

H1

P96/PHI/EXCL

J1

P92/IRQ0#

J2

P91/IRQ1#

K4

P90/IRQ2#

N12

P70/AN0

R13

P71/AN1

P13

P72/AN2

R14

P73/AN3

P14

P74/AN4

R15

P75/AN5

N13

P76/AN6

P15

P77/AN7

P3

PA1/KIN9#/PA2DD

R3

PA0/KIN8#/PA2DC

A5

P40/TMI0/TxD2/TCMCYI0

B5

P41/TMO0/RxD2/TCMCKI0/TCMMCI0

C3

P43/TMI1/SCK2/TCMCKI1/TCMMCI1

B1

P44/TMO1/PWMU2B/TCMCYI2

C2

P45/PWMU3B/TCMCKI2/TCMMCI2

D3

P46/PWX0/PWMU4B/TCMCYI3

C1

P47/PWX1/PWMU5B/TCMCKI3/TCMMCI3

C11

PB5/DTR#

B11

PB4/DSR#

A11

PB3/DCD#/PWMU1B

D10

PB2/RI#/PWMU0B

A10

PB1/LSCI

B10

PB0/LSMI#

C7

P80/PME#

A7

P81/GA20

D11

PB7/RTS#

A12

PB6/CTS#

C6

P84/IRQ3#/TxD1

B3

PH5

R7

PG7/ExIRQ15#/ExSCLB

P7

PG6/ExIRQ14#/ExSDAB

M8

PG5/ExIRQ13#/ExSCLA

R8

PG4/ExIRQ12#/ExSDAA

P8

PG3/ExIRQ11#/SCL2

N9

PG2/ExIRQ10#/SDA2

R9

PG1/ExIRQ9#/TMIY/TDPCKI1/TDPMCI1

P9

PG0/ExIRQ8#/TMIX/TDPCYI1

N5

PF7/PWMU5A

P5

PF6/PWMU4A

R5

PF5/PWMU3A

M6

PF4/PWMU2A

N6

PF3/IRQ11#/TMOX/TDPCKI0/TDPMCI0

R6

PF2/IRQ10#/TMOY/TDPCYI0

P6

PF1/IRQ9#/PWMU1A

M7

PF0/IRQ8#/PWMU0A

H8S2117 BGA176

PA7/KIN15#/PS2CD PA6/KIN14#/PS2CC

PA3/KIN11#/PS2AD PA2/KIN10#/PS2AC

PA5/KIN13#/PS2BD PA4/KIN12#/PS2BC

P66/IRQ6#/KIN6# P67/IRQ7#/KIN7#

P86/IRQ5#/SCK1/SCL1

P42/SDA1/TCMCYI1

PC7/TIOCB2/TCLKD/WUE15#

PC6/TIOCA2/WUE14#

PC5/TIOCB1/TCLKC/WUE13#

PC4/TIOCA1/WUE12# PC3/TIOCD0/TCLKB/WUE11# PC2/TIOCC0/TCLKA/WUE10#

PC1/TIOCB0/WUE9# PC0/TIOCA0/WUE8#

R9G2

R9G2 10K

10K

MD1 MD2

J8G5J8G5

1 2

4

3

P95/IRQ14# P94/IRQ13# P93/IRQ12#

P60/KIN0# P61/KIN1# P62/KIN2# P63/KIN3# P64/KIN4# P65/KIN5#

P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10

P30/LAD0 P31/LAD1 P32/LAD2 P33/LAD3

P34/LFRAME#

P35/LRESET#

P36/LCLK

P37/SERIRQ

P82/CLKRUN#

P83/LPCPD#

P85/IRQ4#/RxD1

PD7/AN15 PD6/AN14 PD5/AN13 PD4/AN12 PD2/AN10 PD3/AN11

PD1/AN9 PD0/AN8

PH2

ETRST#

PE4*/ETMS

PE3*/ETDO

PE2*/ETDI

PE1*/ETCK

PE0/ExEXCL

+V3.3A_KBC 41,42

R9F12

4.7K

.

J8G3J8G3

1 2

3

N1 M4

N3 R2

N2 R1

KBC_CAPSLOCK

H2

KBC_SCROLLOCK

J4

KBC_NUMLOCK

J3

KBC_SCANIN0

L13

KBC_SCANIN1

L14

KBC_SCANIN2

L15

KBC_SCANIN3

K12

KBC_SCANIN4

K13

KBC_SCANIN5

K14

KBC_SCANIN6

J12

KBC_SCANIN7

J13

KBC_SCANOUT15

F14

KBC_SCANOUT14

E13

KBC_SCANOUT13

E15

KBC_SCANOUT12

E14

KBC_SCANOUT11

E12

KBC_SCANOUT10

D15

KBC_SCANOUT9

D14

KBC_SCANOUT8

D13

KBC_SCANOUT7

C15

KBC_SCANOUT6

D12

KBC_SCANOUT5

C14

KBC_SCANOUT4

B15

KBC_SCANOUT3

B14

KBC_SCANOUT2

A15

KBC_SCANOUT1

C13

KBC_SCANOUT0

B12

D9 C9 A9 B9 D8

PLT_RST_R

C8 A8 D7 B7 D6

A6 B6 D5

H12 H13 H15 H14 G12 G13 G15 G14

M10 N10 R10

ALL_SYS_PWRGD_R

P10

KBC_DISABLE#

R11 N11 P11 M11

KBC_FWE

K2

KBC_PE5

L1

KBC_PE4

L2

KBC_PE3

L4

KBC_PE2

M1

KBC_PE1

M2

KBC_PE0

M3

Shunt J8G5 as default and as external programming

Normal Operation

LPC_AD0 21,38,43 LPC_AD1 21,38,43 LPC_AD2 21,38,43 LPC_AD3 21,38,43 LPC_FRAME# 21,38,43

CLK_PCI_KBC 36 INT_SERIRQ 23,38,43 PM_CLKRUN# 23,32,38,43 PM_SUS_STAT# 23,38,43

KBC_GP_DATA 42 KBC_GP_CLK 42

KBC_MOUSE_DATA 42 KBC_MOUSE_CLK 42

KBC_KB_DATA 42 KBC_KB_CLK 42

KBC_SCANIN[7:0] 42

KBC_SCANOUT[15:0] 42

KBC_PROG_RX# 39 SMB_CLK_ME 23,43 SMB_DATA_ME 23,43

BS_CHGB# 43,51 BS_CHGA# 43,51 BS_CLR_LTCH# 43,51

SMC_LID 41,43 VIRTUAL_BATTERY 41 ME_G3_TO_M1# 56

SMC_SHUTDOWN 43,56

BC_SHDN 50 BS_DISB# 43,51

R9G1

R9G1 0

0

.

PM_PWRBTN# 23,43 NMI_GATE 42

R9F4 4.7KR9F4 4.7K R9F2 4.7KR9F2 4.7K R9F3 4.7KR9F3 4.7K R9F5 4.7KR9F5 4.7K R9F6 4.7KR9F6 4.7K R9F7 4.7KR9F7 4.7K

J8G3MD2 1-X 1-2Advanced Single Chip Mode

2

+V3.3A_KBC41,42

R9G5

R9G6

240

LEDD1

LEDD2

CR9G1

CR9G3

CR9G2

CR9G2 GREEN

GREEN

R9H3 100R9H3 100

+V3.3A_KBC41,42

R9H5

10K

.

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,41,43,44,45,46,47,48,50,51,52,55,56,57

R9F9

R9F9 0

0

NO_STUFF

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

Embedded Controller 1 of 2

355659

A

355659

A

355659

A

CR9G3 GREEN

GREEN

1 2

LED_CAPS

3

Q9G3

Q9G3 BSS138

BSS138

1

2

1

BUF_PLT_RST# 22,43

DOCK_EXP_CPPE# 44

KSC_LPC_DOCK# 38 ALL_SYS_PWRGD 23,43,47

LAN_WOL_EN 23,43,55,57

R9F10 4.7KR9F10 4.7K

NOTE: Stuff R9F9 for write protect

2

GREEN

1 2

LED_SCROLL

3

Q9G2

Q9G2 BSS138

BSS138

2

1

+V3.3A_KBC41,42

Boot Mode Programming Straps

P90-P92 needs to be at VCC for boot mode programming. They are already pulled up in the design. MD0, MD1 needs to be at Vss. System needs to supply +V3.3A to flash connector.

R9G3

R9G3 240

240

Mode Type

Run Mode STUFFED

LEDD3

Program Boot Block Program Flash

1 2

LED_NUM

3

Q9G1

Q9G1 BSS138

BSS138

2

J8B1

10K

J8G6J8G6

+V3.3A_KBC41,42

.

1 2

J8B1

1

3

CON3_HDR

KBC

Enable Disable 1-2

2

PM_LAN_ENABLE_H8

R8H1

MD1

0 0

PM_LAN_ENABLE

Enable Disable

J8G6

1-X (Default)

40 58Tuesday, August 28, 2007

1

J8G5 J8G3

MD2

NMI

00 X

1

STUFFED X

1

J8B1

1-2 (Default) 2-3

PM_LAN_ENABLE 23,33,43

Intel Confidential

1

OPEN1 STUFFED

1.0

5

+V3.3A

R8H8 0.002

+V3.3A_KBC40,42

1%

C8H2

C8H2 22uF

22uF

C9W2

0.1uF

10%

10% .

.

C9W1

0.1uF

10%

.

C9V3

0.1uF

10%

10% .

.

C9V2

0.1uF

10%

10% .

.

C8H3

0.1uF

10%

.

D D

C9V4

0.1uF

10%

.

4

3

2

+V3.319,27,32,39,42,43,55,57

R8W1

R8W2

10K

PCI_GATED_RST#32

PLT_GATED_RST#19

Q8H2

Q8H2 BSS138

BSS138

3

2

Q8H3

BSS138

1

3

2

1

PCI_RST# 22,32

PLT_RST# 7,19,22,25,26,38,57

13

1

R9W2

R9W2 0

0

.

R9W4 100

1%

.

R9H4 100

1%

.

R9H6 100

1%

.

MCH_TSATN_LVL

+V3.3A

SW9H1

2

SPDT_SLIDE

VIRTUAL_DOCK_DET#

R9H810K R9H810K

DOCK_PE_PWRGD#

R9C210K R9C210K

HYBRID_GFX_SW

R7J110K R7J110K

1

3

VIRTUAL_DOCK_DET#

EC_PCIE_SLOT3_VAUX_ON26

DOCK_PWR_EN#44

DOCK_PE_PWRGD#44

DOCK_PE_RST#44 DOCK_PE_QSEN#44 DOCK_CRT_EN#16 DOCK_LAN_EN#34

DOCK_TV_EN#18

MCH_TSATN_EC HYBRID_GFX_SW

LIBP_CHG_EN_B51

CHGA_EN#51 CHGB_EN#51

C C

C2Y3

C2Y3 1uF

1uF

20%

20% .

.

R9H16

R9H16 10K

10K

.

R9H18

R9H18 10K

10K

.

HYBRID_GFX_SW

J9H3J9H3

1 2

J9H4J9H4

1 2

+V3.3A

8

U2J4A

3

+

2

-

AD8552

4

5

1

3

SPDT_SLIDE

C2Y1

0.1uF

10%16V

10%16V .

.

1

GND_SYS_CURRENT

SW9H2

1

3

SPDT_SLIDE

SW9H3

2

BIOS_REC23

VIRTUAL_DOCK_DET#

2

VBRK_MON 40

4

SW7J1

1

2

3

SPDT_SLIDE

+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,40,43,44,45,46,47,48,50,51,52,55,56,57

SMC_LID40,43

B B

+V3.3A

VIRTUAL_BATTERY40

+VAC_IN_L

1%

.

15K

A A

15K R2Y4

R2Y4

VBRK_MON_IN

R2Y5

4.02K

1%

1% .

.

K15

J14 F15 A14 C12 C10

B8 C5

G3 H4 H3 K3

L3

M5

N7 N8

A3

L12 M13 M12

M9

N4 E4

HYBRID_GFX_SW

C8G3

0.1uF

10%

10% .

.

U8V1

1

A0

2

A1

3

A2 GND4SDA

AT24C02N

U9G2B

PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0

PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0

NC7 NC6 NC5 NC4 NC3 NC2 NC1

H8S2117 BGA176

16 14 12 10

8 6 4 2

2X8_HDR_KEY12

VCC

WP

SCL

VCC1 VCC2 VCC3 VCC4

VCL

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

VSS10

AVCC1 AVCC2

AVref1 AVref2

AVSS2 AVSS1

J8F1

15 13 11 9 7

3 1

+V3.3A+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,43,44,45,46,47,48,50,51,52,55,56,57

R8V8

4.7K

5%

5% .

.

8 7 6 5

+V3.3A_KBC 40,42

A1 P1 P2 J15

VCL

F1

D2 D1 P4 R4 F12 F13 B13 A13 A4 B4

N14 N15 M14 M15

P12 R12

GND_SYS_CURRENT

HDA_DOCK_EN#_R

R8V7

4.7K

5%

5% .

.

H8S_EEPROM_WPVBRK_MON

H8S_I2C_CLK 40 H8S_I2C_DATA 40

3

C9V1

0.1uF

10%

10% .

.

+V3.3A_KBC 40,42

R2F20 100KR2F20 100K

+VREF_ADC51

RTC_RST# 21ND_SW#56

VIRTUAL_BATTERY 40

HDA_DOCK_EN# 21,27

SMC_LID 40,43

R8V9

R8V9 10K

10K

1%

1% NO_STUFF

NO_STUFF

R8V6

R8V6 100

100

.

+V5A3A_MBL_PWRGD45

ATX_PWROK56

GFX_VR_PWRIN49,52

For External H8 ADC monitor NO_STUFF : R9W5 (Default STUFF) STUFF : R1N27

CPU_VCC52

For External H8 ADC monitor NO_STUFF : R9W7 (Default STUFF) STUFF : R2N19

CPU_ICC52

For Internal H8 ADC monitor STUFF : R9W8 (Default NO_STUFF) NO_STUFF : R1B4

R2P4

MCH_TSATN#7

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

R2P4

0

5%

.

Embedded Controller 2 of 2

355659 1.0

2

R9W5

R9W7

MCH_TSATN_R

0

5%

5% .

.

0

R9W8

CR4W1

BAT54

GFX_PWRMN_R_EC

CPU_VCC_EC

5%

5% .

.

CPU_ICC_EC

0

5%

5% NO_STUFF

NO_STUFF

+V1.05S_ICH24

R8H7

54.9

1%

R8H6 330R8H6 330

LAYOUT NOTE: PLACE R, C close to H8 input pins

AGND_VCORE

41 58Tuesday, August 28, 2007

C9H1

0.1uF

10%

10% .

.

C9H2

0.1uF

10%

10% .

.

C9H3

0.1uF

10%

10% .

.

2

1

SMC_RSTGATE# 40,43

RSMRST#_PWRGD 40,43

GFX_PWRMN_EC 40

CPU_VCC_R_EC 40

CPU_ICC_R_EC 40

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,43,48,49,52,55,56,57

R8H4

R8H4 1K

1K

R8H5

5%

1K

.

5%

5% .

.

MCH_TSATN_EC

3

CR8H1A

5

3904

4

MCH_TSATN_Q

6

CR8H1B

CR8H1B 3904

3904

1

Intel Confidential

5

+V3.3A_KBC40,41

3

U9V1

D D

Circuitry provides an interrupt to the SMC every 1s while in suspend (this allows the SMC to complete housekeeping functions while suspended)

VCC

GND

1

RST#

MAX809

2

SMC_RST#_D

R9V3 100

R9V1

R9V1 100K

100K

.

4

+V3.3A_KBC40,41

14

9 8

7

SMC_RST# 40

3

+V3.3A_KBC40,41

14

U9F2A

SMC_INIT_CLK1

1

Q9H4

Q9H4 BSS138

BSS138

.

R9H17 1MR9H17 1MC9U1

NMI_GATE40

C9U1

0.1uF

20%

20% .

.

U9F2D

SMC_RST SMC_INITCLK#

74HC04

3

1

2

1 2

74HC04

7

3

Q9H1

Q9H1 BSS138

BSS138

.

2

U9F2A

SMC_INIT_CLK4

J9H1J9H1

1 2

14

U9F2B

74HC04

7

R9F1 100

SMC_INIT_CLK3SMC_INIT_CLK2

C9G1

4.7uF

10%

.

R9V2

J9H1

INVD2

13 12

.

3 4

1Hz Clock

Disable Shunt Enable No Shunt (Default)

NMI Jumper NOTE: Shunt J9H1 for SMC Programming

Spare gate

2

14

5 6

74HC04

7

100K

+V3.3A_KBC40,41

14

7

U9F2C

U9F2F

74HC04

TP_INVD2

14

11 10

7

R9G10 100KR9G10 100K

U9F2E

SMC_INITCLK_J

74HC04

J9G2J9G2

1 2

Boot Block Programming

Normal Program No Shunt

J9G2

Shunt (Default)

1

SMC_INITCLK 40

Scan Matrix Key Board

C C

J9E1

KBC_SCANOUT1 KBC_SCANOUT0 KBC_SCANOUT3 KBC_SCANOUT5 KBC_SCANOUT7 KBC_SCANOUT9 KBC_SCANOUT11 KBC_SCANOUT10 KBC_SCANOUT13

+V3.319,27,32,39,41,43,55,57 +V3.319,27,32,39,41,43,55,57

+V5_PS2

.

FB1A3

.

Spare

+V5_PS2

FB1A5

60ohm@100MHz

+V5_PS2

27

RP1B2B

4.7K

4

5

36

RP1B1C

4.7K

C1M1

C1M1 47pF

47pF

.

MOUSE_DATA

CP1B1D

CP1B1D 47PF

47PF

KBD_DATA

+V5_PS2

27

C1A6

C1A6 47pF

47pF

RP1B1B

4.7K

GP_DATA

+V5_PS2 +V5 27,32,43,48,52,55,56,57

R1A1 0.002

1%

.

+V5_PS2

C1A5

C1A5 22uF

22uF

3

C1B1

0.1uF

20%

20% .

.

+V5_PS2

18

RP1B1A

4.7K

FB1A2

KBD_CLK

B B

+V5_PS2

45

RP1B1D

4.7K

GP_CLK

+V5_PS2

A A

MOUSE_CLK

18

1

CP1B1A

CP1B1A 47PF

47PF

8

FB1A7

60ohm@100MHz

2

CP1B1B

CP1B1B 47PF

47PF

7

RP1B2A

4.7K

FB1A8

60ohm@100MHz

3

CP1B1C

CP1B1C 47PF

47PF

6

FB1A2

60ohm@100MHz

.

L_GP_CLK

L_MOUSE_CLK

.

L_PS2_PWR

L_KBD_CLK

5

13 14

10

12

11

6

5

+

PS2_PWR_L

4

6

5

13 14 151516

10

12

11

1 2

4

17

9

F1A1

1.1A

FB1A6

31Ohm@100MHz

.

J1A1

2

1

3

16 17

8

L_MOUSE_DATA

7

DUAL_PS2

L_KBD_DATA

L_GP_DATA

60ohm@100MHz

36

4.7K

RP1B2C

FB1A4

60ohm@100MHz

45

4.7K

RP1B2D

4

KBC_SCANOUT15

KBC_SCANIN1 KBC_SCANIN3 KBC_SCANIN2

KBC_SCANIN7

KBC_GP_DATA40 KBC_GP_CLK40 KBC_MOUSE_DATA40 KBC_MOUSE_CLK40 KBC_KB_DATA40

KBC_KB_CLK40

OE#_PS2

R8N1

R8N1 100

100

.

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

2 4 6

8 10 12 14 16 18 20 22 24 26 28 30

2x15-SHD-HDR

3

1A1

4

1A2

7

1A3

8

1A4

11

1A5

14

2A1

17

2A2

18

2A3

21

2A4

22

2A5

1

1OE#

13

2OE#

SN74CBTD3384

PS2

355659

J9E1

U8B1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

2

KBC_SCANOUT2 KBC_SCANOUT4 KBC_SCANOUT6 KBC_SCANOUT8

KBC_SCANOUT12 KBC_SCANOUT14

KBC_SCANIN0

KBC_SCANIN4KBC_SCANIN5 KBC_SCANIN6

CBTD has integrated diode for 5V to 3.3V voltage translation

24

VCC

2

1B1

5

1B2

6

1B3

9

1B4

10

1B5

15

2B1

16

2B2

19

2B3

20

2B4

23

2B5

12

GND

.

+V5_PS2

GP_DATA GP_CLK MOUSE_DATA MOUSE_CLK KBD_DATA

KBD_CLK

KBC_SCANOUT[15:0] 40

KBC_SCANIN[7:0] 40

C9N1

0.1uF

20%

20% .

.

42 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

5

+V3.3_LPCSLOT

+V3.3A

+V12S 25,26,30,31,32,55,57

SUS_CLK23

D D

H_STPCLK#3,21

MCH_TACHO_FAN12,40

NETDETECT#40,56

LIBP_BAT_SEL40,51 LIBP_CHG_EN_A 40,51

LPCSLOT_B12

H_RCIN#21,40

H_A20GATE21,40

SMC_EXTSMI#23,38,40,44

LPC_DRQ#138

LPC_FRAME#21,38,40

LPC_AD221,38,40 LPC_AD021,38,40

BUF_PLT_RST#22,40

CLK_REF_LPC35

STPCLK#

R6V11

R6V11 0

0

NO_STUFF

+V5_LPCSLOT

LPC SLOT

J8E1

B1

+V12S_1 SUSCLK_32KHZB2NC1(-12V)

B3

GND1

B4

TACHO_FAN

B5

+V3_3

B6

NC7

B7

GND3

B8

NC8

B9

NC9(NETDETECT#)

B10

GND4

B11

LIBP_BAT_SEL

B12

NC10(CPU_PECI)

B13

GND6

B14

+V3ALWAYS

B15

NC11(STPCLK#)

B16

CPU_RESET#

B17

KBC_A20_GATE

B18

GND8

B19

LSMI#

KEY

+V5_3 LDRQ1# LFRAME# GND9 LAD2 LAD0 GND11 LRST# GND13 OSC_14MHZ +V3_4

60Pin_CardCon

KEY

B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30

+V12S_2

PM_DPRSLPVR

LIBP_CHG_EN

NC6(VTTCPU)

SERIRQ

CLKRUN#

PWM_FAN

LDRQ0#

LPCPD#

GND2

+V3_1

GND5

GND7

+V5_1

GND10

GND12

+V5_2

GND14

LAD3 LAD1

GND15

LCLK

GND16

PME#

+V3_2

NC2

NC3 NC4

NC5

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19

A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30

4

+V12S25,26,30,31,32,55,57

+V3.3_LPCSLOT

+V5_LPCSLOT

+V1.05S_CPU_RSVD

PM_DPRSLPVR 7,23,52

NO_STUFF R8F2

NO_STUFF

INT_SERIRQ 23,38,40 PM_CLKRUN# 23,32,38,40

MCH_PWM_FAN 12,40

LPC_DRQ#0 38

LPC_AD3 21,38,40 LPC_AD1 21,38,40

CLK_PCI_LPC 36 PM_SUS_STAT# 23,38,40

LPCS_PME# 38

+V1.05S_CPU 3,4,20,35,39,52,54

R8F2 0

0

3

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,48,49,52,55,56,57

R9M2 0.002

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,44,45,46,47,48,50,51,52,55,56,57 +V5 27,32,42,48,52,55,56,57

R9M2 0.002

R9A3 0.002

1%

+V3.3A_R1_TPM

CLK_PCI_TPM36

SMB_CLK_S419,23

+V3.3S_R1_TPM

TP9A2NO_STUFF TP9A2NO_STUFF

2

C9A5

0.1uF

20%

LPC_FRAME# BUF_PLT_RST# LPC_AD3

LPC_AD0

PM_SUS_STAT#

TPM HEADER

C9A4

0.1uF

20%

2x10-HDR_P4KEY

J9A1

1 3 5 7

9 11 13 15 17 18 19 20

1

+V5_R1_TPM

2

6

LPC_AD2

8

LPC_AD1

10 12 14

INT_SERIRQ

16

PM_CLKRUN#

C9A2

0.1uF

20%

R9M1 0.002

1%

SMB_DATA_S4 19,23

TPM_DRQ#0 38

C C

Note: LPC_SLOT_B12 , H_STPCLK# and +V1.05S_CPU have been routed to LPC slot pins testing purpose.

+V3.319,27,32,39,41,42,55,57

R8F1 0.002

+V5 27,32,42,48,52,55,56,57

R8E3 0.002

B B

Decaps for LPC Slots

1%

C8F1

C8F1 22uF

22uF

1%

C8E3

C8E3 22uF

22uF

+V3.3_LPCSLOT

C8G1

0.1uF

20%

+V5_LPCSLOT

C8F2

0.1uF

20%

C8E4

C8G2

0.1uF

20%

CAD NOTE: Place close to LPC Slot J8E1

LPC SIDE BAND HEADER

J9G1

PM_PWRBTN#23,40 PM_RSMRST#23,40,56 PM_THRM#5,12,23,40 PM_BATLOW#23,40 PM_SLP_S3#11,23,40,44,46,47,49,55,57 PM_S4_STATE#23,32,40,44,55,57 PM_LAN_ENABLE23,33,40

SMC_RUNTIME_SCI#23,40 SMC_WAKE_SCI#23,40 SMC_RSTGATE#40,41 SMC_ONOFF#40,56

A A

SMC_LID40,41 SMC_SHUTDOWN40,56

SMB_THRM_CLK5,12,40 SMB_THRM_DATA5,12,40 SMB_BS_CLK37,40,51,52 SMB_BS_DATA37,40,51,52 SMB_BS_ALRT#40,51

1

A1

3

A3

5

A5

7

A7

9

A9

11

A11

13

A13

15

A15

17

A17

19

A19

21

A21

23

A23

25

A25

27

A27

29

A29

31

A31

33

A33

35

A35

37

A37

39

A39

LPC Sideband Header

5

2

A2

4

A4

6

A6

8

A8

10

A10

12

A12

14

A14

16

A16

18

A18

20

A20

22

A22

24

A24

26

A26

28

A28

30

A30

32

A32

34

A34

36

A36

38

A38

40

A40

ALL_SYS_PWRGD 23,40,47 IMVP_VR_ON 40 CPU_PWM_FAN 5,40 CPU_TACHO_FAN 5,40

ATX_DETECT# 40,56 SMB_DATA_ME 23,40 SMB_CLK_ME 23,40

AC_PRESENT 23,40,56

BC_ACOK 40,50 PM_SLP_M# 23,40,44,47,55,57

BS_CLR_LTCH# 40,51

RSMRST#_PWRGD 40,41

BS_CHGA# 40,51

BS_CHGB# 40,51

BS_DISA# 40,51

BS_DISB# 40,51 LAN_WOL_EN 23,40,55,57

4

SUS_PWR_ACK 23,40

J1G2

PM_DPRSLPVR

H_NMI3,21 H_SMI#3,21 H_PWRGD3,21

3

J1G2

1 2 3 4 5 6 7 8

8Pin HDR

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

H_DPRSTP# 3,7,21 H_DPSLP# 3,21 H_CPUSLP# 3,6

LPC Slot and TPM Header

355659

2

TP7E1NO_STUFF TP7E1NO_STUFF TP6G2NO_STUFF TP6G2NO_STUFF

PM_CLKRUN#

TP6H1NO_STUFF TP6H1NO_STUFF TP9B1NO_STUFF TP9B1NO_STUFF TP9C1NO_STUFF TP9C1NO_STUFF TP7B1NO_STUFF TP7B1NO_STUFF

43 58Tuesday, August 28, 2007

1

PM_RI# 23,38 PM_STPCPU# 23,35 PM_STPPCI# 23,35

PCI_PME# 22,32

PM_SLP_M# 23,40,44,47,55,57

Intel Confidential

1.0

5

D D

C C

DOCK_PE_DET#40

B B

USB_PN9_R22

USB_PP9_R22

CRT_BLUE_DOCK16

CRT_GRN_DOCK16

CRT_RED_DOCK16

CRT_HSYNC_DOCK16

+V3.3A

R9C3

R9C3 100K

100K

5%

+V3.3A_1.5A_HDA_IO24,27,28

HDA_SDATAIN_DOCK27

LAN_LED_1000#_DOCK34

LAN_MDI2N_Q_DOCK34 LAN_MDI3P_Q_DOCK34 LAN_MDI3N_Q_DOCK34

LAN_LED_LINK#_DOCK34

Note: PE_DET# - GND in CRB, Shorted to PE_DET# in Docking Board

DOCK_EXP_CPPE#40

PM_S4_STATE#23,32,40,43,55,57

CRT_VSYNC_DOCK16

TV_DCONSEL0_DOCK18 CRT_DDC_CLK_DOCK16 CRT_DDC_DATA_DOCK16

HDA_SYNC_DOCK27 HDA_SDO_DOCK27

LAN_MDI2P_Q_DOCK34 LAN_MDI1N_Q_DOCK34

AMPS_CONTROL50

PM_SLP_S3#11,23,40,43,46,47,49,55,57

PM_SLP_M#23,40,43,47,55,57

PS_ON_SW#56

DOCK_SYS_PWRGD#40

A A

5

4

SMB_DATA_DOCK

Reserved

SMB_CLK_DOCK

Reserved

4

PCI-Express Docking Interface

J9C2

S1

S2

S3

S4

S5

S7

S8

S9

S10

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

S35

S36

S37

S38

S43

S44

S45

S46

S47

S48

S49

S51

S52

S53

S54

S56

S57

S58

S60

S61

S62

S64

S65

S66

S67

S68

S69

S70

S71

S72

S73

S74

S75

S79

S77

S80

S85

S86

S87

S88

S89

S90

S91

S92

S93

S95

S96

S97

PCI-E DOCKING CONN

S100 S101 S103 S104 S105 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S119 S120 S121 S122 S127 S128 S129 S130 S131 S132 S133 S135 S136 S137 S139 S140 S141 S143 S144 S145 S147 S148 S149 S150 S151 S152 S153 S154 S155 S156 S157 S158 S161 S162 S163 S164

M84

M126

S99

P1 P2 P3 P4

G1 G2 G3 G4 G5 G6 G7 G8

G9 G10 G11 G12

S99 S100 S101 S103 S104 S105 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S119 S120 S121 S122 S127 S128 S129 S130 S131 S132 S133 S135 S136 S137 S139 S140 S141 S143 S144 S145 S147 S148 S149 S150 S151 S152 S153 S154 S155 S156 S157 S158 S161 S162 S163 S164

M84 M126

P1 P2 P3 P4

G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12

PCIE_WAKE#_DOCK

HDA_SPKR_DOCK

PE_OPNREQ#

SMI#_DOCK

3

DOCK_PWR_EN# 41 CLK_REQ#_DOCK 36

PCIE_TXP1_DOCK 22

PCIE_TXN2_DOCK 22 PCIE_TXP2_DOCK 22 PCIE_RXN2_DOCK 22 PCIE_RXP2_DOCK 22

TV_DCONSEL1_DOCK 18

HDA_DOCK_RST# 21,27

LAN_MDI1P_Q_DOCK 34

SATA_RXP4_DOCK 21 SATA_RXN4_DOCK 21

SATA_TXP4_DOCK 21 SATA_TXN4_DOCK 21

RSTBTNDB 56

PE_OPNREQ# 40

DOCK_PE_RST# 41 DOCK_PE_PWRGD# 41

PCIE_TXN1_DOCK 22

PCIE_RXN1_DOCK 22 PCIE_RXP1_DOCK 22

TV_DACA_OUT_DOCK 18

TV_DACB_OUT_DOCK 18

TV_DACC_OUT_DOCK 18

HDA_BCLK_DOCK 27

LAN_LED_100#_DOCK 34

LAN_MDI0N_Q_DOCK 34 LAN_MDI0P_Q_DOCK 34

CLK_PCIE_DOCK 36 CLK_PCIE_DOCK# 36

+VAC_IN_L41,50

NOTE: Power pins rated at 7A per pin.

3

2

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,45,46,47,48,50,51,52,55,56,57

PE_OPNREQ#

R9C1 10K

5%

.

R9E5

R9E5 0 NO_STUFF

0 NO_STUFF

+V1.8_VCT_LAN_DOCK34

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

HDA_SPKR 23,27

SMB_CLK_A123,25,26,32 SMB_DATA_A123,25,26,32

PCIE_WAKE#19,23,25,26 SMC_EXTSMI#23,38,40,43

DOCK_PE_QSEN#41

Docking

355659 1.0

TP_1A5

TP_2A1 TP_2A2

TP_2A4 TP_2A5

+V3.3M_WOL22,24,33,34,48,55,57

3

1A1

4

1A2

7

1A3

8

1A4

11

1A5

14

2A1

17

2A2

18

2A3

21

2A4

22

2A5

1

1OE#

13

2OE#

SN74CBTD3384

U9C1

C9P2

0.1uF

20%

GND

VCC

1B1 1B2 1B3 1B4 1B5

2B1 2B2 2B3 2B4 2B5

2

1

+V5A 24,29,34,38,46,47,50,51,56,57

24

SMB_CLK_DOCK

2

SMB_DATA_DOCK

5

PCIE_WAKE#_DOCK

6

SMI#_DOCK

9

TP_1B5

10

TP_2B1TP_2A3

15

TP_2B2

16

TP_2B3

19

TP_2B4

20

TP_2B5

23

12

Intel Confidential

44 58Tuesday, August 28, 2007

1

5

+V5A_MBL 56

R3W12

40.2K

1%

C3H9

C3H9 1000pF

1000pF

5%

VREF2

AGND_51120

C3W4

C3W4 1000pF

1000pF

5%

VREF2

NO_STUFF

D D

R3H9

R3H9 10K

10K

1%

AGND_51120

+V5_LDO_FILT

R3W15

R3W15 0

0

.

C3H10

C3H10 470pF

470pF

R3H10

5%

9.76k_1%

NO_STUFF

+V5_LDO_FILT_RC1

C3W5

C3W5 2200PF

2200PF

NO_STUFF

R3H5

R3H5 0

0

.

R3W7

30.1K

1%

1% NO_STUFF

NO_STUFF

+V5_LDO_FILT_RC2

C3W2

C3W2 470pF

470pF

5%

5% NO_STUFF

NO_STUFF

AGND_51120

VR_ALW_ENABLE28,56

NO_STUFF

AGND_51120

100pF NO_STUFF

R3H12

R3H12 0

0

C3H4

5%

100K

100K R3H2

R3H2

AGND_51120

+V3.3A_MBL 56

R3H7

23.7K

1%

1% .

.

R3W9

R3W9 10K

10K

1%

AGND_51120

C C

B B

3.3V_EV

NO_STUFF

+V5A3A_MBL_PWRGD41

+V5A_MBL56

R3H8

R3H8 0

0

NO_STUFF

R3H6

0

51120_COMP2

+V5_LDO

C3W3

C3W3 1000pF

1000pF

5%

51120_COMP1

51120_VFB1

VREF2

51120_VFB2

+V3.3A_MBL56

NO_STUFF

AGND_51120

R3W18

R3W18 0

0

.

R3W19

R3W19 0

0

NO_STUFF

AGND_51120

51120_SKIPSEL

EU3H1

1

2

3

4

5

6

7

8

R3W2

R3W2 0

0

.

A A

5

4

R3H15

R3H15 0

0

R3H14

R3H14 0

0

31

32

SKIPSEL

VO1

COMP1

VFB1

VREF2

GND

VFB2

COMP2

VO2

EN59EN310PGOOD211EN2

+V5_LDO_EN3

VR_ALW_ENABLE_R

R3H1

R3H1 0

0

.

5%

PROGRAMMING TABLE

SKIPSEL COMP TONSEL(CH1/2) VFB1 VFB2 EN1,EN2 EN3,EN5

4

+V3_LDO

R3H17

R3H17 10K

10K

5%

5% .

.

51120_TONSEL

29

30

EN1

TONSEL

PGOOD1

TPS51120

12

51120_VR_ALW_ENABLE

R3W6

R3W6 10K

10K

.

+V3.3A

AGND

AUTO-SKIP N/A 380KHz/590KHz N/A N/A SWITCHER OFF LDO OFF

51120_EN1

51120_DRVH1_R

C3H11

0.47uF

51120_VBST1

28

27

VBST1

DRVH1

VBST213DRVH214LL215DRVL2

51120DRVH2

51120VBST2

C3H3

0.47uF

NO_STUFF

AGND_51120

NO_STUFF

AGND_51120

51120_+V5A_MBL_Q

51120_DRVL1_Q

26

25

TH

LL1

DRVL1

PGND1

CS1

VIN

VREG5

V5FILT

VREG3

CS2

PGND2

16

51120VBST2_Q

51120_DRVL2_Q

C3H2

0.1uF

10%

VREF2

AUTO-SKIP FAULTS OFF N/A 290KHz/440KHz SHOULD NOT BE USED SHOULD NOT BE USED SHOULD NOT BE USED SHOULD NOT BE USED

3

V5A_MBL_PWRGD

R3W22

R3W22 0

0

R3H16

R3H16 220K

220K

5%

5% .

.

33

24

23

22

21

20

19

18

17

NO_STUFF

Note: RC network for manually adjusting soft start delay

Q3W3

.

2

BSS138

1

51120_DRVH1_Q

R3H13

R3H13 0

0

.

AGND_51120

51120_CS1_R

51120_CS2_R

R3H4

R3H4 0

0

.

567

4

R3W3

R3W3 0

0

R3W4

.

0

PWM FAULTS OFF N/A 220KHz/330KHz (DEFAULT) N/A N/A N/A N/A

NO_STUFF

3

VR_ALW_ENABLE 28,56

567

4

R3W14

1 2

567

51120DRVH2_RQ

4

8

Q3H1

Q3H1 IRF7822

IRF7822

312

FLOAT

+V5A3A_MBL_PWRGD

R3W11

R3W11 0

0

51120_EN1_C

C3W6

0.1uF

10%

NO_STUFF

AGND_51120

567

4

8

Q3H4

Q3H4 IRF7822

IRF7822

312

10.7K

1%

R3W8

12.4K

1%

51120DRVH2_+VBATA_Q

8

Q3H2

Q3H2 IRF7811A

IRF7811A

312

CR3G2

B320A

NO_STUFF

2 1

V5A_MBL_PWRGD

+V3_LDO

51120_DRVH1_+VBATA

8

Q3H5

Q3H5 IRF7811A

IRF7811A

312

1 2

CR3H1

B320A

NO_STUFF

2 1

+V3_LDO

C3H6

C3H6 10uF

10uF

20%

.

1 2

L3G2

3.3uH

+V5_LDO_FILTPIN

PWM D-CAP MODE 180KHz/280KHz 5V FIXED OUTPUT

3.3V FIXED OUTPUT SWITCHER ON LDO ON

3

R3W20

R3W20 0

0

.

L3H1

3.3uH

AGND_51120

51120VBST2_LR

+V5_LDO_FILT

C3H7

1.0uF

20%

20% 402

402

.

2

R3H11

R3H11 0

+V3_LDO

+VBATA 26,46,47,56,57

R3H18

0.002

1%

C3H13

0.1uF

10%

10% .

.

51120_+V5A_MBL_QL

R3W10

49.9

1%

C3H1

C3H1 22uF

22uF

R3G5

0.002

1%

V5 Output Mode Selection

Fixed Output Mode

V5 Mode Selection

Current Mode D_CAP Mode (default)

Title

Size Document Number Rev

Date: Sheet of

1%

C3H12

C3H12 22uF

22uF

R3J2 0.002

1%

+VBATA26,46,47,56,57

C3H8

0.1uF

10%

10% .

.

C3H5

C3H5 10uF

10uF

20%

.

R3H3

0.002

C3G8

0.1uF

10%

10% .

.

NO_STUFF

Pillar Rock

A

0.002

1%

+

C4H1

0.1uF

10%

+

TPS51120 System Power

355659 1.0

0

.

AGND_51120

12

+

C4Y2

0.1uF

10%

NO_STUFF

+V5_LDO

+VBATA 26,46,47,56,57

+V3.3A_MBL 56

Icc-max=8A OCP=18A

+

C4G4

C3G6

330uF

20%

C3H9, R3W12 & R3H9

STUFF

R3W15

R3H10, C3H10 & C3W5

NO_STUFF STUFF

STUFF NO_STUFF

C3Y1

C3Y1 220uF

220uF

10%

10% .

.

R3H8

STUFFNO_STUFF NO_STUFFAdjustable Mode (default)

+V5A_MBL 56

Icc-max=8A OCP=15A

12

+

C3J1

+

C3J1 220uF

220uF

10%

10% .

.

V3.3 Output Mode Selection

Fixed Output Mode Adjustable Mode (default)

V3.3 Mode Selection

Current Mode D_CAP Mode (default)

2

1

C3W3, R3H10 & R3W9

NO_STUFF STUFF

R3H5

NO_STUFF STUFF

45 58Tuesday, August 28, 2007

1

R3H6

STUFF NO_STUFF

R3W7, C3H4 & C3W2

STUFF NO_STUFF

Intel Confidential

5

Note: C4B7 adjusts the soft-start time for the VTT output. The charge rate at the SS pin is 4uA and the

D D

threshold voltage is 1.6V. A 4700pF capacitor gives a

1.88mS soft-start. This roughly matches the 1.7mS digital soft-start built in to the switching output.

R4B3

TON (Switching Frequency Select) Resistor used: Frequency:

R4N6 R4B4

None (Default) 300KHz

R4B3

OVP/UVP (Protection/Discharge Enable) Resistor used: OVP, Discharge R4N12 (Default)

C C

None (open)

R4N9 R4B5

Note: U4A3, R4M8, C4M4 to be stuffed only for DDR3 board

600KHz 450KHz

200KHz

Enabled Enabled Disabled Disabled

PM_SLP_S4#23,55

UVP Enabled Disabled Enabled Disabled

U4A3

1

2

B B

DDR_POK_RU

PM_SYS_PWRGD48

A A

PM_PGOOD_1_05M47

VRPWRGD_3.3M_WOL48

R4M9

R4M9 10K

10K

5%

5% .

.

U4A4

1

2

U4M2

1

2

+V3.3A

NO_STUFF

53

74AHC1G08

53

74AHC1G08

53

74AHC1G08

R4B4

10K

NO_STUFF

R4N9

10K

NO_STUFF

C4M4

0.1uF

10%16V

4

NO_STUFF

C4M6

0.1uF

10%16V

.

4

.

C4N1

0.1uF

10%16V

.

4

.

SM_PWROK_U

10K

NO_STUFF

R4N6

10K

NO_STUFF

AGND_DDR

R4N12

10K

R4B5

10K

NO_STUFF

AGND_DDR

PM_SLP_S4#23,55

R4M8

12.1K

1%

1% NO_STUFF

NO_STUFF

R4M7

R4M7 10K

10K

1%

1% .

.

CANTIGA_DDR_PWRGD

5

4

.

Note: EU4N1 needs to be moved to MPAD.OLB

SM_PWROK 7

PM_PWROK 47

U4A5U4A5

1

2

Adds 3.3M to the MPWROK tree. Needed to support G3->M1 and Moff to M1 transitions.

4

SKIP# (Pulse Skipping Enable) Resistor used: Skip mode: R4B2(Default) R4N1

DDR_AVDD

.

AGND_DDR

DDR_REF

C4B2

0.22uF

R4N15

R4N15 100K

100K

1%

1% .

.

R4N17

23.7K

1%

1% .

.

AGND_DDR

DDR_TON DDR_OVP

M_VREF_MCH7,48

Note: C4B6 should be placed close to the VTTR pin.

53

0.22uF

20%

20% .

.

DDR_ILIM

DDR_SHDN_RU

DDR_POK_RU2

R4N3

R4N3 0

0

.

R4B6

R4B6 0

0

.

R4N7

R4N7 0

0

.

C4B1

0.1uF

10%16V

.

4

Enabled Disabled

R4B2

10K

AGND_DDR

4 1 2

27

7 5 6

C4B6

C4B6 1uF

1uF

20%

20% .

.

AGND_DDR

MPWROK 7,23

NO_STUFF

DDR_SKIP#

C4B7

4700PF

EU4N1

ILIM TON OVP/UVP SHDN# STBY# POK1 POK2

R4N1

R4N1 10K

10K

DDR_SS

3

8

28

SS

REF

TPO

MAX8632

VTTR10PGND211VTT12VTTI13REFIN

GND

TAB

24

29

DDR_VTTR

R4B8

R4B8 0

0

.

3

R4B1

1.8_VIN

17

22

25

26

VIN

VDD

AVDD

SKIP#

BST

DH

PGND1

OUT

VTTS

9

14

DDR_REFIN

NOTE: Place C4N3 and C4B8 near VTTI pin and C4B5 near REFIN pin.

NOTE: Place VTT bypass caps as close to VTT and PGND2 pins as possible. Connect VTT sense line (VTTS) separately to VTT at the point of regulation.

C4N4

C4N4 10uF

10uF

20%

20% .

.

NOTE: TAB must be star-connected to GND pin (analog gnd) and to PGND2 through R4B8(0-ohm resistor). PGND2 and the low side of the VTT bypass caps are connected to the PGND plane.

+V5A24,29,34,38,44,47,50,51,56,57

10.5%

C4B4

C4B4 1uF

1uF

10%

10% .

.

AGND_DDR

C4N2

4.7uF

10%

10% .

.

20 18 19

LX

21

DL

23 15

FB

16

C4B8

C4B8 10uF

10uF

20%

.

CR4B1

1 3

CMPSH-3

DDR_BST_R DDR_BST_RC

DDR_DH_R

DDR_DL_R

DDR_FB_RR

+V1.89,10,13,14,48,55,57

C4N3

0.1uF

10%

10% 16V

16V

NO_STUFF

+V0.9_R

C4B13

C4B13 10uF

10uF

20%

.

PM_SLP_S3#11,23,40,43,44,47,49,55,57

PM_SLP_S4#23,55

C4N5

C4N5 10uF

10uF

20%

.

R4N10

R4N10 0

0

5%

5% .

.

3

2

1

DDR2 VREG

+VBATA26,45,47,56,57

R4A4

0.002.1%

C4A8

C4A8 10uF

10uF

25V

+V1.89,10,13,14,48,55,57

R5B2

+V1.8_L_R

C5B1

C5B1 330uF

330uF

2.5V

NO_STUFF

DDR2, DDR3, EVMC (remote adjust) Selection:

Note: Stuff these parts for DDR3 memory only. NO_STUFF for DDR2 memory.

SC1563

NO_STUFFU6V1

NO_STUFF

4

OUT

3

LVDS_AD

R5B2

0.002.1%

20%

DDR2

DDR3

EVMC enabled

LVDS_OUT

R5V2

R5V2 10K

10K

1%

1% NO_STUFF

NO_STUFF

C5V3

C5V3 22uF

22uF

NO_STUFF

R5U28

1%

20K

NO_STUFF

R5U24

R5U24 0

0

NO_STUFF

+V1.8_LDO_EVMC_V_CNTL

Note: Place EVMC control resistor near U6V1

46 58Tuesday, August 28, 2007

1

567

123 8

+V1.8_EVMC_R

1

8

Q4B1

Q4B1 IRF7811A

IRF7811A

.

312

765

R4N19 10K

NOTE: R4N19 to be changed to

11.5K, 1%. (for DDR3 board)

NO_STUFF

3

2

1.8_VIN

Q4N1

IRF7834

NO_STUFF

R4N22

R4N22 0

0

C6V2

1.0uF

10%

10% NO_STUFF

NO_STUFF

Q6F1

Q6F1 BSS138

BSS138

NO_STUFF

2

C4A9

C4A7

10uF

25V

L4B1

1 2

1.0uH

CR4N1

CR4N1 MBR0530

MBR0530

.

2 1

DDR_AVDD

R4N20

R4N20 10K

10K

1%

R4N21

R4N21 10K

10K

1%

1% NO_STUFF

NO_STUFF

AGND_DDR

+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,47,48,50,51,52,55,56,57

Note: Keep trace from FB pin short

.

(feedback resistors near pin).

Resistor used Mode selected STUFF : R4N20 NO_STUFF : R4N19, R4N21 STUFF : R4N19, R4N21 NO_STUFF : R4N20 STUFF : R4N19, R4N21, R4N22 NO_STUFF : R4N20

+V1.8_EVMC_V_CNTL

R6V3

R6V3 10K

10K

5%

5% NO_STUFF

NO_STUFF

U6V1

5

IN

1

SHDN

GND2ADJ

LVDS_SHDN

R6G1

R6G1 0

0

NO_STUFF

C4B3

0.22uF.20%

DDR_DH_RQ

R4N13

R4N13 0

0

5%

5% .

.

DDR_LX

DDR_DL_RC

R4N5

R4N5 0

0

5%

5% .

.

NOTE: LX and PGND1 pin connections to the low-side FET must be made as Kelvin-sense connections.

R4B7

R4B7 22

22

5%

5% .

.

C4B5

0.1uF.10%

R4B10

0.002.1%

R5F20

0

NO_STUFF

0

R5F21

NO_STUFF

4

R4N18

10.5%

AGND_DDR

+V0.915,55

5%

PM_SLP_S3_S4_LDO

5%

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

DDR2 VR

355659 1.0

A

355659 1.0

A

355659 1.0

A

Vout, VTT

1.8V, 0.9V

1.5V, 0.75V

+V1.8_LDO10

R5V1

0.01 1%

NO_STUFF

C6V3

0.1uF

10%

NO_STUFF

Intel Confidential

5

4

3

2

1

EV_VCC_V1.05S

+V1.05S4,9,10,24,55

C3U1

C3U1 270uF

270uF

20%

20% .

.

+VBATA26,45,46,56,57

C7U1

C7U1 270uF

270uF

20%

20% .

.

R4G3

0.002

1%

1% .

.

C4F3

C4F3 270uF

270uF

20%

V1.05S_VIN

22UF

R4F7

0.002.1%

C4F4

0.1uF

10%

.

C4G2

C4G1

0.1uF

10%

10% .

.

Q4F1B

IRF9910

L4F1

1 2

1.0uH

CR4F1

CR4F1 B320A

B320A

5 6

2 1

3

Q4F1A

IRF9910

4

51124_DRVH2_R

7 8

1

D D

C4U1

C4U1 270uF

270uF

20%

20% .

.

2

PM_1.5_1.05S_PGOOD

PM_SLP_S3#11,23,40,43,44,46,49,55,57

+V5A24,29,34,38,44,46,50,51,56,57

1

3

51124_VBST2_R

EV_VCC_V1.05S_R 1.05M_EV_R

R4U6

1%R4U6

1%

2.8K

R5U33

R5U33 0

R5F18

R5F18 0

0

51124_VBST2

.

51124_DRVH2

51124_DRVL2

0

.

51124_PGD2

51124_LL2

CR5U1

BAT54

C5F3

0.1uF

10%

10% .

.

R5F17

R5F17 0

0

.

C C

NO_STUFF

51124_TONSEL

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,48,50,51,52,55,56,57

R5H1

R5H1 10K

10K

1%

1% .

.

PM_1.5_1.05S_PGOOD

NO_STUFF

R5G3 10K

PM_PGOOD_1_05M

R4V1

R4V1 0

0

NO_STUFF

R5U27

R5U27 0

0

.

AGND_51124

U4H1

1

2

EU5G1

7

PGD2

8

EN2

9

VBST2

10

DRVH2

11

LL2

12

DRVL2

R5F19 12.1K

53

AGND_51124

R4G1

7.5K

1%

+V1.05S4,9,10,24,55

6

THM

13

25

AGND_51124

1%

.

C5G1

C5G1 1uF

1uF

20%

AGND_51124

4

74AHC1G08

.

R5U32

10K

NO_STUFF

.

51124_VB2

51124_TONSEL

3

4

5

VO2

GND

VFB2

TONSEL

TPS51124

TRIP2

V5FILT

PGND2

V5IN

14

15

16

51124_TRIP2

51124_V5FILT

R5G1 3.9

1%

.

Power Good Logic

C4G5

0.1uF

10%

.

CANTIGA_VR_PWRGD

R4G2

7.5K

1%

1% .

.

+V1.05M9,10,15,35,55

51124_VB1

2

1

VO1

VFB1

PGD1

EN1

VBST1

DRVH1

DRVL1

PGND118TRIP1

17

51124_TRIP1

R5G4

6.49K.1%

+V5A24,29,34,38,44,46,50,51,56,57

C5G2

4.7uF

10%

10% .

.

LL1

NO_STUFF

R4V2

R4V2 0

0

R4V3

R4V3 0

0

.

24

23

22

21

20

19

AGND_51124

R5V3

R5V3 0

0

.

51124_PGD1

51124_VBST151124_VBST1

51124_DRVH151124_DRVH1

51124_LL151124_LL1

51124_DRVL151124_DRVL1

1.05M_EV

+V1.05M9,10,15,35,55

R4V4

2.8K1%

PM_SLP_M# 23,40,43,44,55,57

+V5A 24,29,34,38,44,46,50,51,56,57

51124_VBST1_R

R5G5

R5G5 0

0

.

R5V4

R5V4 0

0

.

PM_PWROK46

+V3.3A

1

CR5V1

CR5V1 BAT54

BAT54

3

C5G3

0.1uF

10%

10% .

.

51124_DRVH1_R

R4V5

R4V5 10K

10K

1%

1% .

.

4

U4W1

1

2

PM_PGOOD_1_05M 46

V1.05M_VIN

C4V4

0.1uF

10%

10% .

.

567

8

Q5V1

Q5V1 IRF7811A

4

567

+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,48,50,51,52,55,56,57

53

74AHC1G08

IRF7811A

.

312

L4G1

1 2

8

Q5G1

Q5G1 IRF7822

IRF7822

2 1

.

312

C4V6

0.1uF

10%16V

.

4

.

51124_LL1_L51124_LL2_L

1.0uH

CR5G3

CR5G3 B320A

B320A

ALL_SYS_PWRGD 23,40,43

R4V10

0.002.1%

C4V5

C4V5 22UF

22UF

AGND_51124

+VBATA26,45,46,56,57

R4G4

0.002

.

VR Current Capability

Rail I continuous Nominal OCP

+V1.05M +V1.05S

TONSEL PIN CH1 CH2

FLOAT 300kHz 360kHz

1%R4G4

1%

C4G3

0.1uF

10%

.

R5U26

R5U26 0

0

.

9A 15A

Switching Frequency

C5U6

C5U5

270uF

20%

.

14A3A

+V1.05M9,10,15,35,55+V1.05S

C4V2

C4V2 270uF

270uF

20%

B B

Note: NO_STUFF V1.5S VR for DDR3. DDR3 will generate V1.5S.

+V1.5S4,10,11,24,28,55,57

PM_SLP_S3#

R5F16

R5U25

R5U25 20K

20K

1%

R5U21

0

AGND_51117

R5F16

200K

.

1%

51117_V5FILT

C5F4

18PF

.

R5U22

1%

20K

.

1

51117_TON

2 3 4

51117_VFB

5 6

AGND_51117

51117_PGOOD

R5U29

R5U29 0

0

.

PM_1.5_1.05S_PGOOD

U5F1

EN_PSV TON VOUT V5FILT VFB

V5DRV PGOOD GND7PGND

TPS_51117

VBST

DRVH

TRIP

DRVL

51117_VBST

14

51117_DRVH

13

51117_LL

12

LL

51117_TRIP

11 10 9 8

+V5A 24,29,34,38,44,46,50,51,56,57

C5V1

C5V1 1uF

1uF

Place C5V1 close

20%

to U5F1.10

.

+V5A

R5F15

R5F15 301

301

1%

C5F2

C5F2 1uF

1uF

20%

.

A A

EV_VCC_V1.5S

AGND_51117

R5U20

NO_STUFF

.

EV_VCC_1.5S_R

0

5

+V5A 24,29,34,38,44,46,50,51,56,57

1

CR5G1

BAT54

3

51117_VBST_R

R5U30

7.87K

.

R5G7

R5G7 0

0

.

1%R5U30

1%

AGND_51117

51117_DRVL

C5G5

0.1uF

10%

10% .

.

+V5A 24,29,34,38,44,46,50,51,56,57

4

51117_DRVH_R

R5G6

R5G6 0

0

.

2

+VBATA26,45,46,56,57

V1.5S_VIN

C5G4

0.1uF

56

10%

10% .

.

Q5G2B

Q5G2B IRF9910

IRF9910

4

3

78

Q5G2A

Q5G2A IRF9910

IRF9910

2 1

1

L5G1

1 2

1.0uH

CR5G2

B320A

C5V2

C5V2 22UF

22UF

1%

R5V5

AGND_51117

0.002

.

51117_LL_L

3

R5U23

R5U23 0

0

.

R5G2

0.002

.

+V1.5S4,10,11,24,28,55,57

1%R5G2

1%

12

+

C5V4

+

C5V4

C6V4

220uF

0.1uF

10%

.

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

Cantiga VR

355659 1.0

A

355659 1.0

A

355659 1.0

A

VR Current Capability

Rail I continuous Nominal OCP

+V1.5S 3A 7.5A

Switching Frequency

TON PIN

200K 400kHz

2

47 58Tuesday, August 28, 2007

1

Intel Confidential

5

4

3

2

1

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,50,51,52,55,56,57

+V3.3M_WOL22,24,33,34,44,55,57

+V5S5,11,12,16,17,18,24,28,30,31,32,39,49,52,55,56,57

D D

VRPWRGD_3.3M_WOL46

Adds 3.3M_WOL to the MPWROK tree.

R4W13

24.9K

1%

1% .

.

R4W11

R4W11 10K

10K

1%

1% .

.

R4W10

R4W10 13K

13K

R4W8

R4W8 100K

100K

1%

+V5S_PWRGD

+V3.3M_WOL_PWRGD

R4W9

R4W9 10K

10K

1%

1% .

.

C4W1

0.1uF

10%

.

R4W12

R4W12 100K

100K

U4H2

1

OUTB

2

OUTA

3

V+

4

INA-

5

INA+

6

INB-

7

INB+

8

REF

LTC1444

PP_REFIN

VREF = 1.221V

OUTC OUTD

HYST

IND+

INC+

IND-

INC-

PM_SYS_PWRGD 46

16 15

PP_HYST

14

+V3.3S_TVDAC_PWRGD

13 12

+V3.3S_PWRGD

11 10 9

V-

R4W7

R4W7 10K

10K

5%

5% .

.

R4W1

2.4M

.

+V3.3S_TVDAC10,11,55

R4W3

R4W3 13K

13K

1%

NO_STUFF

TP4H1

R4W5

R4W5 10K

10K

1%

1% .

.

C C

+V527,32,42,43,52,55,56,57

+V1.89,10,13,14,46,55,57

R3N13

R3N13 10K

R3B5

R3B5 10K

10K

1%

1% .

.

10K

1%

1% .

.

C3B6

C3B6 220pF

220pF

10%

10% .

.

B B

M_VREF_DIMM_B

+V5 27,32,42,43,52,55,56,57

+V527,32,42,43,52,55,56,57

VDD+

2

-

3

+

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,49,52,55,56,57

+V527,32,42,43,52,55,56,57

10

VDD+

U4B1A

U4B1A TLV2463

R4W2

R4W2 13K

13K

1%

R4W4

R4W4 10K

10K

1%

1% .

.

M_VREF_MCH_A

+V527,32,42,43,52,55,56,57

R3B14

R3B14 10K

10K

5%

5% NO_STUFF

10

U3B1A

U3B1A TLV2463

TLV2463

VREF_DIMM1_MARG

1

OPAMP2_SHTDN#

5

GND

4

NO_STUFF

R3N17

R3N17 10K

10K

5%

5% .

.

NO_STUFF

R3N11

R3N11 0

0

UNUSED_BUF_U6A1A_P2

R4N4

R4N4 0

0

.

UNUSED_BUF_U6A1A_P1

+V1.89,10,13,14,46,55,57

R3N2

R3N2 0

0

.

R3N4

R3N4 10K

10K

1%

1% .

.

R3N1

R3N1 10K

10K

1%

1% .

.

2

3

UNUSED_BUF_U6A1A_P3

R4N8

R4N8 0

0

.

C3N3

C3N3 220pF

220pF

10%

10% .

.

TLV2463

-

+

1

OPAMP4_SHTDN#

5

GND

4

+V527,32,42,43,52,55,56,57

C3N2

0.1uF

10%

.

10

VDD+

U4B1B

8

-

7

+

GND

4

TLV2463

VREF_MCH_MARG

9

OPAMP3_SHTDN#

6

R4N14

R4N14 10K

10K

5%

5% NO_STUFF

NO_STUFF

R4N16

R4N16 10K

10K

5%

5% .

.

+V527,32,42,43,52,55,56,57

R3N7

R3N7 10K

10K

5%

5% NO_STUFF

NO_STUFF

R4N11

R4N11 10K

10K

5%

5% .

.

R4N2

R4N2 0

0

NO_STUFF

M_VREF_MCH 7,46

C3N5

0.1uF

10%

.

+V1.89,10,13,14,46,55,57

R3N15

R3N15 10K

10K

1%

1% .

R3B11

R3B11 10K

10K

1%

1% .

.

C3N7

C3N7 220pF

220pF

10%

.

M_VREF_DIMM_A

A A

VDD+

8

-

7

+

.

10

U3B1B

U3B1B TLV2463

TLV2463

VREF_DIMM0_MARG

9

OPAMP1_SHTDN#

6

GND

4

5

R3N16

R3N16 10K

10K

5%

NO_STUFF

R3B12

R3B12 10K

10K

5%

5% .

.

NO_STUFF

4

R3N9

R3N9 0

0

R6P1

R6P1 0

0

.

M_VREF_DIMM0 13

M_VREF_DIMM1 14

Intel Confidential

48 58Tuesday, August 28, 2007

1

Intel Confidential

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

3

Date: Sheet of

DDR2 VREF

355659 1.0

A

355659 1.0

A

355659 1.0

A

2

5

Attach VCC_AXG_SENSE and VCC_AXG_SENSE underneath Cantiga. Ground and output resistors should be tied to +VGFX_CORE bypass caps.

R3V1

R3V1 0

0

.

GND_GVR

D D

R4T1

1 2

10

.

+VGFX_CORE

R4R12

1 2

10

.

+V3.3S

R2G5

R2G5 10K

10K

5%

Placement of R4T1 and R4R12 Place R4R12 close to GMCH pins on +VGFX_CORE Place R4T1 close to GMCH GND pins

R3F7 30.1

J4G1

NO_STUFF

1 2

GND_GVR

VSS_AXG_SENSE 9

1%

1% .

.

R3F4 100

100

VCC_AXG_SENSE 9

R2G3 71.5K 1%R2G3 71.5K 1%

GND_GVR

C C

B B

+V3.3S

J2H2J2H2

A A

.

Connect Power ground to Controller ground under the controller

C3G2

C3G2 1000pF

1000pF

5%

GVR_FB_R

C3F1

C3F1 1000pF

1000pF

10%

GND_GVR

C2G1

C2G1 100pF

100pF

+V5S5,11,12,16,17,18,24,28,30,31,32,39,48,52,55,56,57

GVR_VCC

12

RT3V1

100K

GND_GVR

R2V9 8.2KR2V9 8.2K

GVR_STRAP_VID0

R2V11 8.2KR2V11 8.2K

GVR_STRAP_VID1 GVR_STRAP_VID2 GVR_STRAP_VID3 GVR_STRAP_VID4 GVR_STRAP_VR_EN GVR_STRAP_EXTRA

16

111315

GVR_V5_S0

+V3.3S

R2G10 10K

Refdes R2F2

1.05V (Default)

1.25V 7.87K, 1%

R2F2 11K

GVR_POUT

R3G2

13.7K

1%

1% .

.

R2V7 8.2KR2V7 8.2K

GFXVR_VID_07 GFXVR_VID_17 GFXVR_VID_27 GFXVR_VID_37 GFXVR_VID_47 GFXVR_EN7

R3F6

R3F6 1K

1K

1%

+V3.3S

R2V13 8.2KR2V13 8.2K

R2G11 8.2KR2G11 8.2K

246

13579

GND_GVR

1%R3F4

1%

5%

8

101214

R2V4 8.2KR2V4 8.2K

.

1%

.

GND_GVR

GVR_S2_S1

5

GVR_GNDS

R2V2 8.2KR2V2 8.2K

4

11K, 1%

GVR_FB

GVR_CCV

GVR_TIME

GVR_VRHOT#

C2G2

0.22uF

R2V1 8.2KR2V1 8.2K

2 5

8 11 13 16 18 21 23

3

6

9 12 14 17 19 22 24

1 48

34 39 42

4

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,52,55,56,57

R2G12

.

10K

5%

GVR_VR_EN

GVR_PGDLY

Graphics VR Controller

GVR_REF

R2G8

R2G8 0

R2G9

R2G9 0

0

5%

5% .

.

A

A B

U2G2

A0 A1 A2 A3 A4 A5 A6 A7 A8

B0 B1 B2 B3 B4 B5 B6 B7 B8

S0 S1 S247GND1 GND5 GND6 GND7

74CBT16209A

0

5%

5% NO_STUFF

NO_STUFF

Output

GND0

GND2 GND3 GND4

VCC

C CB

D

C0 C1 C2 C3 C4 C5 C6 C7 C8

D0 D1 D2 D3 D4 D5 D6 D7 D8

GVR_OFS

GVR_THRM

S2Input

S1DS0

1

1 1

1 1 1

1 1

1

GVR_VID0

46

GVR_VID1

44

GVR_VID2

41

GVR_VID3

38

GVR_VID4

36

GVR_VR_EN_R

33 31 28 26

45 43 40

11,23,40,43,44,46,47,55,57

37 35 32 30 27

+V5S

25

7 4 10 15 20 29

3

GVR_VCC

GVR_BST

GVR_DRVH_G

GVR_SW_PHASE

GVR_DRVL_G

GND_GVR

C3F2

0.01uF

10%

.402

.402 25V

25V

GND_GVR

STUFF: R2V6 NO_STUFF: R2V3

NO_STUFF: R2V6

+V5S5,11,12,16,17,18,24,28,30,31,32,39,48,52,55,56,57

12

GND_GVR

R3G4

R3G4 0

0

5%

5% .

.

GVR_POUT

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,52,55,56,57

NO_STUFF

R2G15

R2V14

30.1K

20K

1%

+V5S_GVR

GVR_VID0

0 1

0

PM_SLP_S3#

C2G5

C2G5 .01uF

.01uF

20%

1%

R2G13

R2G13 100K

100K

GVR_VID1

GVR_VID2

GVR_VID3

GVR_VID4

GND_GVR

GVR_CSN

GVR_TON

GVR_CSP

R2V5 200K

1%

C3F3

0.22uF

R3G1

R3G1 0

0

5%

5% .

.

Note: Place R2G2, R2G6, R2G7 & R2G1 close to U2G1 and keep input lines (pins 2 and 3) short. Extend GND (both inputs) and GVR_POUT_R as a pair and connect locally to graphics VR (EU3G1).

.

0.22uF

GVR_VR_EN

R2V3

R2V3 0

0

R2V6

R2V6 0

0

NO_STUFF

GVR_VR_EN

For Teenah

For Cantiga STUFF: R2V3

3

R3F5

0.002

1%

1% .

.

R3G3

R3G3 10

10

5%

5% .

.

C3G3

1.0uF

20%

20% 402

402

.

GVR_BST_R

C3G1

0.1uF

10%

.

2

+VBAT17,53,55,56,57

R3V2

R3V2 .002

.002

1%

C3V2

C3V3

C3G5

C3G5 47uF

47uF

20%

C3V8

0.01uF

10%

10% 402

402

S

.10%

D

2 531

C3V3

0.01uF

10%

402

C3G7

C3V5

47uF

20%

NO_STUFF

Q3V1

HAT2164H

NO_STUFF

R2G4 10

B320A

2 1

GAIN ADJUSTED FOR 4.02

+V3.3S

1%

NO_STUFF

R9H14

R9H14 0

0

R1J8

R1J8 0

0

.

C3V6

C3V7

4.7uF

20%

L3G1

1 2

0.88uH

R3F9

3.57K

1%

1% .

.

CR3G1

Note:Place the 0 ohm resistors close to the source and route a thick trace from source to destination

R3F8

1.78k

GND_SYS_CURRENT

GND_GVR

GFX_VR_PWRIN 41,52

AGND_VCORE

C3V9

0.01uF

10%

402

GVR_VBAT

C3V4

C3V4 47uF

47uF

20%

NO_STUFF

D

G

Q3V3

G

Q3V3 HAT2168H

HAT2168H

4

S

2 531

D

G

4

S

R2G7

C2G6

40.2K

0.1uF

1%

10%

10% .

.

R2V10

R2V10 0

0

NO_STUFF

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

Graphics Core VR

355659

A

355659

A

355659

A

G

Q3V2

4

HAT2164H

2 531

C2G3 0.1uF

R2G1

40.2K .1%

GND_GVR

4

-

U2G1A

2

1

+

3

AD8552

8

OP_GVR_POUT_R

C2G4

0.1uF

10%

10% 16V

16V .

.

GND_GVR

GND_GVR_R

Note: Extend this ground and the output as a pair to the point where the output is being delivered (A/D).

C3G4

0.22uF

C3V1

1.0uF

20%

20% 402

402

.

R2G2

R2G2 10K .1%

10K .1%

R2G6

R2G6 10K .1%

10K .1%

GND_GVR

GVR_POUT_R-

GVR_POUT_R+

2

GVR_NTC

GVR_VID0

GVR_VID1

GVR_VID2

GVR_VID4

1 2

5

6

49 58Tuesday, August 28, 2007

1

RT3F11KRT3F1

1K

1

R3G6

20K

1%

NO_STUFF

R2G19

20K

1%

NO_STUFF

R2G18

20K

1%

NO_STUFF

R2G14

20K

1%

NO_STUFF

+VCC_GFXCORE9

OP_GVR_POUT_R

8

U2G1B

+

7

-

GND_GVR

GVR_8552B_OUT

AD8552

4

Intel Confidential

1.0

5

R2W1

R2W1 0

0

.

PWR_JACK_GND

4A, 50V, DCresist=12mohm-1 line-

CR1W3

4A, 50V, DCresist=12mohm-1 line-

1 4

2 3

NO_STUFF

1 3

BAT54

CR1W4

R2G23

R2G23 0

0

.

J1G9

D D

CASE44GND1

3

CASE3

2

CASE2

1

CASE1

CNTRL_ADFC

PWR_JACK

AMPS_CONTROL44

5 6

GND2

7

PWR1

8

PWR2

9

NO_STUFF CR1W3

NO_STUFF

1 3

BAT54

C C

Battery Wakeup Threshold

WK_TH

0 V

3 V

Threshold Voltage

2.9 V/Cell

3.2 V/Cell

Number of Cells

AMPS_CELLS

AMPS_REF

LOW

Hi Z

Number of Cells

4 Cells

3 Cells

2 Cells

AGND_AMPS

1k@100MHz

L1G1

+V_JACK_PWR

.

+VAC_IN_L

R1H2

4.7K

5%

CR2W2

MMBZ5246BN

(Vzener=16V)

R2H81KR2H8

.

C1V3

C1V3 1uF

1uF

10%

10% ..

..

1K

C1W3

C1W3 22uF

22uF

20%

20% 25V

25V

.

3

1

AMPS_AD+_ZNR

1

R1W1

R1W1 10K

10K

5%

5% .

.

R2W8

R2W8 100K

100K

5%

5% .

.

Q2H1

Q2H1 2N7002

2N7002

C1W4

0.1uF

10%

10% .

.

AGND_AMPSAGND_AMPS

+VAC_IN_L 41,44

.

AMPS_AD+_R

3

2

B B

R2G24 330K

.

AMPS_LM358A_IN+

5

+

6

-

AGND_AMPS

AMPS_REF_LM358A_IN-

R2G25

R2G25 330K

330K

5%

5% .

.

AMPS_PAD_MAX

5%

C2W1 1uF

10%

AMPS_VBS_LM358

8

..

U2H1B

7

LM358

4

AMPS_PAD_MAX_LM358

AGND_AMPS

AMPS_CONT

+VBS51,56

R2V22

R2V22 0

0

.

AMPS_VBS_LM358

8

U2H1A

3

+

AMPS_LM358B_OUT

1

2

-

LM358

4

AMPS_LM358B_IN-

A A

AGND_AMPS AGND_AMPS AGND_AMPS

R2H7

4.99k_1%

R2H6

R2H6 10K

10K

1%

1% .

.

R2V17

R2V17 0

0

NO_STUFF

AMPS_REF

R2G21

R2G21 330K

330K

R2V15

23.7K

.

1%

1% .

.

R2V18

AMPS_REF_R_LM358

330K

R2V19

49.9K

5%

1%

.

5%

5

SI7483ADP

AGND_AMPS AGND_AMPS

R2V27

1 2

84.5K

1%

4

Q1H2

3 2 1

1

3

.

Q2W5

2

2N7002

4

3

2

AGND_AMPS

1

R2H11

R2H11 100K

100K

5%

5% .

.

Q2W6

Q2W6 BSS138

BSS138

BC_SHDN

5

R2H10

R2H10 100K

100K

5%

5% .

.

AMPS_AD+_Q1AMPS_AD+_Q1+V_JACK_PWR

AMPS_AD+_Q

Adapter Over Voltage Protection

R2V16

39.2K

1%

AGND_AMPS

4

Route resistor sense lines from the PADs of the resistor(R1H1)

5

R1G10

R1G10 1K

1K

5%

5% .

.

C1V2

C1V2 1uF

1uF

10%

10% NO_STUFF

NO_STUFF

AGND_AMPS

AMPS_IPROG

AMPS_VPROG

CR1W1

2 1

B320A

Q1H1

R2G22

R2G22 100K

100K

5%

BC_SHDN40

AMPS_REF

3 2 1

SI7483ADP

4

.

AMPS_COMP_R

C2G7

3.3uF

10%

AGND_AMPSAGND_AMPS

1

R2W2

R2W2 162K

162K

1%

1% .

.

R2G26

R2G26 100K

100K

1%

1% .

.

AGND_AMPS AGND_AMPS

AMPS_REF

R2H4

R2H4 232K

232K

.

. 1%

1%

R2W4

R2W4 100K

100K

1%

.

AGND_AMPS AGND_AMPS

3

+VBS51,56

POS_SENSE 51

R1G13

2.2

NO_STUFF

5%

5% .

.

C2H4 2.2uF

17

AMPS_SAMBP

15

16

20

12

24

AMPS_PAD_MAX

11

AMPS_LDO

C2H2

10

4.7uF

10%

.

AGND_AMPS

AMPS_REF

AGND_AMPS

R2V26

R2V26 0

0

NO_STUFF

BC_SHDN

1

R2H9

R2H9 1M

1M

5%

5% .

.

R1G12 0.020R1G12 0.020

10%

AMPS_SBM

EU2G1

SBM

SAMBP

SAP

PA

DCIN

CONT

3

COMP

7

CELLS

8

IBAT

1

PAD_MAX

LDO

REF

JASPERSI_0X

JASPERSI_0X R2V20

C2H1

4.7uF

10%

.

ICHRM 40

VSYS

WUPD

IPROG

VPROG

REF_EN

WK_TH

PAD

ACPRES

THRM

CP

CA

BAT

NC

AMPS_CP

14

13

18

19

21

AMPS_IPROG

6

AMPS_VPROG

2

AMPS_REF_EN

9

5

AMPS_PAD

23

AMPS_ACPRES

4

AMPS_OVP

22

25

AGND_AMPS

AMPS_VPROG : To set maximum charging voltage for

R1H1

R1H1 .007

.007

1%

1% .

.

NO_STUFF

C1W1 2.2uF

10%

AMPS_PA

AMPS_DCIN

AMPS_CONT

AMPS_COMP

AMPS_CELLS

R2G20

R2G20 0

0

.

AGND_AMPS AGND_AMPS

3

2

NO_STUFF

AGND_AMPS

C2V3

0.1uF

10%

.

Q2G2

Q2G2 2N7002

2N7002

Q2W1

2N7002

R2V25

R2V25 100K

100K

NO_STUFF

3

2

AGND_AMPS

AMPS_IBATT

C2V6

0.47uF

AMPS_IPROG : To set maximum charging current

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

System Charger AMPS

355659 1.0

A

355659 1.0

A

355659 1.0

A

C2V5

0.1uF

10%

.

R2V23

R2V23 0

0

NO_STUFF

VCHRM 40

3

2

C1W2

C1V1

22uF

20%

NO_STUFF

CR1W2

21

B320A

FDS6679AZ

3 8 2 1

R1G11

R1G11 100

100

5%

5% .

.

AMPS_CP_C

C2G9

0.47uF

10%

10% .

.

AMPS_CA

AMPS_BATT

Vcell = Vvprog/10 + 4.1 Vvprog = 1 V for 4.2V per cell

C2V4

4.7uF

20%

.

R2H18

R2H18 0

0

NO_STUFF

C2V1

C2V1 1uF

1uF

10%

10% ..

..

Q1H3

4

3

1

AGND_AMPS

AMPS_ACPRES_R

R2V21

R2G17

R2G17 0

0

.

Set to 1.25V for a Charging current of 2A

2

7 6 5

CR2V1

CR2V1 BAT54

BAT54

.

+VCHGR_OUT51

100

5%

R2G16

16.9K

1%

1% .

.

1

+VBS51,56

J2Y1

22 21

1920 1718 15

16

13

14

11

12

9

10

8

7

BC_SHDN

6

Q2V1

Q2V1 BSS138

BSS138

Q2H2

Q2H2 BSS138

BSS138

4 2

2x11-PLG

NO_STUFF

+VCHGR_OUT51

R2V20 10K

10K

.

BC_ACOK_BATT56

BC_ACOK40,43

5 3

AMPS_ACPRES

1

+VBS 51,56

+V3.3A

R2W3

R2W3 10K

10K

.

PSYS40

VCHRM40

AGND_AMPS

C2V2

0.1uF

10%

.

C2G8

C2G8 1000pF

1000pF

10%

10% .

.

+VBS51,56

R2V24

R2V24 100K

100K

5%

1

.

+V5A 24,29,34,38,44,46,47,51,56,57

R2H5

40.2K

1%

R2H1

49.9K

1%

1% .

.

AGND_AMPS

1

.

BC_ACOK#

3

Q2G1

Q2G1 BSS138

BSS138

2

1

.

3

2

3

2

PBATT 40

ICHRM 40

each cell

Intel Confidential

50 58Tuesday, August 28, 2007

1

5

4

3

2

1

System Current Sense Amp (6A Dynamic Range)

+VAC_IN_L_R

POS_SENSE50

D D

+VBS

R1Y9

80.6

1%

1% .

.

R1Y8

R1Y8 475

475

1%

1% .

.

SMBUS Address for Battery B = 1E

SMBUS Address for Battery A = 1C

SMBUS Address for LIBP = 16

C C

B B

DISB#

CHGB

A A

LIBP_BAT_SEL40,43

(Place close to the sense resistor near the brick connector)

1%

POS_SENSE_A

R2Y3 1K

R2Y6 1K

+VAC_IN_L_R

+VAC_IN_L_A

1%

.

GND_SYS_CURRENT

POS_SENSE 50

J1H1

Batt B

CON_1X7_156mil_HDR

+V3.3A

J1H2

Batt A

CON_1X7_156mil_HDR

R1W2 100KR1W2 100K

R1W4 10K

NO_STUFF

C2Y4

C2J2

0.1uF

10%

0.1uF

.

10%

10% .

.

GND_SYS_CURRENT

1

2

3

4

5

6

7

R1W11

R1W11 0

0

NO_STUFF

R1J2

R1J2 0

0

NO_STUFF

1

2

3

4

5

6

7

C2W3

0.1uF

20%

20% .

.

2 4

U2J3

1

SHDN#

GSEL

RS-2VCC

3 4

CURRENT SENSE RANGE

0 - 3A: EN_CS_GAIN_SEL = 3.3V 0-6A EN_CS_GAIN_SEL = 0V (DEFAULT)

BC_THERMB

CHGB

Battery Address Key

Address

14 16 18 1A 1C 1E 20 22

SMB_CLK_BATT_A SMB_DATA_BATT_A BC_THERMA

+V3.3A

RS+ GND

MAX4072

SMB_CLK_BATT_B SMB_DATA_BATT_B

BC_THERMB

BC_THERMA

Host Resistor

CHGA

DISA#

R2H14 10KR2H14 10K R2H12 10KR2H12 10K R2H15 10KR2H15 10K R2H16 10KR2H16 10K

SMB_BS_CLK37,40,43,52 SMB_BS_DATA37,40,43,52

5

U1H1

INVERTER

3

OUT

RFIN

DISB#

820 1800 2700 3900 4700

9100 11000

R1W10 100KR1W10 100K

R1W7 10K

LIBP_I2C_EN_NOT

5

+V5A 24,29,34,38,44,46,47,50,56,57

EC_CS_GAIN_SEL

8 7

MAX4072_OUT

6

MAX4072_REFIN

5

C1J6

0.1uF

10%

.

. 16V

16V

.

Q2J2 BSS138

3

1

GATE_CHGB

R1W3 6.81K1%R1W3 6.81K1%

C1W5 0.1uF

C1W7 0.1uF

R1J1 4.7KR1J1 4.7K

Total (Host + 200)

.

Q2J1 BSS138

3

2

1

GATE_CHGA

5%

NO_STUFF

LIBP_CL1

1

LIBP_CL2

2

LIBP_DA1

18

LIBP_DA2

19

3 4

7 11 14 17 10

C1Y5

0.1uF

10%

.

C1H1

C1H1 10UF

10UF

25V

CHGB_XOR

2

NO_STUFF

NO_STUFF NO_STUFF

NO_STUFF

1020 2000 2900 4100 4900 70006800 9300 11200

CHGA_XOR

U2H2

EXPSCL1 EXPSCL2 EXPSDA1 EXPSDA2

SCL0 SDA0

EN1 EN2 EN3 EN4 VSS

EXP. 5-CH-I2C HUB

+VREF_ADC41

R1Y7

R1Y7 22

22

5%

5% .

C1W6

C1W6 10UF

10UF

25V

.

+VCHGR_OUT50

C2Y2

C2Y2 22UF

22UF

VCC

SCL1 SDA1

SCL2 SDA2

SCL3 SDA3

SCL4 SDA4

R2J3

R2J3 20K

20K

74AHC1G86

LIBP_CHG_EN_B41

74AHC1G86

LIBP_CHG_EN_A40,43

20

5 6

8 9

12 13

15 16

4

MAX4072_OUT_RC

C2J1

C2J1 1uF

1uF

20%

20% .

.

U2J2

U2J1

SMB_CLK_BATT_B SMB_DATA_BATT_B

SMB_CLK_BATT_A SMB_DATA_BATT_A

4

+V3.3A

8

U2J4B

5

+

7

6

-

R2Y1

AD8552

4

1%

100K

.

+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,52,55,56,57

5

BS_CHGB

4

1

2

3

4

5

BS_CHGA

4

1

2

3

4

+V3.3A

C2H5

0.1uF

20%

.

LIBP_CHG_EN_B LIBP_CHG_EN_A LIBP_BAT_SEL SMB_CLK_BATT_B SMB_DATA_BATT_B SMB_CLK_BATT_A SMB_DATA_BATT_A

5

3

53

5

3

53

GATE_CHGB

NO_STUFF

EC_BRK_CURRENT 40

GND_SYS_CURRENT

U1Y2

1

2

74AHC1G02

U1Y1

1

2

74AHC1G08

.

U1J1

1

2

74AHC1G02

U1J2

1

2

74AHC1G08

.

C8H1

R8H2

0.1uF

1M

20%

.

R8V11 100KR8V11 100K R2J1 100KR2J1 100K R2W11 10KR2W11 10K

R1W6 4.7KR1W6 4.7K

R1W5 4.7KR1W5 4.7K

R1W9 4.7KR1W9 4.7K

R1W8 4.7KR1W8 4.7K

3

GND_SYS_CURRENT

R2J2

R2J2 0

0

.

R1J3 100KR1J3 100K

R1J5 100KR1J5 100K

R8V12

R8V12 10K

10K

Q8H1

3

BSS138

.

1

2

+V3.3A

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,52,55,56,57

R1J9

10K

R1J4

R1J4 10K

10K

.

R1Y1

R1Y1 10K

10K

.

+V3.3A+V3.3A

NO_STUFF

EC_CS_GAIN_SEL

R2J4

R2J4 10K

10K

.

*

BS_CHGB# 40,43

BS_DISB# 40,43

BS_CHGA# 40,43

BS_DISA# 40,43

R8H3

R8H3 10K

10K

H8 ADC Reference

(Place very close to the EC)

CAD Note:

*

System current groud trace needs to be 20 mil or larger going from the brick to the EC and MAX4072 current sense amp.

3.0V Precision ADC Reference circuit

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,52,55,56,57

C1Y4

0.1uF

10%

.

. 16V

16V

FLIPFLOP_Q

FLIPFLOP_Q#

+V3.3A +V3.3A

GATE_CHGA

C8G4

0.1uF

20%

NO_STUFF

CHGB_EN# 41

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

3

R8G7

R8G7 1M

1M

.

2

System Charger Battery

355659 1.0

+V5A 24,29,34,38,44,46,47,50,56,57

R9H10

R9H10 475

475

1%

1% .

.

1

LM4040

LM4040 U9H1

U9H1

2

GND_SYS_CURRENT

C1J3

C1Y2

0.1uF

10%

.

16V

R1Y3

R1Y3 1K

1K

5%

PRE_L

U1J3

8 7 6 5

1G D-FLIP FLOP

R8G8

R8G8 10K

10K

Q8G2

Q8G2 BSS138

BSS138

.

1

VCC PRE# CLR# Q

5%

1

CLK

2

D

3

Q#

4

GND

BS_CLR_LTCH# 40,43

R8G10

R8G10 10K

10K

2

3.3V ADC reference

The precision ADC and and 3.3 ADC reference optons are mutually exclusive. DO NOT STUFF BOTH AT THE SAME TIME OR THE PRECISION REFERNCE COULD BE DAMAGED.

C1W9

0.1uF

10%

.

. 16V

16V

C1Y7

0.1uF

10%

.

. 16V

16V

SMB_BS_ALRT#40,43

VBS_TRIP

MAX809 Trip Point = 2.93V VBS Trip Point = 6.0V

U1J4

VBS_TRIP#

CHGA_EN# 41

2

RST#

MAX809

3

VCC

GND

1

C1Y6

0.1uF

10%

.

. 16V

16V

VBS_DIV

+V3.3A

+VBS50,56

R1Y6

12.4K

1%

1% .

.

R9H9

R9H9 0

0

NO_STUFF

R1Y4

R1Y4 13K

13K

1%

LIBP_CHG_EN_A40,43

R1Y2

R1Y2 10K

10K

5%

5% .

.

3

Q1Y1

Q1Y1 BSS138

BSS138

1

.

2

C1W8

C1Y3

0.1uF

47uF

.

3

C1Y8

0.1uF

10%

.

. 16V

16V

1

LIBP_CHG_EN_B41

Intel Confidential

51 58Tuesday, August 28, 2007

1

+VREF_ADC41

C9H4

C9H4 22UF

22UF

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,52,55,56,57

3

2

C2W5

C2W5 47uF

47uF

.

BZX84C2V4LT1

CR1J1

.

R1Y5

R1Y5 10K

10K

5%

5% .

.

C1J2

C1J2 22uF

22uF

25V

25V .

.

R2Y2

R2Y2 10K

10K

C9W3

0.1uF

10%

10% .

.

Q1J2

Q1J2 BSS138

BSS138

1

.

VBS_TRIP#

25V

C1Y1

C1Y1 10UF

10UF

R8G9

R8G9 10K

10K

5

+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,55,56,57

R1N42

R1N42 10K

10K

5%

5% .

.

U1N1

37,40,43,51

SMB_BS_DATA

SMB_BS_CLK

37,40,43,51

D D

.

CPU_VCC_R

6262_PMON

C C

B B

AGND_VCORE

6262_PMON

A A

VCCSENSE

VSSSENSE

NO_STUFF 1%

AGND_VCORE

6262_PMONITOR

R2N19

R2N19 0

0

R1N25

100

.

R2N18

R2N18 0

0

NO_STUFF

Layout Note: Use

27.4 Ohm routing for Vssense and Vccsense

R1N30

R1N30 10K

10K

5%

AD7417_A0

AD7417_A1

AD7417_A2

R1N31

R1N31 10K

10K

5%

5% NO_STUFF

NO_STUFF

AGND_VCORE AGND_VCORE AGND_VCORE

Power Monitoring VCORE Signal

0.1uF

0.1uF C2B16

C2B16

R2B22

49.9K. 1%

NO_STUFF

SPR_GT_5

R2N12 49.9K

1%

R2N13 49.9K

R2B17

49.9K

AGND_VCORE

1%

10%

NO_STUFF

SPR_GT_6

.1%

1 2 3

U1N1_TP

4 5 6

CPU_ICC_R

7 8

6262_PIN

GFX_VR_PWRIN41,49

C1B3

.10%

0.1uF

AGND_VCORE

VCCSENSE4

VSSSENSE4

+V3.3A

R1N34

10K

5%

.

NO_STUFF

R1N35

R1N35 10K

10K

5%

5% .

.

IMVP6_STRAP_VID0

IMVP6_STRAP_VID1 IMVP6_STRAP_VID2 IMVP6_STRAP_VID3 IMVP6_STRAP_VID4 IMVP6_STRAP_VID5 IMVP6_STRAP_VID6

1%

75K

75K R2N9

R2N9

5

+

6

-

AGND_VCORE

R2N16 75K

5

NC1

AD7417

SDA SCL OTI REF_IN GND A_IN1 A_IN2

SMBUS address: 100

AGND_VCORE

R1N46

10K

5%

NO_STUFF

Load Line: -2.1mOhmLL(default) To enable -5.1mOhm LL stuff: R2B16 ,Q2B2, Q2B1, R3B13, J3B1

R1N40

unstuff: R2B11

10K

5%

5% .

.

V3_3_S0

OP_CPU_ICC_R

8

U2B1B

CPU_VCC

7

AD8552

4

1%

+V3.3A

R1N45

R1N45 10K

10K

5%

5% .

.

16

NC2

CONVST#

VDD

A_IN4 A_IN3

100

R1N27

1% R1N27

1%

NO_STUFF

C2N8

C2N8 330pF

330pF

C2N10

0.01uF

10%

.402

J3B1 (1-X): -2.1mOhmLL (DEFAULT)

J3B1 (1-2): -5.1mOhmLL

R1N7

15 14 13

A0

12

A1

11

A2

10

GFX_VR_PWRIN_R

9

.

AGND_VCORE

PSI#3

NO_STUFF

R2N23

27.4

NO_STUFF

+V3.3S

8.2K

C1N4

0.1uF

10%

10% .

.

C2N9

C2N9 330pF

330pF

J1E1

R1N19

8.2K

CONVST#

AD7417_A0 AD7417_A1 AD7417_A2

AGND_VCORE

0

12

NO_STUFF

R1N14

8.2K

15

8

101214

16

V3_3_S0

R1B3

1%

NO_STUFF

100

AGND_VCORE

C1B2

0.1uF

10%

10% .

.

CPU_VCC_R

4

Place RT2C2 thermistor between the inductor L2C1 and one of the bottom switches Q2C2, Q2C3, Q2C4, Q2C6

+V3.3A

C1N7

C1N6

10uF

0.1uF

20%

10%

.

AGND_VCORE AGND_VCORE

R1N39

R1N39 10K

10K

5%

NO_STUFF

R2N26

PM_DPRSLPVR7,23,43

5%

.

R2N22

R2N22 475

475

1%

100pF

.

C2B3

R2N24

27.4

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,55,56,57

R1N11

8.2K

135791113

J2B2.J2B2

246

10%

0.1uF

NO_STUFF

6262_FB_RC

R1N9

R1N5

R1N1

R1N3

8.2K

H_VID04

.

H_VID14 H_VID24 H_VID34 H_VID44 H_VID54 H_VID64

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,55,56,57

R1B2

S2_S1

10K.1%

SPR_GT_6

C2B15

CPU_VCC 41

4

100K

1 2

R2N11

R2N11 0

0

5%

5% .

.

1%

R2N17 499

Place R2N22 near Controller

6262_FB

C3B10

C3B10 56pF

56pF

5%

.

6262_COMP

R3N25 392K

6262_DFB_EX

R2N10

90.9K 1%

C2N7

C2N7 330pF

330pF

+V527,32,42,43,48,55,56,57

R3B13

1K

1%

NO_STUFF

DLL_FET

J3B1

NO_STUFF

1 2

U1B2

2

A0

5

A1

8

A2

11

A3

13

A4

16

A5

18

A6

21

A7

23

A8

3

B0

6

B1

9

B2

12

B3

14

B4

17

B5

19

B6

22

B7

24

B8

1

S0

48

S1 S247GND1

34

GND5

39

GND6

42

GND7

74CBT16209A

3

CPU VCC_Core VR and MUX Buffer

NO_STUFF

R2B10

RT2C2

470K

AGND_VCORE

PM_DPRSLPVR_IMVP6

.

C2B10

560pF

6262_FB

1%

R2B19

.

. NO_STUFF

NO_STUFF

C0 C1 C2 C3 C4 C5 C6 C7 C8

D0 D1 D2 D3 D4 D5 D6 D7 D8

VCC

GND0

GND2 GND3 GND4

Connect from ICH & daisy chain through CPU - Do not 'T'

6262_NTC_MID

R2B7 4.02K

1%

H_PROCHOT#3

10%

VR_PWRGD_CLKEN#23

DELAY_VR_PWRGOOD7,23

6262_FB_C

226 1%

R2B18

R3B25 1.87kR3B25 1.87k

.

1%

6.49K

6.49K R2B13

R2B13

6262_DFB

R2B6

R2B6 0

0

NO_STUFF

1%

6262_SOFT

PSI#_R

C2B9

C2B9 1000pF

1000pF

10%

10% .

.

5%

C2B8 0.015uF

6262_COMP_RC

0

R2B11

13K

1%

1

46 44 41 38 36 33 31 28 26

45 43 40 37 35 32 30 27 25

7 4 10 15 20 29

VR_VID0 39 VR_VID1 39 VR_VID2 39 VR_VID3 39 VR_VID4 39 VR_VID5 39 VR_VID6 39

+V5S5,11,12,16,17,18,24,28,30,31,32,39,48,49,55,56,57

C1N3

C1N3 .01uF

.01uF

20%

20% .

.

R2B15 147K

.

C2B6

.

0.01uF

AGND_VCORE

VR_VID039 VR_VID139 VR_VID239 VR_VID339 VR_VID439 VR_VID539 VR_VID639

3,7,21,43

H_DPRSTP#

IMVP_VR_ON40,43

R2B21

6262_FB_R

R2B20

R2B20 0

0

5%

5% .

.

C3B11

R2B16

R2B9

154K

0

1%

NO_STUFF

6262_DFB_Q

2

3

6262_FET

NO_STUFF

3

NO_STUFF

2

Input

A B

B

3

1%

10%

.

6262_VDIFF

1%

.

6262_COMP_R

R3B24 1K

100pF

NO_STUFF

Q2B2

Q2B2 BSS138

BSS138

Q2B1

Q2B1 BSS138

BSS138

Output

6262_RBIAS

R2N21

R2N21 0

0

.

100

1%

R2B12

1.07k

C C

D

6262_NTC

VT_TT#_R

6262_PMON

6262_FB2

.

C2B7

C2B7 180pF

180pF

5%

5% .

.

AGND_VCORE

S1

S2

1 1 1DA1

+V5S_IMVP6

C3P1 1.0uF

AGND_VCORE

6262_VW

NO_STUFF

C2N6 0.1uF

C3B13

0.1uF

10%

.

AGND_VCORE

R2N5

7.5K

1%

1% .

.

6262_VO_R

C2N4

0.1uF

10%

10% NO_STUFF

NO_STUFF

6262_DROOP

S0

1

0

1

1 1 1 01

1%

1% R2B14

R2N20 10

10%

.

+V3.3S

C2B11 1.0uF

10%

.

CPU Core VR Controller

0

NO_STUFF

R3B22

R2B5

1.07k

6262_DFB_NS

10%

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

6262_VDD

6262_DROOP

6262_OCSET

R2N3 7.5K

1%

R2B3 15K

1%

.

. .

.

AGND_VCORE

IMVP-6 Controller

355659

C2P1

C2P1 1uF

1uF

10%

.

C2B4

0.1uF

10%

10% NO_STUFF

NO_STUFF

6262_VO_RR

6262_DROOP_R

R2N7

R2N7 402K

402K

1%

1% .

.

2

+VDC_PHASE53

+V5S_IMVP6

C2P2

C2P2 1uF

1uF

10%

.

6262_VIN

6262_BOOT1 6262_BOOT1_R

R2N8

R2N8 11K

11K

1%

1% .

.

2

3

C2N5

0.1uF

10%

10% 16V

16V

NO_STUFF

2

R2B14 10

10

1%

6262_UGATE1 53

6262_LGATE1 53

ISEN1 53

6262_UGATE2 53

6262_BOOT2 6262_BOOT2_R

6262_LGATE2 53

ISEN2 53

AGND_VCORE

Put the thermistor RT2C1 as physically close to the inductor L2C1 as possible

R3B27

2.74K

1%

1% .

.

12

R3B26

R3B26 0

0

NO_STUFF

R2B2

R2B2 402K

402K

1%

1% .

.

4

-

U2B1A

1

+

AD8552

8

OP_CPU_ICC_R

C2B5

0.1uF

10%

.

. 16V

16V

AGND_VCORE

Connect Vdd and PVCC to V5S_IMVP6 separately

C2N11

0.1uF

10%

10% .

.

AGND_VCORE

R2C5

R2C5 0

0

.

R2P3

R2P3 0

0

.

Connect PGND2 directly to the sources of the lower FETs of phase 2, Q2C6 and Q2C3

6262_VSUM_R

RT2C1

RT2C1 10K

10K

AGND_VCORE

GAIN ADJUSTED FOR 27

NO_STUFF

R2B8 10

C3B12

C3B12 1uF

1uF

20%

1%

1

+V1.05S_CPU3,4,20,35,39,43,54

H_PROCHOT#

PSI#_R

+V5S5,11,12,16,17,18,24,28,30,31,32,39,48,49,55,56,57

R1B1

1%R1B1

1%

.002

C2C4

0.22uF

10%

10% .

.

6262_PHASE1 53

C2P3

0.22uF

10%

10% .

.

6262_PHASE2 53

CPU_ICC

+V5 27,32,42,43,48,55,56,57

.002

Connect PGND1 directly to the sources of the lower FETs of phase 1, Q2C2 and Q2C4.

R3B28

R3B28 11K

11K

1%

1% .

.

C2B12

0.1uF

C2B13

10%

0.22uF

10%

10% .

NO_STUFF

100.1%

52 58Tuesday, August 28, 2007

.

CPU_ICC 41

R1B4

AGND_VCORE

Intel Confidential

1

R2B23

R2B23 68

68

5%

5% .

.

+V5S_IMVP6

VSUM 53

VCC_PRM 53

CPU_ICC_R

C1B4

0.1uF

10%

10% .

.

1.0

R2N25

R2N25 10K

10K

5%

NO_STUFF

5

D D

6262_UGATE1

6262_PHASE152

6262_LGATE1

C C

Use a large pad for this voltage.

C3C8

0.01uF

10%

.402

.402 25V

25V

B B

6262_UGATE2

6262_PHASE252

6262_LGATE2

A A

C3C9

0.01uF

10%

10% .402

.402 25V

25V

5

C3C12

0.01uF

10%

10% .402

.402 25V

25V

Use a large pad for this voltage.

+VDC_PHASE52

Phase2

Phase1

C3C3

0.01uF

10%

10% .402

.402 25V

25V

Q2C6

C3C2

C3C2 10UF

10UF

G

4

HAT2164H

G

4

G

4

S

4

S

2 531

G

D

2 531

S

C3C10

C3C10 10UF

10UF

D

2 531

4

Q2C1

Q2C1 HAT2168H

HAT2168H

D

Q2C2

Q2C2 HAT2164H

HAT2164H

2 531

NO_STUFF

Q3C1

Q3C1 HAT2168H

HAT2168H

HAT2164H

4

C3P3

C3P3 47uF

47uF

20%

20% 16V

16V

G

4

VCC_PRM52

Q2C3

S

VSUM52 ISEN2

4

NO_STUFF

G

4

C3C1

C3C1 47uF

47uF

20%

20% 16V

16V

NO_STUFF

+VDC_PHASE52

G

4

S

D

2 531

G

S

+VDC_PHASE52

D

2 531

S

D

2 531

B320A

D

2 531

Q2C4

Q2C4 HAT2164H

HAT2164H

C3C11

10UF

Q3C2

Q3C2 HAT2168H

HAT2168H

NO_STUFF

CR2P1

2 1

R1P5

C2C10

0.01uF

10%

.402

.402 25V

25V

Q2C5

Q2C5 HAT2168H

HAT2168H

R2P1

3.32k

1%

.002

CR2P2

B320A

2 1

C3P2

10UF

1%R1P5

1%

C2C13

0.01uF

10%

.402

.402 25V

25V

Connect at the same point.

C3C6

10UF

Connect at the

R2C4

same point.

11K

1%

1% .

.

C2C1 0.1uF

C2B14 0.1uF

3

+VBAT 17,49,55,56,57

C2C9

0.01uF

.402

.402 25V

25V

10%

C2C5

0.01uF

10%

.402

.402 25V

25V

R2P2

3.32k

1%

The jumper and sense resistor for this side of the inductor must be in the same layout fashion as the ones for the other side of the inductor.

1 2

10%

Place near Controller

10%

3

C2C8

C2C8 10UF

10UF

R2C6

R2C6 11K

11K

1%

1% .

.

C2C6 0.1uF

C2C3 0.1uF

10%

C2C7

C2C7 10UF

10UF

10%

C2C12

C2C12 47uF

47uF

20%

20% 16V

16V

NO_STUFF

2

NO_STUFF

C2P5

C2P5 47uF

47uF

20%

20% 16V

16V

R2C3

1.00

1%

1% .

.

C2C11

C2C11 10UF

10UF

R2C7

R2C7 11K

11K

1%

1% NO_STUFF

NO_STUFF

ISEN2

Place near Controller

VCC_PRM 52

C2C2

C2C2 10UF

10UF

C2P4

C2P4 10UF

10UF

+VCC_CORE4,54,55

1

LAYOUT NOTES:

Place R2P2 & R2C6 right next to each other. Route a single trace from the input pad of the inductor and T at the resistors. --> Do not use plane flood. This applies for R2P1 & R2C4

ISEN1

VSUM 52

as well.

Place CR2P2 near Q2C2, Q2C4 and Q2C1 . Route sharing the ground and switch nodes with low side FETs. This

J3C3.J3C3

applies for CR2P1 and Q2C3, Q2C6 and Q3C1as well.

12

.

Place the 0402 caps near the drain of the high side FETs for each

J2C1.J2C1

L2C1

*

ISEN1

1

3

.

R2D2

0.002NO_STUFF

R2C2 11K

NO_STUFF

R2C1

1.00

1%

.

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

2

4

Coupled_Inductor 310nH

1%

IMVP-6 Drivers and FET

2

R2D1

0.002NO_STUFF

The jumper and sense resistor for this side of the inductor must be in the same layout fashion as the ones for the other side of the inductor.

phase.

53 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

5

4

3

2

1

Vccp Core Decoupling

+V1.05S_CPU3,4,20,35,39,43,52

Place these inside socket

C3T7

0.1uF

10%

.

C2T25

0.1uF

10%

.

C2T1

0.1uF

10%

.

0.1uF

10%

.

C2T26

0.1uF

10%

.

C2U1

C2T1

D D

cavity on L8 ( North side

C2T2

Secondary)

0.1uF

10%

.

Vcc Core Decoupling

C2T3

C2T23

22uF

20%

.

C2T24

C2T21

22uF

20%

.

C3T6

C2T22

330uF

10%

NO_STUFF

C2T20

C2T20 22uF

22uF

20%

.

C2T19

C2T19 22uF

22uF

20%

.

C3T1

C3T1 330uF

330uF

10%

C2T18

C2T18 22uF

22uF

20%

.

C2T11

C2T11 22uF

22uF

20%

.

C2T15

C2T15 22uF

22uF

20%

.

C2T8

C2T8 22uF

22uF

20%

.

C2T9

C2T9 22uF

22uF

20%

.

C2T6

C2T6 22uF

22uF

20%

.

C2T13

C2T13 22uF

22uF

20%

.

C2T4

C2T4 22uF

22uF

20%

.

Place these inside socket cavity on L8 ( North side Secondary)

Place these inside socket cavity on L8 ( South side Secondary)

+VCC_CORE4,53,55

C2T7

C2T7 22uF

22uF

20%

.

C2T16

C2T16 22uF

22uF

20%

.

C2T5

C2T5 330uF

330uF

10%

.

C C

C3T3

C2T14

C2T12

Place these outside socket cavity on L8 ( North side Secondary)

Place these outside socket cavity on L8 ( South side Secondary)

Place these inside socket cavity on L8 ( North side Primary)

B B

Place these inside socket cavity on L8 ( South side Primary)

22uF

20%

C2T12 22uF

22uF

20%

.

C3T5

C2T17

22uF

20%

.

C2E1

C2E3

22uF

20%

.

C2E8

C2E5

22uF

20%

.

C3T4

C3T4 22uF

22uF

20%

C2T10

C2T10 22uF

22uF

20%

C2E7

C2E7 22uF

22uF

20%

.

C2E9

C2E9 22uF

22uF

20%

.

C3T3 22uF

22uF

20%

C2E6

C2E6 22uF

22uF

20%

.

C2E12

C2E12 22uF

22uF

20%

.

C3T2

C3T2 22uF

22uF

20%

.

C2E10

C2E10 22uF

22uF

20%

.

C2E4

C2E4 22uF

22uF

20%

.

C2E11

C2E11 22uF

22uF

20%

.

C2E2

C2E2 22uF

22uF

20%

.

A A

5

4

3

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

CPU Decoupling

355659 1.0

A

355659 1.0

A

355659 1.0

A

2

54 58Tuesday, August 28, 2007

1

Intel Confidential

5

4

3

SLP_S3# DISCHARGE CKT DESIGNED FOR ~100ms DISCHARGE ON ALL S3 RAILS.

2

SLP_S4# DISCHARGE CKT DESIGNED FOR ~100ms DISCHARGE ON ALL S4 RAILS.

1

+V12S25,26,30,31,32,43,57

12

R7B1

R7B1 180

180

PP_V12SDIS

3

Q7B1

Q7B1 BSS138

BSS138

1

.

2

+V5S5,11,12,16,17,18,24,28,30,31,32,39,48,49,52,56,57

R4W14

97.6

.

PP_V5SDIS

3

Q4W1

Q4W1 BSS138

BSS138

1

.

2

+V1.5S4,10,11,24,28,47,57

R4V647R4V6 47

PP_V1.5SDIS

3

Q4V1

Q4V1 BSS138

BSS138

1

.

2

R4V11

R4V11 10K

10K

.

PM_SLP_M#23,40,43,44,47,57

C3P5

C3P5 22UF

22UF

3

Q3R1

Q3R1 BSS138

BSS138

.

2

R3D3

R3D3 470

470

5%

5% .

.

PM_SLP_S3_BUF_R

3

Q4D1

Q4D1 BSS138

BSS138

.

2

R4R847R4R8 47

PP_VIMVPDIS

3

Q3R4

Q3R4 BSS138

BSS138

.

2

+VBAT17,49,53,56,57

1

CR3R1

CR3R1 BAT54

BAT54

3

VBATA_DISCHARGE

R3R6

R3R6 100K

100K

PM_SLP_S3

R3R51MR3R5 1M

D D

PM_SLP_S3#11,23,40,43,44,46,47,49,57

1

C C

+V1.05S4,9,10,24,47

+V3.3A

R4D3

R4D3 100K

100K

PM_SLP_S3_BUF

3

Q3R5

Q3R5 BSS138

BSS138

PM_SLP_S3#11,23,40,43,44,46,47,49,57

B B

1

.

2

1

+VCC_CORE4,53,54

1

ATX Mounting Holes

+V3.3S5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,56,57

R4W15

97.6

.

PP_V3SDIS

3

Q4H3

Q4H3 BSS138

BSS138

1

.

2

R5W1

97.6

.

PP_V5DIS

3

Q5V2

R3R1

R3R1 100K

100K

+VBATS16,19,27,30,31,57

12

R5H5

R5H5 180

180

PP_12DIS

3

Q5H1

Q5H1 BSS138

BSS138

1

.

2

PM_S4_STATE#23,32,40,43,44,57

+V3.3S_TVDAC10,11,48

R3R12

4.87K

1%

1% .

.

PP_V3STVDIS

3

Q3R3

Q3R3 BSS138

BSS138

1

.

2

3

Q4G3

Q4G3 BSS138

BSS138

1

.

2

PM_SLP_M

R4V91MR4V9 1M

1

PP_S4GT

R5V101MR5V10 1M

R4V14

R4V14 100K

100K

3

Q3R2

Q3R2 BSS138

BSS138

.

2

PM_SLP_S4#23,46

+V1.05M9,10,15,35,47 +V3.3M13,14,15,23,35,57

R4V13

R4V13 470

470

5%

5% .

.

PP_V105M_DIS

3

Q4G5

Q4G5 BSS138

BSS138

1

.

2

1

DDR_DIS

3

Q4G6

Q4G6 BSS138

BSS138

.

2

+V3.3M_WOL22,24,33,34,44,48,57

1

PP_V33M_DIS

R4G5

R4G5 100K

100K

5%

R4V12

97.6

.

PP_V3MDIS

3

2

1

Q4G4

Q4G4 BSS138

BSS138

.

1

Q5V2 BSS138

BSS138

.

2

+V0.915,46

PP_V0.9DIS

3

1

2

3

2

LAN_WOL_EN 23,40,43,57

R4B9

220

Q4G2

Q4G2 BSS138

BSS138

.

Q4B2

Q4B2 BSS138

BSS138

.

+V3.319,27,32,39,41,42,43,57

R5V11

97.6

.

PP_V3DIS

3

Q5G3

Q5G3 BSS138

BSS138

1

.

2

+VBAT_S419,57+V5 27,32,42,43,48,52,56,57

12

R6N5

R6N5 180

180

PP_BATS4DIS

3

Q6N2

Q6N2 BSS138

BSS138

1

.

2

+V1.89,10,13,14,46,48,57

R5B3

R5B3 68

68

5%

5% .

.

PP_V1.8DIS

3

Q5N1

Q5N1 BSS138

BSS138

1

.

2

R4H1

R4H1 470

470

5%

5% .

.

PP_V33MCKDIS

3

Q4H1

Q4H1 BSS138

BSS138

1

.

2

A A

MT1B1

236

4 5

MT156

236

7

4

8

5

9

NO_STUFF

MT1J1

7 8 9

MT156

NO_STUFF

MT1F1

236

4 5

MT156

7 8 9

NO_STUFF

MT5A1

236

4 5

MT156

7 8 9

NO_STUFF

MT9A1

236

4 5

MT156

7 8 9

NO_STUFF

MT9F1

236

4 5

MT156

7 8 9

NO_STUFF

MT9J1

236

4 5

MT156

5

7 8 9

NO_STUFF

MT5J1

236

4 5

MT156

7 8 9

NO_STUFF

4

Intel Confidential

55 58Tuesday, August 28, 2007

1

Intel Confidential

1.0

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

3

Date: Sheet of

DISCHARGE CIRCUITS

355659

A

355659

A

355659

A

2

+V5A_MBL45

+V5SB_ATXA

D D

+V3.3A_MBL

Q4G7

IRF7822

2 1

4

R4V7

R4V7 0

0

.

+VBATA26,45,46,47,57

R4V8

R4V8 1K

1K

5%

.

783 6 5

C C

MOBILE OPTION

PS_LATCH#

1

CR4W2

CR4W2 BAT54A

BAT54A

PS_ON_SW#

3

2

+V3.3A

B B

ME_G3_TO_M1#40

+V5SB_ATX

R5H9

R5H9 10K

10K

5%

A A

5% .

.

+V5_DL_Q

5V MIN CURRENT DUMMY LOAD: Gives

0.5A min current load

Q4J1

BSS138

3

.

2

1

3

SI4965DY

Q3H6A

8

7

2

6

5

4

R3W21 100KR3W21 100K

ATXPWR

BC_ACOK_BATT

Active High: When AC brick present charger starts and asserts this signal, which starts the on board always rails by forcing the assertion on VR_ALW_ENABLE assuming ATX_PWR_CNTRL is asserted. Ignored by H8 in ATX mode.

Jumper J4H1

Open (Default) No After_G3 support 1-2 After G3 support with ATX supply 2-3 After G3 Support with AC brick

PS_ON#

PS_ON# internally pulled up to 5V standby in all ATX supply per ATX 12V spec.

+V5SB_ATX

R4H3

R4H3 220K

220K

5%

5% .

.

5V_DL

652

4

+V3.3A

+

C4H4

+

C4H4 220uF

220uF

10%

10% .

.

+V5A

321

CON3_HDR

ME_G3_TO_M1

1

R4H5

R4H5 390K

390K

R5J1 3.0

Q5Y1

SI3442BDV

J4H1

1

BC_ACOK_BATT50

.

1

3

Q3H6B

Q3H6B SI4965DY

SI4965DY

3

2

+

C4H2

+

C4H2 220uF

220uF

10%

10% .

.

ATX ALWAYS ON DT OPTION

3

Q4H10

Q4H10 BSS138

BSS138

.

2

5%

+V5A24,29,34,38,44,46,47,50,51,57

Q4G1

Q4G1 BSS138

BSS138

.

R4W21

1 2

0

NO_STUFF

PS_ON#

R4W19

R4W19 1K

1K

NO_STUFF

NO_STUFF 5%

5%

5V_DL_R

R5W20

3.0

5%

5% .

.

+V5_ATX

PS_ATXSENS

12

+

C5H2

C5H2 220uF

220uF

10%

10% .

.

+V3.3_ATX

R5H7

3.0

5%

5% .

.

C4V3

0.1uF

10%

10% .

.

R2W9

R2W9 100K

100K

NO_STUFF

SHUTDWN#

Active High: Goes high on pwr button press turing on the on board always rails in battery mode. Forces VR_ALW_ENABLE high when ATX_PWR_CNTRL is high (in mobile mode). Also allows H8 to shut the board down via SMC_SHUTDOWN when R3W17 is stuffed.

+V5SB_ATXA

12

+

C4H5

C4H5 220uF

220uF

10%

10% .

.

1

R2W7

R2W7 0

0

.

R4Y1 0.002

+V3.3_ATX +V3.3_ATX

R5H6

R5H6 10K

10K

5%

+V3.3_DL_Q

.

5

4

+V5_ATX

R4J1

1 2

0

NO_STUFF

R3V3

R3V3 10K

10K

5%

5% .

.

V12ATXSW

3

Q3G1

Q3G1 BSS138

BSS138

ATX_PWR_CNTRL

Battery Mode: ATX_PWR_CNTRL = VBATA

.

2

ADAPT_PRES_R

SHUTDWN#

.

3

Brick Mode: ATX_PWR_CNTRL = VBATA ATX Mode: ATX_PWR_CNTRL=0V

VR_ALW_ENABLE

Active High: SHUTDWN#||BC_ACOK_BATT)&ATX_PWR_CNTRL

Enables on board Always VRs (5MBL,

3.3MBL, and 1.5A) when running off AC brick or battery. Low in ATX

2

CR2W1

CR2W1 BAT54C

BAT54C

3

1

1 2 3 4 5 6 7 8 9

10

Q4H9

SI3442BDV

1 2 3 4 5 6 7 8 9 10

mode.

PS_ACENABLE

NO_STUFF

Stuff R3W17 only for G3 Mobile power cycling

R4H4 3.0

R3W5

R3W5 100K

100K

-V12A57-V12_ATX

1%

ATX POWER

J4J1

11

12

13

14

15

16

17

18

19

20

CON20_PWR

+V3.3_DL_QR 3.3V_DL_R

652

1

4

VBSGT

3

R3W17

R3W17 0

0

5%

.

+VBS50,51

ATX_PWR_CNTRL 57

Q3W2

Q3W2 BSS138

BSS138

2

.

1

+V5_ATX

R4W20

3.0

5%

5% .

.

Q1J1

SI7483ADP

5

4

VR_ALW_ENABLE 28,45

+V12_ATX

ATX_PWROK 41

3V MIN CURRENT DUMMY LOAD: Gives 0.5A min current load

3 2 1

POWER ON and S5 ENTER/EXIT Button

ND_SW#41

+VBATA26,45,46,47,57

R4Y2

0.002

1%

1% .

.

3

1

R1J7

R1J7 100K

100K

4

2

3

SW1C1

SW1C1 Push_Button

Push_Button

Net Detect Button

+V5SB_ATX

3

+

C1J5

C1J1

0.1uF

15uF

10%

20%

.

PS_ON_SW# 44

1

R5H8 0.002

3

4

1

2

1%

.

2

+VBATA26,45,46,47,57 +VBAT17,49,53,55,57

R2W5

R2W5 100K

100K

PS_PWRBTN

1

3

Q2W2

Q2W2 BSS138

BSS138

.

2

CR8E1

BAT54

SW8E1

SW8E1 Push_Button

Push_Button

+V5SB_ATXA

R9H22

R9H22 10K

10K

5%

5% .

.

1

5SB_ATXA_R

R9H21

R9H21 10K

10K

5%

5% .

.

R2H171MR2H17 1M

13

RESET BUTTON

+V3.3A

3

2

BSS138

5%

3

2

CR2W3

BAT54

BAT54 CR3V1

CR3V1

BAT54

R2W6

R2W6 100K

100K

Q2W4

Q2W4 BSS138

BSS138

.

Q8E4

R9H19

R9H19 10K

10K

.

Q9H5

Q9H5 BSS138

BSS138

.

R1J6

C1J4

390K

0.33uF

80%

.

PWRONLATCHG

13

SMC_ONOFF# 40,43

R8E4

R8E4 100K

100K

Button Latch

NETDETECT_12V#

3

1

.

2

C8E2

C8E2 1000PF

1000PF

10%

SW1C2

1

3

2

4

Push_Button

Shunt pins 13 & 15 for SV forcing ATX on and VBAT on for power cycling

ATX_DETECT#

Acitve Low: Indicates system is powered by ATX supply to H8: Note H8 looks at this signal before BC_ACOK#.

3.3V=Mobile Mode (BATT or Brick) 0V=ATX mode powerd by ATX supply

ATX_DETECT# 40,43

Pillar Rock

Title

Size Document Number Rev

A

Date: Sheet of

FDS6679AZ

3 8 2 1

PS_LATCH#

+V3.3A

+VBATA26,45,46,47,57

Net Detect

R8E1

R8E1 43K

43K

NO_STUFF

.

RSTBTNDB 44

SATA_LED#21

Start Up Sequence

355659 1.0

Tuesday, August 28, 2007

Q2W8

4

R2H13

R2H13 100K

100K

R2G27

3.3K.5%

Force Shutdown

SMC_SHUTDOWN40,43

3

1

2

CR6W1

CR6W1 BAT54

BAT54

7 6 5

R8E2

R8E2 100K

100K

1

3

C7H4

C7H4 470pF

470pF

5%

5% .

.

2

J3J2J3J2

12

SMC_SHUTDOWN_R

132

NETDETECT_12V

Q8E3

Q8E3 BSS138

BSS138

1

.

R5W12

R5W12 10K

10K

.

+V5S5,11,12,16,17,18,24,28,30,31,32,39,48,49,52,55,57

R7H17

R7H17 330

330

.

FRONT1

RST_PUSH#_D

PS_LATCH#

C7H8

C7H8 470pF

470pF

5%

5% .

.

+

C5B2

C5B2 15uF

15uF

20%

20% .

.

12

CR2W4

CR2W4 BAR43S

BAR43S

3

Q8E1

BSS138

2

+V3.3S

U5H2

1

GND

2

IN

MAX6816

XDP_DBRESET#_R

+V5 27,32,42,43,48,52,55,57

C6H4

C6H4 470pF

470pF

5%

5% .

.

+

C2W2

C2W4

15uF

20%

.

Q2W3

BSS138

.

3

J2G1J2G1

.

AC_PRESENT 23,40,43

1

2

R2W10

R2W10 100K

100K

1

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,57

4

VCC

3

OUT

R5W13 100KR5W13 100K

J6H5

1 3 5 7

9 11 13 15

HDR_2x8

Q2W7

Q2W7 BSS138

BSS138

.

+V3.3A

3

2

MASTER_RESET#

2 4 6 8 10 12

16

Front Panel Header

+VBATA_PS_LATCH

20K

20K R3V4

R3V4

Button Latch

3

1

2

4700PF

C3W1

R8T3

R8T3 100K

100K

NETDETECT# 40,43

Q8E2

Q8E2 BSS138

BSS138

SMC_NET_DETECT: Net

.

Detect trigger signal to ICH9M. Also clears netdetect button latch.

C5W6

0.01uF

.

. 10%

10%

1

2

FRONT2

PWR_CONN_D

56

1

+VBATA26,45,46,47,57

3

+VBATA_LATCH_SHUTDOWN

21

CR1

CR1 BAT54A

BAT54A

Power

R3W13

R3W13 43K

43K

NO_STUFF

PM_RSMRST#23,40,43

Signals EC of a net detect button event.

3.3V Net Detect Level Shifter

53

U5H1

4

74AHC1G08

.

Intel Confidential

1

C7H7

C7H7 470pF

470pF

5%

5% .

.

C5W5

0.1uF

10%

.

+V5S

CR7H2

BAT54

58

20K

20K R3W1

R3W1

SHUTDWN#

3

2

Q1V4

BSS138

.

PM_SYSRST# 23

R7H16

R7H16 330

330

.

C7H6

C7H6 470pF

470pF

5%

5% .

.

PS_ON_SW#

13

1

Q3W1

Q3W1 BSS138

BSS138

.

3

2

1

5

+V5A24,29,34,38,44,46,47,50,51,56

D D

+V3.3A

R4H2

R4H2 10K

10K

5%

5% NO_STUFF

NO_STUFF

PM_SLP_S3#11,23,40,43,44,46,47,49,55

PM_S4_STATE#23,32,40,43,44,55

+V3.3A

C C

ATX_PWR_CTRL_1

3

Q4H8

Q4H8 BSS138

BSS138

+VBAT17,49,53,55,56

PM_SLP_S3#

PM_SLP_S3#11,23,40,43,44,46,47,49,55

C6N3

0.33uF

80%

.

1

.

2

3 8 2 1

R6N3

R6N3 100K

100K

1

Q6B2

Q6B2 SI4425DY

SI4425DY

PS_VBATSG

4

PS_VBATSW

3

2

ATX_PWR_CNTRL56

B B

11,23,40,43,44,46,47,49,55

1

R5W16

R5W16 10K

10K

5%

5% .

.

R6M13

R6M13 100K

100K

Q6N3

Q6N3 BSS138

BSS138

.

3

2

1

7 6 5

PS_S3CNTRL

Q4H5

Q4H5 BSS138

BSS138

.

+V5A24,29,34,38,44,46,47,50,51,56

3

2

U5H3

1

2

A A

U9B1

R9M3

R9M3 330

330

.

1

PS_-12OPTSW

TLP280

+V5S

R4W16

R4W16 100K

100K

R4W23

5%

.

R3W16

R3W16 100K

100K

R4W24

PS_S4CNTRL

100K

Q4H6

.

BSS138

5%

.

+VBATA26,45,46,47,56

C5W8

0.1uF

10%

10% .

.

C5W7

0.1uF

10%

53

.

4

74AHC1G08

.

PM_S3#_AND

+VBATS 16,19,27,30,31,55

C6B2

0.33uF

80%

80% .

.

PM_S4_STATE#23,32,40,43,44,55

R9A6

R9A6 10K

10K

5%

5% .

.

4

PS_-12SSW

32

5

1

C327

0.1uF

10%

.

100K

C3W8

0.1uF

10%

.

R5W17

R5W17 100K

100K

1%

1% .

.

PS_12SSW

+VBAT17,49,53,55,56

C9A6

0.1uF

10%

10% .

.

SI4965DY

SI4965DY Q3H3A

Q3H3A

3

1

C6N1

0.1uF

10%

10% .

.

4

2

PS_S3CNTRL_R

Q3H3B

SI4965DY

4

PS_S4CNTRL_R

Q5H3

Q5H3 SI4425DY

SI4425DY

3 8 2 1

4

R4W22

R4W22 100K

100K

PS_12SG

3

Q4H7

Q4H7 BSS138

BSS138

.

2

3 8 2 1

R6N2

R6N2 100K

100K

1

-V12A56

C9A7

0.1uF

10%

10% .

.

1238

Q9A3

SI4420DY

-V12S32

765

4

8

7

1

+V5 27,32,42,43,48,52,55,56

6

5

+V12S25,26,30,31,32,43,55

7

C4Y1

6

0.33uF

5

80%

.

Q6N1

SI4425DY

7 6 5

PS_VBAT_S4_G

4

R6N1

R6N1 100K

100K

PS_VBAT_S4_D

3

Q6M1

Q6M1 BSS138

BSS138

.

2

3

+VBATA26,45,46,47,56

Q4H4

Q4H4 BSS138

BSS138

.

+VBATA26,45,46,47,56

+V3.3A

3

2

R4W18

R4W18 100K

100K

Q4W4

Q4W4 BSS138

BSS138

.

+V3.3A

783 6 5

VBATA_SLEEP

783 6 5

3

2

+V5S5,11,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56

R4W17

R4W17 100K

100K

1

System Power Good

PLT_RST#7,19,22,25,26,38,41

+VBAT_S419,55

C6N7

0.33uF

80%

.

PM_SLP_M#23,40,43,44,47,55

1

Added to isolate CK505 from 3.3M when WOL/Moff is enabled.

2 1

4

C4W2

0.01UF

.

. 10%

10%

+V3.319,27,32,39,41,42,43,55

2 1

4

SLPS4#_CONTROL

C4H3

0.1uF

10%

10% .

.

+VBATA26,45,46,47,56

R5V7 100KR5V7 100K

V3.3M_INV

3

2

+V3.3S

Q4W2

Q4W2 IRF7822

IRF7822

.

Q4H2

Q4H2 IRF7822

IRF7822

.

R5V6

R5V6 100K

100K

Q4W5

Q4W5 BSS138

BSS138

.

1

+V3.3S

SYS_STATUS_PU

1 2

SYS_STATUS_CR

3

2

+V3.3A

1

R8W975R8W9 75

CR7H3

CR7H3 GREEN

GREEN

.

Q7H1

Q7H1 BSS138

BSS138

.

+VBATA26,45,46,47,56

1

Q5W1

Q5W1 IRF7822

IRF7822

783 6 5

V3.3M_SWITCH

3

Q5W2

Q5W2 BSS138

BSS138

.

2

+V1.89,10,13,14,46,48,55

NO_STUFF

Note: only stuff Q4U1 and C4V1 for DDR3 Board

+V3.319,27,32,39,41,42,43,55

PM_SLP_S3#11,23,40,43,44,46,47,49,55

R7N1

R7N1 100K

100K

3

Q7B2

Q7B2 BSS138

BSS138

.

2

+V3.3M13,14,15,23,35,55

2

.

1

4

Title

Size Document Number Rev

Date: Sheet of

1

S3 COLD

PS_S3CNTRL

1

R6N4

R6N4 100K

100K

V3M_G_SWITCH_OR

3

Q6B5

BSS138

.

2

WOL_GPIO56

3

.

2

C5V8

0.01UF

.

. 10%

10%

Pillar Rock

Sleep control

355659 1.0

A

355659 1.0

A

355659 1.0

A

V3M_G_SWITCH

1

BSS138

BSS138 Q7C1

Q7C1

3

2

+V1.5S4,10,11,24,28,47,55

Q4U1

Q4U1 IRF7822

IRF7822

783 6

2

5

1

C4V1

4

Q5W5

SI2307DS

.

3 2

PP_S3CLED

R5W1175R5W11 75

PP_S3CLEDSW

CR5H6

CR5H6 GREEN

GREEN

1 2

PP_S3CLEDSW_D

.

3

Q4W3

Q4W3 BSS138

BSS138

75 ohms chosen for ~16mA of LED current

.

2

+V3.3A

3

Q6B1

Q6B1 BSS138

BSS138

.

2

1

ICH_GPIO12

1 1 1 1 0 0 1 0V 0V Moff / No WOL

PM_SLP_S5#23

0.33uF

80%

80% NO_STUFF

NO_STUFF

+V3.3M13,14,15,23,35,55

R4W675R4W6 75

PP_M0_LED

CR5H3

CR5H3 GREEN

M0/M1

22,24,33,34,44,48,55

Q6B4

Q6B4 IRF7822

IRF7822

783 6 5

4

LAN_WOL_EN 23,40,43,55

Added for WOL in S3/Moff. Enabled by CLGPIO3=LAN_WOL_EN.

ICH_GPIO12 23

SLP_M# LAN_WOL_EN 3.3M_WOL 3.3M SYSTEM STATE

0 0 0

1 1

GREEN

1 2

.

+V3.3M_WOL

2

.

1

C6N2

0.01UF

.

. 10%

10%

1 01

+V3.3A

1

3 2

PP_S5LEDSW

S5

1 2

0V

3.3V 0V

3.3V 3.3V

2

Q5W3

SI2307DS

PP_S5LED

.

R5W775R5W7 75

CR5H5

CR5H5 GREEN

GREEN

.

+V3.3M13,14,15,23,35,55

PP_S5LED

Moff / No WOL Legacy WOL / Moff

PM_S4_STATE#23,32,40,43,44,55

PM_SLP_S5#23

PM_SLP_S3#11,23,40,43,44,46,47,49,55

PP_S3CLED

M1 M1

57 58Tuesday, August 28, 2007

1

+V3.3A19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56

Q5W4

SI2307DS

1

.

PP_S4LEDSW1

3 2

R5W1075R5W10 75

PP_S4LED

S4

PP_S4_LEDSW2

1 2

3

1

2

+V3.3S

SO

PP_S0_LEDSW

1

J8G2

PP_S3CLEDSW_D

1 2

PP_S0_LEDSW

3 4

PP_S4_LEDSW2

5 6

PP_S4LEDSW1

7 8

8Pin HDR

Intel Confidential

1

CR5H7

CR5H7 GREEN

GREEN

.

Q5H2

Q5H2 BSS138

BSS138

.

R5W1475R5W14 75

PP_S0LED

CR5H4

CR5H4 GREEN

GREEN

1 2

.

3

Q5W6

Q5W6 BSS138

BSS138

.

2

5

4

3

2

1

Steps 1 leads to either 1BAT for battery only mode or 1AC for AC mode. 5AC leads to 5a to 5b to 5c to 6. Battery mode requires button press to begin power up. AC mode requires button press to boot.

D D

PM_SLP_S3#

+VBATS

+V3.3S_TVDAC

7

LDO

SHT 11

C C

+V3.3M_WOL

7

+V5S

7

+VBAT_S4

7

+V3.3S

+V5

+V3.3

+V1.8

+V0.9

6

SLP_S3 SWITCHES

SHT 57

PM_S4_STATE#

6

SLP_S4 SWITCHES

SHT 57

PM_SLP_S4#

6

DDR VR

SHT 46

+VBAT

+V5A

+V3.3A

+VBAT

+V5A

+V3.3A

+VBAT

Pillar Rock Mobile Power On Sequence

SHT 56

SMC_ONOFF#

+VBATA

+VBS

BC_ACOK_BATT

5a

4

SMC_RST#

PM_PWRBTN#

PM_RSMRST#

10

1

1AC

+V3.3A

MAX-809

SHT 42

MPWROK

5b

5c

PM_ICH_PWROK

16

SHT 23

Battery OR AC insertion cause 1

i®AMPS Circuit

SHT 50

ICH9M

SHT 21,22,23,24

CLPWROK

PWROK

Sequence waits here for button press before doing step 1BAT = 5AC.

PG 56

+VBATA

SYSTEM

+V5A

3

+V1.5A_HDA_IO

+V5A3A_MBL_PWRGD

3a

VR

+V3.3A

3

SHT 45

PWRGD

LDO

SHT 28

RSMRST#_PWRGD

IMVP_VR_ON

6

to line switches

1BAT

5AC

PS_ON_SW#

VR_ALW_ENABLE

+V3.3A

H8 SMC

SHT 40 & 41

(300ms MAX)

99ms DELAY

11

+VBAT

Startup

Circuit

2

Only AC insertion causes 1AC

VRMPWRGD

CLGPIO3/GPIO9

18

14

CLK_PWRGD

H_PWRGD

17

SHT 51

Battery Pack

AC Adapter

SHT 50

VRPWRGD_3.3M_R

PWRGD

SYSTEM VR POWER

B B

GOOD MONITOR

SHT 48

8

+V3.3M

+V5S

+V3.3S

+V3.3S_TVDAC

PM_SYS_PWRGD

CLK_PWRGD

ENABLE

CK505

DDR_PGGOD_RU

8

14

VR_PWRGD_CLKEN#

+VCC_CORE

+V3.3A

SHT 46

12

System

+V3.3S

Clock

SHT 35

DB800M CLOCK BUFFERS

SHT 36

+V3.3S

EN

5

13

VR_PWRGD_CLKEN

A A

+V3.3A

SHT 46

PM_PGOOD_1_05M

9

MPWROK

to ICH & MCH

PM_PWROK

11

IMVP_VR_ON

ENABLE

IMVP6+ CPU CORE VR

SHT 52

15

4

9

+V3.3M_WOL

+VBAT

+V1.05M

SHT 47

PM_SLP_M#

PM_SLP_S3#

+V1.05S

VCCP

MCH,ICH CORE

PM_1.5_1.05S_PGOOD

8

SHT 47

PM_PWROK

DELAY_VR_PWRGOOD

6

PM_S4_STATE# PM_SLP_S3#

6

7

+V3.3M

SWITCH

7

CANTIGA_VR_PWRGOOD

SHT 57

+VBAT

+V1.5S

ICH LOGIC

SHT 47

+V3.3A

SHT 47

3

+V3.3A

OR

PM_SLP_S3#

ALL_SYS_PWRGD

10

PM_SLP_S4#

6

to DDR VR

PM_SLP_M#

6

LAN_WOL_EN

CANTIGA

GMCH

SHT 6,7,8,9,10,11

PWROK

MPWROK

Pillar Rock

Title

Size Document Number Rev

Date: Sheet of

POWER SEQUENCING TIMING BLOCK DIAGRAM

355659

A

355659

A

355659

A

CLPWROK

+VBAT

2

GVR_VR_EN

GFX VR

PLT_RST#

+VCC_GMCH_CORE, +VCCP

H_CPURST#

19

+VCC_GFXCORE

PWRGD

Intel Confidential

58 58Tuesday, August 28, 2007

1

+VCC_CORE, +VCCP

CPU

SHT 3,4

1.0

Intel PILLAR ROCK Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual