Intel BX80532PG3200D, Pentium Series Datasheet

Intel® Pentium® Processor on 45-nm Process

Datasheet

For Platforms Based on Mobile Intel® 4 Series Express Chipset Family October 2009

Document Number: 322875-001EN

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The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications

enabled for IntelÆ 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information.

Enhanced Intel SpeedStep® Technology for specified units of this processor are available. See the Processor Spec Finder at http:// processorfinder.intel.com or contact your Intel representative for more information.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.



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2 Datasheet

Contents

1Introduction..............................................................................................................7

1.1 Terminology .......................................................................................................8

1.2 References.........................................................................................................9

2 Low Power Features ................................................................................................11

2.1 Clock Control and Low-Power States....................................................................11

2.1.1 Core Low-Power State Descriptions...........................................................13

2.1.2 Package Low-power State Descriptions................................... .. ... .. .. .......... 14

2.2 Enhanced Intel SpeedStep® Technology ..............................................................17

2.3 Extended Low-Power States................................................................................18

2.4 FSB Low Power Enhancements............................................................................19

2.5 Processor Power Status Indicator (PSI-2) Signal.................................................... 19

3 Electrical Specifications........................................................................................... 21

3.1 Power and Ground Pins...................................................................................... 21

3.2 Decoupling Guidelines ........................................................................................21

3.2.1 VCC

3.2.2 FSB AGTL+ Decoupling ........................................................................... 21

3.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking...........................................21

3.3 Voltage Identification and Power Sequencing ........................................................22

3.4 Catastrophic Thermal Protection..........................................................................25

3.5 Reserved and Unused Pins.................................................................................. 25

3.6 FSB Frequency Select Signals (BSEL[2:0])............................................................25

3.7 FSB Signal Groups............................................................................................. 26

3.8 CMOS Signals...................................................................................................27

3.9 Maximum Ratings.............................................................................................. 27

3.10 Processor DC Specifications................................................................................28

4 Package Mechanical Specifications and Pin Information ..........................................33

4.1 Package Mechanical Specifications....................................................................... 33

4.2 Processor Pinout and Pin List .............................................................................. 36

4.3 Alphabetical Signals Reference............................................................................59

5 Thermal Specifications and Design Considerations .................................................. 67

5.1 Monitoring Die Temperature ...............................................................................69

5.1.1 Thermal Diode....................................................................................... 69

5.1.2 Intel® Thermal Monitor........................................................................... 70

5.1.3 Digital Thermal Sensor............................................................................72

5.2 Out of Specification Detection .............................................................................73

5.3 PROCHOT# Signal Pin........................................................................................ 73

Decoupling......................................................................................21

Figures

1 Core Low-Power States.............................................................................................12

2 Package Low-Power States........................................................................................13

3 Active VCC and ICC Loadline for Pentium Processors.....................................................30

4 1-MB die Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)................................... 34

5 1-MB Die Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) .................................. 35

6 Processor Pinout (Top Package View, Left Side)............................................................36

7 Processor Pinout (Top Package View, Right Side)..................................... .. .. ... .. ............ 37

Datasheet 3

Tables

1 Coordination of Core Low-Power States at the Package Level..........................................13

2 Voltage Identification Definition..................................................................................22

3 BSEL[2:0] Encoding for BCLK Frequency............. .........................................................25

4 FSB Pin Groups ........................................................................................................26

5 Processor Absolute Maximum Ratings..........................................................................27

6 Voltage and Current Specifications for the Pentium Processors...................................... ..29

7 AGTL+ Signal Group DC Specifications ........................................................................31

8 CMOS Signal Group DC Specifications..........................................................................32

9 Open Drain Signal Group DC Specifications ..................................................................32

10 Pin Name Listing ......................................................................................................38

11 Pin # Listing............................................................................................................51

12 Signal Description................. ....................................................................................59

13 Power Specifications for the Pentium Processors ...........................................................68

14 Thermal Diode Interface............................................................................................69

15 Thermal Diode Parameters Using Transistor Model ........................................................70

4 Datasheet

Revision History

Document

Number

322875 -001 Initial Draft October 2009

Revision

Number

Description Date

Datasheet 5

6 Datasheet

Introduction

1 Introduction

This document contains electrical, mechanical and thermal specifications for the following processors:

• The Intel® Pentium® support the Mobile Intel® 4 Series Express Chipset and Intel® ICH9M I/O controller.

Notes: In this document

1. Intel Pentium processor are referred to as the processor

2. Mobile Intel 4 Series Express Chipset is referred as the GMCH.

Key features include:

• Dual-core processor for mobile with enhanced performance

• Supports Intel architecture with Intel® Wide Dynamic Execution

• Supports L1 cache-to-cache (C2C) transfer

• On-die, primary 32-KB instruction cache and 32-KB, write-back data cache in each core

• The processor have an on-die, 1-MB second-level, shared cache with Advanced Transfer Cache architecture

• Streaming SIMD extensions 2 (SSE2), streaming SIMD extensions 3 (SSE3), and supplemental streaming SIMD extensions 3 (SSSE3)

• Enhanced Intel SpeedStep® Technology

• The processors are offered at 800-MHz, source-synchronous front side bus (FSB)

• Digital thermal sensor (DTS)

• Intel® 64 architecture

• Enhanced Multi-Threaded Thermal Management (EMTTM)

• Processor offered in Micro-FCPGA packaging technology

• Execute Disable Bit support for enhanced security

• Half ratio support (N/2) for core to bus ratio

Datasheet

1.1 Terminology

Term Definition

A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high,

Front Side Bus (FSB)

AGTL+

Storage Conditions

Processor Core

Execute Disable Bit

Intel® 64 Technology

a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex “A” , and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).

Refers to the interface between the processor and system core logic (also known as the chipset components).

Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on some Intel processors.

Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.

Processor core die with integrated L1 and L2 cache. All AC timing and signal integrity specifications are at the pads of the processor core.

The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals for more detailed information.

64-bit memory extensions to the IA-32 architecture.

Introduction

Half ratio support (N/2) for Core to Bus ratio

TDP Thermal Design Power. V

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Intel Core 2 Duo processors and Intel Core 2 Extreme processors support the N/2 feature that allows having fractional core-to-bus ratios. This featur e provides the flexibility of having more frequency options and being able to have products with smaller frequency steps.

The processor core power supply. The processor ground.

Introduction

1.2 References

Material and concepts available in the following documents may be beneficial when reading this document.

Document

Intel® Pentium® Processor on 45-nm Technology Specification Update Mobile Intel® 4 Series Express Chipset Family Datasheet 320122 Mobile Intel® 4 Series Express Chipset Family Specification Update 320123 Intel® I/O Controller Hub 9 (ICH9)/ I/O Controller Hub 9M (ICH9M)

Datasheet Intel® I/O Controller Hub 9 (ICH9)/ I/O Controller Hub 9M (ICH9M)

Specification Update Intel® 64 and IA-32 Architectures Software Developer's Manuals

Volume 1: Basic Architecture 253665 Volume 2A: Instruction Set Reference, A-M 253666 Volume 2B: Instruction Set Reference, N-Z 253667 Volume 3A: System Programming Guide 253668 Volume 3B: System Programming Guide 253669

NOTE: Contact your Intel representative for the latest revision of this document.

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316973

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Introduction

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Low Power Features

2 Low Power Features

2.1 Clock Control and Low-Power States

The processor supports low-power states both at the individual core level and the package level for optimal power management.

A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, low-power states. When both cores coincide in a common core low-power state, the central power management logic ensures the entire processor enters the respective package lowpower state by initiating a P_LVLx (P_LVL2, P_LVL3) I/O read to the GMCH.

The processor implements two software interfaces for requesting low-power states: MWAIT instruction extensions with sub-state hints and P_L VLx reads to the ACPI P_BLK register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the processor and do not directly result in I/O reads on the processor FSB. The P_LVLx I/O Monitor address does not need to be set up before using the P_LVLx I/O read interface. The sub-state hints used for each P_LVLx read can be configured through the IA32_MISC_ENABLES model specific register (MSR).

If a core encounters a GMCH break event while STPCLK# is asserted, it asserts the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system logic that individual cores should return to the C0 state and the processor should return to the Normal state.

Figure 1 shows the core low-power states and Figure 2 shows the package low-power

states for the processor. Table 1 maps the core low-power states to package low-power states.

Datasheet

Figure 1. Core Low-Power States

†

Stop

Grant

Core state

break

P_LVL2 or

MWAIT(C2)

†

Core state

break

P_LVL3 or

MWAIT(C3)

C1/

MWAIT

Core state

break

MWAIT(C1)

C1/Auto

Halt

Halt break

HLT instruction

STPCLK#

de-asserted

STPCLK#

asserted

STPCLK#

de-asserted

STPCLK#

asserted

STPCLK#

de-asserted

STPCLK#

asserted

halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted) † — STPCLK# assertion and de-assertion have no effect if a core is in C2 or C3.

Low Power Features

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Low Power Features

Stop

Grant

Snoop

Normal

Stop

Grant

STPCLK# asserted

Snoop

serviced

Snoop occurs

Sleep

SLP# asserted

SLP# de-assertedSTPCLK# de-asserted

Deep Sleep

DPSLP# asserted

DPSLP# de-asserted

Figure 2. Package Low-Power States

Table 1. Coordination of Core Low-Power States at the Package Level

Package State Core1 State

Core0 State C0 C1

C0 Normal Normal Normal Normal

Normal Normal Normal Normal C2 Normal Normal Stop-Grant Stop-Grant C3 Normal Normal Stop-Grant Deep Sleep

C2 C3

NOTE:

1. AutoHALT or MWAIT/C1.

2.1.1 Core Low-Power State Descriptions

2.1.1.1 Core C0 State

This is the normal operating state for cores in the processor.

2.1.1.2 Core C1/AutoHALT Powerdown State

C1/AutoHALT is a low-power state entered when a core executes the HALT instruction. The processor core will transition to the C0 state upon occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more information.

The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.

Datasheet

While in AutoHALT Powerdown state, the dual-core processor will process bus snoops and snoops from the other core. The processor core will enter a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the AutoHALT Powerdow n state.

2.1.1.3 Core C1/MWAIT Powerdown State

C1/MWAIT is a low-power state entered when the processor core executes the MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor core to return to the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals,

Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference, N-Z, for more information.

2.1.1.4 Core C2 State

Individual cores of the dual-core processor can enter the C2 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted.

While in the C2 state, the dual-core processor will process bus snoops and snoops from the other core. The processor core will enter a snoopable sub-state (not shown in

Figure 1) to process the snoop and then return to the C2 state.

Low Power Features

2.1.1.5 Core C3 State

Individual cores of the dual-core processor can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering C3, the processor core flushes the contents of its L1 caches into the processor’s L2 cache. Except for the caches, the processor core maintains all its architectural states in the C3 state. The Monitor remains armed if it is configured. All of the clocks in the processor core are stopped in the C3 state.

Because the core’s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the FSB or when the other core of the dual-core processor accesses cacheable memory. The processor core will transition to the C0 state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to immediately initialize itself.

2.1.2 Package Low-power State Descriptions

2.1.2.1 Normal State

This is the normal operating state for the processor. The processor remains in the Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT state.

2.1.2.2 Stop-Grant State

When the STPCLK# pin is asserted, each core of the dual-core processor enters the Stop-Grant state within 20 bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2, C3, or C4 state remain in their current low-power state. When the STPCLK# pin is deasserted, each core returns to its previous core low-power state.

Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to V termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state.

14 Datasheet

) for minimum power drawn by the

CCP

Low Power Features

RESET# causes the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be deasserted prior to RESET# deassertion as per AC Specification T45. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted after the deassertion of SLP# as per AC Specification T75.

While in Stop-Grant state, the processor will service snoops and latch interrupts delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts and will service only one of each upon return to the Normal state.

The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt or Monitor event latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor should return to the Normal state.

A transition to the Stop-Grant Snoop state occurs when the processor detects a snoop on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4) occurs with the assertion of the SLP# signal.

2.1.2.3 Stop-Grant Snoop State

The processor responds to snoop or interrupt transactions on the FSB while in StopGrant state by entering the Stop-Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. The processor returns to the Stop-Grant state once the snoop has been serviced or the interrupt has been latched.

2.1.2.4 Sleep State

The Sleep state is a low-power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through the Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence.

While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 2.1.2.5). While the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur.

Datasheet

2.1.2.5 Deep Sleep State

The Deep Sleep state is entered throug h assertion of the DPSL P# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform-level power savings. BCLK stop/restart timings on appropriate GMCH-based platforms with the CK505 clock chip are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.

• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK periods.

To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted after DPSLP# deassertion as described above. A period of 15 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.

Low Power Features

16 Datasheet

Low Power Features

2.2 Enhanced Intel SpeedStep® Technology

The processor features Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology:

• Multiple voltage and frequency operati ng points provide optimal performance at the lowest power.

• Voltage and frequency selection is software-controlled by writing to processor MSRs:

— If the target frequency is higher than the current frequency, V

in steps by placing new values on the VID pins, and the PLL then locks to the new frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the

new frequency and the VCC is changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in

progress, the new transition is deferred until the previous transition completes.

• The processor controls voltage ramp rates internally to ensure glitch-free transitions.

• Low transition latency and large number of transitions possible per second:

— Processor core (including L2 cache) is unavailable for up to 10 s during the

frequency transition.

— The bus protocol (BNR# mechanism) is used to block snooping.

• Improved Intel® Thermal Monitor mode:

— When the on-die thermal sensor indicates that the die temperature is too high

the processor can automatically perform a transition to a lower frequency and voltage specified in a software-programmable MSR.

— The processor waits for a fixed time period. If the die temperature is down to

acceptable levels, an up-transition to the previous frequency and voltage point occurs.

— An interrupt is generated for the up and down Intel Thermal Monitor transitions

enabling better system-level thermal management.

• Enhanced thermal management features:

— Digital Thermal Sensor and Out of Specification detection. — Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in

case of unsuccessful TM2 transition.

— Dual-core thermal management synchronization.

is ramped up

Each core in the dual-core processor implements an independent MSR for controlling Enhanced Intel SpeedStep Technology, but both cores must operate at the same frequency and voltage. The processor has performance state coordination logic to resolve frequency and voltage requests from the two cores into a single frequency and voltage request for the package as a whole. If both cores request the same frequency and voltage, then the processor will transition to the requested common frequency and voltage. If the two cores have different frequency and voltage requests, then the processor will take the highest of the two frequencies and voltages as the resolved request and transition to that frequency and voltage.

The processor also supports Dynamic FSB Frequency Switching and Intel Dynamic Acceleration Technology mode on select SKUs. The operating system can take advantage of these features and request a lower operating point called SuperLFM (due to Dynamic FSB Frequency Switching) and a higher operating point Intel Dynamic Acceleration Technology mode.

Datasheet

Low Power Features

2.3 Extended Low-Power States

Extended low-power states (CXE) optimize for power by forcibly reducing the performance state of the processor when it enters a package low-power state. Instead of directly transitioning into the package low-power state, the enhanced package lowpower state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point. Upon receiving a break event from the package low-power state, control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs. The advantage of this feature is that it significantly reduces leakage while in the Stop-Grant state.

Note: Long-term reliability cannot be assured unless all the Extended Low Power States are

enabled. The processor implements two software interfaces for requesting enhanced package

low-power states: MWAIT instruction extensions with sub-state hints and via BIOS by configuring IA32_MISC_ENABLES MSR bits to automatically promote package lowpower states to enhanced package low-power states.

Caution: Extended Stop-Grant must be enabled via the BIOS for the processor to

Caution: Enhanced Intel SpeedStep Technology transitions are multistep processes

remain within specification. As processor technology changes, enabling the extended low power states becomes increasingly crucial when building computer systems. Maintaining the proper BIOS configuration is key to reliable, long-term system operation. Not complying to this guideline may affect the long-term reliability of the processor.

that require clocked control. These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low-power states since processor clocks are not active in these states. The transition to the lowest operating point or back to the original software-requested point may not be instantaneous. Furthermore, upon very frequent transitions between active and idle states, the transitions may lag behind the idle state entry resulting in the processor either executing for a longer time at the lowest operating point or running idle at a high operating point. Observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases.

18 Datasheet

Low Power Features

2.4 FSB Low Power Enhancements

The processor incorporates FSB low power enhancements:

• Dynamic FSB Power Down

• BPRI# control for address and control input buffers

• Dynamic Bus Parking

• Dynamic On-Die Termination disabling

•Low V

• Dynamic FSB frequency switching

The processor incorporates the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows a reciprocal power reduction in GMCH address and control input buffers when the processor deasserts its BR0# pin. The On-Die T ermination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all times.

(I/O termination voltage)

CCP

2.5 Processor Power Status Indicator (PSI-2) Signal

The processor incorporates the PSI# signal that is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve intermediate and light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. The algorithm that the processor uses for determining when to assert PSI# is different from the algorithm used in previous mobile processors. PSI-2 functionality is expanded further to support three processor states:

• Both cores are in idle state

• Only one core active state

• Both cores are in active state

PSI-2 functionality improves overall voltage regulator efficiency over a wide power range based on the C-state and P-state of the two cores. The combined C-state and Pstate of both cores are used to dynamically predict processor power.

The real-time power prediction is compared against a set of predefined and configured valu es of CHH and CHL. CHH is indicative of the active C-state of both the cores and CHL is indicative that only one core is in active C-state and the other core is in low power core state. PSI-2# output is asserted upon crossing these thresholds indicating that the processor requires lower power. The voltage regulator will adapt its power output accordingly . Additionally the v oltage regulator may switch to a single phase and/ or asynchronous mode when the processor is idle and fused leakage limit is less than or equal to the BIOS threshold value.

Datasheet

Low Power Features

20 Datasheet

Electrical Specifications

3 Electrical Specifications

3.1 Power and Ground Pins

For clean, on-chip power distribution, the processor will have a large number of VCC (power) and V planes while all V power and ground planes is recommended to reduce I*R drop. The processor V must be supplied the voltage determined by the VID (Voltage ID) pins.

(ground) inputs. All power pins must be connected to V

pins must be connected to system ground planes. Use of multiple

3.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage, such as electrolytic capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in the tables in Section 3.10. Failure to do so can result in timing violations or reduced lifetime of the component.

3.2.1 V

Decoupling

regulator solutions need to provide bulk capacitance with a low Effective Series

Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low-power states, should be provided by the voltage regulator solution depending on the specific system design.

power

pins

3.2.2 FSB AGTL+ Decoupling

The processors integrate signal termination on the die as well as incorporate high frequency decoupling capacitance on the processor package. Decoupling must also be provided by the system motherboard for proper AGTL+ bus operation.

3.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous-generation processors, the processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus r atio multiplier will be set at its default ratio at manufacturing. The processor uses a differential clocking implementation.

Datasheet

Electrical Specifications

3.3 Voltage Identification and Power Sequencing

The processor uses seven voltage identification pins,VID[6:0], to support automatic selection of power supply voltages. The VID pins for the processor are CMOS outputs driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding to the state of VID[6:0]. A 1 in the table refers to a high-voltage level and a 0 refers to a low-voltage level.

Table 2. Voltage Identification Definition (Sheet 1 of 3)

VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)

00 000 0 01.5000 00 000 0 11.4875 00 000 1 01.4750 00 000 1 11.4625 00 001 0 01.4500 00 001 0 11.4375 00 001 1 01.4250 00 001 1 11.4125 00 010 0 01.4000 00 010 0 11.3875 00 010 1 01.3750 00 010 1 11.3625 00 011 0 01.3500 00 011 0 11.3375 00 011 1 01.3250 00 011 1 11.3125 00 100 0 01.3000 00 100 0 11.2875 00 100 1 01.2750 00 100 1 11.2625 00 101 0 01.2500 00 101 0 11.2375 00 101 1 01.2250 00 101 1 11.2125 00 110 0 01.2000 00 110 0 11.1875 00 110 1 01.1750 00 110 1 11.1625 00 111 0 01.1500 00 111 0 11.1375 00 111 1 01.1250 00 111 1 11.1125 01 000 0 01.1000 01 000 0 11.0875 01 000 1 01.0750 01 000 1 11.0625 01 001 0 01.0500 01 001 0 11.0375 01 001 1 01.0250 01 001 1 11.0125

22 Datasheet

Electrical Specifications

Table 2. Voltage Identification Definition (Sheet 2 of 3)

VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)

0 1 0 1 0 0 0 1.0000 0 1 0 1 0 0 1 0.9875 0 1 0 1 0 1 0 0.9750 0 1 0 1 0 1 1 0.9625 0 1 0 1 1 0 0 0.9500 0 1 0 1 1 0 1 0.9375 0 1 0 1 1 1 0 0.9250 0 1 0 1 1 1 1 0.9125 0 1 1 0 0 0 0 0.9000 0 1 1 0 0 0 1 0.8875 0 1 1 0 0 1 0 0.8750 0 1 1 0 0 1 1 0.8625 0 1 1 0 1 0 0 0.8500 0 1 1 0 1 0 1 0.8375 0 1 1 0 1 1 0 0.8250 0 1 1 0 1 1 1 0.8125 0 1 1 1 0 0 0 0.8000 0 1 1 1 0 0 1 0.7875 0 1 1 1 0 1 0 0.7750 0 1 1 1 0 1 1 0.7625 0 1 1 1 1 0 0 0.7500 0 1 1 1 1 0 1 0.7375 0 1 1 1 1 1 0 0.7250 0 1 1 1 1 1 1 0.7125 1 0 0 0 0 0 0 0.7000 1 0 0 0 0 0 1 0.6875 1 0 0 0 0 1 0 0.6750 1 0 0 0 0 1 1 0.6625 1 0 0 0 1 0 0 0.6500 1 0 0 0 1 0 1 0.6375 1 0 0 0 1 1 0 0.6250 1 0 0 0 1 1 1 0.6125 1 0 0 1 0 0 0 0.6000 1 0 0 1 0 0 1 0.5875 1 0 0 1 0 1 0 0.5750 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0.5000 1 0 1 0 0 0 1 0.4875 1 0 1 0 0 1 0 0.4750 1 0 1 0 0 1 1 0.4625 1 0 1 0 1 0 0 0.4500 1 0 1 0 1 0 1 0.4375 1 0 1 0 1 1 0 0.4250

Datasheet

Table 2. Voltage Identification Definition (Sheet 3 of 3)

VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)

10 101 1 10.4125 10 110 0 00.4000 10 110 0 10.3875 10 110 1 00.3750 10 110 1 10.3625 10 111 0 00.3500 10 111 0 10.3375 10 111 1 00.3250 10 111 1 10.3125 11 000 0 00.3000 11 000 0 10.2875 11 000 1 00.2750 11 000 1 10.2625 11 001 0 00.2500 11 001 0 10.2375 11 001 1 00.2250 11 001 1 10.2125 11 010 0 00.2000 11 010 0 10.1875 11 010 1 00.1750 11 010 1 10.1625 11 011 0 00.1500 11 011 0 10.1375 11 011 1 00.1250 11 011 1 10.1125 11 100 0 00.1000 11 100 0 10.0875 11 100 1 00.0750 11 100 1 10.0625 11 101 0 00.0500 11 101 0 10.0375 11 101 1 00.0250 11 101 1 10.0125 11 110 0 00.0000 11 110 0 10.0000 11 110 1 00.0000 11 110 1 10.0000 11 111 0 00.0000 11 111 0 10.0000 11 111 1 00.0000 11 111 1 10.0000

Electrical Specifications

24 Datasheet

Electrical Specifications

3.4 Catastrophic Thermal Protection

The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a catastrophic processor temperature of approximately 125°C (maximum), or if the THERMTRIP# signal is asserted, the V supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. THERMTRIP# functionality is not ensured if the PWRGOOD signal is not asserted, and during Deep Power Down Technology State (C6).

3.5 Reserved and Unused Pins

All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to VCC, V

, or to any other signal (including each other) can result in component malfunction

or incompatibility with future processors. See Section 4.2 for a pin listing of the processor and the location of all RSVD pins.

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active low AGTL+ inputs may be left as no-connects if AGTL+ termination is provided on the processor silicon. Unused active high inputs should be connected through a resistor to ground (V unconnected. The TEST1,TEST2,TEST3,TEST4,TEST5,TEST6,TEST7 pins are used for test purposes internally and can be left as “No Connects”.

). Unused outputs can be left

3.6 FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and the appropriate chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3.

Table 3. BSEL[2:0] Encoding for BCLK Frequency

BSEL[2] BSEL[1] BSEL[0 ] BCLK Frequency

L L L RESERVED L L H RESERVED L H H RESERVED

L H L 200 MHz H H L RESERVED H H H RESERVED H L H RESERVED H L L RESERVED

Datasheet

3.7 FSB Signal Groups

Signals Associated Strobe

REQ[4:0]#, A[16:3]# ADSTB[0]# A[35:17]# ADSTB[1]# D[15:0]#, DINV0# DSTBP0#, DSTBN0# D[31:16]#, DINV1# DSTBP1#, DSTBN1# D[47:32]#, DINV2# DSTBP2#, DSTBN2# D[63:48]#, DINV3# DSTBP3#, DSTBN3#

The FSB signals have been combined into groups by buffer type in the following sections. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.

With the implementation of a source-synchronous data bus, two sets of timing parameters are specified. One set is for common clock signals, which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.), and the second set is for the source-synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle.

Table 4 identifies which signals are common clock, source synchronous, and

asynchronous.

Table 4. FSB Pin Groups

Signal Group Type Signals

Electrical Specifications

AGTL+ Common Clock Input

AGTL+ Common Clock I/O

AGTL+ Source Synchronous I/O

AGTL+ Strobes

CMOS Input Asynchronous

Open Drain Output

Open Drain I/O Asynchronous PROCHOT# CMOS Output Asynchronous PSI#, VID[6:0], BSEL[2:0] CMOS Input Synchronous to TCK TCK, TDI, TMS, TRST# Open Drain

Output FSB Clock Clock BCLK[1:0]

Power/Other

NOTES:See next page

26 Datasheet

Synchronous to BCLK[1:0]

BPRI#, DEFER#, PREQ#

ADS#, BNR#, BPM[3:0]# HIT#, HITM#, LOCK#, PRDY#

, RESET#, RS[2:0]#, TRDY#

, BR0#, DBSY#, DRDY#,

Synchronous to assoc. strobe

Synchronous to BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/ INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK#

Asynchronous FERR#, IERR#, THERMTRIP#

Synchronous to TCK TDO

COMP[3:0], DBR# THERMDA, THERMDC, V V

, V

SS_SENSE

, GTLREF, RSVD, TEST2, TEST1,

, V

, DPWR#

, V

CCA

CCP

, V

CC_SENSE

Electrical Specifications

1. Refer to Chapter 4 for signal descriptions and termination requirements.

2. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.

3. BPM[2:1]# and PRDY# are AGTL+ output-only signals.

4. PROCHOT# signal type is open drain output and CMOS input.

5. On-die termination differs from other AGTL+ signals.

3.8 CMOS Signals

CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) use Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for more than four BCLKs for the processor to recognize them. See Section 3.10 for the DC specifications for the CMOS signal groups.

3.9 Maximum Ratings

Table 5 specifies absolute maximum and minimum ratings only, which lie outside the

functional limits of the processor. Only within specified operation limits, can functionality and long-term reliability be expected.

At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded.

Caution: Although the processor contains protective circuitry to resist damage from static

electric discharge, precautions should always be taken to avoid high static voltages or electric fields.

Table 5. Processor Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes

STORAGE

inAGTL+

inAsynch_CMOS

NOTES:

1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied.

Processor Storage Temperature -40 85 °C 3,4,5 Processor Storage Temperature -25 °C 6 Any Processor Supply Voltage with

Respect to V AGTL+ Buffer DC Input Voltage with

Respect to V CMOS Buffer DC Input Voltage with

Respect to V

-0.3 1.45 V

-0.1 1.45 V

1,2

Datasheet

2. Excessive overshoot or undershoot on any signal will likely re sult i n permanent damage to the processor.

3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, please refer to the processor case temperature specifications.

4. This rating applies to the processor and does not include any tray or packaging.

5. Failure to adhere to this specif ication can affect the long-term reliability of the processor.

6. For Intel® Pentium® processors in 22x22 mm package.

3.10 Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise.

The tables list the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. The Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer to the highest and lowest core operating frequencies supported on the processor. Active mode load line specifications apply in all states except in the Deep Sleep and Deeper Sleep states. V

CC,BOOT

set the VID values. Unless specified otherwise, all specifications for the processor are at TJ = 105 C. Read all notes associated with each parameter.

is the default voltage driven by the voltage regulator at power up in order to

Electrical Specifications

28 Datasheet

Electrical Specifications

Table 6. Voltage and Current Specifications for the Pentium Processors

Symbol Parameter Min Typ Max Unit Notes

CCHFM

CCLFM

CC,BOOT

CCP

CCA

CCDES

AH,

SGNT

SLP

DSLP

CC/DT

CCA

CCP

VCC at Highest Frequency Mode (HFM) 0.9 1.2 V 1, 2 VCC at Lowest Frequency Mode (LFM) 0.85 — 1.15 V 1, 2 Default V

Voltage for Initial Power Up — 1.2 — V 2, 6

AGTL+ Termination Voltage 1.0 1.05 1.1 V PLL Supply Voltage 1.425 1.5 1.575 V ICC for Processors Recommended Design Target — — 47 A 10 ICC for Processors — — — Processor

Number T4500

T4400 T4300 T4200

Core Frequency/Voltage — — —

2.3 GHz & V

2.2 GHz & V

2.1 GHz & V

2.0 GHz & V

1.2 GHz & V

CCHFM CCHFM CCHFM CCHFM CCLFM

——

47 47 47 47

31.7

A3, 4

ICC Auto-Halt & Stop-Grant HFM LFM

— — 25.4

19.4

A3, 4

ICC Sleep HFM LFM

— — 24.7

19.2

A3, 4

ICC Deep Sleep HFM LFM

Power Supply Current Slew Rate at Processor

Package Pin ICC for V I

for V

CCC

for V

Supply — — 130 mA

CCA

Supply before VCC Stable

CCP

Supply after VCC Stable

CCP

— — 22.9

A3, 4

18.5

— — 600 mA/µs 5, 7

——

4.5

2.5

A A

8 9

NOTES:See next page.

Datasheet

Electrical Specifications

CC-CORE

max

{HFM|LFM}

CC-CORE

[V]

CC-CORE

nom {HFM|LFM}

+/-V

CC-CORE

Tolerance

= VR St. Pt. Error 1

CC-CORE, DC

min {HFM|LFM}

CC-CORE, DC

max {HFM|LFM}

CC-CORE

max {HFM|LFM}

CC-CORE

min {HFM|LFM}

10mV= RIPPLE

CC-CORE

[A]

Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required.

Note 1

/ V

CC-CORE

Set Point Error Tolerance is per below:

Tolerance V

CC-CORE

VID Voltage Range

--------------- ------------------------------------------------------- +/-1.5% V

CC-CORE

> 0.7500V

+/-11.5mV 0.5000V </= Vcc_core </= 0.75000V

1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).

2. The voltage specifications are assumed to be measured across V a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-M minimum impedance.

CC_SENSE

and V

SS_SENSE

pins at socket with

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.

3. Specified at 105 °C T

4. Specified at the nominal V

5. Measured at the bulk capacitors on the motherboard.

6. V

tolerance shown in Figure 7 and Figure 8.

CC,BOOT

7. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal V

8. This is a power-up peak current specification that is applicable when V

9. This is a steady-state I

10. Instantaneous current I current will be less than maximum specified I

CC_CORE_INST

. Not 100% tested.

is high and V

CCP

current specification that is applicable when both V

of 57 A has to be sustained for short time (t

. VR OCP threshold should be high enough to support

CCDES

CCP

and V

CC_CORE

) of 35 µs. Average

INST

is low.

are high.

current levels described herein.

Figure 3. Active VCC and ICC Loadline for Pentium Processors

30 Datasheet

Electrical Specifications

Table 7. AGTL+ Signal Group DC Specifications

Symbol Parameter Min Typ Max Unit Notes

CCP

I/O Voltage 1.00 1.05 1.10 V

GTLREF Reference Voltage 0.65 0.70 0.72 V 6

COMP

ODT/A

ODT/D

ODT/Cntrl

TT/A

TT/D

TT/Cntrl

ON/A

ON/D

ON/Cntrl

Compensation Resistor 27.23 27.5 27.78  10 Termination Resistor Address 49 55 63  11, 12 Termination Resistor Data 49 55 63  11, 13 Termination Resistor Control 49 55 63  11, 14 Input High Voltage 0.82 1.05 1.20 V 3,6 Input Low Voltage -0.10 0 0.55 V 2,4 Output High Voltage 0.90 V

CCP

1.10 V 6 Termination Resistance Address 50 55 61  7, 12 Termination Resistance Data 50 55 61  7, 13 Termination Resistance Control 50 55 61  7, 14 Buffer On Resistance Address 23 25 29  5, 12 Buffer On Resistance Data 23 25 29  5, 13 Buffer On Resistance Control 23 25 29  5, 14 Input Leakage Current — — ± 100 µA 8

Cpad Pad Capacitance 1.80 2.30 2.75 pF 9

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. V

3. V

4. V

is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low

value.

is defined as the minimum voltage level at a receiving agent that will be interprete d as a logical high

value.

and VOH may experience excursions above V

. However, input signal drivers must comply with the

CCP

signal quality specifications.

5. This is the pulldown driver resistance. Measured at 0.31*V

0.455*R R

6. GTLREF should be generated from V

specifications is the instantaneous V

7. R

0.31*V

8. Specified with on-die R

(max) = 0.527*RTT. RTT typical value of 55  is used for RON typ/min/max calculations.

with a 1% tolerance resistor divider. The V

CCP

is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at

. R

CCP

is connected to V

and R

on die. Refer to processor I/O buffer models for I/V characteristics.

CCP

turned off. Vin between 0 and V

CCP

. R

(min) = 0.418*RTT, R

CCP

(typ) =

referred to in these

CCP

9. Cpad includes die capacitance only. No package parasitics are included.

10. This is the external resistor on the comp pins.

11. On-die termination resistance, measured at 0.33*V

CCP

12. Applies to Signals A[35:3].

13. Applies to Signals D[63:0].

14. Applies to Signals BPRI#, DEFER#, PREQ#, PREST#, RS[2:0]#, TRDY#, ADS#, BNR#, BPM[3:0], BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#, DPWR#, DSTB[1:0]#, DSTBP[3:0] and DSTBN[3:0]#.

Datasheet

Electrical Specifications

Table 8. CMOS Signal Group DC Specifications

Symbol Parameter Min Typ Max Unit Notes

CCP

Cpad1 Pad Capacitance 1.80 2.30 2.75 pF 6 Cpad2 Pad Capacitance for CMOS Input 0.95 1.2 1.45 pF 7

NOTES:

1. Unless othe rwise noted, all specifications in th is table apply to all processor frequencie s.

2. The V

3. Measured at 0.1 *V

4. Measured at 0.9 *V

5. For Vin between 0 V and V

6. Cpad1 includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package parasitics are

7. Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included.

I/O Voltage 1.00 1.05 1.10 V Input Low Voltage CMOS -0.10 0.00 0.3*V Input High Voltage 0.7*V

CCP

Output Low Voltage -0.10 0 0.1*V Output High Voltage 0.9*V

CCP

+0.1 V 2

CCP

+0.1 V 2

CCP

Output Low Current 1.5 — 4.1 mA 3 Output High Current 1.5 — 4.1 mA 4 Input Leakage Current — — ±100 µA 5

referred to in these specifications refers to instantaneous V

CCP

CCP CCP

. .

. Measured when the driver is tristated.

CCP

included.

Table 9. Open Drain Signal Group DC Specifications

Symbol Parameter Min Typ Max Unit Notes

Output High Voltage V

–5% V

CCP

+5% V 3

CCP

Output Low Voltage 0 — 0.20 V Output Low Current 16 — 50 mA 2 Output Leakage Current — — ±200 µA 4

Cpad Pad Capacitance 1.80 2.30 2.75 pF 5

NOTES:

1. Unless othe rwise noted, all specifications in th is table apply to all processor frequencie s.

2. Measured at 0.2 V.

3. V

4. For Vin between 0 V and V

is determined by value of the external pull-up resistor to V

CCP

5. Cpad includes die capacitance only. No package parasitics are included.

32 Datasheet

Package Mechanical Specifications and Pin Information

4 Package Mechanical

Specifications and Pin Information

4.1 Package Mechanical Specifications

The processor is available in 478-pin Micro-FCPGA packages. The package mechanical dimensions are shown in Figure 9 through Figure 13.

The mechanical package pressure specifications are in a direction normal to the surface of the processor. This protects the processor die from fracture risk due to uneven die pressure distribution under tilt, stack-up tolerances and oth er similar conditions. These specifications assume that a mechanical attach is designed specifically to load one type of processor.

Moreover, the processor package substrate should not be used as a mechanical reference or load-bearing surface for the thermal or mechanical solution.

Datasheet 33

Package Mechanical Specifications and Pin Information

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Figure 4. 1-MB die Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)

34 Datasheet

Package Mechanical Specifications and Pin Information

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SIDE VIEW

BOTTOM VIEW

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       !    !  

    

CORNER KEEP OUT

ZONE 4X

EDGE KEEP OUT

ZONE 4X

4X 7.00

4X 5.00

4X 7.00

13.97

6.985

13.97

6.985

1.625

1.5 MAX ALLOWABLE

COMPONENT HEIGHT

1.625

0.406

0.254

0.305±0.25

Figure 5. 1-MB Die Micro-FCPGA Processor Package Drawing (She et 2 of 2)

Datasheet 35

Package Mechanical Specifications and Pin Information

4.2 Processor Pinout and Pin List

Figure 6 and Figure 7 show the processor pinout as viewed from the top of the

package. Table 10 provides the pin list, arranged numerically by pin number. For signal descriptions, refer to Section 4.3.

Figure 6. Processor Pinout (Top Package View, Left Side)

1 234 5 678910111213

C RESET# VSS TEST7

D VSS RSVD RSVD VSS

E DBSY# BNR# VSS HITM#

F BR0# VSS RS[0]# RS[1]# VSS RSVD VCC VSS VCC VCC VSS VCC VSS F G VSS TRDY# RS[2]# VSS BPRI# HIT# G

H ADS#

J A[9]# VSS

K VSS

L REQ[4]# A[13]# VSS A[5]# A[4]# VSS L

ADSTB[0]

N VSS A[8]# A[10]# VSS RSVD VCCP N

P A[15]# A[12]# VSS A[14]# A[11]# VSS P R A[16]# VSS A[19]# A[24]# VSS VCCP R

T VSS RSVD A[26]# VSS A[25]# VCCP T U A[23]# A[30]# VSS A[21]# A[18]# VSS U

ADSTB[1]

W VSS A[27]# A[32]# VSS A[28]# A[20]# W

Y COMP[3] A[17]# VSS A[29]# A[22]# VSS Y

AA COMP[2] VSS A[35]# A[33]# VSS TDI VCC VSS VCC VCC VSS VCC VCC

AB VSS A[34]# TDO VSS TMS TRST# VCC VSS VCC VCC VSS VCC VSS

AC PREQ# PRDY# VSS

AD BPM[2]# VSS

AE VSS VID[6] VID[4] VSS VID[2] PSI#

AF TEST5 VSS VID[5] VID[3] VID[1] VSS

1 234 5 678910111213

VSS SMI# VSS FERR# A20M# VCC VSS VCC VCC VSS VCC VCC A

RSVD INIT# LINT1 DPSLP# VSS VCC VSS VCC VCC VSS VCC VSS B

IGNNE

REQ[1]

REQ[2]#REQ[0]

VSS A[7]# RSVD VSS VCCP M

VSS RSVD A[31]# VSS VCCP V

VSS LOCK# DEFER# VSS H

REQ[3]

BPM[1]#BPM[0]

A[3]# VSS VCCP J

VSS A[6]# VCCP K

BPM[3]

VSS LINT0

STPCLK#PWRGO

DPRSTP

TCK VSS VCC VSS VCC VCC VSS VCC VCC

VSS VID[0] VCC VSS VCC VCC VSS VCC VSS

THERM

TRIP#

SLP# VSS VCC VCC VSS VCC VSS D

VSS VCC VSS VCC VCC VSS VCC VCC E

VSS

SENSE

VCC

SENSE

VSS VCC VCC VSS VCC V CC C

VSS VCC VCC VSS VCC V CC

VSS VCC VCC VSS VCC VSS

A A

A B

A C

D A

E A

NOTES:

1. Keying option for Micro-FCPGA, A1 and B1 are de-populated.

2. Keying option for Micro-FCBGA, A1 is de-populated and B1 is VSS.

36 Datasheet

Package Mechanical Specifications and Pin Information

Figure 7. Processor Pinout (Top Package View, Right Side)

14 15 16 17 18 19 20 21 22 23 24 25 26

A VSS VCC VSS VCC VCC VSS VCC BCLK[1] BCLK[0] VSS THRMDA VSS TEST6 A B VCC VCC VSS VCC VCC VSS VCC VSS BSEL[0] BSEL[1] VSS THRMDC VCCA B C VSS VCC VSS VCC VCC VSS DBR# BSEL[2] VSS TEST1 TEST3 VSS VCCA C

D VCC VCC VSS VCC VCC VSS IERR#

E VSS VCC VSS VCC VCC VSS VCC VSS D[0]# D[7]# VSS D[6]# D[2]# E F VCC VCC VSS VCC VCC VSS VCC DRDY# VSS D[4]# D[1]# VSS D[13]# F G VCCP D[3]# VSS D[9]# D[5]# VSS G

H VSS D[12]# D[15]# VSS DINV[0]#

J VCCP VSS D[11]# D[10]# VSS

K VCCP D[14]# VSS D[8]# D[17]# VSS K

L VSS D[22]# D[20]# VSS D[29]#

M VCCP VSS D[23]# D[21]# VSS

N VCCP D[16]# VSS DINV[1]# D[31]# VSS N P VSS D[26]# D[25]# VSS D[24]# D[18]# P

R VCCP VSS D[19]# D[28]# VSS

T VCCP D[37]# VSS D[27]# D[30]# VSS T

U VSS DINV[2]# D[39]# VSS D[38]#

V VCCP VSS D[36]# D[34]# VSS D[35]# V

W VCCP D[41]# VSS D[43]# D[44]# VSS W

Y VSS D[32]# D[42]# VSS D[40]#

AA VSS VCC VSS VCC VCC VSS VCC D[50]# VSS D[45]# D[46]# VSS

AB VCC VCC VSS VCC VCC VSS VCC D[52]# D[51]# VSS D[33]# D[47]# VSS

AC VSS VCC VSS VCC VCC VSS

VCC VCC VSS VCC VCC VSS D[54]# D[59]# VSS D[61]# D[49]# VSS GTLREF

AE VSS VCC VSS VCC VCC VSS VCC D[58]# D[55]# VSS D[48]#

AF VCC VCC VSS VCC VCC VSS VCC VSS D[62]# D[56]#

14 15 16 17 18 19 20 21 22 23 24 25 26

DINV[3

PROCHOT

VSS D[60]# D[63]# VSS D[57]# D[53]#

RSVD VSS DPWR# TEST2 VSS D

DSTBP[

0]#

DSTBN[

0]#

DSTBN[

1]#

DSTBP[

1]#

COMP[0

]

COMP[1

]

DSTBN[

2]#

DSTBP[

2]#AA

DSTBP[3]

DSTBN[3]

VSS TEST4

VSS

A B

A C

A D

A E

A F

Datasheet 37

Table 10. Pin Name Listing

Signal

Pin Name Pin #

Buffer

Type

Direction

Package Mechanical Specifications and Pin Information

A[3]# J4

A[4]# L5

A[5]# L4

A[6]# K5

A[7]# M3

A[8]# N2

A[9]# J1

A[10]# N3

A[11]# P5

A[12]# P2

A[13]# L2

A[14]# P4

A[15]# P1

A[16]# R1

A[17]# Y2

A[18]# U5

A[19]# R3

A[20]# W6

A[21]# U4

A[22]# Y5

A[23]# U1

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Input/ Output

38 Datasheet

Package Mechanical Specifications and Pin Information

Table 10. Pin Name Listing

Pin Name Pin #

A[24]# R4

A[25]# T5

A[26]# T3

A[27]# W2

A[28]# W5

A[29]# Y4

A[30]# U2

A[31]# V4

A[32]# W3

A[33]# AA4

A[34]# AB2

A[35]# AA3

A20M# A6 CMOS Input

ADS# H1

ADSTB[0]# M1

ADSTB[1]# V1

BCLK[0] A22 Bus Clock Input BCLK[1] A21 Bus Clock Input

BNR# E2

BPM[0]# AD4

BPM[1]# AD3

BPM[2]# AD1

BPM[3]# AC4

Signal Buffer

Type

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Common

Clock

Source

Synch

Source

Synch

Common

Clock

Common

Clock

Common

Clock

Common

Clock

Common

Clock

Direction

Input/ Output

Output

Input/ Output

Datasheet 39

Table 10. Pin Name Listing

Package Mechanical Specifications and Pin Information

Pin Name Pin #

BPRI# G5

BR0# F1

BSEL[0] B22 CMOS Output BSEL[1] B23 CMOS Output BSEL[2] C21 CMOS Output

COMP[0] R26

COMP[1] U26

COMP[2] AA1

COMP[3] Y1

D[0]# E22

D[1]# F24

D[2]# E26

D[3]# G22

D[4]# F23

D[5]# G25

D[6]# E25

D[7]# E23

D[8]# K24

D[9]# G24

D[10]# J24

D[11]# J23

D[12]# H22

D[13]# F26

Signal Buffer

Type

Common

Clock

Common

Clock

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Direction

Input

Input/ Output

40 Datasheet

Package Mechanical Specifications and Pin Information

Table 10. Pin Name Listing

Pin Name Pin #

D[14]# K22

D[15]# H23

D[16]# N22

D[17]# K25

D[18]# P26

D[19]# R23

D[20]# L23

D[21]# M24

D[22]# L22

D[23]# M23

D[24]# P25

D[25]# P23

D[26]# P22

D[27]# T24

D[28]# R24

D[29]# L25

D[30]# T25

D[31]# N25

D[32]# Y22

D[33]# AB24

D[34]# V24

D[35]# V26

Signal Buffer

Type

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Direction

Input/ Output

Datasheet 41

Table 10. Pin Name Listing

Package Mechanical Specifications and Pin Information

Pin Name Pin #

D[36]# V23

D[37]# T22

D[38]# U25

D[39]# U23

D[40]# Y25

D[41]# W22

D[42]# Y23

D[43]# W24

D[44]# W25

D[45]# AA23

D[46]# AA24

D[47]# AB25

D[48]# AE24

D[49]# AD24

D[50]# AA21

D[51]# AB22

D[52]# AB21

D[53]# AC26

D[54]# AD20

D[55]# AE22

D[56]# AF23

D[57]# AC25

Signal Buffer

Type

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Direction

Input/ Output

42 Datasheet

Package Mechanical Specifications and Pin Information

Table 10. Pin Name Listing

Pin Name Pin #

D[58]# AE21

D[59]# AD21

D[60]# AC22

D[61]# AD23

D[62]# AF22

D[63]# AC23

DBR# C20 CMOS Output

DBSY# E1

DEFER# H5

DINV[0]# H25

DINV[1]# N24

DINV[2]# U22

DINV[3]# AC20

DPRSTP# E5 CMOS Input

DPSLP# B5 CMOS Input

DPWR# D24

DRDY# F21

DSTBN[0]# J26

DSTBN[1]# L26

DSTBN[2]# Y26

DSTBN[3]# AE25

DSTBP[0]# H26

DSTBP[1]# M26

Signal Buffer

Type

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Common

Clock

Common

Clock

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Common

Clock

Common

Clock

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Direction

Input/ Output

Input

Input/ Output

Table 10. Pin Name Listing

Pin Name Pin #

DSTBP[2]# AA26

DSTBP[3]# AF24

FERR# A5

GTLREF AD26

HIT# G6

HITM# E4

IERR# D20

IGNNE# C4 CMOS Input

INIT# B3 CMOS Input LINT0 C6 CMOS Input LINT1 B4 CMOS Input

LOCK# H4

PRDY# AC2

PREQ# AC1

PROCHOT# D21

PSI# AE6 CMOS Output

PWRGOOD D6 CMOS Input

REQ[0]# K3

REQ[1]# H2

REQ[2]# K2

REQ[3]# J3

REQ[4]# L1

RESET# C1

RS[0]# F3

Signal Buffer

Type

Source

Synch

Source

Synch

Open Drain

Power/

Other

Common

Clock

Common

Clock

Open

Drain

Common

Clock

Common

Clock

Common

Clock

Open

Drain

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Source

Synch

Common

Clock

Common

Clock

Direction

Input/ Output

Output

Input

Input/ Output

Output

Input/ Output

Output

Input

Input/ Output

Input

Datasheet 43

Package Mechanical Specifications and Pin Information

Table 10. Pin Name Listing

Signal

Pin Name Pin #

RS[1]# F4

RS[2]# G3

RSVD B2 Reserved RSVD D2 Reserved RSVD D3 Reserved RSVD D22 Reserved RSVD F6 Reserved RSVD M4 Reserved RSVD N5 Reserved RSVD T2 Reserved RSVD V3 Reserved

SLP# D7 CMOS Input SMI# A3 CMOS Input

STPCLK# D5 CMOS Input

TCK AC5 CMOS Input

TDI AA6 CMOS Input

TDO AB3

TEST1 C23 Test TEST2 D25 Test TEST3 C24 Test TEST4 AF26 Test TEST5 AF1 Test TEST6 A26 Test TEST7 C3 Test

THERMTRIP

THRMDA A24

THRMDC B25

TMS AB5 CMOS Input

TRDY# G2

TRST# AB6 CMOS Input

VCC A7

Buffer

Type

Common

Clock

Common

Clock

Open

Drain

Open

Drain

Power/

Other

Power/

Other

Common

Clock

Power/

Other

Direction

Input

Output

Input

Table 10. Pin Name Listing

Signal

Pin Name Pin #

VCC A9

VCC A10

VCC A12

VCC A13

VCC A15

VCC A17

VCC A18

VCC A20

VCC AA7

VCC AA9

VCC AA10

VCC AA12

VCC AA13

VCC AA15

VCC AA17

VCC AA18

VCC AA20

VCC AB7

VCC AB9

VCC AB10

VCC AB12

VCC AB14

Buffer

Type

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Direction

44 Datasheet

Package Mechanical Specifications and Pin Information

Table 10. Pin Name Listing

Pin Name Pin #

VCC AB15

VCC AB17

VCC AB18

VCC AB20

VCC AC7

VCC AC9

VCC AC10

VCC AC12

VCC AC13

VCC AC15

VCC AC17

VCC AC18

VCC AD7

VCC AD9

VCC AD10

VCC AD12

VCC AD14

VCC AD15

VCC AD17

VCC AD18

VCC AE9

VCC AE10

Signal Buffer

Type

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Direction

Table 10. Pin Name Listing

Pin Name Pin #

VCC AE12

VCC AE13

VCC AE15

VCC AE17

VCC AE18

VCC AE20

VCC AF9

VCC AF10

VCC AF12

VCC AF14

VCC AF15

VCC AF17

VCC AF18

VCC AF20

VCC B7

VCC B9

VCC B10

VCC B12

VCC B14

VCC B15

VCC B17

VCC B18

Signal Buffer

Type

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Direction

Datasheet 45

Package Mechanical Specifications and Pin Information

Table 10. Pin Name Listing

Signal

Pin Name Pin #

VCC B20

VCC C9

VCC C10

VCC C12

VCC C13

VCC C15

VCC C17

VCC C18

VCC D9

VCC D10

VCC D12

VCC D14

VCC D15

VCC D17

VCC D18

VCC E7

VCC E9

VCC E10

VCC E12

VCC E13

VCC E15

VCC E17

Buffer

Type

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Direction

Table 10. Pin Name Listing

Signal

Pin Name Pin #

VCC E18

VCC E20

VCC F7

VCC F9

VCC F10

VCC F12

VCC F14

VCC F15

VCC F17

VCC F18

VCC F20

VCCA B26

VCCA C26

VCCP G21

VCCP J6

VCCP J21

VCCP K6

VCCP K21

VCCP M6

VCCP M21

VCCP N6

VCCP N21

Buffer

Type

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Direction

46 Datasheet

Package Mechanical Specifications and Pin Information

Table 10. Pin Name Listing

Pin Name Pin #

VCCP R6

VCCP R21

VCCP T6

VCCP T21

VCCP V6

VCCP V21

VCCP W21

VCCSENSE AF7

VID[0] AD6 CMOS Output VID[1] AF5 CMOS Output VID[2] AE5 CMOS Output VID[3] AF4 CMOS Output VID[4] AE3 CMOS Output VID[5] AF3 CMOS Output VID[6] AE2 CMOS Output

VSS A2

VSS A4

VSS A8

VSS A11

VSS A14

VSS A16

VSS A19

VSS A23

VSS A25

Signal Buffer

Type

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Direction

Table 10. Pin Name Listing

Pin Name Pin #

VSS AA2

VSS AA5

VSS AA8

VSS AA11

VSS AA14

VSS AA16

VSS AA19

VSS AA22

VSS AA25

VSS AB1

VSS AB4

VSS AB8

VSS AB11

VSS AB13

VSS AB16

VSS AB19

VSS AB23

VSS AB26

VSS AC3

VSS AC6

VSS AC8

VSS AC11

Signal Buffer

Type

Power/

Other

Power/

Other

Power/

other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Direction

Datasheet 47

Package Mechanical Specifications and Pin Information

Table 10. Pin Name Listing

Signal

Pin Name Pin #

VSS AC14

VSS AC16

VSS AC19

VSS AC21

VSS AC24

VSS AD2

VSS AD5

VSS AD8

VSS AD11

VSS AD13

VSS AD16

VSS AD19

VSS AD22

VSS AD25

VSS AE1

VSS AE4

VSS AE8

VSS AE11

VSS AE14

VSS AE16

VSS AE19

VSS AE23

Buffer

Type

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Direction

Table 10. Pin Name Listing

Signal

Pin Name Pin #

VSS AE26

VSS AF2

VSS AF6

VSS AF8

VSS AF11

VSS AF13

VSS AF16

VSS AF19

VSS AF21

VSS AF25

VSS B6

VSS B8

VSS B11

VSS B13

VSS B16

VSS B19

VSS B21

VSS B24

VSS C2

VSS C5

VSS C8

VSS C11

Buffer

Type

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Direction

48 Datasheet

Package Mechanical Specifications and Pin Information

Table 10. Pin Name Listing

Pin Name Pin #

VSS C14

VSS C16

VSS C19

VSS C22

VSS C25

VSS D1

VSS D4

VSS D8

VSS D11

VSS D13

VSS D16

VSS D19

VSS D23

VSS D26

VSS E3

VSS E6

VSS E8

VSS E11

VSS E14

VSS E16

VSS E19

VSS E21

Signal Buffer

Type

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Direction

Table 10. Pin Name Listing

Pin Name Pin #

VSS E24

VSS F2

VSS F5

VSS F8

VSS F11

VSS F13

VSS F16

VSS F19

VSS F22

VSS F25

VSS G1

VSS G4

VSS G23

VSS G26

VSS H3

VSS H6

VSS H21

VSS H24

VSS J2

VSS J5

VSS J22

VSS J25

Signal Buffer

Type

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Direction

Datasheet 49

Package Mechanical Specifications and Pin Information

Table 10. Pin Name Listing

Signal

Pin Name Pin #

VSS K1

VSS K4

VSS K23

VSS K26

VSS L3

VSS L6

VSS L21

VSS L24

VSS M2

VSS M5

VSS M22

VSS M25

VSS N1

VSS N4

VSS N23

VSS N26

VSS P3

VSS P6

VSS P21

VSS P24

VSS R2

VSS R5

Buffer

Type

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Direction

Table 10. Pin Name Listing

Signal

Pin Name Pin #

VSS R22

VSS R25

VSS T1

VSS T4

VSS T23

VSS T26

VSS U3

VSS U6

VSS U21

VSS U24

VSS V2

VSS V5

VSS V22

VSS V25

VSS W1

VSS W4

VSS W23

VSS W26

VSS Y3

VSS Y6

Buffer

Type

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Power/

Other

Direction

50 Datasheet

Package Mechanical Specifications and Pin Information

Table 10. Pin Name Listing

Pin Name Pin #

VSS Y21

VSS Y24

VSSSENSE AE7

Signal Buffer

Type

Power/

Other

Power/

Other

Power/

Other

Direction

Output

Table 11. Pin # Listing

Pin # Pin Name

A2 VSS Power/Other A3 SMI# CM OS Input A4 VSS Power/Other A5 FERR# Open Drain Output A6 A20M# CMOS Input A7 VCC Power/Other A8 VSS Power/Other

A9 VCC Power/Other A10 VCC Power/Other A11 VSS Power/Other A12 VCC Power/Other A13 VCC Power/Other A14 VSS Power/Other A15 VCC Power/Other A16 VSS Power/Other A17 VCC Power/Other A18 VCC Power/Other A19 VSS Power/Other A20 VCC Power/Other A21 BCLK[1] Bus Clock Input A22 BCLK[0] Bus Clock Input A23 VSS Power/Other A24 THRMDA Power/Other A25 VSS Power/Other A26 TEST6 Test

AA1 COMP[2] Power/Other AA2 VSS Power/Other AA3 A[35]# Source Synch

AA4 A[33]# Source Synch AA5 VSS Power/Other

AA6 TDI CMOS Input AA7 VCC Power/Other AA8 VSS Power/other AA9 VCC Power/Other

AA10 VCC Power/Other AA11 VSS Power/Other AA12 VCC Power/Other

Signal Buffer

Type

Direction

Input/

Output

Input/

Output

Input/

Output

Datasheet 51

Package Mechanical Specifications and Pin Information

Table 11. Pin # Listing

Pin # Pin Name

AA13 VCC Power/Other AA14 VSS Power/Other AA15 VCC Power/Other AA16 VSS Power/Other AA17 VCC Power/Other AA18 VCC Power/Other AA19 VSS Power/Other AA20 VCC Power/Other

AA21 D[50]# Source Synch AA22 VSS Power/Other AA23 D[45]# Source Synch

AA24 D[46]# Source Synch AA25 VSS Power/Other AA26

AB1 VSS Power/Other AB2 A[34]# Source Synch AB3 TDO Open Drain Output

AB4 VSS Power/Other AB5 TMS CMOS Input AB6 TRST# CMOS Input AB7 VCC Power/Other AB8 VSS Power/Other

AB9 VCC Power/Other AB10 VCC Power/Other AB11 VSS Power/Other AB12 VCC Power/Other AB13 VSS Power/Other AB14 VCC Power/Other AB15 VCC Power/Other AB16 VSS Power/Other AB17 VCC Power/Other AB18 VCC Power/Other AB19 VSS Power/Other AB20 VCC Power/Other

AB21 D[52]# Source Synch

DSTBP[2]

Signal Buffer

Type

Source Synch

Direction

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Table 11. Pin # Listing

Pin # Pin Name

AB22 D[51]# Source Synch AB23 VSS Power/Other AB24 D[33]# Source Synch

AB25 D[47]# Source Synch AB26 VSS Power/Other

AC1 PREQ# Common Clock Input AC2 PRDY# Common Clock Output AC3 VSS Power/Other

AC4 BPM[3]# Common Clock AC5 TCK CMOS Input

AC6 VSS Power/Other AC7 VCC Power/Other AC8 VSS Power/Other

AC9 VCC Power/Other AC10 VCC Power/Other AC11 VSS Power/Other AC12 VCC Power/Other AC13 VCC Power/Other AC14 VSS Power/Other AC15 VCC Power/Other AC16 VSS Power/Other AC17 VCC Power/Other AC18 VCC Power/Other AC19 VSS Power/Other

AC20 DINV[3]# Source Synch AC21 VSS Power/Other AC22 D[60]# Source Synch

AC23 D[63]# Source Synch AC24 VSS Power/Other AC25 D[57]# Source Synch

AC26 D[53]# Source Synch

AD1 BPM[2]# Common Clock Output

AD2 VSS Power/Other

Signal Buffer

Type

Direction

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

52 Datasheet

Package Mechanical Specifications and Pin Information

Table 11. Pin # Listing

Pin # Pin Name

AD3 BPM[1]# Common Clock Output AD4 BPM[0]# Common Clock AD5 VSS Power/Other

AD6 VID[0] CMOS Output AD7 VCC Power/Other AD8 VSS Power/Other

AD9 VCC Power/Other AD10 VCC Power/Other AD11 VSS Power/Other AD12 VCC Power/Other AD13 VSS Power/Other AD14 VCC Power/Other AD15 VCC Power/Other AD16 VSS Power/Other AD17 VCC Power/Other AD18 VCC Power/Other AD19 VSS Power/Other

AD20 D[54]# Source Synch

AD21 D[59]# Source Synch AD22 VSS Power/Other AD23 D[61]# Source Synch

AD24 D[49]# Source Synch AD25 VSS Power/Other

AD26 GTLREF Power/Other Input

AE1 VSS Power/Other AE2 VID[6] CMOS Output AE3 VID[4] CMOS Output AE4 VSS Power/Other AE5 VID[2] CMOS Output AE6 PSI# CMOS Output AE7 VSSSENSE Power/Other Output AE8 VSS Power/Other

AE9 VCC Power/Other AE10 VCC Power/Other AE11 VSS Power/Other AE12 VCC Power/Other

Signal Buffer

Type

Direction

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Table 11. Pin # Listing

Pin # Pin Name

AE13 VCC Power/Other AE14 VSS Power/Other AE15 VCC Power/Other AE16 VSS Power/Other AE17 VCC Power/Other AE18 VCC Power/Other AE19 VSS Power/Other AE20 VCC Power/Other

AE21 D[58]# Source Synch

AE22 D[55]# Source Synch AE23 VSS Power/Other AE24 D[48]# Source Synch

AE25 AE26 VSS Power/Other

AF10 VCC Power/Other AF11 VSS Power/Other AF12 VCC Power/Other AF13 VSS Power/Other AF14 VCC Power/Other AF15 VCC Power/Other AF16 VSS Power/Other AF17 VCC Power/Other AF18 VCC Power/Other AF19 VSS Power/Other AF20 VCC Power/Other AF21 VSS Power/Other

DSTBN[3]

AF1 TEST5 Test AF2 VSS Power/Other AF3 VID[5] CMOS Output AF4 VID[3] CMOS Output AF5 VID[1] CMOS Output AF6 VSS Power/Other

VCCSENS

AF7 AF8 VSS Power/Other

AF9 VCC Power/Other

Signal Buffer

Type

Source Synch

Power/Other

Direction

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Datasheet 53

Package Mechanical Specifications and Pin Information

Table 11. Pin # Listing

Pin # Pin Name

AF22 D[62]# Source Synch

AF23 D[56]# Source Synch

AF24 AF25 VSS Power/Other

AF26 TEST4 Test

DSTBP[3]

B2 RSVD Reserved B3 INIT# CMOS Input B4 LINT1 CMOS Input B5 DPSLP# CMOS Input B6 VSS Power/Other B7 VCC Power/Other B8 VSS Power/Other

B9 VCC Power/Other B10 VCC Power/Other B11 VSS Power/Other B12 VCC Power/Other B13 VSS Power/Other B14 VCC Power/Other B15 VCC Power/Other B16 VSS Power/Other B17 VCC Power/Other B18 VCC Power/Other B19 VSS Power/Other B20 VCC Power/Other B21 VSS Power/Other B22 BSEL[0] CMOS Output B23 BSEL[1] CMOS Output B24 VSS Power/Other B25 THRMDC Power/Other B26 VCCA Power/Other

C1 RESET# Common Clock Input

C2 VSS Power/Other

C3 TEST7 Test

C4 IGNNE# CMOS Input

C5 VSS Power/Other

C6 LINT0 CMOS Input

THERMTRI

Signal Buffer

Type

Source Synch

Open Drain Output

Direction

Input/

Output

Input/

Output

Input/

Output

Table 11. Pin # Listing

Pin # Pin Name

C8 VSS Power/Other

C9 VCC Power/Other C10 VCC Power/Other C11 VSS Power/Other C12 VCC Power/Other C13 VCC Power/Other C14 VSS Power/Other C15 VCC Power/Other C16 VSS Power/Other C17 VCC Power/Other C18 VCC Power/Other C19 VSS Power/Other C20 DBR# CMOS Output C21 BSEL[2] CMOS Output C22 VSS Power/Other C23 TEST1 Test C24 TEST3 Test C25 VSS Power/Other C26 VCCA Power/Other

D1 VSS Power/Other D2 RSVD Reserved D3 RSVD Reserved D4 VSS Power/Other D5 STPCLK# CMOS Input D6 PWRGOOD CMOS Input D7 SLP# CMOS Input D8 VSS Power/Other

D9 VCC Power/Other D10 VCC Power/Other D11 VSS Power/Other D12 VCC Power/Other D13 VSS Power/Other D14 VCC Power/Other D15 VCC Power/Other D16 VSS Power/Other D17 VCC Power/Other D18 VCC Power/Other D19 VSS Power/Other D20 IERR# Open Drain Output

Signal Buffer

Type

Direction

54 Datasheet

Package Mechanical Specifications and Pin Information

Table 11. Pin # Listing

Pin # Pin Name

D21 D22 RSVD Reserved

D23 VSS Power/Other D24 DPWR# Common Clock D25 TEST2 Test

D26 VSS Power/Other

PROCHOT

E1 DBSY# Common Clock

E2 BNR# Common Clock E3 VSS Power/Other E4 HITM# Common Clock E5 DPRSTP# CMOS Input

E6 VSS Power/Other E7 VCC Power/Other E8 VSS Power/Other

E9 VCC Power/Other E10 VCC Power/Other E11 VSS Power/Other E12 VCC Power/Other E13 VCC Power/Other E14 VSS Power/Other E15 VCC Power/Other E16 VSS Power/Other E17 VCC Power/Other E18 VCC Power/Other E19 VSS Power/Other E20 VCC Power/Other E21 VSS Power/Other

E22 D[0]# Source Synch

E23 D[7]# Source Synch E24 VSS Power/Other E25 D[6]# Source Synch

E26 D[2]# Source Synch

F1 BR0# Common Clock

Signal Buffer

Type

Open Drain

Direction

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Table 11. Pin # Listing

Pin # Pin Name

F2 VSS Power/Other F3 RS[0]# Common Clock Input F4 RS[1]# Common Clock Input F5 VSS Power/Other F6 RSVD Reserved F7 VCC Power/Other F8 VSS Power/Other

F9 VCC Power/Other F10 VCC Power/Other F11 VSS Power/Other F12 VCC Power/Other F13 VSS Power/Other F14 VCC Power/Other F15 VCC Power/Other F16 VSS Power/Other F17 VCC Power/Other F18 VCC Power/Other F19 VSS Power/Other F20 VCC Power/Other

F21 DRDY# Common Clock F22 VSS Power/Other F23 D[4]# Source Synch

F24 D[1]# Source Synch F25 VSS Power/Other F26 D[13]# Source Synch

G1 VSS Power/Other G2 TRDY# Common Clock Input G3 RS[2]# Common Clock Input G4 VSS Power/Other G5 BPRI# Common Clock Input

G6 HIT# Common Clock G21 VCCP Power/Other G22 D[3]# Source Synch G23 VSS Power/Other G24 D[9]# Source Synch

Signal Buffer

Type

Direction

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

55 Datasheet

Package Mechanical Specifications and Pin Information

Table 11. Pin # Listing

Pin # Pin Name

G25 D[5]# Source Synch G26 VSS Power/Other

H1 ADS# Common Clock

H2 REQ[1]# Source Synch H3 VSS Power/Other H4 LOCK# Common Clock H5 DEFER# Common Clock Input

H6 VSS Power/Other

H21 VSS Power/Other H22 D[12]# Source Synch

H23 D[15]# Source Synch H24 VSS Power/Other H25 DINV[0]# Source Synch

H26

DSTBP[0]

# J1 A[9]# Source Synch J2 VSS Power/Other J3 REQ[3]# Source Synch

J4 A[3]# Source Synch J5 VSS Power/Other

J6 VCCP Power/Other

J21 VCCP Power/Other J22 VSS Power/Other

J23 D[11]# Source Synch

J24 D[10]# Source Synch J25 VSS Power/Other

DSTBN[0]

J26

K1 VSS Power/Other K2 REQ[2]# Source Synch

Signal Buffer

Type

Source Synch

Direction

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Table 11. Pin # Listing

Pin # Pin Name

K3 REQ[0]# Source Synch K4 VSS Power/Other K5 A[6]# Source Synch K6 VCCP Power/Other

K21 VCCP Power/Other K22 D[14]# Source Synch K23 VSS Power/Other K24 D[8]# Source Synch

K25 D[17]# Source Synch K26 VSS Power/Other

L1 REQ[4]# Source Synch

L2 A[13]# Source Synch L3 VSS Power/Other L4 A[5]# Source Synch

L5 A[4]# Source Synch L6 VSS Power/Other

L21 VSS Power/Other L22 D[22]# Source Synch

L23 D[20]# Source Synch L24 VSS Power/Other L25 D[29]# Source Synch

DSTBN[1]

L26

M1 M2 VSS Power/Other M3 A[7]# Source Synch M4 RSVD Reserved

M5 VSS Power/Other M6 VCCP Power/Other

M21 VCCP Power/Other

ADSTB[0]

Signal Buffer

Type

Source Synch

Direction

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Datasheet 56

Package Mechanical Specifications and Pin Information

Table 11. Pin # Listing

Pin # Pin Name

M22 VSS Power/Other M23 D[23]# Source Synch

M24 D[21]# Source Synch M25 VSS Power/Other M26

N21 VCCP Power/Other N22 D[16]# Source Synch N23 VSS Power/Other N24 DINV[1]# Source Synch

N25 D[31]# Source Synch N26 VSS Power/Other

DSTBP[1]

N1 VSS Power/Other N2 A[8]# Source Synch

N3 A[10]# Source Synch N4 VSS Power/Other

N5 RSVD Reserved N6 VCCP Power/Other

P1 A[15]# Source Synch

P2 A[12]# Source Synch P3 VSS Power/Other P4 A[14]# Source Synch

P5 A[11]# Source Synch P6 VSS Power/Other

P21 VSS Power/Other P22 D[26]# Source Synch

P23 D[25]# Source Synch P24 VSS Power/Other P25 D[24]# Source Synch

Signal Buffer

Type

Source Synch

Direction

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Table 11. Pin # Listing

Pin # Pin Name

P26 D[18]# Source Synch

R1 A[16]# Source Synch R2 VSS Power/Other R3 A[19]# Source Synch

R4 A[24]# Source Synch R5 VSS Power/Other

R6 VCCP Power/Other R21 VCCP Power/Other R22 VSS Power/Other

R23 D[19]# Source Synch

R24 D[28]# Source Synch R25 VSS Power/Other R26 COMP[0] Power/Other

T1 VSS Power/Other

T2 RSVD Reserved

T3 A[26]# Source Synch

T4 VSS Power/Other

T5 A[25]# Source Synch

T6 VCCP Power/Other

T21 VCCP Power/Other T22 D[37]# Source Synch T23 VSS Power/Other T24 D[27]# Source Synch

T25 D[30]# Source Synch T26 VSS Power/Other

U1 A[23]# Source Synch

U2 A[30]# Source Synch

U3 VSS Power/Other

U4 A[21]# Source Synch

Signal Buffer

Type

Direction

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Datasheet 57

Package Mechanical Specifications and Pin Information

Table 11. Pin # Listing

Pin # Pin Name

U5 A[18]# Source Synch U6 VSS Power/Other

U21 VSS Power/Other U22 DINV[2]# Source Synch

U23 D[39]# Source Synch U24 VSS Power/Other U25 D[38]# Source Synch

U26 COMP[1] Power/Other

ADSTB[1]

V1 V2 VSS Power/Other

V3 RSVD Reserved V4 A[31]# Source Synch V5 VSS Power/Other

V6 VCCP Power/Other V21 VCCP Power/Other V22 VSS Power/Other

V23 D[36]# Source Synch

V24 D[34]# Source Synch V25 VSS Power/Other V26 D[35]# Source Synch

W1 VSS Power/Other W2 A[27]# Source Synch

W3 A[32]# Source Synch W4 VSS Power/Other W5 A[28]# Source Synch

W6 A[20]# Source Synch W21 VCCP Power/Other W22 D[41]# Source Synch W23 VSS Power/Other

Signal Buffer

Type

Source Synch

Direction

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Table 11. Pin # Listing

Pin # Pin Name

W24 D[43]# Source Synch

W25 D[44]# Source Synch W26 VSS Power/Other

Y1 COMP[3] Power/Other

Y2 A[17]# Source Synch Y3 VSS Power/Other Y4 A[29]# Source Synch

Y5 A[22]# Source Synch Y6 VSS Power/Other

Y21 VSS Power/Other Y22 D[32]# Source Synch

Y23 D[42]# Source Synch Y24 VSS Power/Other Y25 D[40]# Source Synch

DSTBN[2]

Y26

Signal Buffer

Type

Source Synch

Direction

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

58 Datasheet

Package Mechanical Specifications and Pin Information

Signals Associated Strobe

REQ[4:0]#, A[16:3]# ADSTB[0]# A[35:17]# ADSTB[1]#

4.3 Alphabetical Signals Reference

Table 12. Signal Description (Sheet 1 of 8)

Name Type Description

A[35:3]# (Address) define a 2 space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins tr an sm it

A[35:3]#

A20M# Input

ADS#

ADSTB[1:0]#

Input/

Output

Input/

Output

Input/

Output

transaction type information. These signals must connect the appropriate pins of both agents on the processor FSB. A[35:3]# are source-synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps, which are sampled before RESET# is deasserted.

If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is only supported in real mode.

A20M# is an asynchronous signal. However, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the TRDY# assertion of the corresponding input/ output Write bus transaction.

ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction.

Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below.

-byte physical memory address

BCLK[1:0] Input

BNR#

BPM[2:1]#

BPM[3,0]#

Datasheet 59

Input/

Output

Input/

Output

The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB agents must receive these signals to drive their outputs and latch their inputs.

All external timing parameters are specified with respect to the rising edge of BCLK0 crossing V

BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.

BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all processor FSB agents.This includes debug or performance monitoring tools.

CROSS

Package Mechanical Specifications and Pin Information

Quad-Pumped Signal Groups

Data Group

DSTBN#/

DSTBP#

DINV#

D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3

Table 12. Signal Description (Sheet 2 of 8)

Name Type Description

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of both FSB agents. Observing BPRI# active (as asserted by the priority agent) causes

BPRI# Input

BR0#

BSEL[2:0] Output

COMP[3:0] Analog

Input/

Output

the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#.

BR0# is used by the processor to request the bus. The arbitration is done between the processor (Symmetric Agent) and GMCH (High Priority Agent).

BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. Table 3 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency.

COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors.

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer.

D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#.

D[63:0]#

DBR# Output

DBSY#

60 Datasheet

Input/

Output

Input/

Output

Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high.

DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal.

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both FSB agents.

Package Mechanical Specifications and Pin Information

DINV[3:0]# Assignment To Data Bus

Bus Signal Data Bus Signals

DINV[3]# D[63:48]# DINV[2]# D[47:32]# DINV[1]# D[31:16]# DINV[0]# D[15:0]#

Signals Associated Strobe

D[15:0]#, DINV[0]# DSTBN[0]# D[31:16]#, DINV[1]# DSTBN[1]# D[47:32]#, DINV[2]# DSTBN[2]# D[63:48]#, DINV[3]# DSTBN[3]#

Table 12. Signal Description (Sheet 3 of 8)

Name Type Description

DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is

DEFER# Input

normally the responsibility of the addressed memory or input/ output agent. This signal must connect the appropriate pins of both FSB agents.

DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle.

DINV[3:0]#

DPRSTP# Input

DPSLP# Input

DPWR#

DRDY#

Input/

Output

Input/

Output

Input/

Output

DPRSTP#, when asserted on the platform, causes the processor to transition from the Deep Sleep State to the Deeper Sleep state or Deep Power Down Technology (C6) state. To return to the Deep Sleep State, DPRSTP# must be deasserted. DPRSTP# is driven by the ICH9M.

DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state. T o return to the Sleep State, DPSLP# must be deasserted. DPSLP# is driven by the ICH9M.

DPWR# is a control signal used by the chipset to reduce power on the processor data bus input buffers. The processor drives this pin during dynamic FSB frequency switching

DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents.

Data strobe used to latch in D[63:0]#.

DSTBN[3:0]#

Datasheet 61

Input/

Output

Package Mechanical Specifications and Pin Information

Signals Associated Strobe

D[15:0]#, DINV[0]# DSTBP[0]# D[31:16]#, DINV[1]# DSTBP[1]# D[47:32]#, DINV[2]# DSTBP[2]# D[63:48]#, DINV[3]# DSTBP[3]#

Table 12. Signal Description (Sheet 4 of 8)

Name Type Description

Data strobe used to latch in D[63:0]#.

DSTBP[3:0]#

Input/

Output

FERR#/PBE# Output

GTLREF Input

HIT#

HITM#

Input/

Output

Input/

Output

IERR# Output

IGNNE# Input

FERR# (Floating-point Error)/PBE# (Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel® 387 coprocessor, and is included for compatibility with systems using Microsoft MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event.

For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to Volumes 3A and 3B of the Intel® 64 and IA-32

Architectures Software Developer's Manuals and the Intel® Processor Identification and CPUID Instruction application note.

GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 V receivers to determine if a signal is a logical 0 or logical 1.

. GTLREF is used by the AGTL+

CCP

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall that can be continued by reasserting HIT# and HITM# together.

IERR# (Internal Error) is asserted by the processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute non-control floating-point instructions. If IGNNE# is deasserted, the processor generates an exc eption on a non-co ntrol floating-point instruction i f a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the TRDY# assertion of the corresponding input/ output Write bus transaction.

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Package Mechanical Specifications and Pin Information

Table 12. Signal Description (Sheet 5 of 8)

Name Type Description

INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT#

INIT# Input

LINT[1:0] Input

LOCK#

PRDY# Output

PREQ# Input

PROCHOT#

PSI# Output

Input/

Output

Input/

Output

assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the TRDY# assertion of the corresponding input/output write bus transaction. INIT# must connect the appropriate pins of both FSB agents.

If INIT# is sampled active on the active-to-inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST)

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward-compatible with the signals of those names on the Pentium processor. Both signals are asynchronous.

Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/ INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration.

LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of both FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction.

When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock.

Probe Ready signal used by debug tools to determine processor debug readiness.

Probe Request signal used by debug tools to request debug operation of the processor.

As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active until the system deasserts PROCHOT#.

By default PROCHOT# is configured as an output. The processor must be enabled via the BIOS for PROCHOT# to be configured as bidirectional.

This signal may require voltage translation on the motherboard. Processor Power Status Indicator signal. This signal is asserted

when the processor is both in the normal stat e (HFM to LF M) and in lower power states (Deep Sleep and Deeper Sleep).

Datasheet 63

Package Mechanical Specifications and Pin Information

Table 12. Signal Description (Sheet 6 of 8)

Name Type Description

PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal remains low (capable of sinking leakage

PWRGOOD Input

REQ[4:0]#

Input/

Output

RESET# Input

RS[2:0]# Input

Reserved/

RSVD

Connect

SLP# Input

SMI# Input

current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state .

The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation.

REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#.

Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches with ou t writ ing bac k any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after V proper specifications. On observing active RESET#, both FSB agents will deassert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted.

There is a 55  (nominal) on die pull-up resistor on this signal. RS[2:0]# (Response St atus) are driv en b y the res ponse agent (t he

agent responsible for completion of the current transaction), and must connect the appropriate pins of both FSB agents.

These pins are RESERVED and must be left unconnected on the board. However, it is recommended that routing channels to these pins on the board be kept open for possible future use.

SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to StopGrant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state.

SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enters System Management Mode (SMM). An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler.

If an SMI# is asserted during the deassertion of RESET#, then the processor will tristate its outputs.

and BCLK have reached their

64 Datasheet

Package Mechanical Specifications and Pin Information

Table 12. Signal Description (Sheet 7 of 8)

Name Type Description

STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a StopGrant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units.

STPCLK# Input

TCK Input

TDI Input

TDO Output

TEST1, TEST2, TEST3, TEST4,

Input TEST5, TEST6 TEST7

THRMDA Other Thermal Diode Anode. THRMDC O ther Thermal Diode Cathode.

THERMTRIP# Output

TMS Input

TRDY# Input

TRST# Input VCC Input Processor core power supply.

VSS Input Processor core ground node. VCCA Input VCCA provides isolated power for the internal processor core PLLs VCCP Input Processor I/O Power Supply.

The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resume s execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.

TCK (Test Clock) provides the clock input for the processor T est Bus (also known as the Test Access Port).

TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support.

TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support.

Refer to the appropriate platform design guide for further TEST1, TEST2, TEST3, TEST4, TEST5, TEST6 and TEST7 termination requirements and implementation details.

The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125 °C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin.

TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both FSB agents.

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset.

Datasheet 65

Package Mechanical Specifications and Pin Information

Table 12. Signal Description (Sheet 8 of 8)

Name Type Description

VCCSENSE together with VSSSENSE are voltage feedback signals

VCCSENSE Outpu t

VID[6:0] Output

VSSSENSE Output

that control the 2.1 m loadline at the processor die. It should be used to sense voltage near the silicon with little noise.

VID[6:0] (Voltage ID) pi ns are used to support automatic selection of power supply voltages (V of processors, these are CMOS signals that are driven by the processor. The voltage supply for these pins must be valid before the VR can supply V must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. See Table 2 for definitions of these pins. The VR must supply the voltage that is requested by the pins, or disable itself.

VSSSENSE that control the 2.1-m loadline at the processor die. It should be used to sense ground near the silicon with little noise.

). Unlike some previous generations

to the processor. Conversely, the VR output

together with VCCSENSE are voltage feedback signals

66 Datasheet

Thermal Specifications and Design Considerations

5 Thermal Specifications and

Design Considerations

A complete thermal solution includes both component and system-level thermal management features. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed so the processor remains within the minimum and maximum junction temperature (T listed in the tables below

) specifications at the corresponding thermal design power (TDP) value

Caution: Operating the processor outside these operating limits may result in permanent

damage to the processor and potentially other components in the system.

Datasheet

Thermal Specifications and Design Considerations

Table 13. Power Specifications for the Pentium Processors

Symbol

TDP

Processor

Number

T4500 T4400 T4300 T4200

Core Frequency & Voltage

2.30 GHz & V

2.20 GHz & V

2.1 GHz & V

2.0 GHz & V

1.2 GHz & V

CCHFM

CCHFM CCHFM CCHFM CCLFM

Thermal Design

Power

35 35 35 17

Unit Notes

W1, 4, 5

Symbol Parameter Min Typ Max Unit Notes

AH,

SGNT

Auto Halt, Stop Grant Power at V

CCHFM

at V

CCLFM

——13.9

7.4

W2, 6

Sleep Power

SLP

at V at V

CCHFM CCLFM

——13.1

7.1

W2, 6

Deep Sleep Power

DSLP

at V at V

CCHFM CCLFM

——5.5

3.2

Junction Temperature 0 — 105 C3, 4

W2, 5, 7

NOTES:

1. The TDP specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can generate.

2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated.

3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T

4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications.

5. At Tj of 105

6. At Tj of 50

7. At Tj of 35

has been reached.

68 Datasheet

Thermal Specifications and Design Considerations

5.1 Monitoring Die Temperature

The processor incorporates three methods of monitoring die temperature:

•Thermal Diode

•Intel® Thermal Monitor

• Digital Thermal Sensor

5.1.1 Thermal Diode

Intel’s processors utilize an SMBus thermal sensor to read back the voltage/current characteristics of a substrate PNP transistor. Since these characteristics are a function of temperature, these parameters can be used to calculate silicon temperature values. For older silicon process technologies, it is possible to simplify the voltage/current and temperature relationships by treating the substrate transistor as though it were a simple diffusion diode. In this case, the assumption is that the beta of the transistor does not impact the calculated temperature values. The resultant “diode” model essentially predicts a quasi linear relationship between the base/emitter voltage differential of the PNP transistor and the applied temperature (one of the proportionality constants in this relationship is processor specific, and is known as the diode ideality factor). Realization of this relationship is accomplished with the SMBus thermal sensor that is connected to the transistor.

The processor, howe ver, is built on Intel’s advanced 45-nm processor technology. Due to this new processor technology, it is no longer possible to model the substrate transistor as a simple diode. To accurately calculate silicon temperature use a full bipolar junction transistor-type model. In this model, the voltage/current and temperature characteristics include an additional process dependant parameter which is known as the transistor “beta”. System designers should be aware that the current thermal sensors may not be configured to account for “beta” and should work with their SMB thermal sensor vendors to ensure they have a part capable of reading the thermal diode in BJT model.

Offset between the thermal diode-based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic mode activation of the thermal control circuit. This temperature offset must be considered when using the processor thermal diode to implement power management events. This offset is different than the diode Toffset value programmed into the processor Model-Specific Register (MSR).

Table 14 and Table 15 provide the diode interface and transistor model specifications.

Table 14. Thermal Diode Interface

Signal Name Pin/Ball Number Signal Description

THERMDA A24 Thermal diode anode THERMDC A25 Thermal diode cathode

Datasheet

Thermal Specifications and Design Considerations

Table 15. Thermal Diode Parameters Using Transistor Model

Symbol Parameter Min Typ Max Unit Notes

Beta 0.1 0.4 0.5 2, 3 R

NOTES:

1. Intel does not support or recommend operation of the thermal diode under reverse bias.

2. Characterized across a temperature range of 50-105°C.

3. Not 100% tested. Specified by design characterization.

4. The ideality factor, nQ, represents the deviation from ideal transistor model behavior as

Forward Bias Current 5 — 200 A1 Emitter Current 5 — 200 A1 Transistor Ideality 0.997 1.001 1.008 2, 3, 4

Series Resistance 3.0 4.5 7.0  2

exemplified by the equation for the collector current:

= IS * (e

where I base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute temperature (Kelvin).

= saturation current, q = electronic charge, VBE = voltage across the transistor

qVBE/nQkT

–1)

5.1.2 Intel® Thermal Monitor

The Intel Thermal Monitor helps control the processor temperature by activating the TCC (Thermal Control Circuit) when the processor silicon reaches its maximum operating temperature. The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable. Bus traffic is snooped in the normal manner and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active.

With a properly designed and characterized thermal solution, the TCC would only be activated for very short periods of time when running the most power-intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously.

The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to activate the TCC: automatic mode and on-demand mode. If both modes are activated, automatic mode takes precedence.

There are two automatic modes called Intel Thermal Monitor 1 (TM1) and Intel Thermal Monitor 2 (TM2). These modes are selected by writing values to the MSRs of the processor. After automatic mode is enabled, the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation.

When TM1 is enabled and a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. Cy cle times are processor speed-dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a non-critical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid

70 Datasheet

Thermal Specifications and Design Considerations

active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active.

When TM2 is enabled and a high temperature situation exists, the processor will perform an Enhanced Intel SpeedStep Technology transition to the LFM. When the processor temperature drops below the critical level, the processor will make an Enhanced Intel SpeedStep Technology transition to the last requested operating point. The processor also supports Enhanced Multi-Threaded Thermal Monitoring (EMTTM). EMTTM is a processor feature that enhances TM2 with a processor throttling algorithm known as Adaptive TM2. Adaptive TM2 transitions to intermediate operating points, rather than directly to the LFM, once the processor has reached its thermal limit and subsequently searches for the highest possible operating point. Please ensure this feature is enabled and supported in the BIOS. Also with EMTTM enabled, the oper ating system can request the processor to throttling to any point between Intel

Dynamic Acceleration Technology frequency and SuperLFM frequency as long as these features are enabled in the BIOS and supported by the processor.

The Intel Thermal Monitor automatic mode and Enhanced Multi-Threaded Thermal Monitoring must be enabled through BIOS for the processor to be operating within specifications. Intel recommends TM1 and TM2 be enabled on the

processors.

TM1, TM2 and EMTTM features are collectively referred to as Adaptive Thermal Monitoring features.

TM1 and TM2 can co-exist within the processor. If both TM1 and TM2 bits are enabled in the auto-throttle MSR, TM2 takes precedence over TM1. However, if Force TM1 over TM2 is enabled in MSRs via BIOS and TM2 is not sufficient to cool the processor below the maximum operating temperature, then TM1 will also activate to help cool down the processor.

If a processor load-based Enhanced Intel SpeedStep Technology transition (through MSR write) is initiated when a TM2 period is active, there are two possible results:

1. If the processor load-based Enhanced Intel SpeedStep T echnology transition target frequency is higher than the TM2 transition-based target frequency, the processor load-based transition will be deferred until the TM2 event has been completed.

2. If the processor load-based Enhanced Intel SpeedStep T echnology transition target frequency is lower than the TM2 transition-based target frequency, the processor will transition to the processor load-based Enhanced Intel SpeedStep Technology target frequency point.

The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC will be activated immediately independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the TCC via on-demand mode at the same time autom atic mode is enabled and a high temperature condition exists, automatic mode will take precedence.

An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active.

Datasheet

Thermal Specifications and Design Considerations

Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three MSR, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.

PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep, Deep Sleep, and Deeper Sleep low-power states, hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. If the platform thermal solution is not

able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low-power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low-power state and the processor junction temperature drops below the thermal trip point. However, PROCHOT# will de-assert for the duration of Deep Power Down Technology state (C6) residency.

If Thermal Monitor automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125 °C. At this point the THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3

In all cases the Intel Thermal Monitor feature must be enabled for the processor to remain within specification.

5.1.3 Digital Thermal Sensor

The processor also contains an on-die Digital Thermal Sensor (DTS) that can be read via an MSR (no I/O interface). Each core of the processor will have a unique digital thermal sensor whose temperature is accessible via the processor MSRs. The DTS is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the Thermal Monitor. The DTS is only valid while the processor is in the normal operating state (the Normal package level low-power state).

Unlike traditional thermal devices, the DTS outputs a temperature relative to the maximum supported operating temperature of the processor (T responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the DTS will always be at or below T Catastrophic temperature conditions are detectable via an Out Of Specification status bit. This bit is also part of the DTS MSR. When this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. The processor operation and code execution is not ensured once the activation of the Out of Specification status bit is set.

The DTS-relative temperature readout corresponds to the Thermal Monitor (TM1/TM2) trigger point. When the DTS indicates maximum processor core temperature has been reached, the TM1 or TM2 hardware thermal control mechanism will activate. The DTS and TM1/TM2 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power, mechanical and thermal attach, and software application. The system designer is required to use the DTS to ensure proper operation of the processor within its temperature operating specifications.

J,max

). It is the

J,max

72 Datasheet

Thermal Specifications and Design Considerations

Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details.

5.2 Out of Specification Detection

Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shutdown before the THERMTRIP# is activated. If the processor’s TM1 or TM2 are triggered and the temperature remains high, an Out Of Spec status and sticky bit are latched in the status MSR register and generates a thermal interrupt.

5.3 PROCHOT# Signal Pin

An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If TM1 or TM2 is enabled, then the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Refer to the an interrupt upon the assertion or deassertion o f PROCHOT#. Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details.

The processor implements a bi-directional PROCHOT# capability to allow system designs to protect various components from overheating situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components.

Only a single PROCHOT# pin exists at a package level of the processor. When either core's thermal sensor trips, PROCHOT# signal will be driven by the processor package. If only TM1 is enabled, PROCHOT# will be asserted regardless of which core is above its TCC temperature trip point, and both cores will have their core clocks modulated. If TM2 is enabled then, regardless of which core(s) are above the TCC temperature trip point, both cores will enter the lowest programmed TM2 performance state. It is important to note that Intel recommends both TM1 and TM2 to be enabled.

When PROCHOT# is driven by an external agent, if only TM1 is enabled on both cores, then both processor cores will have their core clocks modulated. If TM2 is enabled on both cores, then both processor cores will enter the lowest programmed TM2 performance state. It should be noted that Force TM1 on TM2, enabled via BIOS, does not have any effect on external PROCHOT#. If PROCHOT# is driven by an external agent when TM1, TM2, and Force TM1 on TM2 are all enabled, then the processor will still apply only TM2.

PROCHOT# may be used for thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR will cool down as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. With a properly designed and characterized thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very short periods

Datasheet

Thermal Specifications and Design Considerations

of time when running the most power-intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss.

74 Datasheet

Intel BX80532PG3200D, Pentium Series Datasheet

Specifications and Main Features

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