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Pentium Series
Datasheet
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Intel BX80532PG3200D, Pentium Series Datasheet

Intel® Pentium® Processor on 45-nm Process
Datasheet
For Platforms Based on Mobile Intel® 4 Series Express Chipset Family October 2009
Document Number: 322875-001EN
UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH T HE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications
enabled for IntelÆ 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information.
Enhanced Intel SpeedStep® Technology for specified units of this processor are available. See the Processor Spec Finder at http:// processorfinder.intel.com or contact your Intel representative for more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.
Intel, Pentium, Centrino, Intel Core Duo, Intel SpeedStep, MMX and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2008-2009, Intel Corporation. All rights reserved.
2 Datasheet
Contents
1Introduction..............................................................................................................7
1.1 Terminology .......................................................................................................8
1.2 References.........................................................................................................9
2 Low Power Features ................................................................................................11
2.1 Clock Control and Low-Power States....................................................................11
2.1.1 Core Low-Power State Descriptions...........................................................13
2.1.2 Package Low-power State Descriptions................................... .. ... .. .. .......... 14
2.2 Enhanced Intel SpeedStep® Technology ..............................................................17
2.3 Extended Low-Power States................................................................................18
2.4 FSB Low Power Enhancements............................................................................19
2.5 Processor Power Status Indicator (PSI-2) Signal.................................................... 19
3 Electrical Specifications........................................................................................... 21
3.1 Power and Ground Pins...................................................................................... 21
3.2 Decoupling Guidelines ........................................................................................21
3.2.1 VCC
3.2.2 FSB AGTL+ Decoupling ........................................................................... 21
3.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking...........................................21
3.3 Voltage Identification and Power Sequencing ........................................................22
3.4 Catastrophic Thermal Protection..........................................................................25
3.5 Reserved and Unused Pins.................................................................................. 25
3.6 FSB Frequency Select Signals (BSEL[2:0])............................................................25
3.7 FSB Signal Groups............................................................................................. 26
3.8 CMOS Signals...................................................................................................27
3.9 Maximum Ratings.............................................................................................. 27
3.10 Processor DC Specifications................................................................................28
4 Package Mechanical Specifications and Pin Information ..........................................33
4.1 Package Mechanical Specifications....................................................................... 33
4.2 Processor Pinout and Pin List .............................................................................. 36
4.3 Alphabetical Signals Reference............................................................................59
5 Thermal Specifications and Design Considerations .................................................. 67
5.1 Monitoring Die Temperature ...............................................................................69
5.1.1 Thermal Diode....................................................................................... 69
5.1.2 Intel® Thermal Monitor........................................................................... 70
5.1.3 Digital Thermal Sensor............................................................................72
5.2 Out of Specification Detection .............................................................................73
5.3 PROCHOT# Signal Pin........................................................................................ 73
Decoupling......................................................................................21
Figures
1 Core Low-Power States.............................................................................................12
2 Package Low-Power States........................................................................................13
3 Active VCC and ICC Loadline for Pentium Processors.....................................................30
4 1-MB die Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)................................... 34
5 1-MB Die Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) .................................. 35
6 Processor Pinout (Top Package View, Left Side)............................................................36
7 Processor Pinout (Top Package View, Right Side)..................................... .. .. ... .. ............ 37
Datasheet 3
Tables
1 Coordination of Core Low-Power States at the Package Level..........................................13
2 Voltage Identification Definition..................................................................................22
3 BSEL[2:0] Encoding for BCLK Frequency............. .........................................................25
4 FSB Pin Groups ........................................................................................................26
5 Processor Absolute Maximum Ratings..........................................................................27
6 Voltage and Current Specifications for the Pentium Processors...................................... ..29
7 AGTL+ Signal Group DC Specifications ........................................................................31
8 CMOS Signal Group DC Specifications..........................................................................32
9 Open Drain Signal Group DC Specifications ..................................................................32
10 Pin Name Listing ......................................................................................................38
11 Pin # Listing............................................................................................................51
12 Signal Description................. ....................................................................................59
13 Power Specifications for the Pentium Processors ...........................................................68
14 Thermal Diode Interface............................................................................................69
15 Thermal Diode Parameters Using Transistor Model ........................................................70
4 Datasheet
Revision History
Document
Number
322875 -001 Initial Draft October 2009
Revision
Number
Description Date
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Datasheet 5
6 Datasheet
Introduction
1 Introduction
This document contains electrical, mechanical and thermal specifications for the following processors:
• The Intel® Pentium® support the Mobile Intel® 4 Series Express Chipset and Intel® ICH9M I/O controller.
Notes: In this document
1. Intel Pentium processor are referred to as the processor
2. Mobile Intel 4 Series Express Chipset is referred as the GMCH.
Key features include:
• Dual-core processor for mobile with enhanced performance
• Supports Intel architecture with Intel® Wide Dynamic Execution
• Supports L1 cache-to-cache (C2C) transfer
• On-die, primary 32-KB instruction cache and 32-KB, write-back data cache in each core
• The processor have an on-die, 1-MB second-level, shared cache with Advanced Transfer Cache architecture
• Streaming SIMD extensions 2 (SSE2), streaming SIMD extensions 3 (SSE3), and supplemental streaming SIMD extensions 3 (SSSE3)
• Enhanced Intel SpeedStep® Technology
• The processors are offered at 800-MHz, source-synchronous front side bus (FSB)
• Digital thermal sensor (DTS)
• Intel® 64 architecture
• Enhanced Multi-Threaded Thermal Management (EMTTM)
• Processor offered in Micro-FCPGA packaging technology
• Execute Disable Bit support for enhanced security
• Half ratio support (N/2) for core to bus ratio
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7
1.1 Terminology
Term Definition
A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high,
#
Front Side Bus (FSB)
AGTL+
Storage Conditions
Processor Core
Execute Disable Bit
Intel® 64 Technology
a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex “A” , and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
Refers to the interface between the processor and system core logic (also known as the chipset components).
Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on some Intel processors.
Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.
Processor core die with integrated L1 and L2 cache. All AC timing and signal integrity specifications are at the pads of the processor core.
The Execute Disable bit allows memory to be marked as executable or non­executable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals for more detailed information.
64-bit memory extensions to the IA-32 architecture.
Introduction
Half ratio support (N/2) for Core to Bus ratio
TDP Thermal Design Power. V
CC
V
SS
8 Datasheet
Intel Core 2 Duo processors and Intel Core 2 Extreme processors support the N/2 feature that allows having fractional core-to-bus ratios. This featur e provides the flexibility of having more frequency options and being able to have products with smaller frequency steps.
The processor core power supply. The processor ground.
Introduction
1.2 References
Material and concepts available in the following documents may be beneficial when reading this document.
Document
Intel® Pentium® Processor on 45-nm Technology Specification Update Mobile Intel® 4 Series Express Chipset Family Datasheet 320122 Mobile Intel® 4 Series Express Chipset Family Specification Update 320123 Intel® I/O Controller Hub 9 (ICH9)/ I/O Controller Hub 9M (ICH9M)
Datasheet Intel® I/O Controller Hub 9 (ICH9)/ I/O Controller Hub 9M (ICH9M)
Specification Update Intel® 64 and IA-32 Architectures Software Developer's Manuals
Volume 1: Basic Architecture 253665 Volume 2A: Instruction Set Reference, A-M 253666 Volume 2B: Instruction Set Reference, N-Z 253667 Volume 3A: System Programming Guide 253668 Volume 3B: System Programming Guide 253669
NOTE: Contact your Intel representative for the latest revision of this document.
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316973
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Introduction
10 Datasheet
Low Power Features
2 Low Power Features
2.1 Clock Control and Low-Power States
The processor supports low-power states both at the individual core level and the package level for optimal power management.
A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, low-power states. When both cores coincide in a common core low-power state, the central power management logic ensures the entire processor enters the respective package low­power state by initiating a P_LVLx (P_LVL2, P_LVL3) I/O read to the GMCH.
The processor implements two software interfaces for requesting low-power states: MWAIT instruction extensions with sub-state hints and P_L VLx reads to the ACPI P_BLK register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the processor and do not directly result in I/O reads on the processor FSB. The P_LVLx I/O Monitor address does not need to be set up before using the P_LVLx I/O read interface. The sub-state hints used for each P_LVLx read can be configured through the IA32_MISC_ENABLES model specific register (MSR).
If a core encounters a GMCH break event while STPCLK# is asserted, it asserts the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system logic that individual cores should return to the C0 state and the processor should return to the Normal state.
Figure 1 shows the core low-power states and Figure 2 shows the package low-power
states for the processor. Table 1 maps the core low-power states to package low-power states.
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Figure 1. Core Low-Power States
C2
†
C0
Stop
Grant
Core state
break
P_LVL2 or
MWAIT(C2)
C3
†
Core state
break
P_LVL3 or
MWAIT(C3)
C1/
MWAIT
Core state
break
MWAIT(C1)
C1/Auto
Halt
Halt break
HLT instruction
STPCLK#
de-asserted
STPCLK#
asserted
STPCLK#
de-asserted
STPCLK#
asserted
STPCLK#
de-asserted
STPCLK#
asserted
halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted) † — STPCLK# assertion and de-assertion have no effect if a core is in C2 or C3.
Low Power Features
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Low Power Features
Stop
Grant
Snoop
Normal
Stop
Grant
STPCLK# asserted
Snoop
serviced
Snoop occurs
Sleep
SLP# asserted
SLP# de-assertedSTPCLK# de-asserted
Deep Sleep
DPSLP# asserted
DPSLP# de-asserted
Figure 2. Package Low-Power States
Table 1. Coordination of Core Low-Power States at the Package Level
Package State Core1 State
Core0 State C0 C1
C0 Normal Normal Normal Normal
1
C1
Normal Normal Normal Normal C2 Normal Normal Stop-Grant Stop-Grant C3 Normal Normal Stop-Grant Deep Sleep
1
C2 C3
NOTE:
1. AutoHALT or MWAIT/C1.
2.1.1 Core Low-Power State Descriptions
2.1.1.1 Core C0 State
This is the normal operating state for cores in the processor.
2.1.1.2 Core C1/AutoHALT Powerdown State
C1/AutoHALT is a low-power state entered when a core executes the HALT instruction. The processor core will transition to the C0 state upon occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to immediately initialize itself.
A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.
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13
While in AutoHALT Powerdown state, the dual-core processor will process bus snoops and snoops from the other core. The processor core will enter a snoopable sub-state (not shown in Figure 1) to process the snoop and then return to the AutoHALT Powerdow n state.
2.1.1.3 Core C1/MWAIT Powerdown State
C1/MWAIT is a low-power state entered when the processor core executes the MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor core to return to the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals,
Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference, N-Z, for more information.
2.1.1.4 Core C2 State
Individual cores of the dual-core processor can enter the C2 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted.
While in the C2 state, the dual-core processor will process bus snoops and snoops from the other core. The processor core will enter a snoopable sub-state (not shown in
Figure 1) to process the snoop and then return to the C2 state.
Low Power Features
2.1.1.5 Core C3 State
Individual cores of the dual-core processor can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering C3, the processor core flushes the contents of its L1 caches into the processor’s L2 cache. Except for the caches, the processor core maintains all its architectural states in the C3 state. The Monitor remains armed if it is configured. All of the clocks in the processor core are stopped in the C3 state.
Because the core’s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the FSB or when the other core of the dual-core processor accesses cacheable memory. The processor core will transition to the C0 state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to immediately initialize itself.
2.1.2 Package Low-power State Descriptions
2.1.2.1 Normal State
This is the normal operating state for the processor. The processor remains in the Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT state.
2.1.2.2 Stop-Grant State
When the STPCLK# pin is asserted, each core of the dual-core processor enters the Stop-Grant state within 20 bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2, C3, or C4 state remain in their current low-power state. When the STPCLK# pin is deasserted, each core returns to its previous core low-power state.
Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to V termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state.
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) for minimum power drawn by the
CCP
Low Power Features
RESET# causes the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be deasserted prior to RESET# deassertion as per AC Specification T45. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted after the deassertion of SLP# as per AC Specification T75.
While in Stop-Grant state, the processor will service snoops and latch interrupts delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts and will service only one of each upon return to the Normal state.
The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt or Monitor event latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor should return to the Normal state.
A transition to the Stop-Grant Snoop state occurs when the processor detects a snoop on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4) occurs with the assertion of the SLP# signal.
2.1.2.3 Stop-Grant Snoop State
The processor responds to snoop or interrupt transactions on the FSB while in Stop­Grant state by entering the Stop-Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. The processor returns to the Stop-Grant state once the snoop has been serviced or the interrupt has been latched.
2.1.2.4 Sleep State
The Sleep state is a low-power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through the Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence.
While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 2.1.2.5). While the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur.
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15
2.1.2.5 Deep Sleep State
The Deep Sleep state is entered throug h assertion of the DPSL P# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform-level power savings. BCLK stop/restart timings on appropriate GMCH-based platforms with the CK505 clock chip are as follows:
• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK periods.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re­started after DPSLP# deassertion as described above. A period of 15 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
Low Power Features
16 Datasheet
Low Power Features
2.2 Enhanced Intel SpeedStep® Technology
The processor features Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology:
• Multiple voltage and frequency operati ng points provide optimal performance at the lowest power.
• Voltage and frequency selection is software-controlled by writing to processor MSRs:
— If the target frequency is higher than the current frequency, V
in steps by placing new values on the VID pins, and the PLL then locks to the new frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
new frequency and the VCC is changed through the VID pin mechanism.
— Software transitions are accepted at any time. If a previous transition is in
progress, the new transition is deferred until the previous transition completes.
• The processor controls voltage ramp rates internally to ensure glitch-free transitions.
• Low transition latency and large number of transitions possible per second:
— Processor core (including L2 cache) is unavailable for up to 10 s during the
frequency transition.
— The bus protocol (BNR# mechanism) is used to block snooping.
• Improved Intel® Thermal Monitor mode:
— When the on-die thermal sensor indicates that the die temperature is too high
the processor can automatically perform a transition to a lower frequency and voltage specified in a software-programmable MSR.
— The processor waits for a fixed time period. If the die temperature is down to
acceptable levels, an up-transition to the previous frequency and voltage point occurs.
— An interrupt is generated for the up and down Intel Thermal Monitor transitions
enabling better system-level thermal management.
• Enhanced thermal management features:
— Digital Thermal Sensor and Out of Specification detection. — Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in
case of unsuccessful TM2 transition.
— Dual-core thermal management synchronization.
is ramped up
CC
Each core in the dual-core processor implements an independent MSR for controlling Enhanced Intel SpeedStep Technology, but both cores must operate at the same frequency and voltage. The processor has performance state coordination logic to resolve frequency and voltage requests from the two cores into a single frequency and voltage request for the package as a whole. If both cores request the same frequency and voltage, then the processor will transition to the requested common frequency and voltage. If the two cores have different frequency and voltage requests, then the processor will take the highest of the two frequencies and voltages as the resolved request and transition to that frequency and voltage.
The processor also supports Dynamic FSB Frequency Switching and Intel Dynamic Acceleration Technology mode on select SKUs. The operating system can take advantage of these features and request a lower operating point called SuperLFM (due to Dynamic FSB Frequency Switching) and a higher operating point Intel Dynamic Acceleration Technology mode.
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17
Low Power Features
2.3 Extended Low-Power States
Extended low-power states (CXE) optimize for power by forcibly reducing the performance state of the processor when it enters a package low-power state. Instead of directly transitioning into the package low-power state, the enhanced package low­power state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point. Upon receiving a break event from the package low-power state, control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs. The advantage of this feature is that it significantly reduces leakage while in the Stop-Grant state.
Note: Long-term reliability cannot be assured unless all the Extended Low Power States are
enabled. The processor implements two software interfaces for requesting enhanced package
low-power states: MWAIT instruction extensions with sub-state hints and via BIOS by configuring IA32_MISC_ENABLES MSR bits to automatically promote package low­power states to enhanced package low-power states.
Caution: Extended Stop-Grant must be enabled via the BIOS for the processor to
Caution: Enhanced Intel SpeedStep Technology transitions are multistep processes
remain within specification. As processor technology changes, enabling the extended low power states becomes increasingly crucial when building computer systems. Maintaining the proper BIOS configuration is key to reliable, long-term system operation. Not complying to this guideline may affect the long-term reliability of the processor.
that require clocked control. These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low-power states since processor clocks are not active in these states. The transition to the lowest operating point or back to the original software-requested point may not be instantaneous. Furthermore, upon very frequent transitions between active and idle states, the transitions may lag behind the idle state entry resulting in the processor either executing for a longer time at the lowest operating point or running idle at a high operating point. Observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases.
18 Datasheet
Low Power Features
2.4 FSB Low Power Enhancements
The processor incorporates FSB low power enhancements:
• Dynamic FSB Power Down
• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On-Die Termination disabling
•Low V
• Dynamic FSB frequency switching
The processor incorporates the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows a reciprocal power reduction in GMCH address and control input buffers when the processor deasserts its BR0# pin. The On-Die T ermination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all times.
(I/O termination voltage)
CCP
2.5 Processor Power Status Indicator (PSI-2) Signal
The processor incorporates the PSI# signal that is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve intermediate and light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. The algorithm that the processor uses for determining when to assert PSI# is different from the algorithm used in previous mobile processors. PSI-2 functionality is expanded further to support three processor states:
• Both cores are in idle state
• Only one core active state
• Both cores are in active state
PSI-2 functionality improves overall voltage regulator efficiency over a wide power range based on the C-state and P-state of the two cores. The combined C-state and P­state of both cores are used to dynamically predict processor power.
The real-time power prediction is compared against a set of predefined and configured valu es of CHH and CHL. CHH is indicative of the active C-state of both the cores and CHL is indicative that only one core is in active C-state and the other core is in low power core state. PSI-2# output is asserted upon crossing these thresholds indicating that the processor requires lower power. The voltage regulator will adapt its power output accordingly . Additionally the v oltage regulator may switch to a single phase and/ or asynchronous mode when the processor is idle and fused leakage limit is less than or equal to the BIOS threshold value.
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Low Power Features
20 Datasheet
Electrical Specifications
3 Electrical Specifications
3.1 Power and Ground Pins
For clean, on-chip power distribution, the processor will have a large number of VCC (power) and V planes while all V power and ground planes is recommended to reduce I*R drop. The processor V must be supplied the voltage determined by the VID (Voltage ID) pins.
(ground) inputs. All power pins must be connected to V
SS
pins must be connected to system ground planes. Use of multiple
SS
3.2 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage, such as electrolytic capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in the tables in Section 3.10. Failure to do so can result in timing violations or reduced lifetime of the component.
3.2.1 V
Decoupling
CC
V
regulator solutions need to provide bulk capacitance with a low Effective Series
CC
Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low-power states, should be provided by the voltage regulator solution depending on the specific system design.
CC
power
CC
pins
3.2.2 FSB AGTL+ Decoupling
The processors integrate signal termination on the die as well as incorporate high frequency decoupling capacitance on the processor package. Decoupling must also be provided by the system motherboard for proper AGTL+ bus operation.
3.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous-generation processors, the processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus r atio multiplier will be set at its default ratio at manufacturing. The processor uses a differential clocking implementation.
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Electrical Specifications
3.3 Voltage Identification and Power Sequencing
The processor uses seven voltage identification pins,VID[6:0], to support automatic selection of power supply voltages. The VID pins for the processor are CMOS outputs driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding to the state of VID[6:0]. A 1 in the table refers to a high-voltage level and a 0 refers to a low-voltage level.
Table 2. Voltage Identification Definition (Sheet 1 of 3)
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)
00 000 0 01.5000 00 000 0 11.4875 00 000 1 01.4750 00 000 1 11.4625 00 001 0 01.4500 00 001 0 11.4375 00 001 1 01.4250 00 001 1 11.4125 00 010 0 01.4000 00 010 0 11.3875 00 010 1 01.3750 00 010 1 11.3625 00 011 0 01.3500 00 011 0 11.3375 00 011 1 01.3250 00 011 1 11.3125 00 100 0 01.3000 00 100 0 11.2875 00 100 1 01.2750 00 100 1 11.2625 00 101 0 01.2500 00 101 0 11.2375 00 101 1 01.2250 00 101 1 11.2125 00 110 0 01.2000 00 110 0 11.1875 00 110 1 01.1750 00 110 1 11.1625 00 111 0 01.1500 00 111 0 11.1375 00 111 1 01.1250 00 111 1 11.1125 01 000 0 01.1000 01 000 0 11.0875 01 000 1 01.0750 01 000 1 11.0625 01 001 0 01.0500 01 001 0 11.0375 01 001 1 01.0250 01 001 1 11.0125
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Electrical Specifications
Table 2. Voltage Identification Definition (Sheet 2 of 3)
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)
0 1 0 1 0 0 0 1.0000 0 1 0 1 0 0 1 0.9875 0 1 0 1 0 1 0 0.9750 0 1 0 1 0 1 1 0.9625 0 1 0 1 1 0 0 0.9500 0 1 0 1 1 0 1 0.9375 0 1 0 1 1 1 0 0.9250 0 1 0 1 1 1 1 0.9125 0 1 1 0 0 0 0 0.9000 0 1 1 0 0 0 1 0.8875 0 1 1 0 0 1 0 0.8750 0 1 1 0 0 1 1 0.8625 0 1 1 0 1 0 0 0.8500 0 1 1 0 1 0 1 0.8375 0 1 1 0 1 1 0 0.8250 0 1 1 0 1 1 1 0.8125 0 1 1 1 0 0 0 0.8000 0 1 1 1 0 0 1 0.7875 0 1 1 1 0 1 0 0.7750 0 1 1 1 0 1 1 0.7625 0 1 1 1 1 0 0 0.7500 0 1 1 1 1 0 1 0.7375 0 1 1 1 1 1 0 0.7250 0 1 1 1 1 1 1 0.7125 1 0 0 0 0 0 0 0.7000 1 0 0 0 0 0 1 0.6875 1 0 0 0 0 1 0 0.6750 1 0 0 0 0 1 1 0.6625 1 0 0 0 1 0 0 0.6500 1 0 0 0 1 0 1 0.6375 1 0 0 0 1 1 0 0.6250 1 0 0 0 1 1 1 0.6125 1 0 0 1 0 0 0 0.6000 1 0 0 1 0 0 1 0.5875 1 0 0 1 0 1 0 0.5750 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0.5000 1 0 1 0 0 0 1 0.4875 1 0 1 0 0 1 0 0.4750 1 0 1 0 0 1 1 0.4625 1 0 1 0 1 0 0 0.4500 1 0 1 0 1 0 1 0.4375 1 0 1 0 1 1 0 0.4250
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