Intel PENTIUM P6000, PENTIUM U5000 User Manual

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Intel® Pentium® P6000 and U5000 Mobile Processor Series

Specification Update

June 2010

Revision 002

Document Number: 323874-002

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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

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2 xxx

Contents

Preface......................................................................................................................5

Summary Tables of Changes......................................................................................7

Identification Information.......................................................................................15

Errata......................................................................................................................17

Specification Changes..............................................................................................45

Specification Clarifications ......................................................................................46

Documentation Changes..........................................................................................47

Specification Update 3

Revision History

Revision Description

-001 • Initial release May 2010

-002 • Added P6000 sku information June 2010

Revision

Date

4 Specification Update

Preface

This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published.

Affected Documents

Intel Pentium P6000 and U5000 Mobile Processor Series Datasheet 323873 Intel® Core™ i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series

Datasheet - Volume 1 and Volume 2

Document Title

Document

Number

Location

322812,

322813

Summary Tables of Changes

The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations:

Codes Used in Summary Tables

Stepping

X: Errata exists in the stepping indicated. Specification Change or

Clarification that applies to this stepping. (No mark) or (Blank box): This erratum is fixed in listed stepping or specification change

does not apply to listed stepping.

Page

Status

Row

(Page): Page location of item in this document.

Doc: Document change or update will be implemented. Plan Fix: This erratum may be fixed in a future stepping of the product. Fixed: This erratum has been previously fixed. No Fix: There are no plans to fix this erratum.

Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document.

Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor Specification Updates:

Specification Update 7

Summary Tables of Changes

A = Dual-Core Intel® Xeon® processor 7000 sequence C = Intel® Celeron® processor D = Dual-Core Intel® Xeon® processor 2.80 GHz E = Intel® Pentium® III processor F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor I = Dual-Core Intel® Xeon® processor 5000 series J = 64-bit Intel® Xeon® processor MP with 1-MB L2 cache K = Mobile Intel® Pentium® III processor L = Intel® Celeron® D processor M = Mobile Intel® Celeron® processor N = Intel® Pentium® 4 processor O = Intel® Xeon® processor MP P = Intel® Xeon® processor Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology on 90-nm process

technology R = Intel® Pentium® 4 processor on 90 nm process S = 64-bit Intel® Xeon® processor with 800-MHz system bus (1-MB and 2-MB L2 cache versions) T = Mobile Intel® Pentium® 4 processor-M U = 64-bit Intel® Xeon® processor MP with up to 8-MB L3 cache V = Mobile Intel® Celeron® processor on 0.13 micron process in Micro-FCPGA package W= Intel® Celeron® M processor X = Intel® Pentium® M processor on 90-nm process with 2-MB L2 cache and Intel® processor A100 and

A110 with 512-KB L2 cache Y = Intel® Pentium® M processor Z = Mobile Intel® Pentium® 4 processor with 533-MHz system bus AA = Intel® Pentium® D processor 900 sequence and Inte l® Pentium® processo r Extreme Edition 955, 965 AB = Intel® Pentium® 4 processor 6x1 sequence AC = Intel® Celeron® processor in 478-pin package AD = Intel® Celeron® D processor on 65-nm process AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65-nm process AF = Dual-Core Intel® Xeon® processor LV AG = Dual-Core Intel® Xeon® processor 5100 series AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 and

E4000 sequence AJ = Quad-Core Intel® Xeon® processor 5300 series AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad processor

Q6000 sequence AL = Dual-Core Intel® Xeon® processor 7100 series AM = Intel® Celeron® processor 400 sequence AN = Intel® Pentium® dual-core processor

8 Specification Update

Summary Tables of Changes

AO = Quad-Core Intel® Xeon® processor 3200 series AP = Dual-Core Intel® Xeon® processor 3000 series AQ = Intel® Pentium® dual-core desktop processor E2000 sequence AR = Intel® Celeron® processor 500 series AS = Intel® Xeon® processor 7200, 7300 series

AT = Intel

Celeron® processor 200 series AU = Intel® Celeron® Dual Core processor T1400 AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad processor Q9000 series AW = Intel® Core™ 2 Duo processor E8000 series AX = Quad-Core Intel® Xeon® processor 5400 series AY = Dual-Core Intel® Xeon® processor 5200 series AZ= Intel® Core™2 Duo processor and Intel® Core™2 Extreme processor on 45-nm process AAA= Quad-Core Intel® Xeon® processor 3300 series AAB= Dual-Core Intel® Xeon® E3110 processor AAC= Intel® Celeron® dual-core processor E1000 series AAD = Intel® Core™2 Extreme processor QX9775 AAE = Intel® Atom™ processor Z5xx series AAF = Intel® Atom™ processor 200 series AAG = Intel® Atom™ processor N series AAH = Intel® Atom™ processor300 series AAI = Intel® Xeon® Processor 7400 series AAJ = Intel® Core™ i7 processor and Intel® Core™ i7 Extreme Edition processor AAK= Intel® Xeon® processor 5500 series AAL = Intel® Pentium Dual-Core processor E5000 series AAN = Intel® Core™ i7-800 and i5-700 desktop processor series AAO = Intel® Xeon® Processor 3400 Series AAP = Intel® Core™ i7-900 Mobile Processor Extreme Edition Series, Intel® Core™ i7-800 and i7-700 Mobile

Processor Series AAT = Intel® Core™ i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series (Arrandale) AAU = Intel® Core™ i5-600, i3-500 desktop processor series and Intel® Pentium® Processor G6950 AAZ = Intel® Celeron® P4000 and U3000 Mobile Processor Series (Arrandale) BG = Intel® Pentium® P6000 and U5000 Mobile Processor Series (Arrandale)

Specification Update 9

Errata (Sheet 1 of 4)

Summary Tables of Changes

Number

BG1 X X No Fix The Processor May Report a #TS Instead of a #GP Fault

BG2 X X No Fix

BG3 X X No Fix

BG4 X X No Fix

BG5 X X No Fix

BG6 X X No Fix M OV To/From Debug Registers Causes Debug Exception

BG7 X X No Fix

BG8 X X No Fix

BG9 X X No Fix

BG10 X X No Fix

BG11 X X No Fix

BG12 X X No Fix

BG13 X X No Fix

BG14 X X No Fix

BG15 X X No Fix

BG16 X X No Fix

BG17 X X No Fix

BG18 X X No Fix

BG19 X X No Fix

BG20 X X No Fix

Steppings

Status ERRATA

C-2 K-0

REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations

Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher Priority Interrupts/Exceptions and May Push the Wrong Address onto the Stack

Performance Monitor SSE Retired Instructions May Return Incorrect Values

Premature Execution of a Load Operation Prior to Exception Handler Invocation

Incorrect Address Computed For Last Byte of FXSAVE/ FXRSTOR Image Leads to Partial Memory Update

Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM

Single Step Interrupts with Floati ng P oint Ex ception P ending May Be Mishandled

Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame

IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception

General Protection Faul t (#GP) for Instr uctions Greater than 15 Bytes May Be Preempted

General Protection (#GP) Fa ult May Not Be Signaled on Data Segment Limit Violation above 4-G Limit

LBR, BTS, BTM May Report a Wrong Address When an Exception/Interrupt Occurs in 64-bit Mode

MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang

Corruption of CS Segment Register during RSM While Transitioning from Real Mode to Protected Mode

Performance Monitoring Events for Read Miss to Level 3 Cache Fill Occupancy Counter May Be Incorrect

Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately

#GP on Segment Selector Descriptor That Straddles Canonical Boundary May Not Provide Correct Exception Error Code

Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint Is Set on a #GP Instruction

10 Specification Update

Summary Tables of Changes

Errata (Sheet 2 of 4)

Number

BG21 XXNo Fix

BG22 X X No Fix

BG23 X X No Fix

BG24 X X No Fix

BG25 X X No Fix

BG26 X X No Fix

BG27 X X No Fix

BG28 X X No Fix

BG29 X X No Fix

BG30 X X No Fix Two xAPIC Timer Event Interrupts May Unexpectedly Occur

BG31 X X No Fix

BG32 X X No Fix

BG33 X X No Fix APIC Error “Received Illegal Vector” May Be Lost

BG34 X X No Fix

BG35 X X No Fix

BG36 X X No Fix

BG37 X X No Fix

BG38 X X No Fix

BG39 X X No Fix

BG40 X X No Fix

BG41 X X No Fix

Steppings

Status ERRATA

C-2 K-0

An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/POP SS Instruction If It Is Followed by an Instruction That Signals a Floating Point Exception

IA32_MPERF Counter Stops Counting during On-Demand TM1

The Memory Controller tTHROT_OPREF Timings May Be Violated during Self-Refresh Entry

Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does Not Work

Disabling Thermal Monitor While Processor is Hot, Then Reenabling, May Result in Stuck Core Operating Ratio

Writing the Local Vector Table (LVT) When an Interrupt is Pending May Cause an Unexpected Interrupt

xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While in Periodic Mode

Changing the Memory Type for an In-Use Page Translation May Lead to Memory-Ordering Violations

Infinite Stream of Interrupts May Occur If an ExtINT Delivery Mode Interrupt is Received While All Cores in Deep Power Down Technology (code name C6 state)

EOI Transaction May Not Be Sent If Software Enters Core Deep Power Down Technology (code name C6 state) during an Interrupt Service Routine

FREEZE_WHILE_SMM Does Not Prevent Event from Pending PEBS during SMM

DR6 May Contain Incorrect Information When the First Instruction after a MOV SS,r/m or POP SS Is a Store

An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May Also Result in a System Hang

IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized

Performance Monitor Counter INST_RETIRED.STORES May Count Higher Than Expected

Sleeping Cores May Not Be Woken Up on Logical Cluster Mode Broadcast IPI Using Destination Field Instead of Shorthand

Faulting Executions of FXRSTOR May Update State Inconsistently

Performance Monitor Event EPT.EPDPE_MISS May Be Counted While EPT Is Disable

Memory Aliasing of Code Pages May Cause Unpredictable System Behavior

Specification Update 11

Errata (Sheet 3 of 4)

Summary Tables of Changes

Number

BG42 X X No Fix Performance Monitor Counters May Count Incorrectly

BG43 X X No Fix

BG44 X X No Fix

BG45 X X No Fix

BG46 X X No Fix

BG47 X X No Fix

BG48 X X No Fix

BG49 X X No Fix

BG50 X X No Fix

BG51 X X No Fix

BG52 X X No Fix

BG53 X X No Fix

BG54 X X No Fix

BG55 X X No Fix

BG56 X X No Fix

BG57 X X No Fix

BG58 X X No Fix LER MSRs May Be Unreliable

BG59 X X No Fix

BG60 X X No Fix

BG61 X X No Fix

BG62 X X No Fix

Steppings

Status ERRATA

C-2 K-0

Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT Stores to Local DRAM Correctly

Back-to-Back Uncorrected Machine Check Errors May Overwrite IA32_MC3_STATUS.MSCOD

Corrected Errors with a Yellow Error Indication May Be Overwritten by Other Corrected Errors

Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST May Overcount

Performance Monitor Events INSTR_RETIRED and MEM_INST_RETIRED May Count Inaccurately

A Page Fault May Not Be Generated When the PS Bit Is Set to “1” in a PML4E or PDPTE

BIST Results May Be Additionally Reported after a GETSEC[WAKEUP] or INIT-SIPI Sequence

Pending x87 FPU Exceptions (#MF) May Be Signaled Earlier Than Expected

Multiple Performance Monitor Interrupts are Possible on Overflow of IA32_FIXED_CTR2

LBRs May Not be Initialized During Power-On Reset of the Processor

LBR, BTM or BTS Records May Have Incorrect Branch From Information After an Enhanced Intel SpeedStep® Technology Transition, T-states, C1E, or Adaptive Thermal Throttling

DPRSLPVR Signal May Be Incorrectly Asserted on Transition between Low Power C-states

Performance Monitoring Events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA May Not Count Events Correctly

Storage of PEBS Record Delayed Following Executi on of MOV SS or STI

Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions

MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error

Debug Exception Flags DR6.B0-B3 Flags May Be Incorrect for Disabled Breakpoints

Critical ISOCH Traffic May Cause Unpredictable System Behavior When Write Major Mode Enabled

A String Instruction That Re-maps a Page May Encounter an Unexpected Page Fault

12 Specification Update

Summary Tables of Changes

Errata (Sheet 4 of 4)

Number

BG63 X X No Fix

BG64 X X No Fix

BG65 X X No Fix PCI Express x16 Root Port Incorrectly NAK's a Nullified TLP

BG66 X X No Fix

BG67 X Fixed

BG68 X X No Fix

BG69 X X No Fix

BG70 X X No Fix

BG71 X Fixed

BG72 X Fixed

BG73 X X No Fix

BG74 X Fixed

BG75 X X No Fix A Synchronous SMI May Be Delayed

BG76 X X No Fix

BG77 X X No Fix PCI Express Cards May Not Train to x16 Link Width

BG78 X X No Fix

BG79 X X No Fix CKE May go Low Within tRFC(min) After a PD Exit

BG80 X X No Fix

Steppings

Status ERRATA

C-2 K-0

MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations

PCI Express* x16 Port Logs Bad TLP Correctable Error When Receiving a Duplicate TLP

PCI Express Graphics x16 Receiver Error Reported When Receiver with L0s Enabled and Link Retrain Performed

Internal Parity Error May Be Incorrectly Signaled during Deep Power Down Technology (code name C6 state) Exit

PMIs during Core Deep Power Down Technology (code name C6 state) Transitions May Cause the System to Hang

2-MB Page Split Lock Accesses Combined with Complex Internal Events May Cause Unpredictable System Behavior

Extra APIC Timer Interrupt May Occur during a Write to the Divide Configuration Register

8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides With Interrupt Acknowledge Cycle From the Preceding Interrupt

CPUID Incorrectly Reports a C-State as Available When this State is Unsupported

The Combination of a Page-Split Lock Access and Data Accesses That Are Split across Cacheline Boundaries May Lead to Processor Livelock

Processor Hangs on Package Deep Power Down technology (code named Deep Power Down Technology (code name C6) State Exit

FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit ModeFP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode

The APIC Timer Current Count Register May Prematurely Read 0x0 While the Timer Is Still Running

Under Certain Low Temperature Conditions, Some Uncore Performance Monitoring Events May Report Incorrect R esults

Specification Update 13

Specification Changes

Number Specification Changes

None for this revision of this specification update.

Specification Clarifications

Number Specif ication Clarifications

None for this revision of this specification update.

Documentation Changes

Number Documentation Changes

None for this revision of this specification update.

Summary Tables of Changes

14 Specification Update

Identification Information

Component Identification via Programming Interface

The Intel® Pentium® P6000 and U5000 Mobile Processor Series stepping can be identified by the following processor signatures:

Reserved

31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0

NOTES:

1. The Extended Family , bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8], to

2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are used to

3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM pro cessor,

4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register

5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register

6. The Stepping ID in bits [3:0] indicates the revision number of that model. See above table for the

Extended

Family

00000000b 0010b 00b 0110 0101b xxxxb

indicate whether the processor belongs to the Intel386®, Intel486®, Pentium®, P entiu m Pro®, Pe ntium® 4, or Intel® Core™ processor family .

identify the model of the processor within the processor’s family.

an OverDrive

after the CPUID instruction is executed with a 1 in the EAX register, an d the generation field of the Device ID register accessible through Boundary Scan.

after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan.

processor stepping ID number in the CPUID information.

Extended

processor, or a dual processor (capable of being used in a dual processor system).

Model

Reserved

Processor

Type

Family

Code

Model

Number

Stepping

When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID

value in the EAX register. Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.

Intel® Pentium® P6000 and U5000 Mobile Processor Series can be identified by the following register contents:

Processor Stepping Vendor ID

C-2 8086h 0044h 12h K-0 8086h 0044h 18h

NOTES:

1. The Vendor ID corresponds to Bits 15:0 of the Vendor ID Register located at offset 00–01h in the PCI

2. The Device ID corresponds to Bits 15:0 of the Device ID Register located at Device 0 offset 02–03h in

3. The Revision Number corresponds to Bits 7:0 of the R evision ID Register located at offset 08h in the PCI

4. Correct Host Device ID requires firmware support.

Specification Update 15

function 0 configuration space. the PCI function 0 configuration space. function 0 configuration space.

Device ID

Revision ID

Identification Information

y For PGA

– GRP1LINE1 (limited to 18 char, 13 pt font): INTEL{M}{C}’YY – GRP2LINE1 (limited to 15 char, 13 pt font): PROC# – GRP3LINE1: (limited to 1 (ex) char, 15 pt font): {e4} – GRP4LINE1 (limited to 9 char, 13 pt font): SSPEC – GRP4LINE2 (limited to 9 char, 13 pt font): {FPO}

y For BGA

– GRP1LINE1 (limited to 23 char, 13 pt font): i{M}{C}’Y Y SSPEC PROC# – GRP2LINE1: (limited to 1 (ex) char, 15 pt font): {e1} – GRP3LINE1 (limited to 12 char, 13 pt font): {FPO}

Component Marking Information

The processor stepping can be identified by the following component markings:

Figure 1-1.Intel® Pentium® Mobile processor PGA Component Markings

Figure 1-2.Intel® Pent ium® Mobile processor BGA Component Markings

Table 1-1. Processor Identification

QDF16/

S-Spec

Number

Processor

SLBWB P6000

SLBUH

U540

Stepping/

Processor Signature/Host Device ID/ Host

Number

Revision ID

C-2/

20652h/

0044h/12h

K-0/

20655h/

0044h/18h

(MB)

L3 Cache

3MB

Frequency

Core Base (GHz)

Graphics Base (MHz)

DDR3 (MT/s)

Core: 1.86 GHz

Gfx: 500 MHz

DDR3: 1066/800

MT/s

Core: 1.2 GHz

Gfx: 166 MHz

DDR3: 800 MT/s

NOTES:

1. Core Tjmax = 105°C, Graphics Tjmax = 100°C

2. Core Tjmax = 90°C, Graphics Tjmax = 85°C

3. Standard voltage with 35W TDP

4. Ultra low voltage with 18W TDP

5. The core frequency reported in the processor b rand string is rounded to 2 decimal digits. (For e xample , c ore fre qu enc y of

2.6666, repeating 6, is reported as @2.67 in brand string. Core frequency of 2.5333, is reported as @2.53 in brand string.)

6. Intel® GPMT is supported. GPMT frequency runs at 366 MHz.

7. This part supports C1, C1E, C3 and Deep Power Down Technology (code name C6 state)

8. This part supports C1, C1E and C3

Max Intel® Turbo Boost Technology

Frequency

Single Core Turbo

Dual Core Turbo

Graphics Turbo

Core1: NA Core2: NA

Gfx: 667 MHz

Core1: NA Core2: NA

Gfx: 500 MHz

LFM Frequency

933 MHz PGA

667 MHz BGA

Package

Notes

2,3,5,

6,8

1,4,5,

6,7

16 Specification Update

Errata

BG1. The Processor May Report a #TS Instead of a #GP Fault

Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)

instead of a #GP fault (general protection exception).

Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP

fault. Intel has not observed this erratum with any commercially-available software.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG2. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page

Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations

Problem: Under certain conditions as described in the Software Developers Manual section “Out-

of-Order Stores For String Operations in Pentium® 4, Intel Xeon, and P6 Family Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data size or may observe memory ordering violations.

Implication: Upon crossing the page boundary the following may occur, dependent on the new page

memory type:

• UC the data size of each write will now always be 8 bytes, as opposed to the

original data size.

• WP the data size of each write will now always be 8 bytes, as opposed to the

original data size and there may be a memory ordering violation.

• WT there may be a memory ordering violation.

Workaround:Software should avoid crossing page boundaries from WB or WC memory type to UC,

WP or WT memory type within a single REP MOVS or REP STOS instruction that will execute with fast strings enabled.

Status: For the steppings affected, see the Summary Tables of Changes.

Specification Update 17

Errata

BG3. Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher

Priority Interrupts/Exceptions and May Push the Wrong Address onto the Stack

Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to

code execution, a #GP (General Protection Exception) fault is generated after all higher priority Interrupts and exceptions are serviced. Due to this erratum, if RSM (Resume from System Management Mode) returns to execution flow that results in a Code Segment Limit or Canonical Fault, the #GP fault may be serviced before a higher priority Interrupt or Exception (e.g., NMI (Non-Maskable Interrupt), Debug break(#DB), Machine Check (#MC), etc.). If the RSM attempts to return to a noncanonical address, the address pushed onto the stack for this #GP fault may not match the non-canonical address that caused the fault.

Implication: Operating systems may observe a #GP fault being serviced before higher priority

Interrupts and Exceptions. Intel has not observed this erratum on any commerciallyavailable software.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG4. Performance Monitor SSE Retired Instructions May Return Incorrect Values

Problem: Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used to track

retired SSE instructions. Due to this erratum, the processor may also count other types of instructions resulting in higher than expected values.

Implication: Performance Monitoring counter SIMD_INST_RETIRED may report count higher than

expected.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

18 Specification Update

Errata

BG5. Premature Execution of a Load Operation Prior to Exception Handler

Invocation

Problem: If any of the below circumstances occur, it is possible that the load portion of the

instruction will have executed before the exception handler is entered.

• If an instruction that performs a memory load causes a code segment limit

violation.

• If a waiting X87 floating-point (FP) instruction or MMX™ technology (MMX)

instruction that performs a memory load has a floating-point exception pending.

• If an MMX or SSE/SSE2/SSE3/SSSE3 extensions (SSE) instruction that performs a

memory load and has either CR0.EM=1 (Emulation bit set), or a floating-point Topof-Stack (FP TOS) not equal to 0, or a DNA exception pending.

Implication: In normal code execution where the target of the load operation is to write back

memory there is no impact from the load being prematurely executed, or from the restart and subsequent re-execution of that instruction by the exception handler. If the target of the load is to uncached memory that has a system side-effect, restarting the instruction may cause unexpected system behavior due to the repetition of the sideeffect. Particularly, while CR0.TS [bit 3] is set, a MOVD/MOVQ with MMX/XMM register operands may issue a memory load before getting the DNA exception.

Workaround:Code which performs loads from memory that has side-effects can effectively

workaround this behavior by using simple integer-based load instructions when accessing side-effect memory and by ensuring that all code is written such that a code segment limit violation cannot occur as a part of reading from side-effect memory.

Status: For the steppings affected, see the Summary Tables of Changes.

BG6. MOV To/From Debug Registers Causes Debug Exception

Problem: When in V86 mode, if a MOV instruction is executed to/from a debug registers, a

general-protection exception (#GP) should be generated. However, in the case when the general detect enable flag (GD) bit is set, the observed behavior is that a debug exception (#DB) is generated instead.

Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to

execute a MOV on debug registers in V86 mode, a debug exception will be generated instead of the expected general-protection fault.

Workaround:In general, operating systems do not set the GD bit when they are in V86 mode. The

GD bit is generally set and used by debuggers. The debug exception handler should check that the exception did not occur in V86 mode before continuing. If the exception did occur in V86 mode, the exception may be directed to the general-protection exception handler.

Status: For the steppings affected, see the Summary Tables of Changes.

Specification Update 19

Errata

BG7. Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image Leads

to Partial Memory Update

Problem: A partial memory state save of the 512-byte FXSAVE image or a partial memory state

restore of the FXRSTOR image may occur if a memory address exceeds the 64-KB limit while the processor is operating in 16-bit mode or if a memory address exceeds the 4-GB limit while the processor is operating in 32-bit mode.

Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as expected

but the memory state may be only partially saved or restored.

Workaround:Software should avoid memory accesses that wrap around the respective 16-bit and

32-bit mode memory limits.

Status: For the steppings affected, see the Summary Tables of Changes.

BG8. Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM

Problem: After a return from SMM (System Management Mode), the CPU will incorrectly update

the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their data invalid. The corresponding data if sent out as a BTM on the system bus will also be incorrect.

Note: This issue would only occur when one of the 3 above-mentioned debug support

facilities are used.

Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be

used.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG9. Single Step Interrupts with Floating Point Exception Pending May Be

Mishandled

Problem: In certain circumstances, when a floating point exception (#MF) is pending during

single-step execution, processing of the single-step debug exception (#DB) may be mishandled.

Implication: When this erratum occurs, #DB will be incorrectly handled as follows:

• #DB is signaled before the pending higher priority #MF (Interrupt 16)

• #DB is generated twice on the same instruction

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

20 Specification Update

Errata

BG10. Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame

Problem: The ENTER instruction is used to create a procedure stack frame. Due to this erratum,

if execution of the ENTER instruction results in a fault, the dynamic storage area of the resultant stack frame may contain unexpected values (i.e., residual stack data as a result of processing the fault).

Implication: Data in the created stack frame may be altered following a fault on the ENTER

instruction. Refer to “Procedure Calls for Block-Structured Languages” in IA-32 Intel Architecture Software Developer's Manual, Vol. 1, Basic Architecture, for information on the usage of the ENTER instructions. This erratum is not expected to occur in Ring 3. Faults are usually processed in Ring 0 and stack switch occurs when transferring to Ring 0. Intel has not observed this erratum on any commercially-available software.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG11. IRET under Certain Conditions May Cause an Unexpected Alignment Check

Exception

Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET

instruction even though alignment checks were disabled at the start of the IRET. This can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e mode, RSP is aligned to a 16-byte boundary before pushing the stack frame.

Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if

alignment checks are disabled at the start of the IRET. This erratum can only be observed with a software generated stack frame.

Workaround:Software should not generate misaligned stack frames for use with IRET. Status: For the steppings affected, see the Summary Tables of Changes.

Specification Update 21

Errata

BG12. General Protection Fault (#GP) for Instructions Greater Than 15 Bytes May Be

Preempted

Problem: When the processor encounters an instruction that is greater than 15 bytes in length, a

#GP is signaled when the instruction is decoded. Under some circumstances, the #GP fault may be preempted by another lower priority fault (e.g., Page Fault (#PF)). However, if the preempting lower priority faults are resolved by the operating system and the instruction retried, a #GP fault will occur.

Implication: Software may observe a lower-priority fault occurring before or in lieu of a #GP fault.

Instructions of greater than 15 bytes in length can only occur if redundant prefixes are placed before the instruction.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG13. General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit

Violation above 4-G Limit

Problem: In 32-bit mode, memory accesses to flat data segments (base = 00000000h) that

occur above the 4-G limit (0ffffffffh) may not signal a #GP fault.

Implication: When such memory accesses occur in 32-bit mode, the system may not issue a #GP

fault.

Workaround:Software should ensure that memory accesses in 32-bit mode do not occur above the

4-G limit (0ffffffffh).

Status: For the steppings affected, see the Summary Tables of Changes.

BG14. LBR, BTS, BTM May Report a Wrong Address When an Exception/Interrupt

Occurs in 64-bit Mode

Problem: An exception/interrupt event should be transparent to the LBR (Last Branch Record),

BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However, during a specific boundary condition where the exception/interrupt occurs right after the execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF) in 64-bit mode, the LBR return registers will save a wrong return address with Bits 63 to 48 incorrectly sign extended to all 1's. Subsequent BTS and BTM operations which report the LBR will also be incorrect.

Implication: LBR, BTS and BTM may report incorrect information in the event of an exception/

interrupt.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

22 Specification Update

Errata

BG15. MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang

Problem: If the target linear address range for a MONITOR or CLFLUSH is mapped to the local

xAPIC's address space, the processor will hang.

Implication: When this erratum occurs, the processor will hang. The local xAPIC's address space

must be uncached. The MONITOR instruction only functions correctly if the specified linear address range is of the type write-back. CLFLUSH flushes data from the cache. Intel has not observed this erratum with any commercially-available software.

Workaround:Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space. Status: For the steppings affected, see the Summary Tables of Changes.

BG16. Corruption of CS Segment Register during RSM While Transitioning from Real

Mode to Protected Mode

Problem: During the transition from real mode to protected mode, if an SMI (System

Management Interrupt) occurs between the MOV to CR0 that sets PE (Protection Enable, bit 0) and the first FAR JMP, the subsequent RSM (Resume from System Management Mode) may cause the lower two bits of CS segment register to be corrupted.

Implication: The corruption of the bottom two bits of the CS segment register will have no impact

unless software explicitly examines the CS segment register between enabling protected mode and the first FAR JMP. Intel

64 and IA-32 Architectures Software

Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section

titled “Switching to Protected Mode” recommends the FAR JMP immediately follows the write to CR0 to enable protected mode. Intel has not observed this erratum with any commercially-available software.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG17. Performance Monitoring Events for Read Miss to Level 3 Cache Fill Occupancy

Counter May Be Incorrect

Problem: Whenever an Level 3 cache fill conflicts with another request's address, the miss to fill

occupancy counter, UNC_GQ_ALLOC.RT_LLC_MISS (Event 02H), will provide erroneous results.

Implication: The Performance Monitoring UNC_GQ_ALLOC.RT_LLC_MISS event may count a value

higher than expected. The extent to which the value is higher than expected is determined by the frequency of the L3 address conflict.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Specification Update 23

Errata

BG18. Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccu rately

Problem: The performance monitor event SEGMENT_REG_LOADS (Event 06H) counts

instructions that load new values into segment registers. The value of the count may be inaccurate.

Implication: The performance monitor event SEGMENT_REG_LOADS may reflect a count higher or

lower than the actual number of events.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG19. #GP on Segment Selector Descriptor That Straddles Canonical Boundary May

Not Provide Correct Exception Error Code

Problem: During a #GP (General Protection Exception), the processor pushes an error code on to

the exception handler’s stack. If the segment selector descriptor straddles the canonical boundary, the error code pushed onto the stack may be incorrect.

Implication: An incorrect error code may be pushed onto the stack. Intel has not observed this

erratum with any commercially-available software.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG20. Improper Parity E rror Signaled in the IQ Following Reset When a Code

Breakpoint Is Set on a #GP Instruction

Problem: While coming out of cold reset or exiting from Deep Power Down Technology (code

name C6 state), if the processor encounters an instruction longer than 15 bytes (which causes a #GP) and a code breakpoint is enabled on that instruction, an IQ (Instruction Queue) parity error may be incorrectly logged resulting in an MCE (Machine Check Exception).

Implication: When this erratum occurs, an MCE may be incorrectly signaled. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

24 Specification Update

Errata

BG21. An Enabled Debug Breakpoint or Single Ste p Trap May Be Taken aft er MOV SS/

POP SS Instruction If It Is Followed by an Instruction That Signals a Floating Point Exception

Problem: A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints

until after execution of the following instruction. This is intended to allow the sequential execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having an invalid stack during interrupt handling. However, an enabled debug breakpoint or single step trap may be taken after MOV SS/POP SS if this instruction is followed by an instruction that signals a floating point exception rather than a MOV [r/e]SP, [r/e]BP instruction. This results in a debug exception being signaled on an unexpected instruction boundary since the MOV SS/POP SS and the following instruction should be executed atomically.

Implication: This can result in incorrect signaling of a debug exception and possibly a mismatched

Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on any exception. Intel has not observed this erratum with any commercially-available software or system.

Workaround:As recommended in the IA32 Intel

Architecture Software Developer’s Manual, the use

of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure since the MOV [r/e]SP, [r/e]BP will not generate a floating point exception. Developers of debug tools should be aware of the potential incorrect debug event signaling created by this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

BG22. IA32_MPERF Counter Stops Counting during On-Demand TM1

Problem: According to the Intel

64 and IA-32 Architectures Software Developer’s Manual

Volume 3A: System Programming Guide, the ratio of IA32_MPERF (MSR E7H) to IA32_APERF (MSR E8H) should reflect actual performance while Intel TM1 or ondemand throttling is activated. Due to this erratum, IA32_MPERF MSR stops counting while Intel TM1 or on-demand throttling is activated, and the ratio of the two will indicate higher processor performance than actual.

Implication: The incorrect ratio of IA32_APERF/IA32_MPERF can mislead software P-state

(performance state) management algorithms under the conditions described above. It is possible for the Operating System to observe higher processor utilization than actual, which could lead the OS into raising the P-state. During Intel TM1 activation, the OS Pstate request is irrelevant and while on-demand throttling is enabled, it is expected that the OS will not be changing the P-state. This erratum should result in no practical implication to software.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Specification Update 25

Errata

BG23. The Memory Controller tTHROT_OPREF Timings May Be Violated during Self-

Refresh Entry

Problem: During self-refresh entry, the memory controller may issue more refreshes than

permitted by tTHROT_OPREF (bits 29:19 in MC_CHANNEL_{0,1}_REFRESH_TIMING CSR).

Implication: The intention of tTHROT_OPREF is to limit current. Since current supply conditions near

self refresh entry are not critical, there is no measurable impact due to this erratum.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG24. Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does

Not Work

Problem: When either the IA32_MPERF or IA32_APERF MSR (E7H, E8H) increments to its

maximum value of 0xFFFF_FFFF_FFFF_FFFF, both MSRs are supposed to synchronously reset to 0x0 on the next clock. This synchronous reset does not work. Instead, both MSRs increment and overflow independently.

Implication: Software can not rely on synchronous reset of the IA32_APERF/IA32_MPERF registers. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG25. Disabling Thermal Monitor While Processor Is Hot, Then Re-enabling, May

Result in Stuck Core Operating Ratio

Problem: If a processor is at its TCC (Thermal Control Circuit) activation temperature and then

Thermal Monitor is disabled by a write to IA32_MISC_ENABLES MSR (1A0H) bit [3], a subsequent re-enable of Intel Thermal Monitor will result in an artificial ceiling on the maximum core P-state. The ceiling is based on the core frequency at the time of Intel Thermal Monitor disable. This condition will only correct itself once the processor reaches its TCC activation temperature again.

Implication: Since Intel requires that Intel Thermal Monitor be enabled in order to be operating

within specification, this erratum should never be seen during normal operation.

Workaround:Software should not disable Intel Thermal Monitor during processor operation. Status: For the steppings affected, see the Summary Tables of Changes.

26 Specification Update

Errata

BG26. Writing the Local Vector Table (LVT) When an Interrupt Is Pending May Cause

an Unexpected Interrupt

Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken

on the new interrupt vector even if the mask bit is set.

Implication: An interrupt may immediately be generated with the new vector when a LVT entry is

written, even if the new LVT entry has the mask bit set. If there is no Interrupt Service Routine (ISR) set up for that vector the system will GP fault. If the ISR does not do an End of Interrupt (EOI) the bit for the vector will be left set in the in-service register and mask all interrupts at the same or lower priority.

Workaround:Any vector programmed into an LVT entry must have an ISR associated with it, even if

that vector was programmed as masked. This ISR routine must do an EOI to clear any unexpected interrupts that may occur. The ISR associated with the spurious vector does not generate an EOI, therefore the spurious vector should not be used when writing the LVT.

Status: For the steppings affected, see the Summary Tables of Changes.

BG27. xAPIC Timer May Decrement Too Quickly Following an Automatic Reload

While in Periodic Mode

Problem: When the xAPIC Timer is automatically reloaded by counting down to zero in periodic

mode, the xAPIC Timer may slip in its synchronization with the external clock. The xAPIC timer may be shortened by up to one xAPIC timer tick.

Implication: When the xAPIC Timer is automatically reloaded by counting down to zero in periodic

mode, the xAPIC Timer may slip in its synchronization with the external clock. The xAPIC timer may be shortened by up to one xAPIC timer tick.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG28. Changing the Memory Type for an In-Use Page Translation May Lead to

Memory-Ordering Violations

Problem: Under complex microarchitectural conditions, if software changes the memory type for

data being actively used and shared by multiple threads without the use of semaphores or barriers, software may see load operations execute out of order.

Implication: Memory ordering may be violated. Intel has not observed this erratum with any

commercially-available software.

Workaround:Software should ensure pages are not being actively used before requesting their

memory type be changed.

Status: For the steppings affected, see the Summary Tables of Changes.

Specification Update 27

Errata

BG29. Infinite Stream of Interrupts May Occur If an ExtINT Delivery Mode Interrupt

Is Received While All Cores Are in Deep Power Down Technology (code name C6 state)

Problem: If all logical processors in a core are in Deep Power Down Technology (code name C6

state), an ExtINT delivery mode interrupt is pending in the xAPIC and interrupts are blocked with EFLAGS.IF=0, the interrupt will be processed after Deep Power Down Technology (code name C6 state) wakeup and after interrupts are re-enabled (EFLAGS.IF=1). However, the pending interrupt event will not be cleared.

Implication: Due to this erratum, an infinite stream of interrupts will occur on the core servicing the

external interrupt. Intel has not observed this erratum with any commercially-available software/system.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG30. Two xAPIC Timer Event Interrupts May Unexpectedly Occur

Problem: If an xAPIC timer event is enabled and while counting down the current count reaches

1 at the same time that the processor thread begins a transition to a low power Cstate, the xAPIC may generate two interrupts instead of the expected one when the processor returns to C0.

Implication: Due to this erratum, two interrupts may unexpectedly be generated by an xAPIC timer

event.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG31. EOI Transact ion May Not Be Sent If Software Enters Core Deep Power D own

Technology (code name C6 state) during an Interrupt Service Routine

Problem: If core Deep Power Down Technology (code name C6 state) is entered after the start of

an interrupt service routine but before a write to the APIC EOI register, the core may not send an EOI transaction (if needed) and further interrupts from the same priority level or lower may be blocked.

Implication: EOI transactions and interrupts may be blocked when core Deep Power Down

Technology (code name C6 state) is used during interrupt service routines. Intel has not observed this erratum with any commercially-available software.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

28 Specification Update

Errata

BG32. FREEZE_WHILE _SMM Does Not Prevent Event from Pending PEBS during SMM

Problem: In general, a PEBS record should be generated on the first count of the event after the

counter has overflowed. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR 1D9H, bit [14]) prevents performance counters from counting during SMM (System Management Mode). Due to this erratum, if

1. a performance counter overflowed before an SMI

2. a PEBS record has not yet been generated because another count of the event has not occurred

3. the monitored event occurs during SMM

then a PEBS record will be saved after the next RSM instruction. When FREEZE_WHILE_SMM is set, a PEBS should not be generated until the event

occurs outside of SMM.

Implication: A PEBS record may be saved after an RSM instruction due to the associated

performance counter detecting the monitored event during SMM; even when FREEZE_WHILE_SMM is s et.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG33. APIC Error “Received Illegal Vector” May Be Lost

Problem: APIC (Advanced Programmable Interrupt Controller) may not update the ESR (Error

Status Register) flag Received Illegal Vector bit [6] properly when an illegal vector error is received on the same internal clock that the ESR is being written (as part of the write-read ESR access flow). The corresponding error interrupt will also not be generated for this case.

Implication: Due to this erratum, an incoming illegal vector error may not be logged into ESR

properly and may not generate an error interrupt.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG34. DR6 May Contain Incorrect Information When the First Instruction after a

MOV SS,r/m or POP SS Is a Store

Problem: Normally, each instruction clears the changes in DR6 (Debug Status Register) caused

by the previous instruction. However, the instruction following a MOV SS,r/m (MOV to the stack segment selector) or POP SS (POP stack segment selector) instruction will not clear the changes in DR6 because data breakpoints are not taken immediately after a MOV SS,r/m or POP SS in st ru c ti on . D ue to this erratum, any DR6 changes caused by a MOV SS,r/m or POP SS instruction may be cleared if the following instruction is a store.

Implication: When this erratum occurs, incorrect information may exist in DR6. This erratum will not

be observed under normal usage of the MOV SS,r/m or POP SS instructions (i.e., following them with an instruction that writes [e/r]SP). When debugging or when developing debuggers, this behavior should be noted.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Specification Update 29

Errata

BG35. An Uncorrectable Error Logged in IA32_C R_MC2_STATUS May Also Result in a

System Hang

Problem: Uncorrectable errors logged in IA32_CR_MC2_STATUS MSR (409H) may also result in a

system hang causing an Internal Timer Error (MCACOD = 0x0400h) to be logged in another machine check bank (IA32_MCi_STATUS).

Implication: Uncorrectable errors logged in IA32_CR_MC2_STATUS can further cause a system hang

and an Internal Timer Error to be logged.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG36. IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized

Problem: The IA32_PERF_GLOBAL_CTRL MSR (38FH) bits [34:32] may be incorrectly set to 7H

after reset; the correct value should be 0H.

Implication: The IA32_PERF_GLOBAL_CTRL MSR bits [34:32] may be incorrect after reset

(EN_FIXED_CTR{0, 1, 2} may be enabled).

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG37. Performance Monitor Counter INST_RETIRED.STORES May Count Higher Than

Expected

Problem: Performance Monitoring counter INST_R ETIRED.STORES (Event: C0H) is used to track

retired instructions which contain a store operation. Due to this erratum, the processor may also count other types of instructions including WRMSR and MFENCE.

Implication: Performance Monitoring counter INST_RETIRED.STORES may report counts higher than

expected.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG38. Sleeping Cores May Not Be Woken up on Logical Cluster Mode Broadcast IPI

Using Destination Field Instead of Shorthand

Problem: If software sends a logical cluster broadcast IPI using a destination shorthand of 00B

(No Shorthand) and writes the cluster portion of the Destination Field of the Interrupt Command Register to all ones while not using all 1s in the mask portion of the Destination Field, target cores in a sleep state that are identified by the mask portion of the Destination Field may not be woken up. This erratum does not occur if the destination shorthand is set to 10B (All Including Self) or 11B (All Excluding Self).

Implication: When this erratum occurs, cores which are in a sleep state may not wake up to handle

the broadcast IPI. Intel has not observed this erratum with any commercially-available software.

Workaround:Use destination shorthand of 10B or 11B to send broadcast IPIs. Status: For the steppings affected, see the Summary Tables of Changes.

30 Specification Update

Errata

BG39. Faulting Executions of FXRSTOR May Update State Inconsistently

Problem: The state updated by a f aulting FXRSTOR instruction may vary from one execution to

another.

Implication: Software that relies on x87 state or SSE state following a faulting execution of

FXRSTOR may behave inconsistently.

Workaround:Software handling a fault on an execution of FXRSTOR can compensate for execution

variability by correcting the cause of the fault and executing FXRSTOR again.

Status: For the steppings affected, see the Summary Tables of Changes.

BG40. Performance Monitor Event EPT.EPDPE_MISS May Be Counted While EPT Is

Disabled

Problem: Performance monitor event EPT.EPDPE_MISS (Event: 4FH, Umask: 08H) is used to

count Page Directory Pointer table misses while EPT (extended page tables) is enabled. Due to this erratum, the processor will count Page Directory Pointer table misses regardless of whether EPT is enabled or not.

Implication: Due to this erratum, performance monitor event EPT.EPDPE_MISS may report counts

higher than expected.

Workaround:Software should ensure this event is only enabled while in EPT mode. Status: For the steppings affected, see the Summary Tables of Changes.

BG41. Memory Aliasing of Code Pages May Cause Unpredictable System Behavior

Problem: The type of memory aliasing contributing to this erratum is the case where two

different logical processors have the same code page mapped with two different memory types. Specifically, if one code page is mapped by one logical processor as write-back and by another as uncachable and certain instruction fetch timing conditions occur, the system may experience unpredictable behavior.

Implication: If this erratum occurs the system may have unpredictable behavior including a system

hang. The aliasing of memory regions, a condition necessary for this erratum to occur, is documented as being unsupported in the Intel 64 and IA-32 Intel

Architecture

Software Developer's Manual, Volume 3A, in the section titled Programming the PAT.

Intel has not observed this erratum with any commercially-available software or system.

Workaround:Code pages should not be mapped with uncacheable and cacheable memory types at

the same time.

Status: For the steppings affected, see the Summary Tables of Changes.

Specification Update 31

Errata

BG42. Performance Monitor Counters May Count Incorrectly

Problem: Under certain circumstances, a general purpose performance counter, IA32_PMC0-4

(C1H - C4H), may count at core frequency or not count at all instead of counting the programmed event.

Implication: The Performance Monitor Counter IA32_PMCx may not properly count the programmed

event. Due to the requirements of the workaround there may be an interruption in the counting of a previously programmed event during the programming of a new event.

Workaround:Before programming the performance event select registers, IA32_PERFEVTSELx MSR

(186H - 189H), the internal monitoring hardware must be cleared. This is accomplished by first disabling, saving valid events and clearing from the select registers, then programming three event values 0x4300D2, 0x4300B1 and 0x4300B5 into the IA32_PERFEVTSELx MSRs, and finally continuing with new event programming and restoring previous programming if necessary. Each performance counter, IA32_PMCx, must have its corresponding IA32_PREFEVTSELx MSR programmed with at least one of the event values and must be enabled in IA32_PERF_GLOBAL_CTRL MSR (38FH) bits [3:0]. All three values must be written to either the same or different IA32_PERFEVTSELx MSRs before programming the performance counters. Note that the performance counter will not increment when its IA32_PERFEVTSELx MSR has a value of 0x4300D2, 0x4300B1 or 0x4300B5 because those values have a zero UMASK field (bits [15:8]).

Status: For the steppings affected, see the Summary Tables of Changes.

BG43. Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT

Stores to Local DRAM Correctly

Problem: When a IA32_PERFEVTSELx MSR is programmed to count the Offcore_response_0

event (Event:B7H), selections in the OFFCORE_RSP_0 MSR (1A6H) determine what is counted. The following two selections do not provide accurate counts when counting NT (Non-Temporal) Stores:

• OFFCORE_RSP_0 MSR bit [14] is set to 1 (LOCAL_DRAM) and bit [7] is set to 1

(OTHER): NT Stores to Local DRAM are not counted when they should have been.

• OFFCORE_RSP_0 MSR bit [9] is set to (OTHER_CORE_HIT_SNOOP) and bit [7] is

set to 1 (OTHER): NT Stores to Local DRAM are counted when they should not hav e been.

Implication: The counter for the Offcore_response_0 event may be incorrect for NT stores. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

32 Specification Update

Errata

BG44. Back to Back Uncorrected Machine Check Errors May Overwrite

IA32_MC3_STATUS.MSCOD

Problem: When back-to-back uncorrected machine check errors occur that would both be logged

in the IA32_MC3_STATUS MSR (40CH), the IA32_MC3_STATUS.MSCOD (bits [31:16]) field may reflect the status of the most recent error and not the first error. The rest of the IA32_MC3_STATUS MSR contains the information from the first error.

Implication: Software should not rely on the value of IA32_MC3_STATUS.MSCOD if

IA32_MC3_STATUS.OVER (bit [62]) is set.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG45. Corrected Erro rs with a Yellow Error Indication May Be Overwritten by Other

Corrected Errors

Problem: A corrected cache hierarchy data or tag error that is reported with

IA32_MCi_STATUS.MCACOD (bits [15:0]) with value of 000x_0001_xxxx_xx01 (where x stands for zero or one) and a yellow threshold-based error status indication (bits [54:53] equal to 10B) may be overwritten by a corrected error with a no tracking indication (00B) or green indication (01B).

Implication: Corrected errors with a yellow threshold-based error status indication may be

overwritten by a corrected error without a yellow indication.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG46. Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST May

Overcount

Problem: The performance monitor events DCACHE_CACHE_LD (Event 40H) and

DCACHE_CACHE_ST (Event 41H) count cacheable loads and stores that hit the L1 cache. Due to this erratum, in addition to counting the completed loads and stores, the counter will incorrectly count speculative loads and stores that were aborted prior to completion.

Implication: The performance monitor events DCACHE_CACHE_LD and DCACHE_CACHE_ST may

reflect a count higher than the actual number of events.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Specification Update 33

Errata

BG47. Performance Monitor Events INSTR_RETIRED and MEM_INST_RETIRED May

Count Inaccurately

Problem: The performance monitor event INSTR_RETIRED (Event C0H) should count the number

of instructions retired, and MEM_INST_ RETIRED (Event 0BH) should count the number of load or store instructions retired. However, due to this erratum, they may undercount.

Implication: The performance monitor event INSTR_RETIRED and MEM_INST_RETIRED may reflect

a count lower than the actual number of events.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG48. A P age Fault May Not Be Generated When the PS bit Is Set to “1” in a PML4E

or PDPTE

Problem: On processors supporting Intel 64 architecture, the PS bit (Page Size, Bit 7) is reserved

in PML4Es and PDPTEs. If the translation of the linear address of a memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due to this erratum, PS of such an entry is ignored and no page fault will occur due to its being set.

Implication: Software may not operate properly if it relies on the processor to deliver page faults

when reserved bits are set in paging-structure entries.

Workaround:Software should not set Bit 7 in any PML4E or PDPTE that has Present Bit (Bit 0) set to

“1”.

Status: For the steppings affected, see the Summary Tables of Changes.

BG49. BIST Results May Be Additionally Reported after a GETSEC[WAKEUP] or INIT-

SIPI Sequence

Problem: BIST results should only be reported in EAX the first time a logical processor wakes up

from the Wait-For-SIPI state. Due to this erratum, BIST results may be additionally reported after INIT-SIPI sequences and when waking up RLP's from the SENTER sleep state using the GETSEC[WAKEUP] command.

Implication: An INIT-SIPI sequence may show a non-zero value in EAX upon wakeup when a zero

value is expected. RLP's waking up for the SENTER sleep state using the GETSEC[WAKEUP] command may show a different value in EAX upon wakeup than before going into the SENTER sleep state.

Workaround:If necessary software may save the value in EAX prior to launching into the secure

environment and restore upon wakeup and/or clear EAX after the INIT-SIPI sequence.

Status: For the steppings affected, see the Summary Tables of Changes.

34 Specification Update

Errata

BG50. Pending x87 FPU Exceptions (#MF) May Be Signaled Earlier Than Expected

Problem: x87 instructions that trigger #MF normally service interrupts before the #MF. Due to

this erratum, if an instruction that triggers #MF is executed while Enhanced Intel SpeedStep® Technology transitions, Intel® Turbo Boost Technology transitions, or Thermal Monitor events occur, the pending #MF may be signaled before pending interrupts are serviced.

Implication: Software may observe #MF being signaled before pending interrupts are serviced. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG51. Multiple Performance Monitor Interrupts Are Possible on Overflow of

IA32_FIXED_CTR2

Problem: When multiple performance counters are set to generate interrupts on an overflow and

more than one counter overflows at the same time, only one interrupt should be generated. However, if one of the counters set to generate an interrupt on overflow is the IA32_FIXED_CTR2 (MSR 30BH) counter, multiple interrupts may be generated when the IA32_FIXED_CTR2 overflows at the same time as any of the other performance counters.

Implication: Multiple counter overflow interrupts may be unexpectedly generated. Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG52. LBRs May Not Be Initialized during Power-On Reset of the Processor

Problem: If a second reset is initiated during the power-on processor reset cycle, the LBRs (Last

Branch Records) may not be properly initialized.

Implication: Due to this erratum, debug software may not be able to rely on the LBRs out of power-

on reset.

Workaround:Ensure that the processor has completed its power-on reset cycle prior to initiating a

second reset.

Status: For the steppings affected, see the Summary Tables of Changes.

BG53. LBR, BTM or BTS Records May Have Incorrect Branch from Information after

an Enhanced Intel SpeedStep® Technology Transition, T-states, C1E, or Adaptive Thermal Throttling

Problem: The “From” address associated with the LBR (Last Branch Record), BTM (Branch Trace

Message) or BTS (Branch Trace Store) may be incorrect for the first branch after an Enhanced Intel SpeedStep Technology transition, T-states, C1E (C1 Enhanced), or Adaptive Thermal Throttling.

Implication: When the LBRs, BTM or BTS are enabled, some records may have incorrect branch

“From” addresses for the first branch after an Enhanced Intel SpeedStep Technology transition, T-states, C1E, or Adaptive Thermal Throttling.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Specification Update 35

Errata

BG54. DPRSLPVR Signal May Be Incorrectly Asserted on Transition between Low

Power C-states

Problem: On entry to or exit from package Deep Power Down Technology (code name C6 state)

states, DPRSLPVR (Deeper Sleep Voltage Regulator) signal may be incorrectly asserted.

Implication: Due to this erratum, platform voltage regulator may shutdown Workaround:It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes.

BG55. Performance Monitoring Events STORE_BLOCKS.NOT_STA and

STORE_BLOCKS.STA May Not Count Events Correctly

Problem: Performance Monitor Events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA

should only increment the count when a load is blocked by a store. Due to this erratum, the count will be incremented whenever a load hits a store, whether it is blocked or can forward. In addition this event does not count for specific threads correctly.

Implication: If Intel® Hyper-Threading Technology is disabled, the Performance Monitor events

STORE_BLOCKS.NOT_STA and STORE_ BLOCKS.STA may indicate a higher occurrence of loads blocked by stores than have actually occurred. If Intel Hyper-Threading Technology is enabled, the counts of loads blocked by stores may be unpredictable and they could be higher or lower than the correct count.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG56. Storage of PEBS Record Delayed Following Execution of MOV SS or STI

Problem: When a performance monitoring counter is configured for PEBS (Precise Event Based

Sampling), overflow of the counter results in storage of a PEBS record in the PEBS buffer. The information in the PEBS record represents the state of the next instruction to be executed following the counter overflow. Due to this erratum, if the counter overflow occurs after execution of either MOV SS or STI, storage of the PEBS record is delayed by one instruction.

Implication: When this erratum occurs, software may observe storage of the PEBS record being

delayed by one instruction following execution of MOV SS or STI. The state information in the PEBS record will also reflect the one instruction delay.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

36 Specification Update

Errata

BG57. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count

Some Transitions

Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts

transitions from x87 Floating Point (FP) to MMX™ instructions. Due to this erratum, if only a small number of MMX instructions (including EMMS) are executed immediately after the last FP instruction, a FP to MMX transition may not be counted.

Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be

lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially-available software.

Workaround:None Identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG58. LER MSRs May Be Unreliable

Problem: Due to certain internal processor events, updates to the LER (Last Exception Record)

MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_LER_TO_LIP (1DEH), may happen when no update was expected.

Implication: The values of the LER MSRs may be unreliable. Workaround:None Identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG59. MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB

Error

Problem: A single Data Translation Look Aside Buffer (DTLB) error can incorrectly set the

Overflow (bit [62]) in the MCi_Status register. A DTLB error is indicated by MCA error code (bits [15:0]) appearing as binary value, 000x 0000 0001 0100, in the MCi_Status register.

Implication: Due to this erratum, the Overflow bit in the MCi_Status register may not be an accurate

indication of multiple occurrences of DTLB errors. There is no other impact to normal processor functionality.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Specification Update 37

Errata

BG60. Debug Exception Flags DR6.B0-B3 Flags May Be Incorrect for Disabled

Breakpoints

Problem: When a debug exception is signaled on a load that crosses cache lines with data

forwarded from a store and whose corresponding breakpoint enable flags are disabled (DR7.G0-G3 and DR7.L0-L3), the DR6.B0-B3 flags may be incorrect.

Implication: The debug exception DR6.B0-B3 flags may be incorrect for the load if the

corresponding breakpoint enable flag in DR7 is disabled.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG61. Critical ISOCH Traffic May Cause Unpredictable System Behavior When Write

Major Mode Enabled

Problem: Under a specific set of conditions, critical ISOCH (isochronous) traffic may cause

unpredictable system behavior with write major mode enabled.

Implication: Due to this erratum unpredictable system behavior may occur. Workaround:Write major mode must be disabled in the BIOS by writing the write major mode

threshold value to its maximum value of 1FH in ISOCHEXITTRESHOLD bits [19:15], ISOCHENTRYTHRESHOLD bits [14:10], WMENTRYTHRESHOLD bits [9:5], and WMEXITTHRESHOLD bits [4:0] of the MC_CHANNEL_{0,1,2}_WAQ_PARAMS register.

Status: For the steppings affected, see the Summary Tables of Changes.

BG62. A String Instruction that Re-maps a Page May Encounter an Unexpected Page

Fault

Problem: An unexpected page fault (#PF) may occur for a page under the following conditions: Implication: Software may see an unexpected page fault that indicates that there is no translation

for the page. Intel has not observed this erratum with any commercially-available software or system.

• The paging structures initially specify a valid translation for the page.

• Software modifies the paging structures so that there is no valid tr anslation for the

page (e.g., by clearing to 0 the present bit in one of the paging-structure entries used to translate the page).

• An iteration of a string instruction modifies the paging structures so that the

translation is again a valid translation for th e page (e.g., by setting to 1 the bit that was cleared earlier).

• A later iteration of the same string instruction loads from a linear address on the

page.

• Software did not invalidate TLB entries for the page between the first modification

of the paging structures and the string instruction. In this case, the load in the later iteration may cause a page fault that indicates that there is no translation for the page (e.g., with bit 0 clear in the page-fault error code, indicating that the fault was caused by a not-present page).

Workaround:Software should not update the paging structures with a string instruction that

accesses pages mapped the modified paging structures.

Status: For the steppings affected, see the Summary Tables of Changes.

38 Specification Update

Errata

BG63. MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology

Core Ratio Multipliers for Non-Existent Core Configurations

Problem: MSR_TURBO_RATIO_LIMIT MSR (1ADH) is designed to describe the maximum Intel

Turbo Boost Technology potential of the processor. On some processors, a non-zero Intel Turbo Boost Technology value will be returned for non-existent core configurations.

Implication: Due to this erratum, software using the MSR_TURBO_RATIO_LIMIT MSR to report Intel

Turbo Boost Technology processor capabilities may report erroneous results.

Workaround:It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes.

BG64. PCI Express x16 Port Logs Bad TLP Correctable Error When Receiving a

Duplicate TLP

Problem: In the PCI Express 2.0 Specification a receiver should schedule an ACK and discard a

duplicate TLP (Transaction Layer Packet) before ending the transaction within the data link layer. In the processor, the PCI Express x16 root port will set the Bad TLP status bit in the Correctable Error Status Register (Bus 0; Device 1 and 6; Function 0; Offset 1D0h; bit 6) in addition to scheduling an ACK and discarding the duplicate TLP. Note: The duplicate packet can be received only as a result of a correctable error in the other end point (Transmitter).

Implication: The processor does not comply with the PCI Express 2.0 Specification. This does not

impact functional compatibility or interoperability with other PCIe devices.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG65. PCI Express x16 Root Port Incorrectly NAK's a Nullified TLP

Problem: In the processor, the PCI Express root port may NAK a nullified TLP (Transaction Layer

Packet). This behavior is a result of an incorrect DW (Double Word) enable generation on the processors when packets end with EDB (End Bad Symbol). This also occurs only if total TLP length <= 8 DW in which CRC (Cyclic Redundancy Check) check/framing upstream checks will fail. This failure causes a NAK to be unexpectedly generated for TLP's which have packets with inverted CRC and EDB's. The PCI-e specification revision

2.0 states that such cycles should be dropped and no NAK should be generated. The processor should NAK a nullified TLP only when there is a CRC error or a sequence check fail.

Implication: The processor does not comply with the PCI Express 2.0 Specification. This does not

impact functional compatibility or interoperability with other PCIe devices.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Specification Update 39

Errata

BG66. PCI Express Graphics x16 Receiver Error Reported When Receiver With L0s

Enabled and Link Retrain Performed

Problem: If the Processor PCI Express root port is the receiver with L0s enabled and the root port

itself initiates a transition to the recovery state via the retrain link configuration bit in the 'Link Control' register (Bus 0; Device 1 and 6; Function 0; Offset B0H; bit 5), then the root port may not mask the receiver or bad DLLP (Data Link La yer Packet) errors as expected. These correctable errors should only be considered valid during PCIe configuration and L0 but not L0s. This causes the processor to falsely report correctable errors in the 'Device Status' register (Bus 0; Device 1 and 6; Function 0; Offset AAH; bit 0) upon receiving the first FTS (Fast Training Sequence) when exiting Receiver L0s. Under normal conditions there is no reason for the Root Port to initiate a transition to Recovery. Note: This issue is only exposed when a recovery event is initiated by the processor.

Implication: The processor does not comply with the PCI Express 2.0 Specification. This does not

impact functional compatibility or interoperability with other PCIe devices.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG67. Internal Parity Error May Be Incorrectly Signaled during Deep Power Down

Technology (code name C6 state) Exit

Problem: In a complex set of internal conditions an internal parity error may occur during a Core

Deep Power Down Technology (code name C6 state) exit.

Implication: Due to this erratum, an uncorrected error may be reported and a machine check

exception may be triggered.

Workaround:It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes.

BG68. PMIs during Core Deep Power Down Technology (code name C6 state)

Transitions May Cause the System to Hang

Problem: If a performance monitoring counter overflows and causes a PMI (Performance

Monitoring Interrupt) at the same time that the core enters Deep Power Down Technology (code name C6 state), then this may cause the system to hang.

Implication: Due to this erratum, the processor may hang when a PMI coincides with core Deep

Power Down Technology (code name C6 state) entry.

Workaround:It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes.

BG69. 2-MB Page Split Lock Accesses Combined with Complex Internal Events May

Cause Unpredictable System Behavior

Problem: A 2-MB Page Split Lock (a locked access that spans two 2-MB large pages) coincident

with additional requests that have particular address relationships in combination with a timing sensitive sequence of complex internal conditions may cause unpredictable system behavior.

Implication: This erratum may cause unpredictable system behavior. Intel has not observed this

erratum with any commercially-available software.

40 Specification Update

Errata

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG70. Extra APIC Timer Interrupt May Occur during a Write to the Divide

Configuration Register

Problem: If the APIC timer Divide Configuration Register (Offset 03E0H) is written at the same

time that the APIC timer Current Count Register (Offset 0390H) reads 1H, it is possible that the APIC timer will deliver two interrupts.

Implication: Due to this erratum, two interrupts may unexpectedly be generated by an APIC timer

event.

Workaround:Software should reprogram the Divide Configuration Register only when the APIC timer

interrupt is disarmed.

Status: For the steppings affected, see the Summary Tables of Changes.

BG71. 8259 Virtual Wire B Mode Interrupt May Be Dropped When It Collides with

Interrupt Acknowledge Cycle from the Preceding Interrupt

Problem: If an un-serviced 8259 Virtual Wire B Mode (8259 connected to IOAPIC) External

Interrupt is pending in the APIC and a second 8259 Virtual Wire B Mode External Interrupt arrives, the processor may incorrectly drop the second 8259 Virtual Wire B Mode External Interrupt request. This occurs when both the new External Interrupt and Interrupt Acknowledge for the previous External Interrupt arrive at the APIC at the same time.

Implication: Due to this erratum, any further 8259 Virtual Wire B Mode External Interrupts will

subsequently be ignored.

Workaround:Do not use 8259 Virtual Wire B mode when using the 8259 to deliver interrupts. Status: For the steppings affected, see the Summary Tables of Changes.

BG72. CPUID Incorrectly Reports a C-State as Available When This State Is

Unsupported

Problem: CPUID incorrectly reports a non-zero value in CPUID MONITOR/MWAIT leaf (5H) EDX

[19:16] when the processor does not support an MWAIT with a target C-state EAX [7:4] > 3.

Implication: If an MWAIT instruction is executed with a target C-state EAX [7:4] > 3 then

unpredictable system behavior may result.

Workaround:It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes.

BG73. The Combination of a Page-Split Lock Access and Data Accesses That Are Split

across Cacheline Boundaries May Lead to Processor Livelock

Problem: Under certain complex micro-architectural conditions, the simultaneous occurrence of a

page-split lock and several data accesses that are split across cacheline boundaries may lead to processor livelock.

Implication: Due to this erratum, a livelock may occur that can only be terminated by a processor

reset. Intel has not observed this erratum with any commercially-available softw are.

Specification Update 41

Errata

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG74. Processor Hangs on Package Deep Power Down Technology (code name C6

state) State Exit

Problem: An internal timing condition in the processor power management logic will result in

processor hangs upon a Package Deep Power Down Technology (code name C6 state) state exit.

Implication: Due to this erratum, the processor will hang during Package Deep Power Down

Technology (code name C6 state) state exit.

Workaround:is possible for the BIOS to contain a workaround for this erratum Status: For the steppings affected, see the Summary Tables of Changes.

BG75. A Synchronous SMI May Be Delayed

Problem: A synchronous SMI (System Management Interrupt) occurs as a result of an SMI

generating I/O Write instruction and should be handled prior to the next instruction executing. Due to this erratum, the processor may not observe the synchronous SMI prior to execution of the next instruction.

Implication: Due to this erratum, instructions after the I/O Write instruction, which triggered the

SMI, may be allowed to execute before the SMI handler. Delayed delivery of the SMI may make it difficult for an SMI Handler to determine the source of the SMI. Software that relies on the IO_SMI bit in SMM save state or synchronous SMI behavior may not function as expected.

Workaround:A BIOS workaround has been identified. Status: For the steppings affected, see the Summary Tables of Changes.

BG76. FP Data Operand Pointer May Be Incorrectly Calculated after an FP Access

Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64bit Mode

Problem: The FP (Floating Point) Data Operand Pointer is the effective address of the operand

associated with the last non-control FP instruction executed by the processor. If an 80bit FP access (load or store) uses a 32-bit address size in 64-bit mode and the memory access wraps a 4-Gbyte boundary and the FP environment is subsequently saved, the value contained in the FP Data Operand Pointer may be incorrect.

Implication: Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping an 80-bit

FP load around a 4-Gbyte boundary in this way is not a normal programming practice. Intel has not observed this erratum with any commercially available software.

Workaround:If the FP Data Operand Pointer is used in a 64-bit operating system which may run

code accessing 32-bit addresses, care must be taken to ensure that no 80-bit FP accesses are wrapped around a 4-Gbyte boundary.

Status: For the steppings affected, see the Summary Tables of Changes.

42 Specification Update

Errata

BG77. PCI Express Cards May Not Train to x16 Link Width

Problem: The Maximum Link Width field in the Link Capabilities register (LCAP; Bus 0; Device 1;

Function 0; offset 0xAC; bits [9:4]) may limit the width of the PCI Express link to x8, even though the processor may actually be capable of supporting the full x16 width.

Implication: Implication: PCI Express x16 Graphics Cards used in normal operation and PCI Express

CLB (Compliance Load Board) Cards used during PCI Express Compliance mode testing may only train to x8 link width.

Workaround:A BIOS workaround has been identified. . Status: For the steppings affected, see the Summary Tables of Changes.

BG78. The APIC Timer Current Count Register May Prematurely Read 0x0 While the

Timer Is Still Running

Problem: The APIC Timer Current Counter Register may prematurely read 0x00000000 while the

timer is still running. This problem occurs when a core frequency or C-state transition occurs while the APIC timer countdown is in progress.

Implication: Due to this erratum, certain software may incorrectly assess that the APIC timer

countdown is complete when it is actually still running. This erratum does not affect the delivery of the timer interrupt.

Workaround:It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes.

BG79. CKE May go Low Within tRFC(min) After a PD Exit

Problem: After a refresh command is issued, followed by an early PD (Power Down) Entry and

Exit, the CKE (Clock Enable) signal may be asserted low prior to tRFC(min), the Minimum Refresh Cycle timing. This additional instance of CKE being low causes the processor not to meet the JEDEC DDR3 DRAM specification requirement (Section

4.17.4 Power-Down clarifications - Case 3).

Implication: Due to this erratum, the processor may not meet the JEDEC DDR3 DRAM specification

requirement that states: “CKE cannot be registered low twice within a tRFC(min) window”. Intel has not observed any functional failure due to this erratum.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

Specification Update 43

Errata

BG80. Under Certain Low Temperature Conditions, Some Uncore

Performance Monitoring Events May Report Incorrect Results

Problem: Due to this erratum, under certain low operating temperatures, a small number of Last

Level Cache and external bus performance monitoring events in the uncore report incorrect counts. This erratum may affect event codes in the ranges 00H to 0CH and 40H to 43H.

Implication: Due to this erratum, the count value for some uncore Performance Monitoring Events

may be inaccurate. The degree of under or over counting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.

Workaround:None identified. Status: For the steppings affected, see the Summary Tables of Changes.

44 Specification Update

Specification Changes

There are no new Specification Changes in this Specification Update revision.

Specification Update 45

Specification Clarifications

There are no new Specification Clarifications in this Specification Update revision.

Specification Clarifications

46 Specification Update

Documentation Changes

There are no new Document Changes in this Specification Update revision.

Specification Update 47

Intel PENTIUM P6000, PENTIUM U5000 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Intel® Pentium® P6000 and U5000 Mobile Processor Series

Preface

Summary Tables of Changes

Identification Information

Errata

Specification Changes

Specification Clarifications

Documentation Changes