Intel PENTIUM P6000, PENTIUM U5000 User Manual

Intel® Pentium® P6000 and U5000 Mobile Processor Series

Specification Update

June 2010

Revision 002

Document Number: 323874-002

Legal Lines and Disclaimers

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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Intel processor numbers are not a measure of performance. Proce ssor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details.

The processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel, Intel Core, Centrino, Celeron, Pentium, Intel Xeon, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

2 xxx

Contents

Preface......................................................................................................................5

Summary Tables of Changes......................................................................................7

Identification Information.......................................................................................15

Errata......................................................................................................................17

Specification Changes..............................................................................................45

Specification Clarifications ......................................................................................46

Documentation Changes..........................................................................................47

Specification Update 3

Revision History

Revision Description

-001 • Initial release May 2010

-002 • Added P6000 sku information June 2010

Revision

Date

4 Specification Update

Preface

This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published.

Affected Documents

Intel Pentium P6000 and U5000 Mobile Processor Series Datasheet 323873 Intel® Core™ i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series

Datasheet - Volume 1 and Volume 2

Document Title

Document

Number

Location

322812,

322813

Summary Tables of Changes

The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations:

Codes Used in Summary Tables

Stepping

X: Errata exists in the stepping indicated. Specification Change or

Clarification that applies to this stepping. (No mark) or (Blank box): This erratum is fixed in listed stepping or specification change

does not apply to listed stepping.

Page

Status

Row

(Page): Page location of item in this document.

Doc: Document change or update will be implemented. Plan Fix: This erratum may be fixed in a future stepping of the product. Fixed: This erratum has been previously fixed. No Fix: There are no plans to fix this erratum.

Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document.

Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor Specification Updates:

Specification Update 7

Summary Tables of Changes

A = Dual-Core Intel® Xeon® processor 7000 sequence C = Intel® Celeron® processor D = Dual-Core Intel® Xeon® processor 2.80 GHz E = Intel® Pentium® III processor F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor I = Dual-Core Intel® Xeon® processor 5000 series J = 64-bit Intel® Xeon® processor MP with 1-MB L2 cache K = Mobile Intel® Pentium® III processor L = Intel® Celeron® D processor M = Mobile Intel® Celeron® processor N = Intel® Pentium® 4 processor O = Intel® Xeon® processor MP P = Intel® Xeon® processor Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology on 90-nm process

technology R = Intel® Pentium® 4 processor on 90 nm process S = 64-bit Intel® Xeon® processor with 800-MHz system bus (1-MB and 2-MB L2 cache versions) T = Mobile Intel® Pentium® 4 processor-M U = 64-bit Intel® Xeon® processor MP with up to 8-MB L3 cache V = Mobile Intel® Celeron® processor on 0.13 micron process in Micro-FCPGA package W= Intel® Celeron® M processor X = Intel® Pentium® M processor on 90-nm process with 2-MB L2 cache and Intel® processor A100 and

A110 with 512-KB L2 cache Y = Intel® Pentium® M processor Z = Mobile Intel® Pentium® 4 processor with 533-MHz system bus AA = Intel® Pentium® D processor 900 sequence and Inte l® Pentium® processo r Extreme Edition 955, 965 AB = Intel® Pentium® 4 processor 6x1 sequence AC = Intel® Celeron® processor in 478-pin package AD = Intel® Celeron® D processor on 65-nm process AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65-nm process AF = Dual-Core Intel® Xeon® processor LV AG = Dual-Core Intel® Xeon® processor 5100 series AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 and

E4000 sequence AJ = Quad-Core Intel® Xeon® processor 5300 series AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad processor

Q6000 sequence AL = Dual-Core Intel® Xeon® processor 7100 series AM = Intel® Celeron® processor 400 sequence AN = Intel® Pentium® dual-core processor

8 Specification Update

Summary Tables of Changes

AO = Quad-Core Intel® Xeon® processor 3200 series AP = Dual-Core Intel® Xeon® processor 3000 series AQ = Intel® Pentium® dual-core desktop processor E2000 sequence AR = Intel® Celeron® processor 500 series AS = Intel® Xeon® processor 7200, 7300 series

AT = Intel

Celeron® processor 200 series AU = Intel® Celeron® Dual Core processor T1400 AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad processor Q9000 series AW = Intel® Core™ 2 Duo processor E8000 series AX = Quad-Core Intel® Xeon® processor 5400 series AY = Dual-Core Intel® Xeon® processor 5200 series AZ= Intel® Core™2 Duo processor and Intel® Core™2 Extreme processor on 45-nm process AAA= Quad-Core Intel® Xeon® processor 3300 series AAB= Dual-Core Intel® Xeon® E3110 processor AAC= Intel® Celeron® dual-core processor E1000 series AAD = Intel® Core™2 Extreme processor QX9775 AAE = Intel® Atom™ processor Z5xx series AAF = Intel® Atom™ processor 200 series AAG = Intel® Atom™ processor N series AAH = Intel® Atom™ processor300 series AAI = Intel® Xeon® Processor 7400 series AAJ = Intel® Core™ i7 processor and Intel® Core™ i7 Extreme Edition processor AAK= Intel® Xeon® processor 5500 series AAL = Intel® Pentium Dual-Core processor E5000 series AAN = Intel® Core™ i7-800 and i5-700 desktop processor series AAO = Intel® Xeon® Processor 3400 Series AAP = Intel® Core™ i7-900 Mobile Processor Extreme Edition Series, Intel® Core™ i7-800 and i7-700 Mobile

Processor Series AAT = Intel® Core™ i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series (Arrandale) AAU = Intel® Core™ i5-600, i3-500 desktop processor series and Intel® Pentium® Processor G6950 AAZ = Intel® Celeron® P4000 and U3000 Mobile Processor Series (Arrandale) BG = Intel® Pentium® P6000 and U5000 Mobile Processor Series (Arrandale)

Specification Update 9

Errata (Sheet 1 of 4)

Summary Tables of Changes

Number

BG1 X X No Fix The Processor May Report a #TS Instead of a #GP Fault

BG2 X X No Fix

BG3 X X No Fix

BG4 X X No Fix

BG5 X X No Fix

BG6 X X No Fix M OV To/From Debug Registers Causes Debug Exception

BG7 X X No Fix

BG8 X X No Fix

BG9 X X No Fix

BG10 X X No Fix

BG11 X X No Fix

BG12 X X No Fix

BG13 X X No Fix

BG14 X X No Fix

BG15 X X No Fix

BG16 X X No Fix

BG17 X X No Fix

BG18 X X No Fix

BG19 X X No Fix

BG20 X X No Fix

Steppings

Status ERRATA

C-2 K-0

REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations

Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher Priority Interrupts/Exceptions and May Push the Wrong Address onto the Stack

Performance Monitor SSE Retired Instructions May Return Incorrect Values

Premature Execution of a Load Operation Prior to Exception Handler Invocation

Incorrect Address Computed For Last Byte of FXSAVE/ FXRSTOR Image Leads to Partial Memory Update

Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM

Single Step Interrupts with Floati ng P oint Ex ception P ending May Be Mishandled

Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame

IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception

General Protection Faul t (#GP) for Instr uctions Greater than 15 Bytes May Be Preempted

General Protection (#GP) Fa ult May Not Be Signaled on Data Segment Limit Violation above 4-G Limit

LBR, BTS, BTM May Report a Wrong Address When an Exception/Interrupt Occurs in 64-bit Mode

MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang

Corruption of CS Segment Register during RSM While Transitioning from Real Mode to Protected Mode

Performance Monitoring Events for Read Miss to Level 3 Cache Fill Occupancy Counter May Be Incorrect

Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately

#GP on Segment Selector Descriptor That Straddles Canonical Boundary May Not Provide Correct Exception Error Code

Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint Is Set on a #GP Instruction

10 Specification Update

Summary Tables of Changes

Errata (Sheet 2 of 4)

Number

BG21 XXNo Fix

BG22 X X No Fix

BG23 X X No Fix

BG24 X X No Fix

BG25 X X No Fix

BG26 X X No Fix

BG27 X X No Fix

BG28 X X No Fix

BG29 X X No Fix

BG30 X X No Fix Two xAPIC Timer Event Interrupts May Unexpectedly Occur

BG31 X X No Fix

BG32 X X No Fix

BG33 X X No Fix APIC Error “Received Illegal Vector” May Be Lost

BG34 X X No Fix

BG35 X X No Fix

BG36 X X No Fix

BG37 X X No Fix

BG38 X X No Fix

BG39 X X No Fix

BG40 X X No Fix

BG41 X X No Fix

Steppings

Status ERRATA

C-2 K-0

An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/POP SS Instruction If It Is Followed by an Instruction That Signals a Floating Point Exception

IA32_MPERF Counter Stops Counting during On-Demand TM1

The Memory Controller tTHROT_OPREF Timings May Be Violated during Self-Refresh Entry

Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does Not Work

Disabling Thermal Monitor While Processor is Hot, Then Reenabling, May Result in Stuck Core Operating Ratio

Writing the Local Vector Table (LVT) When an Interrupt is Pending May Cause an Unexpected Interrupt

xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While in Periodic Mode

Changing the Memory Type for an In-Use Page Translation May Lead to Memory-Ordering Violations

Infinite Stream of Interrupts May Occur If an ExtINT Delivery Mode Interrupt is Received While All Cores in Deep Power Down Technology (code name C6 state)

EOI Transaction May Not Be Sent If Software Enters Core Deep Power Down Technology (code name C6 state) during an Interrupt Service Routine

FREEZE_WHILE_SMM Does Not Prevent Event from Pending PEBS during SMM

DR6 May Contain Incorrect Information When the First Instruction after a MOV SS,r/m or POP SS Is a Store

An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May Also Result in a System Hang

IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized

Performance Monitor Counter INST_RETIRED.STORES May Count Higher Than Expected

Sleeping Cores May Not Be Woken Up on Logical Cluster Mode Broadcast IPI Using Destination Field Instead of Shorthand

Faulting Executions of FXRSTOR May Update State Inconsistently

Performance Monitor Event EPT.EPDPE_MISS May Be Counted While EPT Is Disable

Memory Aliasing of Code Pages May Cause Unpredictable System Behavior

Specification Update 11

Errata (Sheet 3 of 4)

Summary Tables of Changes

Number

BG42 X X No Fix Performance Monitor Counters May Count Incorrectly

BG43 X X No Fix

BG44 X X No Fix

BG45 X X No Fix

BG46 X X No Fix

BG47 X X No Fix

BG48 X X No Fix

BG49 X X No Fix

BG50 X X No Fix

BG51 X X No Fix

BG52 X X No Fix

BG53 X X No Fix

BG54 X X No Fix

BG55 X X No Fix

BG56 X X No Fix

BG57 X X No Fix

BG58 X X No Fix LER MSRs May Be Unreliable

BG59 X X No Fix

BG60 X X No Fix

BG61 X X No Fix

BG62 X X No Fix

Steppings

Status ERRATA

C-2 K-0

Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT Stores to Local DRAM Correctly

Back-to-Back Uncorrected Machine Check Errors May Overwrite IA32_MC3_STATUS.MSCOD

Corrected Errors with a Yellow Error Indication May Be Overwritten by Other Corrected Errors

Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST May Overcount

Performance Monitor Events INSTR_RETIRED and MEM_INST_RETIRED May Count Inaccurately

A Page Fault May Not Be Generated When the PS Bit Is Set to “1” in a PML4E or PDPTE

BIST Results May Be Additionally Reported after a GETSEC[WAKEUP] or INIT-SIPI Sequence

Pending x87 FPU Exceptions (#MF) May Be Signaled Earlier Than Expected

Multiple Performance Monitor Interrupts are Possible on Overflow of IA32_FIXED_CTR2

LBRs May Not be Initialized During Power-On Reset of the Processor

LBR, BTM or BTS Records May Have Incorrect Branch From Information After an Enhanced Intel SpeedStep® Technology Transition, T-states, C1E, or Adaptive Thermal Throttling

DPRSLPVR Signal May Be Incorrectly Asserted on Transition between Low Power C-states

Performance Monitoring Events STORE_BLOCKS.NOT_STA and STORE_BLOCKS.STA May Not Count Events Correctly

Storage of PEBS Record Delayed Following Executi on of MOV SS or STI

Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions

MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error

Debug Exception Flags DR6.B0-B3 Flags May Be Incorrect for Disabled Breakpoints

Critical ISOCH Traffic May Cause Unpredictable System Behavior When Write Major Mode Enabled

A String Instruction That Re-maps a Page May Encounter an Unexpected Page Fault

12 Specification Update

Summary Tables of Changes

Errata (Sheet 4 of 4)

Number

BG63 X X No Fix

BG64 X X No Fix

BG65 X X No Fix PCI Express x16 Root Port Incorrectly NAK's a Nullified TLP

BG66 X X No Fix

BG67 X Fixed

BG68 X X No Fix

BG69 X X No Fix

BG70 X X No Fix

BG71 X Fixed

BG72 X Fixed

BG73 X X No Fix

BG74 X Fixed

BG75 X X No Fix A Synchronous SMI May Be Delayed

BG76 X X No Fix

BG77 X X No Fix PCI Express Cards May Not Train to x16 Link Width

BG78 X X No Fix

BG79 X X No Fix CKE May go Low Within tRFC(min) After a PD Exit

BG80 X X No Fix

Steppings

Status ERRATA

C-2 K-0

MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations

PCI Express* x16 Port Logs Bad TLP Correctable Error When Receiving a Duplicate TLP

PCI Express Graphics x16 Receiver Error Reported When Receiver with L0s Enabled and Link Retrain Performed

Internal Parity Error May Be Incorrectly Signaled during Deep Power Down Technology (code name C6 state) Exit

PMIs during Core Deep Power Down Technology (code name C6 state) Transitions May Cause the System to Hang

2-MB Page Split Lock Accesses Combined with Complex Internal Events May Cause Unpredictable System Behavior

Extra APIC Timer Interrupt May Occur during a Write to the Divide Configuration Register

8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides With Interrupt Acknowledge Cycle From the Preceding Interrupt

CPUID Incorrectly Reports a C-State as Available When this State is Unsupported

The Combination of a Page-Split Lock Access and Data Accesses That Are Split across Cacheline Boundaries May Lead to Processor Livelock

Processor Hangs on Package Deep Power Down technology (code named Deep Power Down Technology (code name C6) State Exit

FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit ModeFP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode

The APIC Timer Current Count Register May Prematurely Read 0x0 While the Timer Is Still Running

Under Certain Low Temperature Conditions, Some Uncore Performance Monitoring Events May Report Incorrect R esults

Specification Update 13

Specification Changes

Number Specification Changes

None for this revision of this specification update.

Specification Clarifications

Number Specif ication Clarifications

None for this revision of this specification update.

Documentation Changes

Number Documentation Changes

None for this revision of this specification update.

Summary Tables of Changes

14 Specification Update

Identification Information

Component Identification via Programming Interface

The Intel® Pentium® P6000 and U5000 Mobile Processor Series stepping can be identified by the following processor signatures:

Reserved

31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0

NOTES:

1. The Extended Family , bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8], to

2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are used to

3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM pro cessor,

4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register

5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register

6. The Stepping ID in bits [3:0] indicates the revision number of that model. See above table for the

Extended

Family

00000000b 0010b 00b 0110 0101b xxxxb

indicate whether the processor belongs to the Intel386®, Intel486®, Pentium®, P entiu m Pro®, Pe ntium® 4, or Intel® Core™ processor family .

identify the model of the processor within the processor’s family.

an OverDrive

after the CPUID instruction is executed with a 1 in the EAX register, an d the generation field of the Device ID register accessible through Boundary Scan.

after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan.

processor stepping ID number in the CPUID information.

Extended

processor, or a dual processor (capable of being used in a dual processor system).

Model

Reserved

Processor

Type

Family

Code

Model

Number

Stepping

When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID

value in the EAX register. Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.

Intel® Pentium® P6000 and U5000 Mobile Processor Series can be identified by the following register contents:

Processor Stepping Vendor ID

C-2 8086h 0044h 12h K-0 8086h 0044h 18h

NOTES:

1. The Vendor ID corresponds to Bits 15:0 of the Vendor ID Register located at offset 00–01h in the PCI

2. The Device ID corresponds to Bits 15:0 of the Device ID Register located at Device 0 offset 02–03h in

3. The Revision Number corresponds to Bits 7:0 of the R evision ID Register located at offset 08h in the PCI

4. Correct Host Device ID requires firmware support.

Specification Update 15

function 0 configuration space. the PCI function 0 configuration space. function 0 configuration space.

Device ID

Revision ID

+ 32 hidden pages