Intel HH80552PG0962M - Pentium 4 3.4 GHz Processor, Pentium 4 631, Pentium 4 641, Pentium 4 651, Pentium 4 661 Datasheet

Intel® Pentium® 4 Processor

∆

6x1

Datasheet

Sequence

– On 65 nm Process in the 775-land LGA Package supporting

Hyper-Threading Technology and Intel

January 2007

®

64 architecture

Document Number: 310308-002

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELL ECTUA L PROP ER TY RIGHTS IS GRAN TED BY TH IS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
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MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT
INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.

Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Pentium® 4 Processor 6x1 sequence may contain design defects or errors known as errata which may cause the product to deviate from

published specifications.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

∆

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different
processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in
clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular
feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/
processor_number for details.

Intel® 64 requires a computer system with a processor , chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor
will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software
configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or
consult with your system vendor for more information.

1

Hyper-Threading Technolo gy re qui res a comp ut er system wi th an Intel® Pentium® 4 processor supporting Hyper-Threading Technology and an HT
Technology enabled chipset, BIOS, and an operating system. Performance will vary depending on the specific hardware and software you use. See
<http://www.intel.com/products/ht/hyperthreading_more.htm> for information including details on which processors support HT Technology.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check
with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

Not all specified units of this processor support Enhanced HALT State and Enhanced Intel SpeedStep
http://processorfinder.intel.com or contact your Intel representative for more information.

Intel, Pentium, Intel NetBurst Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the
United States and other countries.

®

Technology. See the Processor Spec Finder at

*Other names and brands may be claimed as the property of others.
Copyright © 2006 Intel Corporation.

2 Datasheet

Contents

1 Introduction .......................................................................................................9

1.1 Terminology .....................................................................................................10

1.1.1 Processor Packaging Terminology.............................................................10

1.2 References.......................................................................................................11

2 Electrical Specifications...............................................................................13

2.1 Power and Ground Lands....................................................................................13

2.2 Decoupling Guidelines........................................................................................13

2.2.1 VCC Decoupling ................................................ ............................ ..........13

2.2.2 VTT Decoupling ......................................................................................13

2.2.3 FSB Decoupling......................................................................................14

2.3 Voltage Identification.........................................................................................14

2.4 Reserved, Unused, and TESTHI Signals ................................................................16

2.5 Voltage and Current Specification........................................................................17

2.5.1 Absolute Maximum and Minimum Ratings ..................................................17

2.5.2 DC Voltage and Current Specification.................................................... .. ..18

2.5.3 VCC Overshoot .......................... .. ...........................................................21

2.5.4 Die Voltage Validation............................. ........................... .. .. ... ..............22

2.6 Signaling Specifications................................................................. .. .. .................22

2.6.1 FSB Signal Groups..................................................................................23

2.6.2 GTL+ Asynchronous Signals.....................................................................25

2.6.3 Processor DC Specifications.....................................................................25

2.6.3.1 GTL+ Front Side Bus Specifications .............................................28

2.7 Clock Specifications...........................................................................................29

2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking............................29

2.7.2 FSB Frequency Select Signals (BSEL[2:0]).................................................30

2.7.3 Phase Lock Loop (PLL) and Filter ..............................................................30

2.7.4 BCLK[1:0] Specifications.........................................................................32

3 Package Mechanical Specifications..................................................................33

3.1 Package Mechanical Drawing................ .. .. .. .........................................................33

3.2 Processor Component Keep-Out Zones................................................... .. ............37

3.3 Package Loading Specifications ................................... .. .. ... ........................... .. .. ..37

3.4 Package Handling Guidelines........................ ... ....................................................37

3.5 Package Insertion Specifications............................................... .. .........................38

3.6 Processor Mass Specification ...............................................................................38

3.7 Processor Materials............................................................................................38

3.8 Processor Markings............................................................................................38

3.9 Processor Land Coordinates................................................................................39

4 Land Listing and Signal Descriptions...............................................................41

4.1 Processor Land Assignments...............................................................................41

4.2 Alphabetical Signals Reference............................................................................64

5 Thermal Specifications and Design Considerations.......................................75

5.1 Processor Thermal Specifications.........................................................................75

5.1.1 Thermal Specifications............................................................................75

5.1.2 Thermal Metrology .................................................................................79

5.2 Processor Thermal Features................................................................................79

5.2.1 Thermal Monitor.....................................................................................79

5.2.2 Thermal Monitor 2..................................................................................80

5.2.3 On-Demand Mode ..................................................................................81

5.2.4 PROCHOT# Signal..................................................................................82

Datasheet 3

5.2.5 THERMTRIP# Signal.............................. .. ........................... .....................82

5.2.6 T

5.2.7 Thermal Diode............................. ............................ ........................... ....82

CONTROL

and Fan Speed Reduction...........................................................82

6 Features..............................................................................................................85

6.1 Power-On Configuration Options..........................................................................85

6.2 Clock Control and Low Power States.............................................. .......................85

6.2.1 Normal State .........................................................................................86

6.2.2 HALT and Enhanced HALT Powerdown States..............................................86

6.2.2.1 HALT Powerdown State....................................... .......................86

6.2.2.2 Enhanced HALT Powerdown State . ...............................................87

6.2.3 Stop Grant State ....................................................................................87

6.2.4 Enhanced HALT Snoop or HALT Snoop State,

Stop Grant Snoop State...........................................................................88

6.2.4.1 HALT Snoop State, Stop Grant Snoop State ..................................88

6.2.4.2 Enhanced HALT Snoop State.......................................................88

7 Boxed Processor Specifications........................................................................89

7.1 Mechanical Specifications....................................................................................89

7.1.1 Boxed Processor Cooling Solution Dimensions.............................................89

7.1.2 Boxed Processor Fan Heatsink Weight .......................................................91

7.1.3 Boxed Processor Retention Mechanism and Heatsink

7.2 Electrical Requirements ................................................ .. ............................ ........91

7.2.1 Fan Heatsink Power Supply.............................. .. .. .. ............................ .. .. ..91

7.3 Thermal Specifications................................................ .. ............................ .. ........93

7.3.1 Boxed Processor Cooling Requirements......................................................93

Attach Clip Assembly...............................................................................91

8 Balanced Technology Extended (BTX) Boxed Processor Specifications.....95

8.1 Mechanical Specifications....................................................................................96

8.1.1 Balanced Technology Extended (BTX) Type I and

8.1.2 Boxed Processor Thermal Module Assembly Weight .....................................98

8.1.3 Boxed Processor Support and Retention Module (SRM) ................................98

8.2 Electrical Requirements ................................................ .. ............................ ........99

8.2.1 Thermal Module Assembly Power Supply....................................................99

8.3 Thermal Specifications....................... ........................... .. .. ............................ .. ..101

8.3.1 Boxed Processor Cooling Requirements....................................................101

8.3.2 Variable Speed Fan........................ .. .. ...................................................102

Type II Boxed Processor Cooling Solution Dimensions..................................96

9 Debug Tools Specifications..............................................................................105

9.1 Logic Analyzer Interface (LAI) ...........................................................................105

9.1.1 Mechanical Considerations ..................................................................... 105

9.1.2 Electrical Considerations........................ ................................................105

4 Datasheet

Figures

1VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream)

and for 775_VR_CONFIG_06 Processors................ ............................................. .. ....... 21

2VCC Overshoot Example Waveform.............................................................................22

3 Phase Lock Loop (PLL) Filter Requirements..................................................................31

4 Processor Package Assembly Sketch...........................................................................33

5 Processor Package Drawing Sheet 1 of 3........................................ .. .. .........................34

6 Processor Package Drawing Sheet 2 of 3........................................ .. .. .........................35

7 Processor Package Drawing Sheet 3 of 3........................................ .. .. .........................36

8 Processor Top-Side Markings Example ........................................................................38

9 Processor Land Coordinates and Quadrants (Top View) .................................................39

10 land-out Diagram (Top View – Left Side).....................................................................42

11 land-out Diagram (Top View – Right Side)...................................................................43

12 Thermal Profile for 775_VR_CONFIG_05A Processors....................................................77

13 Thermal Profile for 775_VR_CONFIG_06 Processors......................................................78

14 Case Temperature (TC) Measurement Location ............................................................79

15 Thermal Monitor 2 Frequency and Voltage Ordering......................................................81

16 Processor Low Power State Machine ...........................................................................86

17 Mechanical Representation of the Boxed Processor .................................... .. ... ..............89

18 Space Requirements for the Boxed Processor (Side View; applies to all four side views) ....90

19 Space Requirements for the Boxed Processor (Top View)...............................................90

20 Space Requirements for the Boxed Processor (Overall View)................................ .. ........91

21 Boxed Processor Fan Heatsink Power Cable Connector Description.................................. 92

22 Baseboard Power Header Placement Relative to Processor Socket...................................93

23 Boxed Processor Fan Heatsink Airspace Keep-out Requirements

(Side 1 View) ..........................................................................................................94

24 Boxed Processor Fan Heatsink Airspace Keep-out Requirements

(Side 2 View) ..........................................................................................................94

25 Mechanical Representation of the Boxed Processor with a Type I TMA .............................95

26 Mechanical Representation of the Boxed Processor with a Type II TMA ............................96

27 Requirements for the Balanced Technology Extended (BTX) Type I Keep-out Volumes....... 97

28 Requirements for the Balanced Technology Extended (BTX) Type II Keep-out Volume....... 98

29 Assembly Stack Including the Support and Retention Module.........................................99

30 Boxed Processor TMA Power Cable Connector Description............................................ 100

31 Balanced Technology Extended (BTX) Mainboard Power Header Placement

(Hatched Area)...................................................................................................... 101

32 Boxed Processor TMA Set Points............................................................................... 102

Datasheet 5

Tables

1 References ..............................................................................................................11

2 Voltage Identification Definition..................................................................................15

3 Absolute Maximum and Minimum Ratings ...................... .. ........................... .. ... .. ..........17

4 Voltage and Current Specification...............................................................................18

5VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream)

and for 775_VR_CONFIG_06 Processors......................................................................20

6VCC Overshoot Specifications................... .. .. .. ........................... ... .. ........................... ..21

7 FSB Signal Groups....................................................................................................23

8 Signal Characteristics................................................................................................24

9 Signal Reference Voltages ................................................. .. ............................ .. ........24

10 GTL+ Signal Group DC Specifications..........................................................................25

11 GTL+ Asynchronous Signal Group DC Specifications......................................................25

12 PWRGOOD and TAP Signal Group DC Specifications.......................................................26

13 VTTPWRGD DC Specifications.....................................................................................27

14 BSEL[2:0] and VID[5:0] DC Specifications........................................ ...........................27

15 BOOTSELECT DC Specifications ................................................ ... ........................... .. ..27

16 GTL+ Bus Voltage Definitions.....................................................................................28

17 Core Frequency to FSB Multiplier Configuration.............................................................29

18 BSEL[2:0] Frequency Table for BCLK[1:0] ...................................................................30

19 Front Side Bus Differential BCLK Specifications.............................................................32

20 Processor Loading Specifications.................................................................................37

21 Package Handling Guidelines..................................................................... .................37

22 Processor Materials...................................................................................................38

23 Alphabetical Land Assignments...................................................................................44

24 Numerical Land Assignment.......................................................................................54

25 Signal Description (Sheet 1 of 9)................................................................................64

26 Processor Thermal Specifications for 775_VR_CONFIG_05A Processors ............................76

27 Processor Thermal Specifications for 775_VR_CONFIG_06 Processors..............................76

28 Thermal Profile for 775_VR_CONFIG_05A Processors.....................................................77

29 Thermal Profile for 775_VR_CONFIG_06 Processors ......................................................78

30 Thermal “Diode” Parameters using Diode Model............................................................83

31 Thermal “Diode” Parameters using Transistor Model......................................................83

32 Thermal “Diode” n

33 Thermal Diode Interface............................................................................................84

34 Power-On Configuration Option Signals .......................................................................85

35 Fan Heatsink Power and Signal Specifications...............................................................92

36 TMA Power and Signal Specifications.........................................................................100

37 TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed Processors............103

and Diode_Correction_Offset................................ .. .. ...................84

trim

§

6 Datasheet

Revision History

Revision No. Description Date of Release

-001 • Initial release January 2006

-002 • Added Intel Pentium 4 processor 651, 641, and 631 at 65 W. January 2007

§

Datasheet 7

Intel® Pentium® 4 Processor 6x1 Sequence

• Available at 3.6 GHz , 3.40 GHz, 3.20 GHz, and
3

GHz

• Supports Hyper-Threading Technology1
(HT Technology) for all frequencies with
800

MHz front side bus (FSB)

• Supports Intel® 64 architecture

• Supports Execute Disable Bit capability

• Binary compatible with applications running on
previous members of the Intel microprocessor line

• Intel NetBurst® microarchitecture

• FSB frequency at 800 MHz

• Hyper-Pipelined Technology

• Advance Dynamic Execution

• Very deep out-of-order execution

• Enhanced branch prediction

• Optimized for 32-bit applications running on
advanced 32-bit operating systems

The Intel® Pentium® 4 processor family supporting Hyper-Threading Technology1 (HT Technology) delivers
Intel's advanced, powerful processors for desktop PCs and entry-level workstations that are based on the Intel
NetBurst
usages where end-users can truly appreciate and experience the performance. These applications include Internet
audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and
multitasking user environments. Intel
systems and applications written to take advantage of the Intel 64 architecture.

®

microarchitecture. The Pentium 4 processor is designed to deliver performance across applications and

®

64 architecture enables the Intel® Pentium® processor to execute operating

• 16-KB Level 1 data cache

• 2-MB Advanced Transfer Cache (on-die, full­speed Level 2 (L2) cache) with 8-way associativity
and Error Correcting Code (ECC)

• 144 Streaming SIMD Extensions 2 (SSE2)
instructions

• 13 Streaming SIMD Extensions 3 (SSE3)
instructions

• Enhanced floating point and multimedia unit for
enhanced video, audio, encryption, and 3D
performance

• Power Management capabilities

• System Management mode

• Multiple low-power states

• 8-way cache associativity provides improved
cache hit rate on load/store operations

• 775-land Package

§ §

8 Datasheet

Introduction

1 Introduction

The Intel® Pentium® 4 processors 6x1 sequence are the first single-core desktop
processors on the 65 nm process. The Pentium 4 processor uses Flip-Chip Land Grid
Array (FC-LGA6) package technology, and plugs into a 775-land surface mount, Land
Grid Array (LGA) socket, referred to as the LGA775 socket.

Note: In this document, unless otherwise specified, the Intel® Pentium® 4 processor 6x1

sequence refers to Intel Pentium 4 processors 661, 651, 641, 631.

Note: In this document the Intel® Pentium® 4 processor 6x1 sequence on 65 nm process in

the 775-land package will be referred to as the “Pentium 4 processor,” or simply “the
processor.”

The Pentium 4 processor supports Intel® 64 architecture. This enhancement allows the
processor to execute operating systems and applications written to take advantage of
Intel 64 architecture. Further details on the 64-bit extension architecture and
programming model are in the Intel

®

Extended Memory 64 Technology Software

Developer Guide at http://developer.intel.com/technology/64bitextensions/.

The Pentium 4 processor supports Hyper-Threading Technology1. Hyper-Threading
Technology allows a single, physical processor to function as two logical processors.
While some execution resources such as caches, execution units, and buses are shared,
each logical processor has its own architecture state with its own set of general­purpose registers and control registers to provide increased system responsiveness in
multitasking environments and headroom for next generation multithreaded
applications. Intel recommends enabling Hyper-Threading Technology with Microsoft
Windows* XP Professional or Windows* XP Home, and disabling Hyper-Threading
Technology via the BIOS for all previous versions of Windows operating systems. For
more information on Hyper-Threading Technology, see http://www.intel.com/products/
ht/hyperthreading_more.htm. Refer to

Section 6.1 for Hyper-Threading Technology

configuration details.
The Pentium 4 processor’s Intel NetBurst® microarchitecture front side bus (FSB) uses

a split-transaction, deferred reply protocol like previous Intel

®

Pentium® 4 processors.
The Intel NetBurst microarchitecture FSB uses Source-Synchronous Transfer (SST) of
address and data to improve performance by transferring data four times per bus clock
(4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can
deliver addresses two times per bus clock and is referred to as a “double-clocked” or 2X
address bus. Working together, the 4X data bus and 2X address bus provide a data bus
bandwidth of up to 8.5 GB/s.

Intel will enable support components for the Pentium 4 processor including heatsink,
heatsink retention mechanism, and socket. Manufacturability is a high priority; hence,
mechanical assembly may be completed from the top of the baseboard and should not
require any special tooling.

The Pentium 4 processor also include the Execute Disable Bit capability previously
available in Intel

®

Itanium® processors. This feature, combined with a supported

operating system, allows memory to be marked as executable or non-executable. If
code attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms that
exploit buffer over run vulnerabilities and can thus help improve the overall security of
the system. See the Intel

®

64 and IA-32 Architecture Software Developer’s Manual for

more detailed information.

Datasheet 9

The processor includes an address bus powerdown capability that removes power from
the address and data signals when the FSB is not in use. This feature is always enabled
on the processor.

Enhanced Intel® SpeedStep® technology allows trade-offs to be made between
performance and power consumptions. This may lower average power consumption (in
conjunction with OS support).

1.1 Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

Front Side Bus refers to the interface between the processor and system core logic
(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors,
memory, and I/O.

1.1.1 Processor Packaging Terminology

Introduction

Commonly used terms are explained here for clarification:

• Intel® Pentium® 4 processor on 65 nm process in the 775-land package —
Processor in the FC-LGA6 package with a 2 MB L2 cache.

• Processor — For this document, the term processor is the generic form of the

• Keep-out zone — The area on or near the processor that system design can not

• Intel® 945G/945GZ/945P/945PL Express chipsets — Chipset that supports

• Processor core — Processor core die with integrated L2 cache.

• LGA775 socket — The P entium 4 processor mates with the system board through

• Integrated heat spreader (IHS) —A component of the processor package used

• Retention mechanism (RM) — Since the LGA775 socket does not include any

• FSB (Front Side Bus) — The electrical interface that connects the processor to

• Storage conditions — Refers to a non-operational state. The processor may be

®

Pentium® 4 processor 6x1 sequence on 65 nm process in the 775-land

Intel
package.

utilize.

DDR and DDR2 memory technology for the Pentium 4 processor.

a surface mount, 775-land, LGA socket.

to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.

mechanical features for heatsink attach, a retention mechanism is required.
Component thermal solutions should attach to the processor via a retention
mechanism that is independent of the socket.

the chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.

installed in a platform, in a tray , or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased, or receive any clocks.
Upon exposure to “free air”(i.e., unsealed packaging or a device removed from

10 Datasheet

Introduction

packaging material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.

• Functional operation — Refers to normal operating conditions in which all
processor specifications, including DC, AC, system bus, signal quality, mechanical
and thermal are satisfied.

1.2 References

Material and concepts available in the following documents may be beneficial when
reading this document.

Table 1. References

Intel® Pentium® 4 Processor 6x1 Sequence Specification
Update

Intel® Pentium® D Processor, Intel® Pentium® Processor
Extreme Edition, and Intel
and Mechanical Design Guidelines

NOTE: Refer to this document for 86 W processors.

Intel® Core™2 Duo Desktop Processor E6000 Sequence and

®

Intel

Pentium® 4 Processor 6x1 Sequence Thermal and

Mechanical Design Guidelines

NOTE: Refer To this document for 65 W processors.

Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery
Design Guidelines For Desktop LGA775 Socket

LGA775 Socket Mechanical Design Guide
Balanced Technology Extended (BTX) System Design Guide http://www.formfactors.org

Intel® 64 and IA-32 Architecture Software Developer’s
Manuals

Volume 1: Basic Architecture

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide

Volume 3B: System Programming Guide

Document Location

http://www.intel.com/design/
pentium4/specupdt/

310309.htm

®

Pentium® 4 Processor Thermal

http://www.intel.com/design/
pentiumXE/designex/

306830.htm

http://www.intel.com/design/
processor/designex/

313685.htm

http://www.intel.com/design/
Pentium4/guides/302356.htm

http://www.intel.com/design/
Pentium4/guides/302666.htm

http://www.intel.com/
products/processor/manuals/

http://www.intel.com/
products/processor/manuals/

http://www.intel.com/
products/processor/manuals/

http://www.intel.com/
products/processor/manuals/

http://www.intel.com/
products/processor/manuals/

§ §

Datasheet 11

Introduction

12 Datasheet

Electrical Specifications

2 Electrical Specifications

This chapter describes the electrical characteristics of the processor interfaces and
signals. DC electrical characteristics are provided.

2.1 Power and Ground Lands

The Pentium 4 processor has 226 VCC (power), 24 VTT and 273 VSS (ground) inputs
for on-chip power distribution. All power lands must be connected to V
lands must be connected to a system ground plane. The processor VCC lands must be
supplied the voltage determined by the Voltage IDentification (VID) lands.

T wenty -four (24) signals are denoted as VT T, that provide termination for the front side
bus and power to the I/O buffers. A separate supply must be implemented for these
lands, that meets the VTT specifications outlined in Table 4.

2.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings. This may cause voltages on power planes
to sag below their minimum specified values if bulk decoupling is not adequate. Larger
bulk storage (C
current during longer lasting changes in current demand by the component, such as
coming out of an idle condition. Similarly, they act as a storage well for current when
entering an idle condition from a running condition. The motherboard must be designed
to ensure that the voltage provided to the processor remains within the specifications
listed in
the component.

Table 4. Failure to do so can result in timing violations or reduced lifetime of

), such as electrolytic or aluminum-polymer capacitors, supply

BULK

, while all VSS

CC

2.2.1 VCC Decoupling

VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the
processor voltage specifications. This includes bulk capacitance with low effective series
resistance (ESR) to keep the voltage rail within specifications during large swings in
load current. In addition, ceramic decoupling capacitors are required to filter high
frequency content generated by the front side bus and processor activity. Consult the

Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable
LGA775 Socket for further information.

2.2.2 VTT Decoupling

Decoupling must be provided on the motherboard. Decoupling solutions must be sized
to meet the expected load. T o insure complian ce with the specifications, various factors
associated with the power delivery solution must be considered including regulator
type, power plane and trace sizing, and component placement. A conservative
decoupling solution would consist of a combination of low ESR bulk capacitors and high
frequency ceramic capacitors.

Datasheet 13

2.2.3 FSB Decoupling

The processor integrates signal termination on the die. In addition, some of the high
frequency capacitance required for the FSB is included on the processor package.
However, additional high frequency capacitance must be added to the motherboard to
properly decouple the return currents from the front side bus. Bulk decoupling must
also be provided by the motherboard for proper [A]GTL+ bus operation.

2.3 Voltage Identification

The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775
Socket. The voltage set by the VID signals is the reference VR output voltage to be

delivered to the processor VCC lands (see
specifications). Refer to Table 14 for the DC specifications for these signals. A minimum
voltage for each processor frequency is provided in Table 4.

Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core speed may have different default VID settings. This is
reflected by the VID Range values provided in
Processor Specification Update for further details on specific valid core frequency and
VID values of the processor. Note that this differs from the VID employed by the
processor during a power management event (Thermal Monitor 2, Enhanced Intel
SpeedStep technology, or Enhanced HALT State).

Electrical Specifications

Chapter 2.5.3 for VCC overshoot

Table 4. Refer to the Intel® Pentium® 4

The processor uses 6 voltage identification signals, VID[5:0], to support automatic
selection of power supply voltages.
the state of VID[5:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to
a low voltage level. If the processor socket is empty (VID[5:0] = x11111), or the
voltage regulation circuit cannot supply the voltage that is requested, it must disable
itself. See the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and
Transportable LGA775 Socket for further details.

The processor provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (V
line. It should be noted that a low-to-high or high-to-low voltage state change may
result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted.
and DC shift ranges. Minimum and maximum v oltages must be maintained as shown in

Table 5 and Figure 1 as measured across the VCC_SENSE and VSS_SENSE lands.

The VRM or VRD used must be capable of regulating its output to the value defined by
the new VID. DC specifications for dynamic VID transitions are included in

Table 5. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop

and Transportable LGA775 Socket for further details.

Table 2 specifies the voltage level corresponding to

). This will represent a DC shift in the load

CC

Table 4 includes VID step sizes

Table 4 and

14 Datasheet

Electrical Specifications

Table 2. Voltage Identification Definition

VID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID

0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125
1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250
0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375
1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500
0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625
1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750
0 0 0 1 1 1 0.9125 0 1 0 1 1 1 1.2875
1 0 0 1 1 0 0.9250 1 1 0 1 1 0 1.3000
0 0 0 1 1 0 0.9375 0 1 0 1 1 0 1.3125
1 0 0 1 0 1 0.9500 1 1 0 1 0 1 1.3250
0 0 0 1 0 1 0.9625 0 1 0 1 0 1 1.3375
1 0 0 1 0 0 0.9750 1 1 0 1 0 0 1.3500
0 0 0 1 0 0 0.9875 0 1 0 1 0 0 1.3625
1 0 0 0 1 1 1.0000 1 1 0 0 1 1 1.3750
0 0 0 0 1 1 1.0125 0 1 0 0 1 1 1.3875
1 0 0 0 1 0 1.0250 1 1 0 0 1 0 1.4000
0 0 0 0 1 0 1.0375 0 1 0 0 1 0 1.4125
1 0 0 0 0 1 1.0500 1 1 0 0 0 1 1.4250
0 0 0 0 0 1 1.0625 0 1 0 0 0 1 1.4375
1 0 0 0 0 0 1.0750 1 1 0 0 0 0 1.4500
0 0 0 0 0 0 1.0875 0 1 0 0 0 0 1.4625
1 1 1 1 1 1 VR output off 1 0 1 1 1 1 1.4750
0 1 1 1 1 1 VR output off 0 0 1 1 1 1 1.4875
1 1 1 1 1 0 1.1000 1 0 1 1 1 0 1.5000
0 1 1 1 1 0 1.1125 0 0 1 1 1 0 1.5125
1 1 1 1 0 1 1.1250 1 0 1 1 0 1 1.5250
0 1 1 1 0 1 1.1375 0 0 1 1 0 1 1.5375
1 1 1 1 0 0 1.1500 1 0 1 1 0 0 1.5500
0 1 1 1 0 0 1.1625 0 0 1 1 0 0 1.5625
1 1 1 0 1 1 1.1750 1 0 1 0 1 1 1.5750
0 1 1 0 1 1 1.1875 0 0 1 0 1 1 1.5875
1 1 1 0 1 0 1.2000 1 0 1 0 1 0 1.6000

Datasheet 15

2.4 Reserved, Unused, and TESTHI Signals

All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS,

, or to any other signal (including each other) can result in component malfunction

V

TT

or incompatibility with future processors. See
processor and the location of all RESERVED lands.

In a system level design, on-die termination has been included by the processor to
allow signals to be terminated within the processor silicon. Most unused GTL+ inputs
should be left as no connects as GTL+ termination is provided on the processor silicon.
However, see

Table 7 for details on GTL+ signals that do not include on-die termination.

Unused active high inputs, should be connected through a resistor to ground (VSS).
Unused outputs can be left unconnected; however, this may interfere with some TAP
functions, complicate debug probing, and prevent boundary scan testing. A resistor
must be used when tying bidirectional signals to power or ground. When tying any
signal to power or ground, a resistor will also allow for system testability. Resistor
values should be within ± 20% of the impedance of the motherboard trace for front
side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the
same value as the on-die termination resistors (RT

TAP, GTL+ Asynchronous inputs, and GTL+ Asynchronous outputs do not include on-die
termination. Inputs and utilized outputs must be terminated on the motherboard.
Unused outputs may be terminated on the motherboard or left unconnected. Note that
leaving unused outputs unterminated may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing.

Chapter 4 for a land listing of the

). For details, see Table 16.

T

Electrical Specifications

All TESTHI[13:0] lands should be individually connected to VTT via a pull-up resistor
that matches the nominal trace impedance.

The TESTHI signals may use individual pull-up resistors or be grouped together as
detailed below. A matched resistor must be used for each group:

•TESTHI[1:0]

•TESTHI[7:2]

• TESTHI8 – cannot be grouped with other TESTHI signals

• TESTHI9 – cannot be grouped with other TESTHI signals

• TESTHI10 – cannot be grouped with other TESTHI signals

• TESTHI11 – cannot be grouped with other TESTHI signals

• TESTHI12 – cannot be grouped with other TESTHI signals

• TESTHI13 – cannot be grouped with other TESTHI signals

However, using boundary scan test will not be functional if these lands are connected
together. For optimum noise margin, all pull-up resistor values used for TESTHI[13:0]
lands should have a resistance value within ± 20% of the impedance of the board
transmission line traces. For example, if the nominal trace impedance is 50
value between 40

Ω and 60 Ω should be used.

Ω, then a

16 Datasheet

Electrical Specifications

2.5 Voltage and Current Specification

2.5.1 Absolute Maximum and Minimum Ratings

Table 3 specifies absolute maximum and minimum ratings. Within functional operation

limits, functionality and long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute

maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function, or its reliability will be
severely degraded.

Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.

Table 3. Absolute Maximum and Minimum Ratings

Symbol Parameter Min Max Unit Notes

V

CC

V

TT

T

C

T

STORAGE

NOTES:

1. For functional operation, all processor electrical, signal quality, mechanical and ther mal specifications must be
satisfied.

2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive
a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long­term reliability of the device. For functional operation, refer to the processor case temperature specifications.

4. This rating applies to the processor and does not include any tray or packaging.

5. Failure to adhere to this specification can affect the long term reliability of the processor.

Core voltage with respect to V
FSB termination voltage with

respect to V

Processor case temperature

Processor storage temperature –40 85 °C

SS

SS

–0.3 1.55 V

–0.3 1.55 V

See

Chapter 5

See

Chapter 5

1,2

°C

3, 4, 5

Datasheet 17

Electrical Specifications

2.5.2 DC Voltage and Current Specification

Table 4. Voltage and Current Specification

Symbol Parameter Min Typ Max Unit Notes

VID Range VID 1.200 — 1.3375 V

Processor
number

VCC for 775_VR_CONFIG_05A

1, 2

3

V

CC

I

CC

I

SGNT

I

ENHANCED_

AUTO_HALT

I

TCC

V

TT

661
651
641
631

Processor

3.6 GHz

3.4 GHz

3.2 GHz
3 GHz

ICC for 775_VR_CONFIG_05A

Refer to Table 5 and

Figure 1

number

661
651
641
631

Processor

ICC for 775_VR_CONFIG_06

3.6 GHz

3.4 GHz

3.2 GHz
3 GHz

— —

number

651
641
631

Processor
number

661
651
641
631

Processor
number

651
641
631

Processor
number

661
651
641
631

Processor
number

651
641
631

ICC Stop-Grant for

775_VR_CONFIG_05A

ICC Stop-Grant for
775_VR_CONFIG_06

ICC Enhanced Halt for

775_VR_CONFIG_05A

ICC Enhanced Auto HALT for
775_VR_CONFIG_06

3.4 GHz

3.2 GHz
3 GHz

3.6 GHz

3.4 GHz

3.2 GHz
3 GHz

3.4 GHz

3.2 GHz
3 GHz

3.6 GHz

3.4 GHz

3.2 GHz
3 GHz

3.4 GHz

3.2 GHz
3 GHz

— —

— —

ICC TCC active — — I
FSB termination voltage

(DC + AC specifications)

1.14 1.20 1.26 V

100
100
100
100 A

65
65
65

50
50
50
50

40
40
40

40
40
40
40

25
25
25

CC

V

A

A

A

4, 5, 6

7

8,9,10,11

8,10,11

12

13, 14

18 Datasheet

Electrical Specifications

Table 4. Voltage and Current Specification

Symbol Parameter Min Typ Max Unit Notes

VTT_OUT_LEFT
and
VTT_OUT_RIGHT
I

CC

I

TT

I

TT_POWER-UP

I

CC_VCCA

I

CC_VCCIOPLL

I

CC_GTLREF

DC Current that may be drawn from
VTT_OUT_LEFT and VTT_OUT_RIGHT per

— — 580 mA

pin
Steady-state FSB termination current — — 3.5 A

Power-up FSB termination current — — 4.5 A
ICC for PLL lands — — 35 mA
ICC for I/O PLL land — — 26 mA
ICC for GTLREF — — 200 µA

NOTES:

1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.

2. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation.

3. Each processor is programmed with a maximum valid voltage identification value (VID) that is set at manufacturing and can
not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same
frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor
during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep technology, or Enhanced HALT State).

4. These voltages are targets only . A vari able voltage source should exist on systems in the event that a different

voltage is required. See Section 2.3 and Table 2 for more information.

5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz
bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1
wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into t he oscilloscope probe.

6. Refer to Table 5 and Figure 1 for the minimum, typical, and maximum V

processor should not be subjected to any VCC and ICC combination wherein VCC exceeds V
current.

7. I

8. The current specified is also for AutoHALT State.

9. ICC Stop-Grant is specified at V

10.I

11.Th ese parameters are based on design characterization and are not tested.

12.The maximum instantaneous current the processor will draw while the thermal control circuit is active (as indicated by the

13.VTT must be provided via a separate voltage source and not be connected to VCC. This specification is measured at the land.

14.Baseboard bandwidth is limited to 20 MHz.

15.This is maximum total current drawn from V

16.This is a steady-state ITT current specification, which is applicable when both VTT and VCC are high.

17.This is a power-up peak current specification that is applicable when VTT is high and VCC is low.

is specified at V

CC_MAX

and I

SGNT

assertion of PROCHOT#) is the same as the maximum

the current coming from RTT (through the signal line). Refer to the Voltage Regulato r-Down (VRD) 10.1 Design Gui de

For Desktop and Transportable LGA775 Socket

ENHANCED_AUTO_HALT

.

CC_MAX

CC_MAX

are specified at V

.

and TC = 50 °C.

CC_TYP

ICC for the processor.

plane by only the processor. This specification does not include

TT

to determine the total ITT drawn by the system.

MΩ minimum impedance. The maximum length of ground

allowed for a given current. The

CC

CC_MAX

1, 2

15, 16

15, 17

for a given

Datasheet 19

Electrical Specifications

Table 5. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream)

and for 775_VR_CONFIG_06 Processors

Voltage Deviation from VID Setting (V)

ICC (A)

Maximum Voltage

1.7 mΩ

Typical Voltage

1.75 mΩ

0 0.000 -0.019 -0.038

5 -0.009 -0.028 -0.047
10 -0.017 -0.037 -0.056
15 -0.026 -0.045 -0.065
20 -0.034 -0.054 -0.074
25 -0.043 -0.063 -0.083
30 -0.051 -0.072 -0.092
35 -0.060 -0.080 -0.101
40 -0.068 -0.089 -0.110
45 -0.077 -0.098 -0.119
50 -0.085 -0.107 -0.128
55 -0.094 -0.115 -0.137
60 -0.102 -0.124 -0.146
65 -0.111 -0.133 -0.155
70 -0.119 -0.142 -0.164
75 -0.128 -0.150 -0.173
80 -0.133 -0.156 -0.178
85 -0.145 -0.168 -0.191
90 -0.153 -0.177 -0.200
95 -0.162 -0.185 -0.209

100 -0.170 -0.194 -0.218

NOTES:

1. The loadline specification includes both static and transient limits except for

overshoot allowed as shown in

2. This table is intended to aid in reading discrete points on Figure 1.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and

VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be
taken from processor VCC and VSS lands. Refer to the

10.1 Design Guide For Desktop and Transportable LGA775 Socket

guidelines and VR implementation details.

4. Adherence to this loadline specification for the Pentium 4 processor is required to ensure reliable
processor operation.

Section 2.5.3.

Voltage Regulator-Down (VRD)

1,2,3,4

Minimum Voltage

1.8 mΩ

for socket loadline

20 Datasheet

m

Electrical Specifications

Figure 1. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A ( Mainstream)

and for 775_VR_CONFIG_06 Processors

0 102030405060708090100

VID - 0.000

VID - 0.019

VID - 0.038

VID - 0.057

VID - 0.076

VID - 0.095

VID - 0.114

Vcc [V]

VID - 0.133

VID - 0.152

VID - 0.171

VID - 0.190

VID - 0.209

VID - 0.228

Vcc Typical

Icc [A]

Vcc Maxim u

Vcc Minimum

NOTES:

1. The loadline specification includes both static and transie nt limits except for overshoot
allowed as shown in

Section 2.5.3.

2. This loadline specification shows the deviation from the VID set point.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken
from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 10.1
Design Guide For Desktop and Transportable LGA775 Socket for socket loadline guidelines
and VR implementation details.

2.5.3 VCC Overshoot

The processor can tolerate short transient overshoot events where VCC exceeds the VID
voltage when transitioning from a high to low current load condition. This overshoot
cannot exceed VID + V
The time duration of the overshoot event must not exceed T

OS_MAX

maximum allowable time duration above VID). These specifications apply to the
processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.

Table 6. VCC Overshoot Specifications

Symbol Parameter Min Max Unit Figure Notes

V

OS_MAX

T

OS_MAX

NOTES:

1. Adherence to these specifications for the Pentium 4 processor is required to ensure reliable processor

operation.

Datasheet 21

Magnitude of VCC overshoot above VID — 0.050 V 2
Time duration of VCC overshoot above

VID

(V

OS_MAX

is the maximum allowable overshoot voltage).

OS_MAX

(T

OS_MAX

— 25 µs 2

is the

1

1

Figure 2. VCC Overshoot Example Waveform

Example Oversho o t Waveform

Electrical Specifications

VID + 0.050

VID

Voltage (V)

TOS: Overshoot time above VID
V

: Overshoot above VID

OS

NOTES:

1. VOS is measured overshoot voltage.

2. TOS is measured time duration above VID.

2.5.4 Die Voltage Validation

Overshoot events on the processor must meet the specifications in Table 6 when
measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are
< 10 ns in duration may be ignored. These measurements of processor die level
overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or
equal to 100 MHz bandwidth limit.

V

OS

T

OS

Time

2.6 Signaling Specifications

Most processor front side bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Platforms implement a
termination voltage level for GTL+ signals defined as V
separate power planes for each processor (and chipset), separate V
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see

Table 16 for GTLREF specifications). Termination resistors (RTT) for

GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel
chipsets will also provide on-die termination, thus eliminating the need to terminate the
bus on the motherboard for most GTL+ signals.

22 Datasheet

. Because platforms implement

TT

and V

CC

supplies

TT

Electrical Specifications

2.6.1 FSB Signal Groups

The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers that use GTLREF[1:0] as a reference level. In this
document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+
I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as
well as the GTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals that are dependent
on the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the
source synchronous signals that are relative to their respective strobe lines (data and
address) as well as the rising edge of BCLK0. Asychronous signals are still present
(A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle.

Table 7 identifies which signals are common clock, source synchronous, and

asynchronous.

Table 7. FSB Signal Groups (Sheet 1 of 2)

Signal Group Type Signals

GTL+ Common
Clock Input

GTL+ Common
Clock I/O

Synchronous to
BCLK[1:0]

Synchronous to
BCLK[1:0]

1

BPRI#, DEFER#, RESET#, RS[2:0]#, RSP# , TRDY#

AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#,
DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#,
MCERR#

GTL+ Source
Synchronous I/O

GTL+ Strobes

GTL+
Asynchronous
Input

GTL+
Asynchronous
Output

GTL+
Asynchronous
Input/Output

TAP Input

Synchronous to
assoc. strobe

Synchronous to
BCLK[1:0]

Synchronous to
TCK

Signals Associated Strobe

REQ[4:0]#, A[16:3]#
A[35:17]#
D[15:0]#, DBI0# DSTBP0#, DSTBN0#
D[31:16]#, DBI1# DSTBP1#, DSTBN1#
D[47:32]#, DBI2# DSTBP2#, DSTBN2#
D[63:48]#, DBI3# DSTBP3#, DSTBN3#

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,
STPCLK#, PWRGOOD

FERR#/PBE#, IERR#, THERMTRIP#

PROCHOT#

TCK, TDI, TMS, TRST#

3

3

ADSTB0#
ADSTB1#

Datasheet 23

Table 7. FSB Signal Groups (Sheet 2 of 2)

Signal Group Type Signals

TAP Output

Synchronous to

TCK

FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]

Power/Other

NOTES:

1. Refer to Section 4.2 for signal descriptions.

2. In processor systems where no debug port is implemented on the system board, these

signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.

3. The value of these signals during the active-to-inactive edge of RESET# defines the

.

processor configuration options. See

Table 8. Signal Characteristics

Electrical Specifications

1

TDO

2

VCC, VTT, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA,
GTLREF[1:0], COMP[5:4,1:0], RESERVED, TESTHI[13:0],
THERMDA, THERMDC, VCC_SENSE,
VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, BSEL[2:0], SKTOCC#, DBR#

2

,
VTTPWRGD, BOOTSELECT, VTT_OUT_LEFT,
VTT_OUT_RIGHT, VTT_SEL, LL_ID[1:0], MSID[1:0], FCx,
IMPSEL

Section 6.1 for details.

Signals with R

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#,
BINIT#, BNR#, BOOTSELECT

1

D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
MSID[1:0]
RSP#, TRDY#, IMPSEL

1

, PROCHOT#, REQ[4:0]#, RS[2:0]#,

1

Open Drain Signals

THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,
BR0#, TDO, LL_ID[1:0], FCx

NOTES:

1. These signals have a 500–5000 Ω pull-up to V

2. Signals that do not have RTT, nor are actively driven to their high-voltage level.

Table 9. Signal Reference Voltages

GTLREF VTT/2

BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#,
BINIT#, BNR#, HIT#, HITM#, MCERR#, PROCHOT#,
BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#,
BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,
LOCK#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

NOTES:

1. These signals also have hysteresis added to the reference voltage. See Table 12 for more

information.

TT

, BPRI#,

2

Signals with No R

A20M#, BCLK[1:0], BPM[5:0]#, BSEL[2:0],
COMP[5:4,1:0], FERR#/PBE#, IERR#,
IGNNE#, INIT#, ITP_CLK[1:0], LINT0/INTR,
LINT1/NMI, PWRGOOD, RESET#, SKTOCC#,
SMI#, STPCLK#, TDO, TESTHI[13:0],
THERMDA, THERMDC, THERMTRIP#,
VID[5:0], VTTPWRGD, GTLREF[1:0], TCK,
TDI, TMS, TRST#, VTT_SEL

rather than on-die termination.

TT

BOOTSELECT, VTTPWRGD, A20M#,
IGNNE#, INIT#, MSID[1:0],
PWRGOOD
TDI1, TMS1, TRST#

TT

1

, SMI#, STPCLK#, TCK1,

1

24 Datasheet

Electrical Specifications

2.6.2 GTL+ Asynchronous Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of these signals follow the same DC requirements as GTL+ signals;
however, the outputs are not actively driven high (during a logical 0-to-1 transition) by
the processor. These signals do not have setup or hold time specifications in relation to
BCLK[1:0].

All of the GTL+ Asynchronous signals are required to be asserted/deasserted for at
least six BCLKs in order for the processor to recognize the proper signal state. See

Section 2.6.3 for the DC specifications for the GTL+ Asynchronous signal groups. See
Section 6.2 for additional timing requirements for entering and leaving the low power

states.

2.6.3 Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads)
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.

Table 10. GTL+ Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

V
V

V

I

I

I

R

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3. The VTT referred to in these specifications is the instantaneous VTT.

4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the signal quality
specifications.

6. Leakage to VSS with land held at VTT.

7. Leakage to VTT with land held at 300 mV.

Input Low Voltage 0.0 GTLREF – (0.10 * VTT) V

IL

Input High Voltage GTLREF + (0.10 * VTT) V

IH

Output High Voltage 0.90*V

OH

Output Low Current N/A

OL

Input Leakage

LI

Current
Output Leakage

LO

Current
Buffer On Resistance 6 12 W

ON

TT

N/A ± 200 µA

N/A ± 200 µA

[(0.50*R

V

V

TT_MAX

TT_MIN

TT
TT

)+(R

/

ON_MIN

1

2, 3

3, 4, 5

V

5, 6

V

A

)]

6

7

Table 11. GTL+ Asynchronous Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

V
V

V

I

Datasheet 25

Input Low Voltage 0.0 VTT/2 – (0.10 * VTT) V

IL

Input High Voltage VTT/2 + (0.10 * VTT) V

IH

Output High Voltage 0.90*V

OH

Output Low Current —

OL

TT

[(0.50*R

V

VTT/

TT_MIN

TT
TT

)+(R

ON_MIN

V
V

A

)]

1

2, 3

3, 4, 5, 6

5, 6, 7

8

Table 11. GTL+ Asynchronous Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

I

I

R

Input Leakage

LI

Current
Output Leakage

LO

Current
Buffer On Resistance 6 12 W

ON

N/A ± 200 µA

N/A ± 200 µA

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3. LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals,
VIH = GTLREF + (0.10 * VTT) and VIL= GTLREF – (0.10 * VTT).

4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the signal qual ity
specifications.

6. The VTT referred to in these specifications refers to instantaneous VTT.

7. All outputs are open drain.

8. The maximum output current is based on maximum current handling capability of the buffer and is not specified into
the test load.

9. Leakage to VSS with land held at VTT.

10.Leakage to VTT with land held at 300 mV.

.

Table 12. PWRGOOD and TAP Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

V

V

V

V

I

I

I

R

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. All outputs are open drain.

3. VHYS represents the amount of hysteresis, nominally centered about 0.5 * V

4. The VTT referred to in these specifications refers to instantaneous VTT.

5. 0.24 V is defined at 20% of nominal VTT of 1.2 V.

6. The TAP signal group must meet the signal quality specifications.

7. The maximum output current is based on maximum current handling capability of the buffer and is not specified into
the test load.

8. Leakage to Vss with land held at VTT.

9. Leakage to VTT with land held at 300 mV.

Input Hysteresis 120 396 mV

HYS

PWRGOOD Input low­to-high threshold
voltage

T+

TAP Input low-to-high
threshold voltage

0.5 * (V

0.5 * (V

TT + VHYS_MIN

+ 0.24)

TT + VHYS_MIN

0.5 * (V

) 0.5 * (V

PWRGOOD Input high­to-low threshold
voltage

T-

TAP Input high-to-low
threshold voltage

Output High Voltage N/A V

OH

Output Low Current — 22.2 mA

OL

Input Leakage Current — ± 200 µA

LI

Output Leakage Current — ± 200 µA

LO

Buffer On Resistance 6 12 W

ON

0.5 * (V

0.4 * V

– V

TT

TT

HYS_MAX

) 0.5 * (V

TT + VHYS_MAX

+ 0.24)

TT + VHYS_MAX

0.6 * V

TT

– V

TT

HYS_MIN

TT

Electrical Specifications

10

V

4, 5

) V

V

) V

V

, for all TAP inputs.

TT

4, 6

1

9

1, 2

3

4

4

4

7
8
9

26 Datasheet

Electrical Specifications

Table 13. VTTPWRGD DC Specifications

Symbol Parameter Min Typ Max Unit

V

IL

V

IH

Input Low Voltage — — 0.3 V
Input High Voltage 0.9 — — V

Table 14. BSEL[2:0] and VID[5:0] DC Specifications

Symbol Parameter Max Unit Notes

RON (BSEL) Buffer On Resistance 120 Ω

RON (VID) Buffer On Resistance 120 Ω

I

OL

I

LO

V

TOL

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. These parameters are not tested and are based on design simulations.

3. Leakage to VSS with land held at 2.5 V.

Max Land Current 2.4 mA
Output Leakage Current 200 µA
Voltage Tolerance VTT(max) V

1, 2

3

Table 15. BOOTSELECT DC Specifications

Symbol Parameter Min Typ Max Unit Notes

V

V

NOTES:

1. These parameters are not tested and are based on design simulations.

Input Low Voltage — — 0.24 V

IL

Input High Voltage 0.96 — — V

IH

1

1

Datasheet 27

2.6.3.1 GTL+ Front Side Bus Specifications

In most cases, termination resistors are not required as these are integrated into the
processor silicon. See
termination.

Table 8 for details on which GTL+ signals do not include on-die

Electrical Specifications

Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF.
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits.

Table 16. GTL+ Bus Voltage Definitions

Symbol Parameter Min Typ Max Units Notes

GTLREF_PU GTLREF pull up resistor 124 * 0.99 124 124 * 1.01 Ω
GTLREF_PD GTLREF pull down resistor 210 * 0.99 210 210 * 1.01 Ω

R

PULLUP

R

TT

COMP[1:0]

COMP[5:4]

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. GTLREF is to be generated from V

GTLREF land).

3. These pull-ups are to VTT.

4. RTT is the on-die termination resistance measured at VTT/2 of the GTL+ output driver. The IMPSEL pin is used
to select a 50

5. COMP resistance must be provided on the system board with 1% resistors. COMP[1:0] resistors are to VSS.
COMP[5:4] resistors are to V

On die pull-up for
BOOTSELECT signal

60 Ω Platform Termination
Resistance

50 Ω Platform Termination
Resistance

60 Ω Platform Termination
COMP Resistance

50 Ω Platform Termination
COMP Resistance

60 Ω Platform Termination
COMP Resistance

50 Ω Platform Termination
COMP Resistance

Ω or 60 Ω buffer and RTT value.

.

TT

Table 16 lists the GTLREF specifications. The GTL+

2

2

500 — 5000 Ω

51 60 66 Ω

39 50 55 Ω

59.8 60.4 61 Ω

49.9 * 0.99 49.9 49.9 * 1.01 Ω

59.8 60.4 61 Ω

49.9 * 0.99 49.9 49.9 * 1.01 Ω

by a voltage divider of 1% resistors (one divider for each

TT

3

4

4

5

5

5

5

1

28 Datasheet

Electrical Specifications

2.7 Clock Specifications

2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the Pentium 4 processor core
frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier
will be set at its default ratio during manufacturing. Refer to
supported ratios.

The processor uses a differential clocking implementation. For more information on
processor clocking, contact your Intel representative.

Table 17. Core Frequency to FSB Multiplier Configuration

Table 17 for the processor

Multiplication of System Core

Frequency

NOTES:

1. Individual processors operate only at or below the rated frequency.

2. Listed frequencies are not necessarily committed production frequencies.

to FSB Frequency

1/12 2.40 GHz
1/13 2.60 GHz
1/14 2.80 GHz
1/15 3 GHz
1/16 3.20 GHz
1/17 3.40 GHz
1/18 3.60 GHz
1/19 3.80 GHz
1/20 4 GHz
1/21 4.20 GHz
1/22 4.40 GHz
1/23 4.60 GHz
1/24 4.80 GHz
1/25 5 GHz

Core Frequency

(200 MHz BCLK/

800

MHz FSB)

Notes

1,2

Datasheet 29

2.7.2 FSB Frequency Select Signals (BSEL[2:0])

Electrical Specifications

The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]).

Table 18 defines the possible combinations of the signals and the

frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.

The Pentium 4 processor will operate at an 800 MHz FSB frequency (selected by a
200

MHz BCLK[1:0] frequency).

For more information about these signals, refer to Section 4.2.

Table 18. BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2 BSEL1 BSEL0 FSB Frequency

L L L RESERVED
L L H RESERVED
L H H RESERVED

L H L 200 MHz
H H L RESERVED
H H H RESERVED
H L H RESERVED
H L L RESERVED

2.7.3 Phase Lock Loop (PLL) and Filter

V

and V

CCA

Pentium 4 processor silicon. Since these PLLs are analog, they require low noise power

are power sources required by the PLL clock generators for the

CCIOPLL

supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O
timings as well as internal core timings (i.e., maximum frequency). To prevent this
degradation, these supplies must be low pass filtered from V

TT

.

The AC low-pass requirements, with input at VTT are as follows:

• < 0.2 dB gain in pass band

• < 0.5 dB attenuation in pass band < 1 Hz

• > 34 dB attenuation from 1 MHz to 66 MHz

• > 28 dB attenuation from 66 MHz to core frequency

The filter requirements are illustrated in Figure 3.

30 Datasheet