Intel Pentium 4 571, Pentium 4 560, Pentium 4 561, Pentium 4 550, Pentium 4 551 Datasheet

Intel® Pentium® 4 Processors
570/571, 560/561, 550/551,
540/541, 530/531 and 520/521∆
Supporting Hyper-Threading
Technology

1

Datasheet

On 90 nm Process in 775-land LGA Package and
supporting Intel

May 2005

®

Extended Memory 64 Technology

Φ

Document Number: 302351-004

Contents

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS.

Intel may make changes to specifications and product descripti ons at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflict s or inco mpatibilities arising from future changes to them.

®

The Intel
the product to deviate from published specifications. Current characterized errata are available on request.

∆

different processor families.

1

Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http:/

/www.intel.com/info/hyperthreading/ for more information including details on which processors support HT Technology.

ΦIntel

drivers and applications enabled for Intel EM64T. Processor will not operate (including 32-bit operation) without an Intel EM64T-enabled BIOS.
Performance will vary depending on your hardware and software configurations. See http://www.intel.com/info/em64t for more information including
details on which processors support EM64T or consult with your system vendor for more information.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a support ing operating system.
Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Pentium, Itanium, Intel Xeon, Intel NetBurst and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in

the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2004–2005 Intel Corporation.

Pentium® 4 processor in the 775-land package on 90 nm process may contain design defects or errors known as errata which may cause

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across

Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting Hyper-Threading Technology and an HT

®

Extended Memory 64 Technology (Intel® EM64T) requires a computer system with a processor, chipset, BIOS, operating system, device

2 Datasheet

Contents

Contents

1 Introduction....................................................................................................................................11

1.1 Terminology........................................................................................................................12

1.1.1 Processor Packaging Terminology........................................................................12

1.2 References .........................................................................................................................13

2 Electrical Specifications................ .... ... ... ... ... .... ... ... ... .... ... ... .......................................... ... .............15

2.1 FSB and GTLREF...............................................................................................................15

2.2 Power and Ground Lands...................................................................................................15

2.3 Decoupling Guidelines........................................................................................................15

2.3.1 VCC Decoupling ....................................................................................................16

2.3.2 FSB GTL+ Decoupling...........................................................................................16

2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking ...................................................16

2.4 Voltage Identification ..........................................................................................................17

2.4.1 Phase Lock Loop (PLL) Power and Filter..............................................................19

2.5 Reserved, Unused, FC and TESTHI Signals......................................................................20

2.6 FSB Signal Groups.............................................................................................................21

2.7 GTL+ Asynchronous Signals..............................................................................................22

2.8 Test Access Port (TAP) Connection...................................................................................23

2.9 FSB Frequency Select Signals (BSEL[2:0]) .......................................................................23

2.10 Absolute Maximum and Minimum Ratings .........................................................................24

2.11 Processor DC Specifications ..............................................................................................24

2.12 VCC Overshoot Specification .......................................................... ... ... ... .... ... ...................33

2.12.1 Die Voltage Validation ...........................................................................................33

2.13 GTL+ FSB Specifications....................................................................................................34

3 Package Mechanical Specifications ..............................................................................................35

3.1 Package Mechanical Drawing ............................................................................................35

3.2 Processor Component Keep-Out Zones.............................................................................39

3.3 Package Loading Specifications.........................................................................................39

3.4 Package Handling Guidelines.............................................................................................39

3.5 Package Insertion Specifications........................................................................................40

3.6 Processor Mass Specification.............................................................................................40

3.7 Processor Materials............................................................................................................40

3.8 Processor Markings............................................................................................................40

3.9 Processor Land Coordinates ..............................................................................................41

4 Land Listing and Signal Descriptions ............................................................................................43

4.1 Processor Land Assignments.............................................................................................43

4.2 Alphabetical Signals Reference..........................................................................................66

5 Thermal Specifications and Design Considerations......................................................................75

5.1 Processor Thermal Specifications ......................................................................................75

5.1.1 Thermal Specifications ..........................................................................................75

5.1.2 Thermal Metrology.................................................................................................79

5.2 Processor Thermal Features ..............................................................................................79

5.2.1 Thermal Monitor.....................................................................................................79

5.2.2 Thermal Monitor 2..................................................................................................80

Datasheet 3

Contents

5.2.3 On-Demand Mode.................................................................................................81

5.2.4 PROCHOT# Signal................................................................................................82

5.2.5 THERMTRIP# Signal.............................................................................................82

5.2.6 T

CONTROL

and Fan Speed Reduction....................................................................82

5.2.7 Thermal Diode................... ... ... .... ... ... ... .... .......................................... ... ... ... ..........83

6 Features ........................................................................................................................................85

6.1 Power-On Configuration Options........................................................................... ... ... .... ...85

6.2 Clock Control and Low Power States.................................................................................85

6.2.1 Normal State................................... ... ... .... ... .......................................... ... ... ... .......86

6.2.2 HALT and Enhanced HALT Powerdown States ....................................................86

6.2.3 Stop-Grant State................................... .... ... .......................................... ... ... ... .......87

6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State......................88

7 Boxed Processor Specifications....................................................................................................89

7.1 Mechanical Specifications ..................................................................................................90

7.1.1 Boxed Processor Cooling Solution Dimensions ....................................................90

7.1.2 Boxed Processor Fan Heatsink Weight.................................................................91

7.1.3 Boxed Processor Retention Mechanism and Heatsink

Attach Clip Assembly.............................................................................................91

7.2 Electrical Requirements......................................................................................................91

7.2.1 Fan Heatsink Power Supply ..................................................................................91

7.3 Thermal Specifications .......................................................... ... ... ... .... ... ... ... .... ...................93

7.3.1 Boxed Processor Cooling Requirements...............................................................93

7.3.2 Variable Speed Fan...............................................................................................95

4 Datasheet

Contents

Figures

2-1 Phase Lock Loop (PLL) Filter Requirements . .............................................................................19

2-2 VCC Static and Transient Tolerance for 775_VR_CONFIG_04A...............................................28

2-3 VCC Static and Transient Tolerance for 775_VR_CONFIG_04B...............................................30

2-4 VCC Overshoot Example Waveform ..........................................................................................33

3-1 Processor Package Assembly Sketch........................................................................................35

3-2 Processor Package Drawing 1 ...................................................................................................36

3-3 Processor Package Drawing 2 ...................................................................................................37

3-4 Processor Package Drawing 3 ...................................................................................................38

3-5 Processor Top-Side Marking Example.......................................................................................40

3-6 Processor Top-Side Marking Example for Processors Supporting Intel

3-7 Processor Land Coordinates (Top View)....................................................................................42

4-1 Landout Diagram (Top View – Left Side)....................................................................................44

4-2 Landout Diagram (Top View – Right Side).................................................................................45

5-1 Thermal Profile for Processors with PRB = 1 .............................................................................77

5-2 Thermal Profile for Processors with PRB = 0 .............................................................................78

5-3 Case Temperature (TC) Measurement Location........................................................................79

5-4 Thermal Monitor 2 Frequency and Voltage Ordering .................................................................81

6-1 Processor Low Power State Machine.........................................................................................87

7-1 Mechanical Representation of the Boxed Processor..................................................................89

7-2 Space Requirements for the Boxed Processor (Side View) .......................................................90

7-3 Space Requirements for the Boxed Processor (Top View) ........................................................90

7-4 Space Requirements for the Boxed Processor (Overall View)...................................................91

7-5 Boxed Processor Fan Heatsink Power Cable Connector Description........................................92

7-6 Baseboard Power Header Placement Relative to Processor Socket .........................................93

7-7 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top View)...........................94

7-8 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side View).... ... ... ... ... .... ... ...94

7-9 Boxed Processor Fan Heatsink Set Points.................................................................................95

®

EM64T......................41

Datasheet 5

Contents

Tables

1-1 References .................................................................................................................................13

2-1 Core Frequency to FSB Multiplier Configuration........................................................................16

2-2 Voltage Identification Definition ..................................................................................................18

2-3 FSB Signal Groups.....................................................................................................................21

2-4 Signal Characteristics.................................................................................................................22

2-5 Signal Reference Voltages.........................................................................................................22

2-6 BSEL[2:0] Frequency Table for BCLK[1:0].................................................................................23

2-7 Processor DC Absolute Maximum Ratings ................................................................................24

2-8 Voltage and Current Specifications ............................................................................................25

2-9 VCC Static and Transient Tolerance for 775_VR_CONFIG_04A Processors ...........................27

2-10VCC Static and Transient Tolerance for 775_VR_CONFIG_04B Processors ...........................29

2-11 GTL+ Asynchronous Signal Group DC Specifications ..............................................................31

2-12GTL+ Signal Group DC Specifications .......................................................................................31

2-13PWRGOOD and TAP Signal Group DC Specifications..............................................................32

2-14VTTPWRGD DC Specifications..................................................................................................32

2-15BSEL [2:0] and VID[5:0] DC Specifications................................................................................32

2-16BOOTSELECT DC Specifications..............................................................................................32

2-17VCC Overshoot Specifications ...................................................................................................33

2-18GTL+ Bus Voltage Definitions ....................................................................................................34

3-1 Processor Loading Specifications ..............................................................................................39

3-2 Package Handling Guidelines ....................................................................................................39

3-3 Processor Materials....................................................................................................................40

4-1 Alphabetical Land Assignments .................................................................................................46

4-2 Numerical Land Assignment................................................... .... ... ... ... ... .... ... ... ... .... ... ... ... ..........56

4-3 Signal Description.......................................................................................................................66

5-1 Processor Thermal Specifications..............................................................................................76

5-2 Thermal Profile for Processors with PRB = 1 .............................................................................77

5-3 Thermal Profile for Processors with PRB = 0 .............................................................................78

5-4 Thermal Diode Parameters ........................................................................................................83

5-5 Thermal Diode Interface.............................................................................................................83

6-1 Power-On Configuration Option Signals.....................................................................................85

7-1 Fan Heatsink Power and Signal Specifications..........................................................................92

7-2 Fan Heatsink Power and Signal Specifications..........................................................................96

§

6 Datasheet

Revision History

Revision No. Description Date of Release

-001 • Initial release June 2004

• Added specifications for processor number 550 with PRB = 0

-002

-003 • Added specifications for processor number 570 with PRB = 1 November 2004

-004

• Added support for Execute Disable Bit capability

• Added Icc Enhanced Auto Halt specifications

• Added support for Thermal Monitor 2

• Added specifications for processor numbers 571, 561, 551, 541,
531, and 521.

• Modified Table 2-3, “FSB Signal Groups“.

• Added Note 5 to Table 2-18.

• Updated Figure 3-5 Top SIde Marking Example and added
Figure 3-6.

• Minor edits throughout for clarity.

Contents

September 2004

May 2005

§

Datasheet 7

Contents

8 Datasheet

Contents

Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531, and 520/521

• Available at 3.80 GHz, 3.60 GHz, 3.40 GHz,

3.20 GHz, 3 GHz, and 2.80 GHz

• Supports Hyper-Threading Technology

(HT Technology) for all frequencies with
800 MHz front side bus (FSB)

®

• Intel

Pentium® 4 processors 571, 561, 551, 541,
531, and 521 support Intel
Technology (EM64T)

®

Extended Memory 64

Φ

1

• Supports Execute Disable Bit capability

• Binary compatible with applications run ning on

previous members of the Intel microprocessor line

• Intel NetBurst

®

microarchitecture

• FSB frequency at 800 MHz

• Hyper-Pipelined Technology

• Advance Dynamic Execution

• Very deep out-of-order execution

• Enhanced branch prediction

• 16-KB Level 1 data cache

• 1-MB Advanced Transfer Cache (on-die, full-

speed Level 2 (L2) cache) with 8-way associativity
and Error Correcting Code (ECC)

• 144 Streaming SIMD Extensions 2 (SSE2)

instructions

• 13 Streaming SIMD Extensions 3 (SSE3)

instructions

• Enhanced floating point and multimedia unit for

enhanced video, audio, encryption, and 3D
performance

• Power Management capabilities

• System Management mode

• Multiple low-power states

• 8-way cache associativity provides improved

cache hit rate on load/store operations

• 775-land Package

• Optimized for 32-bit applications running on

advanced 32-bit operating systems

The Intel® Pentium® 4 processor family supporting Hyper-Threading Technology1 (HT Technology) delivers
Intel's advanced, powerful processors for desktop PCs and entry-level workstations that are based on the Intel
NetBurst
usages where end-users can truly appreciate and experience the performance. These applications include Internet
audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and
multitasking user environments. Intel
execute operating systems and applications written to take advange of the Intel EM64T

®

microarchitecture. The Pentium 4 processor is designed to deliver performance across applications and

®

Extended Memory 64 Technology enables the Intel® Pentium® processor to

Φ

.

§

Datasheet 9

Contents

10 Datasheet

1 Introduction

Introduction

The Intel® Pentium® 4 processor on 90 nm process in the 775-land package is a follow on to the
Pentium 4 processor in the 478-pin package with enhancements to the Intel NetBurst
microarchitecture. The Pentium 4 processor on 90 nm process in the 775-land package uses Flip­Chip Land Grid Array (FC-LGA4) package technology, and plugs into a 775LGA socket. The
Pentium 4 processor in the 775-land package, like its predecessor, the Pentium 4 processor in the
478-pin package, is based on the same Intel 32-bit microarchitecture and maintains the tradition of
compatibility with IA-32 software.

Note: In this document the Pentium 4 processor on 90 nm process in the 775-land package is also referred

to as the processor.
The Pentium 4 processor on 90 nm process in the 775-land package supports Hyper-Threading

Technology
logical processors. While some execution resources (such as caches, execution units, and buses)
are shared, each logical processor has its own architecture state with its own set of general-purpose
registers, control registers to provide increased system responsiveness in multitasking
environments, and headroom for next generation multithreaded applications. Intel recommends
enabling Hyper-Threading Technology with Microsoft Windows* XP Professional or
Windows* XP Home, and disabling Hyper-Threading Technology via the BIOS for all previous
versions of Windows operating systems. For more information on Hyper-Threading Technology,
see http://www.intel.com/info/hyperthreading. Refer to Section 6.1, for Hyper-Threading
T echnology configuration details.

The Intel Pentium 4 processor 571, 561, 541, 531, and 521 su pport Intel
T echnology (EM64T)
the processor to execute operating systems and applications written to take advantage of Intel
EM64T. With appropriate 64 bit supporting hardware and software, platforms based on an Intel
processor supporting Intel
Further details on the 64-bit extension architecture and programming model is provided in th e

Intel

technology/64bitextensions/.

1

. Hyper-Threading Technology allows a single, physical processor to function as two

®

Φ

as an enhancement to Intel’ s IA-32 architecture. This enhancement enables

®

EM64T can enable use of extended virtual and physical memory.

®

Extended Memory 64 Technology Software Developer Guide at: http://developer.intel.com/

Extended Memory 64

®

In addition to supporting all the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new
instructions that further extend the capabilities of Intel processor technology. These new
instructions are called Streaming SIMD Extensions 3 (SSE3). These new instructions enhance the
performance of optimized applications for the digital home such as video, image processing, and
media compression technology. 3D graphics and other entertainment applications such as gaming
will have the opportunity to take advantage of these new instructions as platforms with the Pentium
4 processor in the 775-land package and SSE3 become available in the market place.

The processor’s Intel NetBurst microarchitecture FSB uses a split-transaction, deferred reply
protocol like the Pentium 4 processor. The Intel NetBurst microarchitecture FSB uses Source­Synchronous Transfer (SST) of address and data to improve performance by transferring data four
times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address
bus can deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X
address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth
of up to 6.4 GB/s.

Datasheet 11

Introduction

The Pentium 4 processor on 90 nm process in the LGA775-land package will also include the
Execute Disable Bit capability previously available in Intel
combined with a support operating system allows memory to be marked as executable or non­executable. If code attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms that exploit buffer
overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel
Architecture Software Developer's Manual for more detailed information.

Intel will enable support components for the processor including heatsink, heatsink retention
mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be
completed from the top of the baseboard and should not require any special tooling.

The processor includes an address bus powerdown capability that removes power from the address
and data pins when the FSB is not in use. This feature is always enabled on the processor.

1.1 Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

“FSB” refers to the interface between the processor and system core logic (a.k.a. the chipset
components). The FSB is a multiprocessing interface to processors, memory, and I/O.

®

Itanium® processors. This feature

®

1.1.1 Processor Packaging Terminology

Commonly used terms are explained here for clarification:

• Pentium 4 processor on 90 nm process in the 775-land package — Processor in the FC-

LGA4 package with a 1-MB L2 cache.

• Processor — For this document, the term processor is the generic form of the Pentium 4

processor in the 775-land package.

• Keep-out zone — The area on or near the processor that system design can not use.

• Intel 925X/915G/915P Express chipsets — Chipsets that supports DDR and DDR2 memory

technology for the Pentium 4 processor in the 775-land package.

• Processor core — Processor core die with integrated L2 cache.

• FC-LGA4 package — The Pentium 4 processor in the 775-land package is available in a Flip-

Chip Land Grid Array 4 package, consisting of a processor core mounted on a substrate with
an integrated heat spreader (IHS).

• LGA775 socket — The Pentium 4 processor in the 775-land package mates with the system

board through a surface mount, 775-land, LGA socket.

• Integrated heat spreader (IHS) —A component of the processor package used to enhance

the thermal performance of the package. Component thermal solutions interface with the
processor at the IHS surface.

12 Datasheet

• Retention mechanism (RM)—Since the LGA775 socket does not include any mechanical

features for heatsink attach, a retention mechanism is required. Component thermal solutions
should attach to the processor via a retention mechanism that is independent of the socket.

• Storage conditions—Refers to a non-operational state. The processor may be installed in a

platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air.
Under these conditions, processor lands should not be connect ed to any supp ly voltages, have
any I/Os biased, or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or
a device removed from packaging material) the processor must be handled in accordance with
moisture sensitivity labeling (MSL) as indicated on the packaging material.

• Functional operation—Refers to normal operating conditions in which all processor

specifications, including DC, AC, system bus, signal quality, mechanical and thermal, are
satisfied.

1.2 References

Material and concepts available in the following documents may be beneficial when reading this
document.

Table 1-1. References

Introduction

Document

®

Intel

Pentium® 4 Processor on 90 nm Process Specification Update

®

Intel

Pentium® 4 Processor on 90 nm Process in the 775-Land Package

Thermal Design Guidelines

Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket

®

Intel

Architecture Software Developer's Manual

IA-32 Intel
Architecture

IA-32 Intel
Set Reference Manual A–M

IA-32 Intel
Set Reference Manual, N–Z

IA-32 Intel
Programming Guide

IA-32 Intel
Developer's Manual Documentation Changes

®

Architecture Software Developer's Manual Volume 1: Basic

®

Architecture Software Developer's Manual Volume 2A: Instruction

®

Architecture Software Developer's Manual Volume 2B: Instruction

®

Architecture Software Developer's Manual Volume 3: System

®

Architecture and Intel® Extended Memory 64 Software

Document Numbers/

Location

http://developer.intel.com/
design/Pentium4/
specupdt/302352.htm

http://developer.intel.com/
design/Pentium4/guides/

302553.htm
http://developer.intel.com/

design/Pentium4/guides/

302356.htm

http://developer.intel.com/
design/pentium4/
manuals/index_new.htm

http://developer.intel.com/
design/pentium4/
manuals/index_new.htm

§

Datasheet 13

Introduction

14 Datasheet

2 Electrical Specifications

This chapter describes the electrical characteristics of the processor interfaces and signals. DC
electrical characteristics are provided.

2.1 FSB and GTLREF

Most processor FSB signals use Gunning Transceiver Logic (GTL+) signaling technology.
Platforms implement a termination voltage level for GTL+ signals defined as V
provided via a separate voltage source and not be connected to V
improved noise tolerance as processor frequency increases. Because of the speed improvements to
the data and address bus, signal integrity and platform design methods have beco me m ore critical
than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine
if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board (see

Table 2-18 for GTLREF specifications). T ermination resistors are provided on the processor silicon

and are terminated to V
need to terminate the bus on the system board for most GTL+ signals.

. Intel chipsets will also provide on-die termination, thus eliminating the

TT

CC

Electrical Specifications

. VTT must be

. This configuration allows for

TT

Some G TL+ signals do not include on-die termination and must be terminated on the system board.
See Table 2-4 for details regarding these signals.

The GTL+ bus depends on incident wave switching. Therefore, timing calculations for GTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
FSB, including trace lengths, is highly recommended when designing a system.

2.2 Power and Ground Lands

For clean on-chip power distribution, the Pentium 4 processor in the 775-land package has
226 V
all V
plane. The processor V
IDentification (VID) signals.

(power), 24 VTT and 273 V

CC

lands must be connected to VTT, while all VSS lands must be connected to a system ground

TT

lands must be supplied the voltage determined by the Voltage

CC

(ground) lands. All power lands must be connected to VCC,

SS

2.3 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of
generating large current swings between low and full power states. This may cause voltages on
power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be
taken in the board design to ensure that the voltage provided to the processor remains within the
specifications listed in Table 2-8. Failure to do so can result in timing violations or reduced lifetime
of the component. For further information and design guidelines, refer to th e Voltage Regulator
Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket.

Datasheet 15

Electrical Specifications

2.3.1 VCC Decoupling

Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the
large current swings when the part is powering on, or entering/exiting low power states, must be
provided by the voltage regulator solution (VR). For more details on this topic, refer to the Voltage
Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket.

2.3.2 FSB GTL+ Decoupling

The Pentium 4 processor in the 775-land package integrates signal termination on the die as well as
incorporating high frequency decoupling capacitance on the processor package. Decoupling must
also be provided by the system baseboard for proper GTL+ bus operation.

2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor .
As in previous generation processors, the Pentium 4 processor in the 775-land package core
frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set
at its default ratio during manufacturing. No user intervention is necessary, and the processor will
automatically run at the speed indicated on the package.

The Pentium 4 processor in the 775-land package uses a differential clocking implementation. For
more information on the Pentium 4 processor in the 775-land package clocking, refer to the
CK410/CK410M Clock Synthesizer/Driver Specification.

Table 2-1. Core Frequency to FSB Multiplier Configuration

Multiplication of System Core
Frequency to FSB Frequency

1/14 2.80 GHz ­1/15 3 GHz ­1/16 3.20 GHz ­1/17 3.40 GHz ­1/18 3.60 GHz ­1/19 3.80 GHz -

NOTES:

1. Individual processors operate only at or below the rated frequency.

2. Listed frequencies are not necessarily committed production frequencies.

Core Frequency (200 MHz

BCLK/800 MHz FSB)

Notes

1, 2

16 Datasheet

2.4 Voltage Identification

The VID specification for the Pentium 4 processor in the 775-land package is supported by the
Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket. The voltage set
by the VID signals is the reference VR output voltage to be delivered to the processor V
minimum voltage is provided in Table 2-8 and changes with frequency. This allows processors
running at a higher frequency to have a relaxed minimum voltage specification. The specifications
have been set such that one voltage regulator can work with all supported frequencies.

Individual processor VID values may be calibrated during manufacturing such that two devices at
the same speed may have different VID settings.

The Pentium 4 processor in the 775-land package uses six voltage identification signals, VID[5:0],
to support automatic selection of power supply voltages. Table 2-2 specifies the voltage level
corresponding to the state of VID[5:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’
refers to low voltage level. I f the processor socket is empty (VID[5:0] = x11111), or the voltage
regulation circuit cannot supply the voltage that is requested, it must disable itself. See the Voltage
Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for more details.

Power source characteristics must be guaranteed to be stable when the supply to the voltage
regulator is stable.

Electrical Specifications

pins. A

CC

The LL_ID[1:0] lands are used by the platform to configure the proper loadline slope for the
processor. LL_ID[1:0] = 00 for the Pentium 4 processor in the 775-land package.

The VTT_SEL land is used by the platform to configure the proper V

voltage level for the

TT

processor. VTT_SEL = 1 for the Pentium 4 processor in the 775-land package.
The GTLREF_SEL signal is used by the platform to select the appropriate chipset GTLREF level.

GTLREF_SEL = 0 for the Pentium 4 processor in the 775-land package.
LL_ID[1:0] and VTT_SEL are signals that are implemented on the processor package. That is,

they are either connected directly to V

or are open lands.

SS

Datasheet 17

Electrical Specifications

Table 2-2. Voltage Identification Definition

VID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID

0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125
1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250
0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375
1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500
0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625
1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750
0 0 0 1 1 1 0.9125 0 1 0 1 1 1 1.2875
1 0 0 1 1 0 0.9250 1 1 0 1 1 0 1.3000
0 0 0 1 1 0 0.9375 0 1 0 1 1 0 1.3125
1 0 0 1 0 1 0.9500 1 1 0 1 0 1 1.3250
0 0 0 1 0 1 0.9625 0 1 0 1 0 1 1.3375
1 0 0 1 0 0 0.9750 1 1 0 1 0 0 1.3500
0 0 0 1 0 0 0.9875 0 1 0 1 0 0 1.3625
1 0 0 0 1 1 1.0000 1 1 0 0 1 1 1.3750
0 0 0 0 1 1 1.0125 0 1 0 0 1 1 1.3875
1 0 0 0 1 0 1.0250 1 1 0 0 1 0 1.4000
0 0 0 0 1 0 1.0375 0 1 0 0 1 0 1.4125
1 0 0 0 0 1 1.0500 1 1 0 0 0 1 1.4250
0 0 0 0 0 1 1.0625 0 1 0 0 0 1 1.4375
1 0 0 0 0 0 1.0750 1 1 0 0 0 0 1.4500
0 0 0 0 0 0 1.0875 0 1 0 0 0 0 1.4625
1 1 1 1 1 1 VR output off 1 0 1 1 1 1 1.4750
0 1 1 1 1 1 VR output off 0 0 1 1 1 1 1.4875
1 1 1 1 1 0 1.1000 1 0 1 1 1 0 1.5000
0 1 1 1 1 0 1.1125 0 0 1 1 1 0 1.5125
1 1 1 1 0 1 1.1250 1 0 1 1 0 1 1.5250
0 1 1 1 0 1 1.1375 0 0 1 1 0 1 1.5375
1 1 1 1 0 0 1.1500 1 0 1 1 0 0 1.5500
0 1 1 1 0 0 1.1625 0 0 1 1 0 0 1.5625
1 1 1 0 1 1 1.1750 1 0 1 0 1 1 1.5750
0 1 1 0 1 1 1.1875 0 0 1 0 1 1 1.5875
1 1 1 0 1 0 1.2000 1 0 1 0 1 0 1.6000

18 Datasheet

2.4.1 Phase Lock Loop (PLL) Power and Filter

V

and V

CCA

CCIOPLL

processor in the 775-land package. Since these PLLs are analog, they require low noise power
supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as
well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies
must be low pass filtered from V

are power sources required by the PLL clock generators for the Pentium 4

.

TT

Electrical Specifications

The AC low-pass requirements, with input at V

• < 0.2 dB gain in pass band

• < 0.5 dB attenuation in pass band < 1 Hz

• > 34 dB attenuation from 1 MHz to 66 MHz

• > 28 dB attenuation from 66 MHz to core freq uency

.

Figure 2-1. Phase Lock Loop (PLL) Filter Requirements

The filter requirements are illustrated in Figure 2-1.

0.2 dB
0 dB

–0.5 dB

Forbidden

Zone

–28 dB

are as follows:

TT

Forbidden

Zone

–34 dB

1 MHz 6 6 MHz fcorefpeak1 HzDC

Passband

NOTES:

1. Diagram not to scale.

2. No specification exists for frequencies beyond fcore (core frequency).

3. fpeak, if existent, should be less than 0.05 MHz.

Datasheet 19

High

Frequency

Band

Filter_Spec

Electrical Specifications

2.5 Reserved, Unused, FC and TESTHI Signals

All RESERVED signals must remain unconnected. Connection of these signals to VCC, VSS, V
or to any other signal (including each other) can result in component malfunction or
incompatibility with future processors. See Chapter 4 for a land listing of the processor and the
location of all RESERVED signals.

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. In a system level design, on-die termination has been included on the Pentium 4
processor in the 775-land package to allow signals to be terminated within the processor silicon.
Most unused GTL+ inputs should be left as no connects, as GTL+ termination is provided on the
processor silicon. However, see Table 2-4 for details on GTL+ signals that do not include on-die
termination. Unused active high inputs should be connected through a resistor to ground (V
Unused outputs can be left unconnected, however this may interfere with some test access port
(TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be
used when tying bidirectional signals to power or ground. When tying any signal to power or
ground, a resistor will also allow for system testability. For unused GTL+ input or I/O signals, use
pull-up resistors of the same value as the on-die termination resistors (R
more details.

TAP, GTL+ Asynchronous inputs, and GTL+ Asynchronous outputs do not include on-die
termination. Inputs and used outputs must be terminated on the system board. Unused outputs may
be terminated on the system board or left unconnected. Note that leaving unused outputs
unterminated may interfere with some TAP functions, complicate debug probing, and prevent
boundary scan testing.

FCx signals are signals that are available for compatibility with other processors.
The TESTHI signals must be tied to the processor V

resistor has a resistance value within ±20% of the impedance of the board transmission line traces.
For example, if the trace impedance is 60 Ω, then a value between 48 Ω and 72 Ω is required.

using a matched resistor, where a matched

TT

). Refer to Table 2-18 for

TT

SS

TT,

).

The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below.
A matched resistor must be used for each group:

• TESTHI[1:0]

• TESTHI[7:2]

• TESTHI8 – cannot be grouped with other TESTHI signals

• TESTHI9 – cannot be grouped with other TESTHI signals

• TESTHI10 – cannot be grouped with other TESTHI signals

• TESTHI11 – cannot be grouped with other TESTHI signals

• TESTHI12 – cannot be grouped with other TESTHI signals

• TESTHI13 – cannot be grouped with other TESTHI signals

20 Datasheet

2.6 FSB Signal Groups

The FSB signals have been combined into groups by buffer type. GTL+ input signals have
differential input buffers, which use GTLREF as a reference level. In this document, the term
"GTL+ Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving.
Similarly, "GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group when
driving.

With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals which are dependent upon the rising edge
of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals
which are relative to their respective strobe lines (data and address) as well as the rising edge of
BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at
any time during the clock cycle. Table 2-3 identifies which signals are common clock, source
synchronous, and asynchronous.

Table 2-3. FSB Signal Groups

Signal Group Type Signals

GTL+ Common Clock Input

GTL+ Common Clock I/O

Synchronous to
BCLK[1:0]

Synchronous to
BCLK[1:0]

Electrical Specifications

1

BPRI#, DEFER#, RS[2:0]#, RSP#, TRDY#
AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, DBSY#,

DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR#

Signals Associated Strobe

REQ[4:0]#, A[16:3]#

GTL+ Source Synchronous I/O

GTL+ Strobes

GTL+ Asynchronous Input
GTL+ Asynchronous Output FERR#/PBE#, IERR#, THERMTRIP#

GTL+ Asynchronous Input/Output PROCHOT#
TAP Input Synchronous to TCK TCK, TDI, TMS, TRST#
TAP Output Synchronous to TCK TDO
FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]

Power/Other

Synchronous to assoc.
strobe

Synchronous to
BCLK[1:0]

A[35:17]#
D[15:0]#, DBI0# DSTBP0#, DSTBN0#
D[31:16]#, DBI1# DSTBP1#, DSTBN1#
D[47:32]#, DBI2# DSTBP2#, DSTBN2#
D[63:48]#, DBI3# DSTBP3#, DSTBN3#

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,

STPCLK#, RESET#

VCC, VTT, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA, GTLREF,
COMP[1:0], RESERVED, TESTHI[13:0], THERMDA,
THERMDC, VCC_SENSE, VSS_SENSE, BSEL[2:0],
SKTOCC#, DBR#
VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, LL_ID[1:0],
FCx, VSS_MB_REGULATION, VCC_MB_REGULATION,
MSID[1:0]

3

3

2

2

, VTTPWRGD, BOOTSELECT, PWRGOOD,

ADSTB0#
ADSTB1#

Datasheet 21

Electrical Specifications

NOTES:

1. Refer to Section 4.2 for signal descriptions.

2. In processor systems where there is no debug port implemented on the system board, these signals are used
to support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.

3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration
options. See Section 6.1 for details.

Table 2-4. Signal Characteristics

Signals with R

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BOOTSELECT
DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
PROCHOT#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

Open Drain Signals

BSEL[2:0], VID[5:0], THERMTRIP#, FERR#/PBE#,
IERR#, BPM[5:0]#, BR0#, TDO, VTT_SEL, LL_ID[1:0],
MSID[1:0]

NOTES:

1. The BOOTSELECT signal has a 500-5000 Ω pull-up to VTT rather than on-die termination.

2. Signals that do not have RTT, nor are actively driven to their high-voltage level.

.

Table 2-5. Signal Reference Voltages

BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, BINIT#,
BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BR0#,
A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,
DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,
RSP#, TRDY#

NOTES:

1. These signals also have hysteresis added to the reference voltage. See Table 2-13 for more information.

TT

A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[2:0],

1

, BPRI#, D[63:0]#, DBI[3:0]#,

2

GTLREF VTT/2

COMP[1:0], FERR#/PBE#, IERR#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#,
SKTOCC#, SMI#, STPCLK#, TDO, TESTHI[13:0],
THERMDA, THERMDC, THERMTRIP#, VID[5:0],
VTTPWRGD, GTLREF, TCK, TDI, TRST#, TMS

BOOTSELECT, VTTPWRGD, A20M#,
IGNNE#, INIT#, PWRGOOD
STPCLK#, TCK

Signals with no R

1

, TDI1, TMS1, TRST#

TT

1

, SMI#,

1

2.7 GTL+ Asynchronous Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input
buffers. All of these signals follow the same DC requirements as GTL+ signals, however the
outputs are not actively driven high (during a logical 0 to 1 transition) by the processor. These
signals do not have setup or hold time specifications in relation to BCLK[1:0].

All of the GTL+ Asynchronous signals are required to be asserted/de-asserted for at least six
BCLKs for the processor to recognize the proper signal state. See Section 6.2 for additional timing
requirements for entering and leaving the low power states.

22 Datasheet

Electrical Specifications

2.8 Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the Pentium 4 processor in the 775-land package be first in the TAP chain and
followed by any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of accepting an input
of the appropriate voltage level. Similar considerations must be made for TCK, TMS, TRST#, TDI,
and TDO. Two copies of each signal may be required, with each driving a different voltage level.

2.9 FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]).

Table 2-6 defines the possible combinations of the signals and the frequency associated with each

combination. The required frequency is determined by the processor, chipset, and clock
synthesizer. All agents must operate at the same frequency.

The Pentium 4 processor in the 775-land package currently operates at a 533 MHz or 800 MHz
FSB frequency (selected by a 133 MHz or 200 MHz BCLK[1:0] frequency). Individual processors
will only operate at their specified FSB frequency.

For more information about these signals, refer to Section 4.2.

Table 2-6. BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2 BSEL1 BSEL0 FSB Frequency

L L L RESERVED
L L H 133 MHz
L H H RESERVED

L H L 200 MHz
H L L RESERVED
H L H RESERVED
H H H RESERVED
H H L RESERVED

Datasheet 23

Electrical Specifications

2.10 Absolute Maximum and Minimum Ratings

Table 2-7 specifies absolute maximum and minimum ratings. Within functional operation limits,

functionality and long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute maximum and

minimum ratings, neither functionality nor long-term reliability can be expected. If a device is
returned to conditions within functional operation limits after having been subjected to conditions
outside these limits, but within the absolute maximum and minimum ratings, the device may be
functional, but with its lifetime degraded depending on exposure to conditions exceeding the
functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long­term reliability can be expected. Moreover, if a device is subjected to these conditions for any
length of time then, when returned to conditions within the functional operating condition limits, it
will either not function, or its reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from static electric discharge,
precautions should always be taken to avoid high static voltages or electric fields.

Table 2-7. Processor DC Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes

V

CC

V

TT

T

C

T

STORAGE

NOTES:

1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied.

2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and
no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of th e device.
For functional operation, refer to the processor case temperature specifications.

4. This rating applies to the processor and does not include any tray or packaging.

Core voltage with respect to
V

SS

FSB termination voltage with
respect to V

Processor case temperature See Section 5 See Section 5 °C —
Processor storage temperature –40 +85 °C

SS

–0.3 1.55 V —

–0.3 1.55 V —

1, 2

3, 4

2.11 Processor DC Specifications

The processor DC specifications in this section are defined at the processor core silicon and
not at the package lands unless noted otherwise. See Chapter 4 for the signal definiti ons and

signal assignments. Most of the signals on the processor FSB are in the GTL+ signal group. The
DC specifications for these signals are listed in Table 2-12.

Previously, legacy signals and Test Access Port (TAP) signals to the processor used low-voltage
CMOS buffer types. However , these interfaces now follow DC specifications similar to GTL+. The
DC specifications for these signal groups are listed in Table 2-11 and Table 2-13.

Table 2-8 through Table 2-15 list the DC specifications for the Pentium 4 processor in the 775-land

package and are valid only while meeting specifications for case temperature, clock frequency, and
input voltages. Care should be taken to read all notes associated with each parameter.

MSR_PLATFORM_BRV bit 18 is a Platform Requirement Bit (PRB) that indicates that the
processor has specific platform requirements.

24 Datasheet

Electrical Specifications

Table 2-8. Voltage and Current Specifications (Sheet 1 of 2)

Symbol Parameter Min Typ Max Unit Notes

VID range VID 1.200 — 1.425 V

Processor Number Core Frequency

for 775_VR_CONFIG_04B

V

CC

processors

V

CC

570/571
560/561

550

V

CC

550/551
540/541
530/531
520/521

570/571
560/561

I

CC

550
550/551
540/541
530/531
520/521

3.80 GHZ (PRB = 1)

3.60 GHz (PRB = 1)

3.40 GHz (PRB = 1)

for 775_VR_CONFIG_04A

V

CC

processors

3.40 GHz (PRB = 0)

3.20 GHz (PRB = 0)
3 GHz (PRB = 0)

2.80 GHz (PRB = 0)

for processor with multiple

I

CC

VID

3.80 GHZ (PRB = 1)

3.60 GHz (PRB = 1)

3.40 GHz (PRB = 1)

3.40 GHz (PRB = 0)

3.20 GHz (PRB = 0)
3 GHz (PRB = 0)

2.80 GHz (PRB = 0)

Stop-Grant

I

CC

Refer to Table 2-10 and

Figure 2-3

Refer to Table 2-9 and

Figure 2-2

119
119

——

119

V

V

A

78
78
78
78

1

2

3, 4, 5, 6

3, 4, 6, 7, 8

9

I

SGNT

I

ENHANCED_AUTO_

HALT

I

TCC

V

TT

VTT_OUT I
I

TT

CC

570/571
560/561

550
550/551
540/541
530/531
520/521

570/571
560/561
550/551
540/541
530/531
520/521

ICC TCC active — — I

3.80 GHZ (PRB = 1)

3.60 GHz (PRB = 1)

3.40 GHz (PRB = 1)

3.40 GHz (PRB = 0)

3.20 GHz (PRB = 0)
3 GHz (PRB = 0)

2.80 GHz (PRB = 0)

Enhanced Auto Halt

I

CC

3.80 GHZ (PRB = 1)

3.60 GHz (PRB = 1)

3.40 GHz (PRB = 0)

3.20 GHz (PRB = 0)
3 GHz (PRB = 0)

2.80 GHz (PRB = 0)

——

——

56
56
56
40
40
40
40

37
37
31
31
40
40

A

A

CC

A
FSB termination voltage (DC+AC specifications) 1.14 1.20 1.26 V
DC Current that may be drawn from VTT_OUT per pin — — 580 mA
FSB termination current — — 3.5 A

10, 11, 15

11, 15

12

13, 14

15, 16

Datasheet 25

Electrical Specifications

Table 2-8. Voltage and Current Specifications (Sheet 2 of 2)

Symbol Parameter Min Typ Max Unit Notes

I

CC_VCCA

I

CC_VCCIOPLL

I

CC_GTLREF

I

CC FOR PLL LANDS

I

CC FOR I/O PLL LAND

— — 120 mA
— — 100 mA

ICC for GTLREF — — 200 µA

NOTES:

1. Unless otherwise noted, all specifications in this table are based on est imate s an d si mulati ons or emp irical data. These sp ecifications will be up­dated with characterized data from silicon measurements at a later date.

2. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered.
Individual maximum VID values are calibrated during manufacturing such tha t two pro cessors at th e same freque ncy may have diffe r ent se ttings
within the VID range. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2 or En­hanced HALT State).

3. These voltages are targets only. A variable voltage source should exist on systems in th e event that a different voltage is required. Se e Section 2.4
and Table 2-2 for more information.

4. The voltage specification requirements are measured acr oss VCC_SE NSE and VS S_S ENSE lands a t the socket wit h a 100 MHz band wid th os­cilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum l ength of ground wire on the probe should be less
than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

5. Refer to Table 2-10 and Figure 2-3 for the minimum, typical, and maximum V
jected to any Vcc and Icc combination wherein V

6. 775_VR_CONFIG_04A and 775_VR_CONFIG_04B refer to voltage regulator configurations that are defined in the Voltage Regulator Down
(VRD) 10.1 Design Guide For Desktop LGA775 Socket.

7. Refer to Table 2-9 and Figure 2-2 for the minimum, typical, and maximum V
to any V

8. These frequencies will operate in a system designed for 775_VR_CONFIG_04B processors. The power and I
this configuration due to the improved loadline and resultin g hi gher V

9. I

cc_max

10. The current specified is also for AutoHALT State.

11. Icc Stop-Grant and I

12. The maximum instantaneous current the processor will dra w while the thermal control circuit is active as indicated by the assertion of PROCHOT#
is the same as the maximum Icc for the processor.

13. V

14. Baseboard bandwidth is limited to 20 MHz.

15. These parameters are based on design characterization and are not tested.

16. This is maximum total current drawn from V
(through the signal line). Refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket to determine the total I

and ICC combination wherein VCC exceeds V

CC

is specified at V

CC

must be provided via a separate voltage source and not be connected t o VCC. This specification is measured at the land.

TT

.

CC_max

Enhanced Auto Halt are specified at V

exceeds V

CC

CC_max

plane by only the processor. This specification does not include the current coming from R

TT

for a given current.

cc_max

for a given current.

CC

.

CC_max

drawn by the system.

allowed for a given current. The processor should not be sub-

CC

allowed for a given current. The processor should not be subjected

CC

will be incrementally higher in

.

CC

1

15
15
15

TT
TT

26 Datasheet

Electrical Specifications

Table 2-9. VCC Static and Transient Tolerance for 775_VR_CONFIG_04A Processors

Voltage Deviation from VID Setting (V)

ICC (A)

Maximum Voltage

1.70 mΩ

Typical Voltage

1.75 mΩ

0 0.000 -0.025 -0.050

5 -0.009 -0.034 -0.059
10 -0.017 -0.043 -0.068
15 -0.026 -0.051 -0.077
20 -0.034 -0.060 -0.086
25 -0.043 -0.069 -0.095
30 -0.051 -0.078 -0.104
35 -0.060 -0.086 -0.113
40 -0.068 -0.095 -0.122
45 -0.077 -0.104 -0.131
50 -0.085 -0.113 -0.140
55 -0.094 -0.121 -0.149
60 -0.102 -0.130 -0.158
65 -0.111 -0.139 -0.167
70 -0.119 -0.148 -0.176
75 -0.128 -0.156 -0.185
78 -0.133 -0.162 -0.190

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.12.

2. This table is intended to aid in reading discrete points on Figure 2-2.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must be taken from processor V
the Volt age Regulator Down (VRD) 10.1 Design Guide For Deskt op LGA775 Socket for socket loadli ne guide­lines and VR implementation details.

4. Adherence to this loadline specification for the processor is required to ensure reliable processor operation.

1, 2, 3, 4

Minimum Voltage

1.80 mΩ

and VSS lands. Refer to

CC

Datasheet 27

Electrical Specifications

Figure 2-2. VCC Static and Transient Tolerance for 775_VR_CONFIG_04A

Icc [A]

Vcc Maximum

VID - 0.000

VID - 0.025

VID - 0.050

VID - 0.075

VID - 0.100

Vcc [V]

VID - 0.125

VID - 0.150

VID - 0.175

VID - 0.200

0 10203040506070

Vcc Typical

Vcc Minimum

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.12.

2. This loadline specification shows the deviation from the VID set point.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation
feedback for voltage regulator circuits must be taken from processor V
Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for socket loadline guidelines and VR impl ementation details.

4. Adherence to this loadline specification for the processor is required to ensure reliable processor operation.

and VSS lands. Refer to the Voltage Regulator

CC

28 Datasheet

Electrical Specifications

Table 2-10. VCC Static and Transient Tolerance for 775_VR_CONFIG_04B Processors

Voltage Deviation from VID Setting (V)

ICC (A)

Maximum Voltage

1.30 mΩ

Typical Voltage

1.35 mΩ

0 0.000 -0.019 -0.038

5 -0.007 -0.026 -0.045
10 -0.013 -0.033 -0.052
15 -0.020 -0.039 -0.059
20 -0.026 -0.046 -0.066
25 -0.033 -0.053 -0.073
30 -0.039 -0.060 -0.080
35 -0.046 -0.066 -0.087
40 -0.052 -0.073 -0.094
45 -0.059 -0.080 -0.101
50 -0.065 -0.087 -0.108
55 -0.072 -0.093 -0.115
60 -0.078 -0.100 -0.122
65 -0.085 -0.107 -0.129
70 -0.091 -0.114 -0.136
75 -0.098 -0.120 -0.143
80 -0.104 -0.127 -0.150
85 -0.111 -0.134 -0.157
90 -0.117 -0.141 -0.164
95 -0.124 -0.147 -0.171

100 -0.130 -0.154 -0.178
105 -0.137 -0.161 -0.185
110 -0.143 -0.168 -0.192
115 -0.150 -0.174 -0.199
119 -0.155 -0.180 -0.205

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.12.

2. This table is intended to aid in reading discrete points on Figure 2-2.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must be taken from processor V
the Volt age Regulator Down (VRD) 10.1 Design Guide For Deskt op LGA775 Socket for socket loadli ne guide­lines and VR implementation details.

4. Adherence to this loadline specification for the processor is required to ensure reliable processor operation.

1, 2, 3, 4

Minimum Voltage

1.40 mΩ

and VSS lands. Refer to

CC

Datasheet 29