inter
iAPX 432
Interface Processor
Architecture Reference
Manual
171863-001
iAPX
432
INTERFACE
INTEL
P~OR
Manual Orner
Release
Number
1.1
171863-001
Oamponents
Intel
Cb~right
Corporation,
3065
(C)
Bowers
1981,
Intel
Avenue, Santa
Corporation
Clara,
California
95051
Additional
obtained
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from:
of
this
manual
or
other
Intel
literature
may
be
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Intel
3065
Santa
The
information
Intel
material,
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BCMers
Clara,
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including,
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95051
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products
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7-104.9
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PREFACE
Understanding
432,
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432
Interface
general
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INTEL
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Subsystems
Detailed
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descriptions
understand
in
forming a
the
representations
faults,
iii
of
TABLE
OF
CCNl'ENI'S
TITLE
1.
KE'Y'
1-1.
1-2.
1-3.
1-4.
1-5.
crncEP'l'S
Peripheral
Basic
Peripheral
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Subsystems
I/O
~e1
Subsystem
Peripheral
Attached Processor
Interface
Peripheral
I/O
Controller
Execution Environments
Wind~
Functions
I/O
lv1OO.el
Data
I/O
StmmaI"Y
Flow
EKaII1J?le
GOP
Process
Printer
Printer
Printer
Supplementary
Physical
Reference
Interconnect
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Interface
Subsystem
Interface
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Hardware
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Processor
Subsystem
Interface
Software
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Summary
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Server Task
Task (Device Task)
Reply Task
Interface
Access
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Perspective
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Perspective
Perspective
Perspective
Processor
r.t:>de
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Facilities
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PAGE
1-1
1-1
1-4
l-7
1-7
1-7
1-9
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1-19
1-21
1-21
1-21
1-22
1-22
1-22
2.
CB.:JEX::!'IS
2-1.
2-2.
2-3.
2-4.
2-5.
2-6.
2-7.
2-8.
iv
.ANI) OPERAroRS
S~y
Envi romnent
IP
C>]?er
Obj
ect
Addressing and Global
Of
Interface
ators
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Processor
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Facilities
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Storage
Objects For Program Environments
Facilities
Processes
Process
Facilities
For Asynchronous Communication
and IĀ£x::al Storage Resource
Scheduling and Dispatching
For Object
Management
Context Environment Manipulation
The
Four
Direct
Oi:>ject
vs.
Selectors
Entering
Entering
Entry
an Access Segment
the
Access Segments
Indirect
Accessibility
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Global Access Segment
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Management
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Management
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II
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2-1
2-1
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2-7
2-7
2-8
2-8
2-8
2-8
2-9
2-9
2-10
2-12
2-12
2-12
3.
~
3-1.
3-2.
3-3.
3-4.
3-5.
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WindCM
WindCM
Random
Block Mode.Data
Interconnect
AttribJtes
Wioo~
Subrange Base Address
Object
Direction
Transfer
Transfer
O\Terlay
Address Recognition
Consistency
Block
Block
Block
Block
Block
Status
Reference
............................................
Status
Mode
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Operation
Check
Mode
Data
Mode
Mode
MOde
r.1c>de
Mode
Transfers
Transfer
Transfer
Attributes
Consistency
Operation
Termination
Addressing
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arrl
Subrange
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Size
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Ā· ............................... .
Check
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3-1
3-2
3-2
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3-5
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3-6
3-6
3-7
3-9
3-9
3-9
3-12
3-14
3-14
3-15
3-15
3-16
3-17
3-20
4.
FtJNCI'IOOS
4-1.
4-2.
4-3.
4-4.
5 ā¢
PIIY'S
5-1.
5-2.
5-3.
6.
FAULTS
6-1.
6-2.
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Function
Function
Process
Function
Function
Function
Function
ICAI..
Reference
Physical
Physical
Facility
Requests
Selection
Opcodes
Operands
~ecu
Completion
REF'ERmCE:
Reference
Reference
tion
Mode
Interface
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lvDDE
Switching
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Ā· ............................... .
MOde
Addressing
Mode
Functions
. ...................... .
......................................................
Fault
Fault
Reporting
Physical
Wgical
Categories
Window-Mapped
Mode
Context-level
Process-level
Processor-level
Haooling . ......................................... .
..........................................
Mode
.........................................
..........................................
of
Logical
Data
Mode
Faults
Faults
Faults
Transfer
Faults
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4-1
4-1
4-4
4-4
4-4
4-6
4-9
4-9
5-1
5-1
5-2
5-2
6-1
6-1
6-2
6-2
6-2
6-3
6-3
6-4
6-4
6-6
v
APPENDICES
APPENDICES
A.
SYS'm1
A-I.
A-2.
A-3.
B.
FUNCTICN
c.
FA~T
C-l.
C-2.
C-3.
C-4.
D. IN'lERRlJP'r
E.
SYS'I'm
E-l.
E-2.
E-3.
F.
INTERPRX!ESS
~
Context
Process
Processor
S~y
Fault
Fault
Object
Non-Instruction
INITIAl.JIZATlOO
System Reset
Establishing
System
S~
Objects
Objects
Objects
S~Y
Reporting ..........................................
Information
Level
lIAN'DLING...........................................
............................................
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Operator
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.
.........................................
........................................
"
Areas
Interface
..................................
Faults
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Faults
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e._
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.............................................
an
Startup
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Execution
...........................................
Environment
AND
DISPATCHING
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EXAMPLE
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Page
A-l
A-I
A-3
A-7
B-1
C-l
C-l
C-l
C-5
C-IO
D--1
E-l
E-l
E-2
E-5
F-l
vi
TABLES
TITLE
1-1.
2-1.
2-2.
2-3.
3-1.
B-1.
B-2.
B-3.
D-l.
E-l.
Printer
IP/GDP
IP/GDP
Example Legend
System Object Comparison
Operator Comparison
Direct/Indirect
Window
Attribute
Alphabetical
IP
Function
IP Function
Interrupt
Window
Configuration
Summary
Summary
Sources
Accessibility
Summary
Index
to
by Function
by Operator
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PAGE
1-2
1-5
1-6
1-8
1-12
1-15
1-17
1-20
.
3-8
3-10
3-11
3-13
3-18
3-19
4-2
4-3
4-5
4-7
4-8
4-10
6-5
D-2
E-3
F-2
F-ll
F-12
F-13
F-14
F-15
viii
CHAPTER
KEY
CCNCEPTS
1
This
connection
Peripheral
Section
Peripheral
of
chapter
chapter
first
I/O
four
operations,
Interface
reviews
for
an
the
simple
example
with
Subsystems
Processors
the
interface
1-3
Subsystem
IP.
introduces
addressing,
special
1-1.
A
typical
consists
situations.
PERIPHERAL
application
of
Subsystems.
which employs
composed
or
more
these
more
of
one
Interface
processors.
processes
introduces
sections
inIXlt/output
fran
432' s
basic
between a
descr
In
ibes
the
fourth
~lementation
two
additional
the
iAPX
cover
(PS),
the
432
link
model
Peripheral
the
hardware and
interface,
section
physical
the
operations.
which
data
these
of
with
is
reviewed.
reference
IP
SUBSYSTEMS
based
on
the
a 432 .system and one
Figure
two
or
which
1-1
illustrates
Per
ipheral
more
iAPx
Processors,
The 432
system
execute
Subsystems. The 432 system hardware
432
General
and a
on
the
432
Interface
IP
as
it
Section
are
responsible
processing
together.
inp.lt/outp,lt,
Subsystem and
software
particular
the
I/O
roc>del
The
m::>de
facilities
iAPX
432
or
more
a
hypothetical
Data
COII1I'OC>n
software
memory
is a collection
GDP(s).
Processor
is
used
1-1
distinguishes
for
system,
and shows how
The second
pointing
the
that
conpr
emphasis on
i.s
summar
final
section
and
that
are
provid.ed
microprocessor
satellite
configuration
Processors
which
(IP).
The
normally
the
bulk
section
out
the
need
432
system.
ise
this
the
role
ized
and a
of
the
interconnect
for
family
Peripheral
(GDPs),
is
shared
of
one
one
in
of
is
by
or
A fundamental
system
processes
environment
have any
Conceptually,
objects
in
oper.ations.
principle
the
432 system
memory
of
is
direct
from
the
432
se
If-contained.;
oontact
is
enclosed
possible
architecture
nei
ther
with
by
the
a
damage by
is
that
processors
"outside
wall
that
uncontrolled
the
432
nor
world."
protects
I/O
1-1
iAPX
432
Interface
Processor
Architecture
Reference Manual
432
System/Peripheral
Figure
1-1
Memory
Subsystem
432
System and
432
Boundary
Peripheral
SljbSystems
1-2
In
a 432-based
inplt/out];Xlt
includes
A
Peripheral
memory,
software.
application
number
number
A
Peripheral
that
executes
channel,
complement
device
I/O
The number
depems
may
be
of
GDPs
it
assumes
in
however, each
of
application
system
that
microcooputer
a
432
Peripheral
A
Peripheral
iAPX
Interface
these
very
and
432
is
general
16-bit
Interface
Processor
the
microcomputer
system,
operations
control,
Subsystem
devices
var
ied
in
the
is
am
of
on
the
with
system.
the
bulk
is
delegated
timing,
an autonomous computer system
controllers,
Peripheral
I/O-intensiveness
changing
Subsystem resembles a
responsibility
parallel
with
for
432 system
Peripheral
hardware and
cost
can
bus,
am
oonmunicate
such
performance
as
Intel's
software
Subsystem.
Subsystem
is
attached
Processor
presents
standard
interface
432
that
two
processor
can
buses.
of
processing
to
Peripheral
interrupt
at
handling
least
Subsystems employed
of
needs,
and
conventional
l~level
I/O
processor(s).
Subsystem
can
resources
requirements.
over
a
standard
Multibus'IM
to
the
432
(IP).
separate
be
At
packet
adapted
the
bus
bus and
to
required
Subsystems;
and
one
processor,
the
application;
is
independent
mainframe
device
Unlike a simple
be
configured
that
precisely
In
8-
design,
system
by
hardware
interfaces.
the
nost
traditional
KEY
CCHE?TS
to
support
buffer
with
in
its
any
channel
su~rt
general,
or
may
serve
means
level,
One
other
this
ing
given
of
with
fits
l6-bi
of
is
ā¢
own
and
the
the
in
and
a
any
t
as
an
an
of
a
8-
The
Interface
'lb
sUQ?Ort
separates
the
a
Peripheral
provides a set
expose a
its
single
contents
Subsystem. Tb
protection
with
windowed
mechanisms
segment.
An
Interface
which
are
operation
considerably,
be
manipulated
system
processes
Processor
also
of
they
Processor
is
transfer
Subsystem from
of
software-controlled
object
may
(data
be
transferred
preserve
in
the
access
to
432
additionally
invoked
these
by
Peripheral
functions
generally
as
enti
ties,
and
software
driven
of
information
structure)
the
integrity
432
system,
objects
(and
permit
and
executing
by
Peripheral
through
the
432
windows. A window
in
432
system
to
or
from
of
the
the
IP
only
which
provides
Subsystem
the
objects
enable
are
of
a
software.
returned
in
432 system
conmunication between 432
in a Peripheral
Subsystem
the
software.
wall
system,
is
memory
the
Peri.pheral
capability-based
provides
system
set
of
functions,
type
While
results)
memory
Subsystem.
that
the
used
so
that
the
data
varies
IP
to
PS
the
to
1-3
iAPX
It
is
~rtant
utilize
and
protection
object,
Subsystem
1-2.
As
figure
are
and a
software
BASIC
based
processes
this
software
manual, a
in
managing an
consumer
device
or
(e.
spc:x>ler).
432
Interface
to
strictly
systems.
function
I/O
MODEL
1-2
illustrates,
on
the
and
device
device
the
I/O
device.
producer
9
.,
a
Processor
note
that
enforce
Thus, a window
provides
to
interact
notion
of
tasks
task
Peripheral
An
of
data.
terminal),
Architecture
both
the
the
window and
standard
provides
a
E.rotected
with
input/output
passing
located
is
the
432
operations
messages between 432 system
in a Peripheral
consi.dered
Subsystem which
I/O
device
is
Thus an
a
file,
or
Reference
function
432
protected
way
system.
to
be
the
is
considered
I/O
device
a
pseudo-device
Manual
facilities
addressing
access
for
Peripheral
in
a 432
Subsystem.
hardware and
responsible
to
be
either
may
be
a
(e.
and
to
an
system
In
for
a
real
g.,
a
A message
contains
"read
carries
the
device
process.
acknowledge
A
very
between
Peripheral
but
in
with
the
the
subsystem boundary,
system
sent
information
file
XYZ"). The
out
the
task
The
completion
general
processes
Subsystem may,
any
case,
432's.
can
be
from a
operation.
returns
device
and
By
made
compatible
GOP
that
describes
device
the
task
may
of a request.
very
is
such a
powerful
inherent
or
may
facility
inter:PQsing a
the
standard
process
If
an
data
also
in
not,
with
which
the
requested
task
interprets
operation
as
a message
return
mechanism
the
432
have
will
not
Peripheral
432
any
device
requests
operation
the
generates
to
a message
for
passing
architecture.
its
own message
be
directly
Subsystem
interprocess
task
(see
I/O
service
(e.g.,
message and
input
the
originating
to
posi
ti
messages
A
facility,
compatible
interface
comnunication
figure
1-3).
data,
vel
y
given
at
1-4
432
System
Service
Order
Messaqe
Peripheral
KEY
Subayatem
CONCEP'IS
-------------------
Procesa
O.
1.
2.
order,
o
Process
service
Process
describing
device
Device
task
task
interprets
running
formulates
service,
receives
on
GDP
message
sends
service
it
Figure
needs
it
1-2
I/O
to
Service
Reply
Message
Basic
3.
Device
service
4.
Device
containing
it
5.
Originating
it,
I/O
task
order
task
back
to
executes
Service
transfers
parameters
formulates
result
originating
of
process
accordingly
Cycle
Device
Task
data
reply
transfer
process.
receives
-V
according
message
operation,
reply,
(:;'\
to
sends
interprets
1-5
iAPX
432
432
Interface
System
Processor
-------Peripheral
Architecture
Reference
Subsystem
Manual
------------
Figure
1-3
Peripheral Subsystem
Interface
Device
Task
f
1-6
1-
3.
PERIPHERAL
A
Peripheral
software
that
SUBSYS'lm
Subsystem
acts
as
oammunication between a
in a Peripheral
Subsystem
Peripheral
desired
a
collection
appearance
Subsystem. Viewed from
interface
Subsystem
to a device
of
tasks.
INTERFACE
interface
is
an ad.aptor which
process
appears
interface
to
in
be
may
task.
a
collection
enables
the
432 system and a
the
432
a
set
be
designed
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side,
of
processes.
it
of
hardware and
message-based
device
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Peripheral
to
present
may
look
task
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any
like
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figure
~
controller.
facili
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both
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be
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ties.
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system and
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general-purpose
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synchronization
multiple
as
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the
processors,
AP.
may
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INTERFACE
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an
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improve
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I/O
processor,
be
used
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example,
Thus,
the
or
and
coordination,
only
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processors ( or
be
given
should
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interface
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performance,
AP
and
as
a whole,
which
the
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processor,
as
an
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to
working
also
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it
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execute
may
may
of
access
be
centralized
hardware
Processor
the
the
supports
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such
with
device
be
be
one
in
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should
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are
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Figure 1-4
Peripheral
Subsystem
Interface
Hardware
KEY
COOCEPTS
Continuing
Processor
alter
transfer
the
operations
INTERFACE
The
IP
completes
between
the
provides
so
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they
As
software
432
are
figure
discussed
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packet
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and
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same way
memory,
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functional
the
notion
fetches
flow
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instructions,
of
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running
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in
1-4
shows,
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interface.
link
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as a GDP.
the
IP
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redundancy
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within
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next
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interface
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br
permits
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checking.
logical
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and
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I/O
processor
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extend
logical
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section.
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idging
data
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other
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to
flOll between
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to
432
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processor,
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instructions
arithmetic,
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by
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432
system.
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AP's
processor
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able
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logic
data
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instruction
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operate
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in
exactly
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access
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paths
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processor
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the
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microprocessor
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component
IP
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oonnected
memory
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component;
long.
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range.
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nature
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side,
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as
references
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to
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noted
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information
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and
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that
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signal.
its
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attention.
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iAPX
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8-
or
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86
families.
as
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up
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Interface
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bus
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were a
to
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to
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ize,
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respoms
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of
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address
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other
as
~
IP's
windows.
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Interface
references
Since
active
controllers,
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Processor
generated
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obtain
PERIPHERAL
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this
manual
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approach
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ipheral
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inposes
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to
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00
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insic
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form
of
parameters.
am
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procedure
calis,
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interface
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constraints
simplify
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organization
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oommunication
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controller.
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on
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software
to
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iRMX-80ā¢,
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by
software,
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the
facilities
data
between
structure
organization
organizing
of
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controller,
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of
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similar
facility.
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well
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controller
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also
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or
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thin
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in
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three
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structured,
facilities
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these
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controller
provided
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by
interacts
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execution
with
the
432
Processor.
environments,
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Interface
within
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controller
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ects
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environment
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Processor
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in
the
432
system.
objects
I/O
associated
software
to
that
controller
by a
processor
like
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environment
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context
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used
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represented
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ects.
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framework
432
system.
process
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addressing
operation
environment
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in
432
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an
execution
running
for
is
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memory
by
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the
environment
on a
addressing,
KEY
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as a set
IP.
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IP
IP
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its
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selects
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controller,
processes
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Subsystem.
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transfer
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occupied
system
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obtains
address
object.
address
reference.
writing
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by
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memory
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data
transfers
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to
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IP
suworts
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environment
permits,
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function
error
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of
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figure
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it
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1-5).
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iAPX
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to
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ect
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may
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like
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of
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to
directly
has
imposed by
the
432
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will
not
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always
device
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a windoo becomes
device
may
transfers
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memory
may
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objects.
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may
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example,
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and 432
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available.
in
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system
onto
four
during
by
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processor
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seriously
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execution
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agents
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of
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window,
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disk
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transfer
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function.
may
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oontrol
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opcode
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requests
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request
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of
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information
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through
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sequences
IP
controller
facility.
in
the
controller
function,
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IP
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it
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control
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respond
executing
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with
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ting
IP
IP
3
the
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The
iAPX
IP's
o
432
function
alter
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windows;
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the
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o
manitulate
set
permits
432
objects.
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the
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interprocess
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controller
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Reference
to:
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functions
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operate
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in
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designing
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432
by
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1-4
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Figure
components
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and
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I/O
I/O
system
I/O
controllers
IDDEL
SUMMARY
1-6
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menory.
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task
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device;
system.
in
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service
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target
in
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sending
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same
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communication
may
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instruction
432
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the
set,
am
possibly
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models.
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controllers
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only a subset
can
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432
system/peripheral
characteristics
is
concerned,
it
may
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a 432
system
working on
the
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way
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viewed
set,
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available
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relationship
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means
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job
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via
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processing.
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between
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is
to
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need
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a
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and windows,
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are
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1-15
iAPx 432
I/O
EXAMPLE
To
illustrate
this
output
one
the
section
might
of
many
example does
implementation,
to
and from a number
In
this
example,
implemented
multitasking
cornnunicate
432
interprocess
the
OS
are
operator.
mailboxes
or
messages
Interface
the
operation
provides
be implemented. Of
possible
not
with
of
all
Peripheral
as a collection
operating
with
one
another
corrmunication
messages,
Messages
are
queue
waiting
are
structures
for
moves a message from a
fran
not,
a message
to
and
a
mailbox
the
task
432
ports
RECEIVE
to
is
to
the
and
operators.
the
queued
mailbox.
TRANSMIT
Processor
of
a
simple
awroaches
show
the
Peripheral
devices
of
system.
in
mailboxes,
arbitrary
tasks.
task
to a mailbox
issuing
at
the
In
and
Architecture
the
432
I/O
Reference
model more
example which shows
course,
that
all
the
might
the
be
detail
Subsystem
example
taken.
supporting
concurrently.
Subsystem
tasks
This
a
fashion
OS
facility.
a
TRANSMIT
data
that
hold
When
task
mailbox
other
ACCEPT
running
if
words,
software
under
is
assumed
that
The mechanisms
operator
structures
tasks
executed
and
waiting
by
ACCEPT
a message
until
another
mailboxes
are
analogous
Manual
specifically,
how
line
describes
Furthermore,
of
a
is
assumed
the
control
to
allow
is
analogous
provided
and
an
in
memory, and
for
a
task,
moves a message
is
available;
task
are
to
the
printer
only
typical
transfers
to
be
of
a
tasks
to
to
the
by
ACCEPT
messages
TRANSMIT
if
TRANSMITs
analogous
432
SEND
Figure
flON
1-7
of
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printer
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fran
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printer;
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a
pool
at
one
structure
element
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when
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of
these
tbne.
to
to
data
to
the
as
process
sending
messages,
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the
another
pr
int
the
data
a
positive
may
it
example
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data
also
on
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has
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acknowledgement
then
off
send more
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with
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table
the
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printed,
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432
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432
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subayatem
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8
Figure
1-7
Printer
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1-17
iAPX
432
Interface
Processor
Architecture
Reference Manual
.Table
1-1
Item
SEND,/R:ErnIVE
P:t;int order_mailbaK
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Pr
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Example Legend
Description
Object (message)
operation
point
432
of
communications
convention
432
communicat
process
432
operators
fram
view (see
to
queue
waits
for
requesting
figure
ions
result
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message queue
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03
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printer
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port
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int
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the
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RECEIVE
analogous
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to
432
SEND
and
1-18
KEY
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Figure
1-8
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text
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the
432
returned,
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The
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printed.
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to
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example.
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the
1-19
iAPX
432
Interface
Processor
Text~
Architecture
Reference
Manual
CI
Object
Print
References".,.;;
Text
Figure 1-8
__
Example
Print
Print
Status
Command
Object
Data
1-20
KEY
CONCEPTS
Printer
The
printer
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by
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432
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432
1-21