Intel I5-520E, P4505, I7-610E, I7-620UE, P4500 User Manual
...
Intel® Core
i7-620LE/UE, i7-610E,
®
TM
i5-520E and Intel
Celeron®
Processor P4500, P4505 Series
Datasheet Addendum
April 2010
Document Numbe r: 323178-002
Lega l Li nes and Discl a imers
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Copyright © 2010, Intel Corporation. All Rights Reserved.
Intel® Core
Datashe et A dd en d um April 2010
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
2 Document Numbe r: 32 31 78-002
Contents
1 Introduction and Features Summary .........................................................................8
1.1 Introduction .......................................................................................................8
1.2 Interfaces ........................................................................................................10
1.2.1 System Memory Support.........................................................................10
1.2.2 PCI Express* .........................................................................................10
1.3 Package........................................................................................................... 11
1.4 Terminology .....................................................................................................12
1.5 Related Documents ...........................................................................................13
2Interfaces................................................................................................................15
2.1 System Memory Interface .................................................................................. 15
2.1.1 System Memory Technology Supported.....................................................15
2.1.2 System Memory Timing Support............................................................... 16
2.1.3 System Memory Organization Modes.........................................................16
2.1.4 Rules for Populating Memory Slots............................................................ 18
2.1.5 Technology Enhancements of Intel
2.1.6 DRAM Clock Generation...........................................................................19
2.1.7 DDR3 On-Die Termination ....................................................................... 19
2.2 PCI Express* Interface.......................................................................................19
2.2.1 PCI Express* Configuration Mechanism .....................................................19
2.2.2 PCI Express Port Bifurcation..................................................................... 20
3 Signal Description ...................................................................................................21
3.1 System Memory Interface .................................................................................. 21
3.2 Reset and Miscellaneous Signals..........................................................................24
4 Electrical Specifications ...........................................................................................25
4.1 Signal Groups...................................................................................................25
4.2 DC Specifications ............. .................................................................................25
4.2.1 Voltage and Current Specifications............................................................25
5 Processor Ball and Signal Information.....................................................................27
5.1 Processor Ball Assignments.................................................................................27
6 Processor Configuration Registers...........................................................................69
6.1 Register Terminology.........................................................................................69
6.1.1 DEVEN - Device Enable ...........................................................................71
6.1.2 ERRSTS - Error Status ............................................................................72
6.1.3 ERRCMD - Error Command ......................................................................73
6.1.4 SMICMD - SMI Command........................................................................75
6.1.5 C0WRDATACTRL - Channel 0 Write Data Control.........................................76
6.1.6 COECCERRLOG - Channel 0 ECC Error Log.................................................77
6.1.7 C1WRDATACTRL - Channel 1 Write Data Control.........................................79
6.1.8 C1ECCERRLOG - Channel 1 ECC Error Log .................................................79
6.2 PCI Device 6.....................................................................................................80
6.2.1 VID6 - Vendor Identification ....................................................................84
6.2.2 DID6 - Device Identification.....................................................................84
6.2.3 PCICMD6 - PCI Command........................................................................ 85
6.2.4 PCISTS6 - PCI Status..............................................................................87
6.2.5 RID6 - Revision Identification...................................................................89
6.2.6 CC6 - Class Code ...................................................................................89
6.2.7 CL6 - Cache Line Size .............................................................................90
6.2.8 HDR6 - Header Type...............................................................................90
6.2.9 PBUSN6 - Primary Bus Number ................................................................91
®
Fast Memory Access (Intel® FMA).......... 18
April 2010 Datasheet Addendum
Document Number: 32 31 78 - 00 2 3
Intel® Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
6.2.10 SBUSN6 - Secondary Bus Number.............................................................91
6.2.11 SUBUSN6 - Subordinate Bus Number ........................................................92
6.2.12 IOBASE6 - I/O Base Address....................................................................92
6.2.13 IOLIMIT6 - I/O Limit Address ...................................................................93
6.2.14 SSTS6 - Secondary Status.......................................................................94
6.2.15 MBASE6 - Memory Base Address...............................................................95
6.2.16 MLIMIT6 - Memory Limit Address..............................................................96
6.2.17 PMBASE6 - Prefetchable Memory Base Address...........................................97
6.2.18 PMLIMIT6 - Prefetchable Memor y Limit Address ..........................................98
6.2.19 PMBASEU6 - Prefetchable Memory Base Address Upper................................99
6.2.20 PMLIMITU6 - Prefetchable Memory Limit Address Upper.............................100
6.2.21 CAPPTR6 - Capabilities Pointer................................................................101
6.2.22 INTRLINE6 - Interrupt Line ........................................ ............................101
6.2.23 INTRPIN6 - Interrupt Pin........................................................................102
6.2.24 BCTRL6 - Bridge Control........................................................................102
6.2.25 PM_CAPID6 - Power Management Capabilities ..........................................104
6.2.26 PM_CS6 - Power Management Control/Status...........................................105
6.2.27 SS_CAPID - Subsystem ID and Vendor ID Capabilities...............................107
6.2.28 SS - Subsystem ID and Subsystem Vendor ID..........................................107
6.2.29 MSI_CAPID - Message Signaled Interrupts Capability ID ............................108
6.2.30 MC - Message Control............................................................................108
6.2.31 MA - Message Addre ss...........................................................................110
6.2.32 MD - Message Data...............................................................................110
6.2.33 PEG_CAPL - PCI Express-G Capability List............................ ....................111
6.2.34 PEG_CAP - PCI Express-G Capabilities.....................................................111
6.2.35 DCAP - Device Capabilities.....................................................................112
6.2.36 DCTL - Device Co ntrol...........................................................................113
6.2.37 DSTS - Device Status............................................................................114
6.2.38 LCAP - Link Capab ilities.........................................................................115
6.2.39 LCTL - Link Control ...............................................................................118
6.2.40 LSTS - Link Status ................................................................................120
6.2.41 SLOTCAP - Slot Capabilities....................................................................122
6.2.42 SLOTCTL - Slot Control..........................................................................123
6.2.43 SLOTSTS - Slot Status...........................................................................126
6.2.44 RCTL - Root Control ..............................................................................128
6.2.45 RSTS - Root Status................................ ...............................................129
6.2.46 LCTL2 - Link Control 2...........................................................................129
6.2.47 LSTS2 - Link Status 2............................................................................131
6.2.48 PEGLC - PCI Express-G Legacy Control ........................................... .........132
6.3 PCI Device 6 - Extended Configuration................................................................133
6.3.1 VCECH - Virtual Channel Enhanced Capability Header................................133
6.3.2 PVCCAP1 - Port VC Capability Register 1..................................................133
6.3.3 PVCCAP2 - Port VC Capability Register 2..................................................134
6.3.4 PVCCTL - Port VC Control.......................................................................135
6.3.5 VC0RC AP - VC0 Re sou r ce Capab ilit y ..... ... .... . ... .. ... ... .. ... ... .. ... . .... ... . .... ... . ..135
6.3.6 VC0RCTL - VC0 Resource Control............................................................136
6.3.7 VC0RSTS - VC0 Resource Status................ .............................................137
Intel® Core
Datashe et A dd en d um April 2010
4 Document Numbe r: 32 31 78-002
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Figures
1Intel® CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505
Series on the Intel
2Intel
®
Flex Memory Technology Operation...................................................................17
3 Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes ............. ..... 18
4 PCI Express* Related Register Structures in the
5Intel
®
Intel
Series.....................................................................................................................20
®
Core
Core
TM
TM
Series Ballmap
(Top View, Upper-Left Quadrant) ...............................................................................28
6Intel
®
Core
TM
Series Ballmap
(Top View, Upper-Right Quadrant) .............................................................................29
7Intel
®
Core
TM
Series Ballmap
(Top View, Lower-Left Quadrant) ...............................................................................30
8Intel
®
Core
TM
Series Ballmap
(Top View, Lower-Right Quadrant) .............................................................................31
®
CoreTM i7 processor based low-power platform.................................9
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505
Tables
1 Processor Documents ...............................................................................................13
2 PCH Documents.......................................................................................................14
3 Public Specifications .................................................................................................14
4 Supported DIMM Module Configurations......................................................................15
5 DDR3 System Memory Timing Support........................................................................16
6 Signal Description Buffer Types..................................................................................21
7 Memory Channel A...................................................................................................21
8 Memory Channel B...................................................................................................23
9 Reset and Miscellaneous Signals ................................................................................ 24
10 Mobile Signal Groups1..............................................................................................25
11 DDR3 Signal Group DC Specifications .........................................................................25
12 Intel
13 Intel
14 Register Terminology................................................................................................69
15 DEVEN - Device Enable Register.................................................................................71
16 Error Status Register................................................................................................72
17 Error Command Registers .........................................................................................74
18 SMI Command Registers...........................................................................................75
19 Channel 0 Write Data Control Registers....................................................................... 76
20 Channel 0 ECC Error Registers...................................................................................77
21 Channel 1 Write Data Control Registers....................................................................... 79
22 Channel 1 ECC Error Registers...................................................................................80
23 PCI Device 6 Register...............................................................................................81
24 VID6 - Vendor Identification Register..........................................................................84
25 DID6 - Device Identification Register..........................................................................84
26 PCICMD6 - PCI Command Register.............................................................................85
27 PCISTS6 - PCI Status Register...................................................................................87
28 RID6 - Revision Identification Register........................................................................89
29 CC6 - Class Code Register.........................................................................................89
30 CL6 - Cache Line Size Register...................................................................................90
31 HDR6 - Header Type Register....................................................................................90
32 PBUSN6 - Primary Bus Number Register......................................................................91
®
Series Ball List by Ball Name .....................................................................................32
®
Core
Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505
Series Ball List by Ball Number ..................................................................................49
April 2010 Datasheet Addendum
Document Number: 32 31 78 - 00 2 5
Intel® Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
33 SBUSN6 - Secondary Bus Number Register..................................................................91
34 SUBUSN6 - Subordinate Bus Number Register..............................................................92
35 IOBASE6 - I/O Base Address Register .........................................................................93
36 IOLIMIT6 - I/O Limit Address Register................................................ .........................93
37 SSTS6 - Secondary Status Register.............................................................................94
38 MBASE6 - Memory Base Address Register....................................................................95
39 MLIMIT6 - Memory Limit Address Register ...................................................................96
40 PMBASE6 - Prefetchable Memory Base Address Register ................................................97
41 PMLIMIT6 - Prefetchable Mem o ry Limit Address Register................................................98
42 PMBASEU6 - Prefetchable Memory Base Address Upper Register.....................................99
43 PMLIMITU6 - Prefetchable Memory Limit Address Upper Register ..................................100
44 CAPPTR6 - Capabilities Pointer Register.....................................................................101
45 INTRLINE6 - Interrupt Line Register..........................................................................101
46 INTRPIN6 - Interrupt Pin Register.............................. ...............................................102
47 BCTRL6 - Bridge Control Register .............................................................................102
48 PM_CAPID6 - Power Management Capabilities Register................................................104
49 PM_CS6 - Power Management Control/Status Register ................................................105
50 SS_CAPID - Subsystem ID and Vendor ID Capabilities Register ....................................107
51 SS - Subsystem ID and Subsystem Vend or ID Register................................................107
52 MSI_CAPID - Message Signaled Interrupts Capability ID Register..................................108
53 MC - Message Control Register.................................................................................108
54 MA - Message Address Register................................................................................110
55 MD - Message Data Register ....................................................................................110
56 PEG_CAPL - PCI Express-G Capability List Register......................................................111
57 PEG_CAP - PCI Express-G Capabilities Register...........................................................111
58 DCAP - Device Capabilities Register ..........................................................................112
59 DCTL - Device Control Register.................................................................................113
60 DSTS - Device Status Register .................................................................................114
61 LCAP - Link Capabilities Register...............................................................................115
62 LCTL - Link Control Register.....................................................................................118
63 LSTS - Link Status Register......................................................................................120
64 SLOTCAP - Slot Capabilities Register.........................................................................122
65 SLOTCTL - Slot Control Register ...............................................................................123
66 SLOTSTS - Slot Status Register ................................................................................126
67 RCTL - Root Control Register....................................................................................128
68 RSTS - Root Status Register ....................................................................................129
69 LCTL2 - Link Control 2 Register ................................................................................129
70 LSTS2 - Link Status 2 Register.................................................................................131
71 PEGLC - PCI Express-G Legacy Control Register..........................................................132
72 PCI Device 6 - Extended Configuration ......................................................................133
73 VCECH - Virtual Channel Enhanced Capability Header..................................................133
74 PVCCAP1 - Port VC Capability Register 1....................................................................134
75 PVCCAP2 - Port VC Capability Register 2....................................................................135
76 PVCCTL - Port VC Control ........................................................................................135
77 VC0RCAP - VC0 Resource Capability..........................................................................135
78 VC0RCTL - VC0 Resource Control.............................................................................. 137
79 VC0RSTS - VC0 Resource Status ..............................................................................138
Intel® Core
Datashe et A dd en d um April 2010
6 Document Numbe r: 32 31 78-002
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Revision History
Date Revision Description
January 2010 001 • Initial release of this document.
April 20 10 002
• Added information for the Intel® Celeron® Processor P4500 and P4505 Series.
•Corrected first bullet in Section 2.1.1 to “No support for mixed ECC and non-ECC DIMM
configurations.”
April 2010 Datasheet Addendum
Document Number: 32 31 78 - 00 2 7
Intel® Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Introduction and Features Summary
1 Introduction and Features
Summary
1.1 Introduction
This Datasheet Addendum is a supplement to the Intel® CoreTM i7-600, i5-500 and i3-
300 Mobile Processor Series Datasheet. It contains the additional DC and AC electrical
specifications, signal integrity, differential signaling specifications, pinout and signal
definitions, interface functional descriptions, additional feature information and
configuration registers pertinent to the implementation and operation of the Intel
TM
Core
Series on its respective platform.
Intel
P4505 Series is the next generation of 64-bit, multi-core mobile processor built on a
32- nanometer process technology. Throughout this document, Intel
620LE/UE, i7-610E, i5-520E and Intel
be referred to as simply the processor. The processor is designed for a two-chip
platform as opposed to the traditional three-chip platforms (processor, GMCH, and
ICH). The two-chip platform consists of a processor and the Platform Controller Hub
(PCH) and enables higher performance, lower cost, easier validation, and improved x-y
footprint. The PCH may also be referred to as Mobile Intel® 5 Series Chipset (formerly
Ibex Peak-M). Intel
Processor P4500, P4505 Series is designed for the Intel
low-power platform and is offered in a BGA1288 package.
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505
®
Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500,
®
Core
®
Core
®
Celeron® Processor P4500, P4505 Series may
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron®
®
CoreTM i7 processor based
TM
i7-
®
Included in this family of processors is an integrated graphics and memory controller
die on the same package as the processor core die. This two-chip solution of a
processor core die with an integrated graphics and memory controller die is known as a
multi-chip package (MCP) processor.
Note: Integrated graphics and memory controller die is built on 45-nanometer process
technology.
®
Intel
Datashe et A dd en d um April 2010
8 Document Numbe r: 32 31 78-002
TM
Core
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Introduc tion and Features Summary
ts
Figure 1. Intel® CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor
P4500, P4505 Series on the Intel
®
CoreTM i7 processor based low-p ow er
platform
Dual-core
Processor
Discrete Graphics
(PE G)
OR
Embedded
DisplayPort* (eDP)
PCI Express* x16
Intel C o reTM i7/i5 and C e lero n
Processor
(MCP Proces so r)
GPU, Memor y
800/1066 MT/s
2 Channels
1 DIM M / Channel
Cont r ol le r
DDR3 DIMMs
PCI Express x 1
Intel® F lexib le
Display Int erf ace
Digital Dis p la y x 3
LVDS Flat Panel
DMI2
(x4)
Intel®
Management
Engine
Serial ATA
U SB 2.0
6 Ports
3 Gb/s
14 Por
Analog C R T
SPI Flash
PCI
FWH
TP M 1.2
Super I/ O
M o bile Intel 5 S eries Chipset
PC H
SPI
PCI
LPC
PEC I
GPI O
PC I Express*
8 PCI Express* x1
(2.5 G T/s)
Intel® HD Audio
SMBUS 2.0
C ontroller Link 1
Gigabit
Network Connection
Port s
April 2010 Datasheet Addendum
Document Number: 32 31 78 - 00 2 9
Intel® Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
1.2 Interfaces
1.2.1 System Memory Support
• One or two channels of DDR3 memory with a maximum of one DIMM per channel
• Single- and dual-channel memory organization modes
• Data burst length of eight for all memory organization modes
• Memory DDR3 data transfer rates of 800 and 1066 MT/s
• 64-bit wide channels (72-bit wide including ECC)
• DDR3 I/O Voltage of 1.5 V
• Supports ECC and non-ECC, unbuffered DDR3 DIMMs
— Mixing of ECC and Non-ECC DIMMS is not supported
• Theoretical maximum memory bandwidth of:
— 12.8 GB/s in dual-channel mode assuming DDR3 800 MT/s
— 17.1 GB/s in dual-channel mode assuming DDR3 1066 MT/s
• 1-Gb, and 2-Gb DDR3 DRAM technologies for x8 and x16 devices
• Using 2-Gb device technologies, the largest memory capacity possible is 8 GB,
assuming dual-channel mode with two x8, dual-rank, un-buffered, DIMM memory
configuration.
• Up to 32 simultaneous open pages, 16 per channel (assuming 4 Ranks of 8 Bank
Devices)
• Memory organizations:
— Single-channel modes
— Dual-channel modes
Dual-channel symmetric (Interleaved)
Dual-channel asymmetric
®
Flex Memory Technology
Intel
• Command launch modes of 1n/2n
• Partial Writes to memory using Data Mask (DM) signals
• On-Die Termination (ODT)
®
•Intel
Fast Memory Ac ce ss (I nte l® FMA):
— Just-in-Time Command Scheduling
—Command Overlap
— Out-of-Order Scheduling
Introduction and Features Summary
1.2.2 PCI Express*
• The processor PCI Express* port(s) are fully-compliant to the PCI Express Base
Specification, Revision 2.0 at 2.5GT/s.
• The processor supports:
— One 16-lane PCI Express port for graphics or I/O.
— Two 8-lane PCI Express ports for graphics or I/O.
• PCI Express Port 0 is mapped to PCI Device 1.
• PCI Express Port 1 is mapped to PCI Device 6.
®
Intel
Datashe et A dd en d um April 2010
10 Document Numbe r: 32 31 78-002
TM
Core
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Introduc tion and Features Summary
1.3 Package
The Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel Celeron Processor P4500,
P4505 Series are available on a 34 x 28 mm BGA package (BGA1288).
Note: Although the BGA1288 package is shared with Intel
UM/LM, i5-540M, i5-520M/UM and i5-430M Processor Series they are not ball-out
compatible.
®
CoreTM i7-640UM/LM, i7-620M/
April 2010 Datasheet Addendum
Document Number: 32 31 78 - 00 2 11
Intel® Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
1.4 Terminology
Term Description
BLT Block Level Transfer
CRT Cathode R ay Tube
DDR3 Third generation Double Data Rate SDRAM memory technology
DP DisplayPort*
DMA Direct Memory Access
DMI Direct Media Interface
DTS Digital Thermal Sensor
ECC Error Correction Code
eDP* Embedded DisplayPort*
®
DPST Intel® Disp lay P ower Saving Technology
Intel
Enhanced Intel
SpeedStep
Execute Disa b le Bit
EU Execution Unit
(G)MCH Legacy component - Graphics Memory Controller Hub.
GPU Graphics Processing Unit
ICH
IMC I ntegrated Me mo ry Con troller
Intel
Intel
Intel® TXT Intel® Trusted Execution Technology
Intel
Technology
ITPM Integrated Trusted Platform Module
IOV I/O Virtualization
LCD Liquid Crystal Display
LVDS
MCP Multi- Chip Package
NCTF
PCH
PECI Platform Environment Control Interface
®
Technolog y
®
64 Technology 64-bit memory extensions to the IA-32 architecture.
®
FDI Intel® Flexible Display Interface.
®
Virtualization
Introduction and Features Summary
Technology that provides power management capabilities to laptops.
The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the Intel® 64 and IA-32 Architectures Software
Devel oper's Man uals for more detailed information.
The legacy I/O Controller Hub component that contains the main PCI interface,
LPC interface, USB2, Serial ATA, and other I/O functions. It communicates with
the legacy (G)MCH over a proprietary interconnect called DMI.
Processor virtualizatio n which when used in conj unction with Virtual Machine
Monitor software enables multiple, robust independent software environments
inside a single platform.
Low Voltage Differential Signaling
A high speed, low power data transmission standard used for display connections
to LCD panels.
Non-Critical to Function: NCTF locations are typically redundant ground or noncritical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
Platform Controller Hub. The new 2009 chipset with centralized platform
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features. The PCH may also be referred to using the code name Ibex Peak.
®
Intel
Datashe et A dd en d um April 2010
TM
Core
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
12 Document Numbe r: 32 31 78-002
Introduc tion and Features Summary
Term Description
PEG
Processor The 64-bit, single-core or multi-core component (package)
Processo r Co re
Rank
SCI Sy st em Control I nterrupt. Used in ACPI protocol.
Storage Conditions
TA C Thermal Averaging Constant
TDP Thermal Design Power
TOM Top of Mem o r y
TTM Time-To-Market
V
CC
V
SS
V
AXG
V
TT
V
DDQ
VLD Variable Length Decoding
x1 Refers to a Link or Port with one Physical Lane
x4 Refers to a Link or Port with four Physical Lanes
x8 Refers to a Link or Port with eight Physical Lanes
x16 Refers to a Link or Port with sixteen Physical Lanes
PCI Express* Graphics. External Graphics using PCI Express Architecture. A
high-speed serial interface whose configuration is software compatible with the
existing PCI specifications.
The term “processor core” refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a SODIMM.
A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to free air. Under
these conditions, processor landings should not be connected to any supply
voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air”
(i.e., unsealed packaging or a device removed from packaging material) the
processor must be handled in accordance with moisture sensitivity labeling
(MSL) as indicated on the packaging material.
Processor core power supply
Processor ground
Graphics core power supply
L3 shared cache, memory controller, and processor I/O power rail
DDR3 powe r rail
1.5 Related Documents
Refer to the documents in Table 1 for additional information.
Table 1. Processor Documents
Document
Intel® CoreTM i7-600, i5-500 and i3-300 Mobile Processor Series Datasheet http://www.intel.com
Intel® CoreTM i7-620LE/UE, i7-610E and i5-520E Processor Series Datasheet
Addendum Specification Update
April 2010 Datasheet Addendum
Document Number: 32 31 78 - 00 2 13
Intel® Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Document Number/
Location
http://www.intel.com
Table 2. PCH Docu ments
Introduction and Features Summary
Intel® 5 Series Chipset and Intel® 3400 Series Chipset Datasheet http://www.intel.com
Table 3. Public Specifications
Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info/
PCI Local Bus Specification 3.0
PCI Express Base Specification 2.0 http://www.pcisig.com
DDR3 SDRAM Specification http://www.jedec.org
DisplayPort Specification http://www.vesa.org
®
Intel
64 and IA-32 Architectures Software Developer's Manuals
Volume 1: Basic Architecture 253665
Volume 2A: Instruction Set Reference, A-M 253666
Volume 2B: Instruction Set Reference, N-Z 253667
Volume 3A: System Programming Guide 253668
Volume 3B: System Programming Guide 253669
Document
Document
Document Number/
Location
Document Number/
Location
http://www.pcisig.com/
specifications
http://www.intel.com/
products/processor/
manuals/index.htm
§ §
®
Intel
Datashe et A dd en d um April 2010
14 Document Numbe r: 32 31 78-002
TM
Core
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Interfaces
2Interfaces
This chapter describes the interfaces supported by the processor.
2.1 System Memory Interface
2.1.1 System Memory Technology Supported
The Integrated Memory Controller (IMC) supports DDR3 protocols with two,
independent, 64-bit wide channels each accessing one DIMM. It supports:
— ECC and non-ECC un-buffered DIMMs. No support for mixed ECC and non-ECC
DIMM configurations.
DDR3 Data Transfer Rates:
— 800 MT/s (PC3-6400), and 1066 MT/s (PC3-8500)
• DDR3 DIMM Modules:
— Raw Card A – single rank x8 unbuffered non-ECC
— Raw Card B – dual rank x8 unbuffered non-ECC
— Raw Card C – single rank x16 unbuffered non-ECC
— Raw Card D – single rank x8 unbuffered ECC
— Raw Card E – dual rank x8 unbuffered ECC
— Raw Card F - dual rank x16 unbuffered non-ECC
• DDR3 DRAM Device Technology:
— Standard 1-Gb, and 2-Gb technologies and addressing are supported for x16
and x8 devices. There is no support for memory modules with different
technologies or capacities on opposite sides of the same memory module. If
one side of a memory module is populated, the other side is either identical or
empty.
Table 4. Supported DIMM Module Configurations (Sheet 1 of 2)
Raw
Card
Version
A
B
C
April 2010 Datasheet Addendum
Document Number: 32 31 78 - 00 2 15
DIMM
Capacity
512 MB 512 Mb 64 M x 8 8 1 13/10 8 8K
1 GB 1 Gb 128 M x 8 8 1 14/10 8 8K
2 GB 2 Gb 256M x 8 8 1 15/ 10 8 8K
1 GB 512 Mb 64 M x 8 16 2 13/10 8 8K
2 GB 1 Gb 128 M x 8 16 2 14/1 0 8 8K
4 GB 2 Gb 256 M x 8 16 2 15/1 0 8 8K
256MB 512 Mb 32 M x 16 4 1 12/10 8 8K
512 MB 1 Gb 6 4 M x 8 4 1 13 / 10 8 8K
1 GB 2 Gb 128 M x 16 4 1 14/10 8 8K
DRAM
Device
Technology
Intel® Core
DRAM
Organization
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
# of
DRAM
Devices
# of
Physical
Device
Ranks
# of Row/
Col
Address
Bits
# of
Banks
Inside
DRAM
Page
Size
Table 4. Supported DIM M Modu l e Conf igurations (Sheet 2 of 2)
Interfaces
Raw
Card
Version
D
E
F
DIMM
Capacity
512 MB 512 Mb 64 M x 8 9 1 13/10 8 8K
1 GB 1 Gb 128 M x 8 9 1 14/10 8 8K
2 GB 2 Gb 256 M x 8 9 1 15/10 8 8K
1 GB 512 Mb 64M x 8 18 2 13/10 8 8K
2 GB 1 Gb 128 M x 8 18 2 14/10 8 8K
4 GB 2 Gb 256 M x 8 18 2 15/10 8 8K
512 MB 512 Mb 32 M x 16 8 2 12/10 8 8K
1 GB 1 Gb 64 M x 16 8 2 13/10 8 8K
2 GB 2 Gb 128 M x 16 8 2 14/10 8 8K
DRAM
Device
Technology
DRAM
Organization
# of
DRAM
Devices
Physical
Device
2.1.2 System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
•CWL = CAS Write Latency
• Command Signal modes = 1n indicates a new command may be issued every clock
and 2n indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.
# of
Ranks
# of Row/
Col
Address
Bits
# of
Banks
Inside
DRAM
Page
Size
Table 5. DDR3 System Memory Timing Support
Transfer
Rate
(MT/s)
800 6 6 6 5 1n and 2n 1
1066
NOTES:
1. System Memory timing support is based on availability and is subject to change.
tCL
(tCK)
777
888
tRCD
(tCK)
tRP
(tCK)
CWL
(tCK)
CMD Mode Notes
61n and 2n 1
2.1.3 System Memory Organizati on Modes
The IMC supports two memory organization modes, single-channel and dual-channel.
Depending upon how the DIMM Modules are populated in each memory channel, a
number of different configurations can exist.
2.1.3.1 Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated in any
order, but not both.
®
Intel
Datashe et A dd en d um April 2010
16 Document Numbe r: 32 31 78-002
TM
Core
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Interfaces
2.1.3.2 Dual-Channel Mode - Intel® Flex Memory Technology Mode
The IMC supports Intel® Flex Memory Technology Mode. This mode combines the
advantages of the Dual-Channel Symmetric (Interleaved) and Dual-Channel
Asymmetric Modes. Memory is divided into a symmetric and a asymmetric zone. The
symmetric zone starts at the lowest address in each channel and is contiguous until the
asymmetric zone begins or until the top address of the channel with the smaller
capacity is reached. In this mode, the system runs with one zone of dual-channel mode
and one zone of single-channel mode, simultaneously, across the whole memory array.
Figure 2. Intel
®
Flex Memory Technology Operation
C
B B
CH BCH A
C
BB
CH BCH A
B – Th e largest physical memory amou nt of the smaller size mem ory m o dule
C – T he rem aining physical mem ory am ount of the la rger siz e m emory mo dule
2.1.3.2.1 Dual-Channel Symmetric Mode
Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum
performance on real world applications. Addresses are ping-ponged between the
channels after each cache line (64-byte boundary). If there are two requests, and the
second request is to an address on the opposite channel from the first, that request can
be sent before data from the first request has returned. If two consecutive cache lines
are requested, both may be retrieved simultaneously, since they are ensured to be on
opposite channels. Use Dual-Channel Symmetric mode when both Channel A and
Channel B DIMM connectors are populated in any order, with the total amount of
memory in each channel being the same.
TOM
C
B
B
Non interleaved
access
Du al channel
interleaved access
When both channels are populated with the same memory capacity and the boundary
between the dual channel zone and the single channel zone is the top of memory, IMC
operates completely in Dual-Channel Symmetric mode.
Note: The DRAM device technology and width may vary from one channel to the other.
2.1.3.2.2 Dual-Channel Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode,
addresses start at the bottom of Channel B and stay there until the end of the highest
rank in Channel B, and then addresses continue from the bottom of Channel A to the
top. Real world applications are unlikely to make requests that alternate between
addresses that sit on opposite channels with this memory organization, so in most
cases, bandwidth is limited to a single channel.
April 2010 Datasheet Addendum
Document Number: 32 31 78 - 00 2 17
Intel® Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Interfaces
This mode is u sed whe n Inte l® Flex Memory Technology is disabled and both Channel A
and Channel B DIMM connectors are populated in any order with the total amount of
memory in each channel being different.
Figure 3. Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes
Dual Channel Interleaved
(memory sizes mus t m atch)
CL
CH. B
CH. A
CH. B
CH. A
CH. B
CH. A
Top of
Memory
0
Dual Channel Asymmetric
(memory sizes can differ)
2.1.4 Rules for Populating Memory Slots
CL
CH. A
CH. B
Top of
Memory
CH.B-top
DRB
0
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports only one DIMM connector
per channel.For dual-channel modes both channels must have an DIMM connector
populated and for single-channel mode only a single-channel must have an DIMM
connector populated.
2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel
2.1.5.1 Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
®
Intel
Datashe et A dd en d um April 2010
18 Document Numbe r: 32 31 78-002
TM
Core
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
®
FMA technology enhancements.
Interfaces
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
2.1.5.2 Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Precharge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
2.1.5.3 Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,
the IMC continuo usl y monit or s pen ding req uest s to sy st em memory f or the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back to back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the IMC
to further reduce latency and increase bandwidth efficiency.
2.1.6 DRAM Clock Generation
T wo differential clock pairs for every supported DIMM. There are total of four clock pairs
driven directly by the processor to two DIMMs.
2.1.7 DDR3 On-Die Termination
On-Die Termination (ODT) is a feature that allows a DRAM device to turn on/off internal
termin ation resi stan ce for ea ch DQ, DQS/DQ S#, and DM sign al via the ODT contr ol pin.
The ODT feature improves signal integrity of the memory channel by allowing the
DRAM controller to independently turn on or off the termination resistance for any or all
DRAM devices themselves instead of on the motherboard.
The IMC drives out the required ODT signals, based on the memory configuration and
which rank is being written to or read from, to the DRAM devices on a targeted DIMM
module rank to enable or disable their termination resistance.
2.2 PCI Express* Interface
This section describes the PCI Express* interface capabilities of the processor. See the
PCI Expres s Bas e Spe ci fica t ion for further details on PCI Express.
The processor has two options for PCI Express controllers available:
• 1 x16 PCI Express Port
or
•2 x8 PCI Express Ports
— Enabled with CFG[0] strapping, see Section 2.2.2 an d Section 3.2
2.2.1 PCI Express* Configuration Mechanism
The PCI Express* link is mapped through a PCI-to-PCI bridge structure.
April 2010 Datasheet Addendum
Document Number: 32 31 78 - 00 2 19
Intel® Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Interfaces
Figure 4. PCI Express* Related Register Structures in the
Intel
®
Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor
P4500, P4505 Series
PCI Express
Device
PCI Express
Device
Port 0
Port 1
PCI- PCI Bridge
representing r oot
PCI Express port
(Device 1)
PCI- PCI Bridge
representing r oot
PCI Express port
(Device 6)
2.2.2 PCI Express Port Bifurcation
When bifurcated, the wires which had previously been assigned to lanes 15:8 of the
single x16 primary port (Port 0) are reassigned to lanes 7:0 of the x8 secondary port
(Port 1). This assignment applies whether the lane numbering is reversed or not. The
controls for the secondary port (Port 1) and the associated virtual PCI-to-PCI bridge
can be found in PCI Device 6.
PCI Compatible
Host Bridge Device
(Device 0)
DMI
When the primary port is not bifurcated, Device 6 is hidden from the discovery
mechanism used in PCI enumeration, such that configuration of the device is neither
possible nor necessary.
®
Intel
Datashe et A dd en d um April 2010
20 Document Numbe r: 32 31 78-002
TM
Core
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Signal Description
3 Signal Description
This chapter describes the processor signals. They are arranged in functional groups
according to their associated interface or category. The following notations are used to
describe the signal type:
Notatio n s Signal Ty pe
IInput Pin
OOutput Pin
I/O Bi-directional Input/Output Pin
The signal description also includes the type of buffer used for the particular signal:
Table 6. Signal Description Buffer Types
Signal Description
PCI Express*
FDI
DMI
CMOS CMOS buffers. 1.1-V tolerant
DDR3 DDR3 buffers: 1.5-V tolerant
A
GTL Gunning Transceiver Logic signaling technology.
Ref Voltage reference signal.
Asynchronous
1
PCI Express interface signals. These signals are compatible with PCI Express 2.0
Signalling Environment AC Specifications and are AC coupled. The buffers are not 3.3V tolerant. Refer to the PCIe specification.
Intel Flexible Display interface signals. These signals are compatible with PCI Express
2.0 Signaling Environment AC Specifications, but are DC coupled. The buffers are not
3.3-V tolerant.
Direct Media Interface signals. These signals are compatible with PCI Express 2.0
Signaling Environment AC Specifications, but are DC coupled. The buffers are not 3.3V tole rant.
Analog reference or output. May be u sed as a threshold voltage or for buffer
compensation.
Signal has no timing relationship with any reference clock.
NOTES:
1. Qualifier for a buffer type.
3.1 System Memory Interface
Table 7. Memory Channel A (Sheet 1 of 2)
Signal Name Description
SA_BS[2:0]
SA_WE#
April 2010 Datasheet Addendum
Document Number: 32 31 78 - 00 2 21
Intel® Core
TM
Bank Select: These signals define which banks
are se lected within each SD RAM rank.
Write Enable Control Signal: Used with
SA_RAS# and SA_CAS# (along with SA_CS#) to
define the SDRAM Commands.
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Direction/Buffer
Type
O
DDR3
O
DDR3
Table 7. Memory Channel A (Sheet 2 of 2)
Signal Description
Signal Name Description
SA_RAS#
SA_CAS#
SA_DM[7:0]
SA_DQS[8]
SA_DQS[7:0]
SA_DQS#[8]
SA_DQS#[7:0]
SA_DQ[71:64]
SA_DQ[63:0]
SA_MA[15:0]
SA_CK[1:0]
SA_CK#[1:0]
SA_CKE[1:0]
SA_CS#[1:0]
SA_ODT[1:0] O n Die Termination: Active Termination Control.
RAS Control Signal: Used with SA_CAS# and
SA_WE# (along with SA_CS#) to define the SRAM
Commands.
CAS Control Signal: Used with SA_RAS# and
SA_WE# (along with SA_CS#) to define the SRAM
Commands.
Data Mask: These signals ar e used to mask
individual bytes of data in the case of a partial
write and to interrupt burst writes. When activated
during writes, the corresponding data groups in
the SDRAM are masked. There is one SA_DM[7:0]
for every data byte lane.
ECC Data Strobe: SA_DQS[8] is the data strobe
for the ECC check data bits SA_DQ[71:64]
Note: Not required for non-ECC mode
Data Strobes: SA_DQS[7:0] and its complement
signal group make up a differential strobe pair . The
data is captured at the crossing point of
SA_DQS[7:0] and its SA_DQS#[7:0] during read
and write transactions
ECC Data Strobe Complement: SA_DQS#[8] is
the complement strobe for the ECC check data bits
SA_DQ[71:64]
Note: Not required for non-ECC mode
Data Strobe Complements: These are the
complementary str obe signals .
ECC Check Data Bits: SA_DQ[71:64] are the ECC
check data bits for Channel A.
Note: Not required for non-ECC mode
Data Bus: Channel A data signal interface to the
SDRAM data bus.
Memory Address: These signals are used to
provide the multiplexed row and column address
to the SDRAM.
SDRAM Differential Clock: Channel A SDRAM
Differential clock signal pair. The crossing of the
positive edge of SA_CK and the negative edge of
its complement SA_CK# are used to sample the
command and control signals on the SDRAM.
SDRAM Inverted Differential Clock: Channel A
SDRAM Differential clock signal-pair complement.
Clock Enable: (1 per rank) Used to:
- Initialize the SDRAMs during power-up
- Power-down SD RAM ranks
- Place all SDRAM ranks into a nd out of se lf-refresh
during STR
Chip Select: (1 per rank) Used to select particular
SDRAM components during the active state. There
is one Chip Select for each SDRAM rank.
Direction/Buffer
Type
O
DDR3
O
DDR3
O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
®
Intel
Datashe et A dd en d um April 2010
22 Document Numbe r: 32 31 78-002
TM
Core
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Signal Description
Table 8. Memory Channel B (Sheet 1 of 2)
Signal N ame Descr iption
SB_BS[2:0]
SB_WE#
SB_RAS#
SB_CAS#
SB_DM[7:0]
SB_DQS[8]
SB_DQS[7:0]
SB_DQS#[8]
SB_DQS#[7:0]
SB_DQ[71:64]
SB_DQ[63:0]
SB_MA[15:0]
SB_CK[1:0]
SB_CK#[1:0]
SB_CKE[1:0]
SB_CS#[1:0]
Bank Select: These signals define which banks
are se lected withi n each SDRAM rank.
Write Enable Control Signal: Used with
SB_RAS# and SB_CAS# (along with SB_CS#) to
define the SDRAM Commands.
RAS Control Signal: Used with SB_CAS# and
SB_WE# (along with SB_CS#) to define the SRAM
Commands.
CAS Control Signal: Used with SB_RAS# and
SB_WE# (along with SB_CS#) to define the SRAM
Commands.
Data Mask: These signals are used to mask
individual bytes of data in the case of a partial
write, and to interrupt burst writes. When
activa ted during writes, the corr esponding d at a
groups in the SDRAM are masked. There is one
SB_DM[7:0] for every data byte lane.
ECC Data Strobe: SB_DQS[8] is the data strobe
for the ECC check data bits SB_DQ[71:64]
Note: Not required for non-ECC mode
Data Strobes: SB_DQS[7:0] and its complement
signal group make up a differential strobe pair. The
data is captured at the crossing point of
SB_DQS[7:0] and its SB_DQS#[7:0] during read
and write transactions.
ECC Data Strobe Complement: SB_DQS#[8] is
the complement strobe for the ECC check data bits
SB_DQ[71:64]
Note: Not required for non-ECC mode
Data Strobe Complements: These are th e
complementary strobe signals.
ECC Check Data Bits: SB_DQ[71: 64] are the ECC
check data bits for Channel B
Note: Not required for non-ECC mode
Data Bus: Channel B data signal interface to the
SDRAM data bus.
Memory Address: These signals are used to
provide the multiplexed row and column address
to the SDRAM.
SDRAM Differential Clock: Channel B SDRAM
Differential clock signal pair. The crossing of the
positive edge of SB_CK and the negative edge of
its complement SB_CK# are used to sample the
command and control signals on the SDRAM.
SDRAM Inverted Differential Clock: Channel B
SDRAM Differential clock signal-pair complement.
Clock Enable: (1 per rank) Used to:
- Initialize the SDRAMs during power-up.
- Power-down SDRAM ranks.
- Place all SDRAM ranks into and out of self -refresh
during STR.
Chip Select: (1 per rank) Used to select particular
SDRAM components during the active state. There
is one Chip Select for each SDRAM rank.
Direction/Buffer
Type
O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
I/O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
April 2010 Datasheet Addendum
Document Number: 32 31 78 - 00 2 23
Intel® Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Table 8. Memory Channel B (Sheet 2 of 2)
Signal Description
Signal Name Description
SB_ODT[1:0] On Die Termination: Active T erm ination Control.
3.2 Reset and Miscellaneous Signals
Table 9. Reset and Misce l laneous Signals
Signal N ame Desc ription
SM_DRAMRST#
CFG[17:0]
DDR3 DRAM Reset: Reset signal from processor
to DRAM devices. One for all channels of DIMMs.
Configuration signals:
The CFG signals have a default value of 1 if not
terminated on the board. Refer to the Platfo rm
Design Guide for pull-down recommendations
when logic low is desired.
• CFG[0]: PCI Express* Bifurcation:
—1 = 1 x16 PCI Express I/O
— 0 = 2 x 8 PCI Express I/O
• CFG[1]: Rese rve d
• CFG[2]: Reserved configuration lands. A test
point may be placed on the board for this land.
• CFG[3]: PCI Express* Static Lane Numbering
Reversal. A test point may be placed on the
board for this land. Lane reversal will be
applied across all 16 lanes.
—1: No Reversal
—0: Reversal
In the case of Bifurcation with NO Lane Reversal
the physical lane mapping is as follows:
— Lanes 15:8 => Port 1 Lanes 7:0
— Lanes 7: 0 => Po rt 0 Lanes 7:0
In the case of Bifurcation with WITH Lane Reversal
the physical lane mapping is as follows:
— Lanes 15:8 => Port 0 Lanes 0:7
— Lanes 7: 0 => Po rt 1 Lanes 0:7
• CFG[4]: Embedded DisplayPort Detection:
This is used to detect the presence of a device
on the Embedded DisplayPort.
— 1: No Physical Display Port attached to
the Embedded Display Port
— 0: An external Display Port device is
connected to the Embedded Display Port
• CFG[17:5]: Reserved configuration lands.
Intel does not recommend a test point on the
board for these lands.
Direction/Buffer
Type
O
DDR3
Direction/Buffer
Type
O
DDR3
I
CMOS
§ §
®
Intel
Datashe et A dd en d um April 2010
24 Document Numbe r: 32 31 78-002
TM
Core
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Electrical Specifications
4 Electrical Specifications
4.1 Signal Groups
Signals are grouped by buffer type and similar characteristics as listed in Table 10. The
buffer type indicates which signaling technology and specifications apply to the signals.
All the differential signals, and selected DDR3 and Control Sideband signals have OnDie Termination (ODT) resistors. There are some signals that do not have ODT and
need to be terminated on the board.
Table 10. Mobile Signal Groups
Signal Group
DDR3 Data Signals
Single ended (e) DDR3 Bi-directional SA_DQ[71:0], SB_DQ[71:0]
Differential (f) DDR3 Bi-directional
Power/Ground/Other
Single Ended (z) Other DBR#, PROC_DETECT, VCAP0, VCAP1, VCAP2
1
Alpha
Group
2
NOTES:
1. Refer to Chapter 3 for signal description details.
2. SA and SB refer to DDR3 Channel A and DDR3 Channel B.
All Control Sideband Asynchronous signals are required to be asserted/deasserted for
at least eight BCLKs in order for the processor to recognize the proper signal state. See
Section 4.2 for the DC specif icat io ns.
4.2 DC Specifications
The processor DC specifications in this section are defined at the processor
pins, unless noted otherwise. See Chapter 5 for the processor pin listings and
Chapter 3 for signal definitions.
The DC specifications for the DDR3 signals are listed in Table 11.
Type Signals
SA_DQS[8:0], SA_DQS#[8:0]
SB_DQS[8:0], SB_DQS#[8:0]
4.2.1 Voltage and Current Specifications
Table 11. DDR3 Signal Group DC Specifications (Sheet 1 of 2)
Symbol Parameter
V
IL
Input L o w Voltage (e,f) 0.43*V
Alpha
Group
Min Typ Max Units Notes
DDQ
V2,4
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
3. V
4. V
5. R
April 2010 Datasheet Addendum
Document Number: 32 31 78 - 00 2 25
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
IL
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
IH
and VOH may experience exc u rsio ns abo ve V
IH
specifications.
is the termination on the DIMM and in not controlled by the processor.
VTT_TERM
Intel® Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
. However, input signal drivers must comply with the signal quality
DDQ
1,9
Table 11. DDR3 Signal Group DC Specifications (Sheet 2 of 2)
Electrical Specifications
Symbol Parameter
V
IH
V
OL
V
OH
Input Hi gh Voltage (e, f) 0.57*V
Output Low Volt age (c,d,e,f)
Output High Voltage (c,d,e,f)
Alpha
Group
Min Typ Max Units Notes
DDQ
/ 2)* (R
(V
DDQ
(R
ON+RVTT_TERM
- ((V
V
DDQ
(R
(R
ON+RVTT_TERM
ON
DDQ
/
/
ON
))
/ 2)*
))
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
3. V
4. V
5. R
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
IL
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
IH
and VOH may experience exc ursions abo ve V
IH
specifications.
is the termination on the DIMM and in not controlled by the processor.
VTT_TERM
. However, input signal drivers must comply with the signal quality
DDQ
1,9
V3
5
V4,5
®
Intel
Datashe et A dd en d um April 2010
TM
Core
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
26 Document Numbe r: 32 31 78-002
Process or Ball and Signal Information
5 Processor Ball and Signal
Information
5.1 Processor Ball Assignments
• Table 12 provides a listing of all processor pins ordered alphabetically by ball name
for the Intel
P4500, P4505 Series package respectively.
• Table 13 provides a listing of all processor pins ordered alphabetically by ball
number for the Intel® Core
Processor P4500, P4505 Series package respectively.
• Figure 5, Figure 6, Figure 7, and Figure 8 show the Top-Down view of the Intel
TM
Core
P4505 Series ballmap
®
TM
Core
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500,
i7-620LE/UE, i7-610E , i5-52 0E and Int el® Celeron® Process or
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron®
®
April 2010 Datasheet Addendum
Document Number: 32 31 78 - 00 2 27
Intel® Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series
Processor Ball and Signal Information
Figure 5. Intel® Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series Ballmap
(Top View, U pper-Left Quadrant)
71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36
DC_TES
BV
T_BV71
BU
DC_TES
BT
T_BT71
DC_TES
BR
T_BR71
BP
VSS
BN
BM
VSS
BL
BK
SB_DQ[5
BJ
6]
BH
SB_DQ[5
BG
8]
BF
RSVD VSS RSVD VSS
BE
SB_DQ[6
BD
2]
BC
VSS RSVD
BB
BA
VSS RSVD VSS
AY
AW
RSVD RSVD
AV
RSVD VSS RSVD VSS VT T0 VT T0 VSS VCAP0 VSS VC AP0 VSS VC AP0 VSS VCAP1 VSS VCAP1 VSS VCAP 1
AU
AT
RSVD RSVD VS S VTT 0 VTT 0 VS S VC AP0 VSS VCAP0 VSS VCAP0 VSS VCAP 1 VS S VC AP1 VSS VCAP1
AR
AP
GFX_ VID
AN
[4]
AM
GFX_DP
AL
RSLPVR
RSVD VSS RSVD RSVD VSS VCAP 2 VCAP2 VCAP2 VCAP0 VS S VC AP0 VSS VCAP0 VSS VCAP1 VSS VC AP1 VSS VC AP1 VSS
AK
AJ
GFX_ VID
AH
[3]
AG
GFX_ VID
AF
[0]
AE
COMP3 COMP1 VSS VCAP2 VCAP2 VSS VCC VSS VCC VSS VC C VSS VCC VSS VCC VT T0 VT T0
AD
RSVD COMP2 RSVD VSS VSS
AC
DC_TES
DC_TES
T_BV69
T_BV68
DC_TES
VSS
T_BT69
VSS VSS
SB_DQ[5
VSS
SB_DQ[6
0]
VSS
SB_DQ[5
7]
SA_DQ[6
3]
VSS
RSVD VSS VS S VT T0 VSS VCAP 0 VS S VC AP0 VSS VCAP0 VSS VCAP1 VSS VC AP1 VSS VC AP1 VSS
RSVD RSVD VSS
VSS RSVD VSS
GFX_ VID
[6]
VSS
GFX_ VID
[2]
VSS COMP0 VSS
4]
SB_DQ[5
5]
SB_DQS
[7]
SB_DQS
#[7]
SB_DQ[6
3]
RSVD VSS VT T0 VT T0 VCAP0 VSS VCAP 0 VS S VC AP0 VSS VCAP1 VSS VCAP 1 VS S VC AP1 VSS
GFX_IM
ON
GFX_ VR
_EN
VSS VSS VCAP2 VCAP2 VCC VCC VCC VC C VCC VC C VCC VC C VCC VCC VTT 0 VTT 0
VSS VSS
SB_DM[6
]
SB_DQ[5
0]
SB_DQ[6
1]
SA_DQ[6
0]
SB_DM[7
]
SB_DQ[5
9]
SA_DQ[5
9]
PM_EXT
_TS#[0]
GFX_ VID
RSVD VSS
[5]
RSVD VSS VCAP2 VCAP2 VSS VSS VS S VS S VS S VS S VS S VS S VS S VSS VS S VS S
GFX_ VID
[1]
SB_DQ[5
1]
SA_DQ[5
VSS
0]
SA_DQ[5
4]
VSS
SA_DQ[61]SA_DQ[5
7]
SA_DQS[
7]
SA_DQ[5
8]
SA_DQ[6
2]
PM_EXT
_TS#[1]
VSS
SB_DQS
SB_DQ[4
[6]
SB_DQS
#[6]
VSS
SA_DQ[5
6]
8]
VSS
SB_DQ[5
3]
SB_DQ[5
2]
SA_DM[6
]
SA_DQ[5
5]
SA_DQ[5
1]
VSS VTT0 VTT0
SA_DQS
#[7]
VSS VT T0 VT T0 VSS VCAP0 VSS VC AP0 VSS VC AP0 VSS VCAP1 VSS VCAP1 VSS VCAP 1
VSS VT T0 VSS VCAP0 VSS VCAP 0 VS S VC AP0 VSS VCAP1 VSS VCAP 1 VS S VC AP1 VSS
VSS VT T0 VT T0 VCAP0 VSS VCAP 0 VS S VC AP0 VSS VCAP1 VSS VCAP 1 VS S VC AP1 VSS
SB_DQ[4
7]
SB_DQ[4
6]
SB_DQ[4
2]
SB_DQ[4
9]
SA_DQS[
6]
VSS VSS
SA_DM[7
VTT 0 VTT 0 VSS VCAP 0 VS S VC AP0 VSS VCAP0 VSS VCAP1 VSS VCAP 1 VS S VC AP1
SB_DM[5
]
VSS
SB_DQ[4
3]
SA_DQS
#[6]
SA_DQ[4
9]
VSS VSS VSS
SA_DQ[5
3]
]
VSS VSS
SA_DQ[5
2]
SB_DQS
[5]
SB_DQ[4
5]
SB_DQS
SB_DQ[3
#[5]
9]
VSS
SB_DQ[44]SB_DQ[3
8]
SA_DQ[4
7]
SA_DQ[4
3]
SA_DQ[4
8]
SB_DQ[4
1]
SB_DQ[4
0]
SA_DQ[4
6]
SA_DQ[4
2]
SA_DM[5
]
SB_DQ[3
7]
SB_DQS
[4]
SB_DQ[3
4]
VSS
SB_DQS
#[4]
SA_DQ[4
1]
VSS VSS
SA_DQS
#[5]
SA_DQS[
5]
VSS
SB_ODT
[1]
SB_DQ[3
5]
SB_DQ[33]SB_DM[4
]
VSS
SB_DQ[32]SB_DQ[3
6]
SA_DQ[40]SA_DQ[3
9]
SA_ODT[
1]
SA_DQ[45]SA_CS#[
1]
SA_DQ[4
VSS
4]
SA_DQ[35]SA_DQ[3
4]
SB_CAS
#
SB_CS#[
0]
SB_ODT
[0]
SB_MA[1
3]
SB_BS[1
]
VSS
SB_CS#[
1]
SA_DQ[3
8]
SA_DQ[3
3]
SA_DQS[4]SA_CAS
#
SA_DQS
SA_DQ[3
#[4]
7]
SA_DM[4]SA_DQ[7
0]
SA_ODT[
0]
SB_MA[1
0]
VSS
SB_BS[0]SM_RCO
MP[2]
SA_DQ[66]SB_CK#[
SB_RAS
SB_WE#
#
SA_DQ[3
6]
VSS
SA_DQ[3
2]
SA_CS#[
0]
SA_MA[1
3]
1]
SM_RCO
MP[1]
SB_CK[1
]
SA_BS[0]
SB_DQ[6
8]
SA_RAS
#
SA_DQ[7
1]
SA_BS[1]
SA_WE#
SA_MA[2
]
VSS
SA_MA[0
]
SA_CK#[
1]
SA_CK[1
]
VSS
323178-002 28
Processor Ball and Signal Information
VCCPW
SM_DRA
Figure 6. Intel® Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series Ballmap
(Top View, Upper-Right Qu adrant)
3534333231302928272625242322212019181716151413121110987654321
SB_CK#[0]SM_RCO
SA_DQ[6
7]
SA_CK#[
0]
VDDQ
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VSS VSS VSS VSS VSS VS S VS S VS S VSS VSS VS S VSS VSS VSS VT T0 VS S
VTT0 VTT0
VSS VSS VSS VSS VSS VS S VS S VS S VSS VSS VS S VSS VSS VT T0 VSS RSVD
VSS VSS VSS VSS VSS VS S VS S VS S VSS VSS VS S VSS VSS VT T0 VSS VSS
VTT 0 VTT 0 VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VTT 0 VTT 0 VTT 0 VTT 0 VTT 0
VSS VSS VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VTT 0 VTT 0 VTT 0 VTT 0 CFG[0] VSS
VTT 0 VT T0 VS S VS S VSS VS S VS S VSS VS S VS S VSS VS S VAXG VAXG BC LK # BC LK CFG[4] CFG[3] CFG[2]
VSS VSS VSS VSS VSS VS S VS S VS S VSS VSS VS S VSS VAXG VAXG VSS CFG[10]
VTT 0 VTT 0 VTT 0 VTT 0 VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG
VTT 0 VTT 0 VTT 0 VTT 0 VAXG VAXG VAXG VAXG VAXG VAXG VAXG VTT1 VTT1 VTT1 VSS CFG[14]
MP[0]
SB_CK[0
]
SB_MA[0]SB_MA[5
]
SA_MA[1
]
SA_CK[0
]
VSS
SA_MA[1
0]
SA_MA[3
]
SA_DQS[8]SA_DQS
VSS
SA_MA[5
]
VSS
SA_MA[6
]
SB_DQ[6
6]
SA_MA[4
]
#[8]
VTT0_D
DR
SB_MA[4
]
SB_MA[6
]
SB_MA[3
]
SB_MA[1
]
SA_MA[8
]
SB_DQ[7
0]
SA_MA[7
]
SA_MA[1
1]
VSS
SA_DQ[6
4]
VTT0_D
DR
SB_MA[2
]
SB_MA[1
2]
SB_DQ[7
1]
SA_MA[1
4]
VSS
SA_MA[1
2]
SA_DQ[6
9]
SA_MA[9
]
SA_DQ[6
5]
VTT0_D
DR
SB_MA[8]SB_MA[1
4]
SB_MA[1
1]
SB_MA[9]SB_CKE[
0]
SB_MA[7
]
SA_DQ[6
8]
VTT0_D
DR
SB_BS[2
]
VSS
SB_CKE[
1]
SA_MA[15]SA_DM[3
]
SB_DQ[6
VSS VSS
7]
SA_DQ[26]SA_CKE[
1]
SA_DQ[2
VSS
7]
SA_DQ[31]SA_DQ[3
0]
SB_DQ[65]SB_DQ[6
VTT0_DDRVTT0_D
SB_MA[1
5]
9]
DR
SB_DQ[2
6]
SB_DQ[2
7]
SB_DM[3
]
SB_DQ[30]SB_DQ[2
VSS
SB_DQ[31]SB_DQS
SA_DQS[3]SA_DQ[2
4]
SA_DQS
VSS
#[3]
SA_DQ[2
VSS
8]
SA_DQ[2
VSS
9]
SA_CKE[
SA_BS[2]
0]
SB_DQ[6
4]
VTT0_D
DR
9]
SB_DQ[2
5]
#[3]
SB_DQ[2
8]
SB_DQS
[8]
VTT0_D
DR
VSS
SB_DQ[2
2]
SB_DQ[2
3]
SB_DQS
[3]
SA_DQ[1
6]
SA_DQ[2
3]
SA_DQ[1
8]
SA_DQ[1
9]
VDDQ VDDQ VSS
SB_DQS
#[8]
VTT0_D
DR
SB_DQ[1
9]
SB_DQ[1
8]
SB_DQ[2
4]
SA_DM[2
]
SA_DQ[2
2]
VSS
SA_DQ[2
5]
VDDQ VSS
VTT0_D
DR
SB_DQS
[2]
VSS
SB_DM[2]SB_DQ[1
SA_DQS
#[2]
SA_DQS[
2]
SA_DQ[1
1]
VDDQ_C
K
VTT0 VTT0
SB_DQ[2
0]
SB_DQS
#[2]
7]
SB_DQ[2
1]
SM_DRA
MRST#
VDDQ_C
K
VAXG_S
ENSE
SB_DQ[1
5]
VSS
SB_DQ[1
6]
SA_DQ[2
0]
VSS
SA_DQ[1
0]
SA_DQ[9
]
SA_DQ[8
]
SA_DM[0]SA_DQ[3
VSS
VTT0 VSS
VAXG CFG[5]
VSSAXG
_SENSE
RSVD_N
CTF
SB_DQ[1
4]
SB_DQ[1
1]
SA_DQ[17]SA_DQ[1
5]
SA_DQ[2
1]
VSS
SA_DQ[1
VSS
2]
SA_DQ[7
VSS
]
]
VSS
SA_DQ[0
]
VSS CFG[7] VSS CFG[9]
CFG[15] CFG[16] CFG[8] VSS
FDI_FSY FDI_FSY
RSVD_N
CTF
VSS
SB_DQ[10]RSVD_N
VSS
SA_DQ[1
4]
SA_DQS
#[1]
SA_DQ[1
3]
SA_DQ[6
]
VSS
SA_DQS[
0]
SA_DQ[4]SA_DQ[5
]
SA_DQ[1
]
RSVD_T
P
RGOOD
DC_TES
T_BV5
RSVD_N
CTF
CTF
SB_DQS
SB_DM[1
SA_DM[1
]
SA_DQS[1]SB_DQ[1
SB_DQ[8
SB_DQ[3
SB_DQS
SA_DQ[2]SB_DM[0
SA_DQS
#[0]
VSS VSS
MPWRO
DC_TES
T_BV3
DC_TES
T_BT3
VSS
#[1]
SB_DQS
[1]
]
2]
]
]
[0]
]
VSS
RSVD VSS
SB_DQ[1
3]
SB_DQ[7
]
SB_DQ[6
]
SB_DQS
#[0]
SB_DQ[5
]
SB_DQ[0
]
SB_DQ[1
]
CFG[6]
RSVD_T
P
CFG[1]
CFG[13]
DC_TES
T_BV1
DC_TES
T_BT1
DC_TES
T_BR1
SB_DQ[9
SB_DQ[2
SB_DQ[4
RSVD_T
VTT_SE
LECT
VSS
VSS
VSS
VSS
VSS
BV
BU
BT
BR
BP
BN
BM
BL
BK
BJ
BH
BG
]
BF
BE
BD
]
BC
BB
BA
AY
]
AW
AV
AU
P
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
29
323178-002
Processor Ball and Signal Information
VCCPW
PROC_D
P
Figure 7. Intel® Core
TM
i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series Ballmap
(Top View, Lower-Left Quadrant)
COMP3 COMP1 VSS VCAP2 VCAP2 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VTT0 VTT0
AD
RSVD COMP2 RSVD VSS VSS
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
VSS VSS VCAP2 VCAP2 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS
RSVD RSVD VSS VSS VSS VCAP2 VCAP2 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS
TAPPWR
GOOD
DBR# VSS RSVD RSVD VSS VCAP2 VCAP2 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCCPLL VCCPLL
VSS
PRDY# PREQ# VSS VSS VCAP2 VCAP2 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCCPLL
TDO TDO_M TDI TCK
VSS RSVD RSVD VSS VCAP2 VCAP2 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCCPLL VCCPLL
TDI_M TRST# VCC
RESET_
OBS#
PROC_D
ETECT
BCLK_IT
P
VSS VCC VSS VCC VCC VSS VSS
VSS PSI#
DC_TES
T_E71
DC_TES
T_C71
DC_TES
T_A71
BPM#[7] VCC VSS VCC VCC VSS VSS
VSS VSS VCC VSS VSS
BPM#[6] BPM#[3] VSS BPM#[4] VCC VSS VCC VCC VSS VSS
BCLK_IT
BPM#[0] BPM#[1] VSS BPM#[5] BPM#[2] VSS VCC VSS VSS VSS
P #
VSS VCC VSS VCC VSS VCC VSS VSS VCC VSS
VSS VSS VCC VCC VCC VCC VCC VCC VSS
DC_TES
T_C69
DC_TES
T_A69
VSS
DC_TES
T_A68
RGOOD
PROCH
OT#
TMS VSS
VCC_SE
PRSLPV
VID[6] VID[5] VID[2] VID[1] VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS
VSS VID[4] VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS
VSS VSS VID[3] VID[0] VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC ISENSE VSS
NSE
VSS_SE
NSE
CATERR
#
VSS VCC VSS VSS
VSS VCC VSS VCC VSS VCC VSS VCC VCC
PEG_TX
#[0]
PEG_TX[
0]
PEG_RX
#[0]
PEG_RX[
0]
PEG_TX
#[3]
PEG_TX[
71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36
PEG_TX[
1]
PEG_TX
#[1]
PEG_RX[
1]
PEG_RX
#[1]
PEG_TX[
4]
PEG_TX[
7]
VSS
VSS
3]
PEG_TX
#[4]
323178-002 30
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