Intel i5-4570TE User Manual

Mobile 4th Generation Intel® Core

™

Processor Family, Mobile Intel

Pentium® Processor Family, and Mobile Intel® Celeron® Processor Family

Datasheet – Volume 1 of 2

Supporting 4th Generation Intel® Core™ processor based on Mobile M-Processor and H-Processor Lines

Supporting Mobile Intel® Pentium® Processor and Mobile Intel Celeron® Processor Families

July 2014

Order No.: 328901-007

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™

Mobile 4th Generation Intel

Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron

Processor Family Datasheet – Volume 1 of 2 July 2014 2 Order No.: 328901-007

Contents—Processor

Revision History..................................................................................................................9

1.0 Introduction................................................................................................................10

1.1 Supported Technologies.........................................................................................11

1.2 Interfaces............................................................................................................ 12

1.3 Power Management Support...................................................................................12

1.4 Thermal Management Support................................................................................13

1.5 Package Support...................................................................................................13

1.6 Processor Testability............................................................................................. 13

1.7 Terminology.........................................................................................................13

1.8 Related Documents............................................................................................... 17

2.0 Interfaces................................................................................................................... 18

2.1 System Memory Interface...................................................................................... 18

2.1.1 System Memory Technology Supported.......................................................18

2.1.2 System Memory Timing Support................................................................. 19

2.1.3 System Memory Organization Modes........................................................... 20

2.1.4 System Memory Frequency........................................................................ 21

2.1.5 Intel® Fast Memory Access (Intel® FMA) Technology Enhancements............... 21

2.1.6 Data Scrambling...................................................................................... 22

2.1.7 DRAM Clock Generation............................................................................. 22

2.1.8 DRAM Reference Voltage Generation........................................................... 22

2.2 PCI Express* Interface.......................................................................................... 23

2.2.1 PCI Express* Support................................................................................23

2.2.2 PCI Express* Architecture.......................................................................... 24

2.2.3 PCI Express* Configuration Mechanism........................................................ 24

2.3 Direct Media Interface (DMI).................................................................................. 26

2.4 Processor Graphics................................................................................................28

2.5 Processor Graphics Controller (GT)..........................................................................28

2.5.1 3D and Video Engines for Graphics Processing.............................................. 29

2.5.2 Multi Graphics Controllers Multi-Monitor Support........................................... 31

2.6 Digital Display Interface (DDI)................................................................................31

2.7 Intel® Flexible Display Interface (Intel® FDI)............................................................37

2.8 Platform Environmental Control Interface (PECI)....................................................... 38

2.8.1 PECI Bus Architecture................................................................................38

3.0 Technologies...............................................................................................................40

3.1 Intel® Virtualization Technology (Intel® VT)............................................................. 40

3.2 Intel® Trusted Execution Technology (Intel® TXT).....................................................44

3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)....................................... 45

3.4 Intel® Turbo Boost Technology 2.0..........................................................................46

3.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)................................................47

3.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI).......................47

3.7 Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI)..... 48

3.8 Intel® 64 Architecture x2APIC................................................................................ 48

3.9 Power Aware Interrupt Routing (PAIR)....................................................................49

3.10 Execute Disable Bit..............................................................................................49

3.11 Supervisor Mode Execution Protection (SMEP)........................................................50

Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron

Processor Family July 2014 Datasheet – Volume 1 of 2 Order No.: 328901-007 3

Processor—Contents

4.0 Power Management.................................................................................................... 51

4.1 Advanced Configuration and Power Interface (ACPI) States Supported......................... 52

4.2 Processor Core Power Management......................................................................... 53

4.2.1 Enhanced Intel® SpeedStep® Technology Key Features..................................53

4.2.2 Low-Power Idle States............................................................................... 54

4.2.3 Requesting Low-Power Idle States...............................................................55

4.2.4 Core C-State Rules....................................................................................56

4.2.5 Package C-States......................................................................................57

4.2.6 Package C-States and Display Resolutions....................................................61

4.3 Integrated Memory Controller (IMC) Power Management............................................63

4.3.1 Disabling Unused System Memory Outputs...................................................63

4.3.2 DRAM Power Management and Initialization..................................................63

4.3.3 DRAM Running Average Power Limitation (RAPL) .........................................66

4.3.4 DDR Electrical Power Gating (EPG).............................................................. 66

4.4 PCI Express* Power Management............................................................................66

4.5 Direct Media Interface (DMI) Power Management...................................................... 66

4.6 Graphics Power Management..................................................................................66

4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM)................................66

4.6.2 Graphics Render C-State............................................................................67

4.6.3 Intel® Smart 2D Display Technology (Intel® S2DDT)..................................... 67

4.6.4 Intel® Graphics Dynamic Frequency............................................................ 67

4.6.5 Intel® Display Power Saving Technology (Intel® DPST)................................. 67

4.6.6 Intel® Automatic Display Brightness ........................................................... 68

4.6.7 Intel® Seamless Display Refresh Rate Technology (Intel® SDRRS

Technology)............................................................................................ 68

5.0 Thermal Management................................................................................................. 69

5.1 Thermal Considerations......................................................................................... 69

5.2 Intel® Turbo Boost Technology 2.0 Power Monitoring.................................................70

5.3 Intel® Turbo Boost Technology 2.0 Power Control..................................................... 70

5.3.1 Package Power Control.............................................................................. 70

5.3.2 Turbo Time Parameter............................................................................... 71

5.4 Configurable TDP (cTDP) and Low-Power Mode......................................................... 71

5.4.1 Configurable TDP...................................................................................... 71

5.4.2 Low-Power Mode.......................................................................................72

5.5 Thermal and Power Specifications........................................................................... 72

5.6 Thermal Management Features...............................................................................76

5.6.1 Adaptive Thermal Monitor.......................................................................... 76

5.6.2 Digital Thermal Sensor.............................................................................. 78

5.6.3 PROCHOT# Signal.....................................................................................79

5.6.4 On-Demand Mode..................................................................................... 81

5.6.5 Intel® Memory Thermal Management.......................................................... 81

6.0 Signal Description....................................................................................................... 83

6.1 System Memory Interface Signals........................................................................... 84

6.2 Memory Reference Compensation Signals.................................................................86

6.3 Reset and Miscellaneous Signals............................................................................. 86

6.4 PCI Express* Interface Signals............................................................................... 87

6.5 embedded DisplayPort* (eDP*) Signals....................................................................87

6.6 Display Interface Signals....................................................................................... 88

6.7 Direct Media Interface (DMI).................................................................................. 88

Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron Processor Family Datasheet – Volume 1 of 2 July 2014 4 Order No.: 328901-007

Contents—Processor

6.8 Phase Locked Loop (PLL) Signals.............................................................................88

6.9 Testability Signals.................................................................................................89

6.10 Error and Thermal Protection Signals..................................................................... 90

6.11 Power Sequencing Signals.................................................................................... 90

6.12 Processor Power Signals.......................................................................................91

6.13 Sense Signals..................................................................................................... 91

6.14 Ground and Non-Critical to Function (NCTF) Signals.................................................91

6.15 Processor Internal Pull-Up / Pull-Down Terminations................................................ 92

7.0 Electrical Specifications.............................................................................................. 93

7.1 Integrated Voltage Regulator..................................................................................93

7.2 Power and Ground Pins..........................................................................................93

7.3 VCC Voltage Identification (VID).............................................................................. 93

7.4 Reserved or Unused Signals................................................................................... 98

7.5 Signal Groups.......................................................................................................98

7.6 Test Access Port (TAP) Connection........................................................................ 100

7.7 DC Specifications............................................................................................... 100

7.8 Voltage and Current Specifications........................................................................ 101

7.8.1 Platform Environment Control Interface (PECI) DC Characteristics................. 106

7.8.2 Input Device Hysteresis........................................................................... 107

8.0 Package Specifications..............................................................................................108

8.1 Package Mechanical Specifications.........................................................................108

8.1.1 Processor Mass....................................................................................... 110

8.2 Package Loading Specifications............................................................................. 110

8.3 Package Storage Specifications............................................................................. 111

9.0 Processor Pin and Signal Information....................................................................... 112

10.0 DDR Data Swizzling.................................................................................................135

Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron

Processor Family July 2014 Datasheet – Volume 1 of 2 Order No.: 328901-007 5

Processor—Figures

Figures

1 Platform Block Diagram............................................................................................ 11

2 Intel® Flex Memory Technology Operations................................................................. 21

3 PCI Express* Related Register Structures in the Processor............................................ 25

4 PCI Express* Typical Operation 16 Lanes Mapping....................................................... 26

5 Processor Graphics Controller Unit Block Diagram........................................................ 29

6 Processor Display Architecture...................................................................................33

7 DisplayPort* Overview............................................................................................. 34

8 HDMI* Overview..................................................................................................... 35

9 PECI Host-Clients Connection Example....................................................................... 39

10 Device to Domain Mapping Structures........................................................................ 43

11 Processor Power States............................................................................................ 51

12 Idle Power Management Breakdown of the Processor Cores ..........................................54

13 Thread and Core C-State Entry and Exit......................................................................55

14 Package C-State Entry and Exit................................................................................. 59

15 Package Power Control............................................................................................. 71

16 Input Device Hysteresis.......................................................................................... 107

17 BGA Package.........................................................................................................109

18 rPGA Package........................................................................................................109

19 rPGA946B/947 Socket............................................................................................ 110

Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron Processor Family Datasheet – Volume 1 of 2 July 2014 6 Order No.: 328901-007

Tables—Processor

Tables

1 Terminology........................................................................................................... 13

2 Related Documents..................................................................................................17

3 Processor DIMM Support Summary by Product............................................................ 18

4 Supported SO-DIMM Module Configurations ............................................................... 19

5 Supported Maximum Memory Size Per DIMM...............................................................19

6 DDR3L / DDR3L-RS System Memory Timing Support.................................................... 20

7 PCI Express* Supported Configurations in Mobile Products............................................ 23

8 Processor Supported Audio Formats over HDMI*and DisplayPort*.................................. 36

9 Valid Three Display Configurations through the Processor..............................................36

10 DisplayPort and embedded DisplayPort* Resolutions for 1, 2, 4 Lanes – Link Data

Rate of RBR, HBR, and HBR2.....................................................................................37

11 System States.........................................................................................................52

12 Processor Core / Package State Support..................................................................... 52

13 Integrated Memory Controller States..........................................................................52

14 PCI Express* Link States.......................................................................................... 52

15 Direct Media Interface (DMI) States........................................................................... 53

16 G, S, and C Interface State Combinations .................................................................. 53

17 D, S, and C Interface State Combination.....................................................................53

18 Coordination of Thread Power States at the Core Level................................................. 55

19 Coordination of Core Power States at the Package Level............................................... 58

20 Deepest Package C-State Available – M-Processor Line................................................. 61

21 Targeted Memory State Conditions............................................................................ 65

22 Intel® Turbo Boost Technology 2.0 Package Power Control Settings............................... 70

23 Configurable TDP Modes........................................................................................... 72

24 Thermal Design Power (TDP) Specifications.................................................................73

25 Junction Temperature Specification............................................................................ 74

26 Idle Power Specifications.......................................................................................... 75

27 Signal Description Buffer Types................................................................................. 83

28 Memory Channel A Signals........................................................................................84

29 Memory Channel B Signals........................................................................................85

30 Memory Reference and Compensation Signals............................................................. 86

31 Reset and Miscellaneous Signals................................................................................ 86

32 PCI Express* Graphics Interface Signals..................................................................... 87

33 embedded Display Port* Signals................................................................................ 87

34 Display Interface Signals.......................................................................................... 88

35 Direct Media Interface (DMI) – Processor to PCH Serial Interface................................... 88

36 Phase Locked Loop (PLL) Signals............................................................................... 88

37 Testability Signals....................................................................................................89

38 Error and Thermal Protection Signals..........................................................................90

39 Power Sequencing Signals........................................................................................ 90

40 Processor Power Signals........................................................................................... 91

41 Sense Signals......................................................................................................... 91

42 Ground and Non-Critical to Function (NCTF) Signals..................................................... 91

43 Processor Internal Pull-Up / Pull-Down Terminations.................................................... 92

44 Voltage Regulator (VR) 12.5 Voltage Identification....................................................... 94

45 Signal Groups......................................................................................................... 98

46 Processor Core (VCC) Active and Idle Mode DC Voltage and Current Specifications.......... 101

47 Memory Controller (V

48 VCCIO_OUT, VCOMP_OUT, and VCCIO_TERM ........................................................... 102

49 DDR3L / DDR3L-RS Signal Group DC Specifications.................................................... 103

50 Digital Display Interface Group DC Specifications....................................................... 104

51 embedded DisplayPort* (eDP*) Group DC Specifications............................................. 104

52 CMOS Signal Group DC Specifications.......................................................................105

53 GTL Signal Group and Open Drain Signal Group DC Specifications................................ 105

) Supply DC Voltage and Current Specifications....................... 102

DDQ

Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron

Processor Family July 2014 Datasheet – Volume 1 of 2 Order No.: 328901-007 7

Processor—Tables

54 PCI Express* DC Specifications................................................................................106

55 Platform Environment Control Interface (PECI) DC Electrical Limits...............................106

56 Package Mechanical Attributes.................................................................................108

57 Processor Mass......................................................................................................110

58 Package Loading Specifications................................................................................110

59 BGA and rPGA Package Storage Conditions................................................................111

60 rPGA946B/947 Processor Pin List by Signal Name.......................................................112

61 BGA1364 Processor Ball List by Signal Name............................................................. 121

62 DDR Data Swizzling Table – Channel A..................................................................... 135

63 DDR Data Swizzling Table – Channel B..................................................................... 136

Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron Processor Family Datasheet – Volume 1 of 2 July 2014 8 Order No.: 328901-007

Revision History—Processor

Revision History

Revision Description Date

001 • Initial Release June 2013

002

003 • Minor updates throughout for clarity. November 2013

004 • Minor updates throughout for clarity. December 2013

005 • Updated table 37, "Testability Signals" March 2014

006

007

• Added Mobile 4th Generation Intel® Core™ i7-4960HQ, i7-4600M, i5-4330M, i5-4300M, i5-4200H, i5-4200M, i3-4100M, i3-4000M processors

• Added Mobile Intel® Pentium® 3550M processor

• Added Mobile Intel® Celeron® 2950M processor

• Added Section 4.2.6, "Package C-States and Display Resolutions".

• Added Mobile 4th Generation Intel® Core™ i7-4760HQ, i7-4712HQ, i7-4710HQ, i7-4712MQ, i7-4710MQ, i5-4210M, i3-4110M, i3-4100M processors

• Added Mobile Intel® Pentium® 3560M processor

• Added Mobile Intel® Celeron® 2970M processor

• Added Mobile 4th Generation Intel® Core™ i7-4980HQ, i7-4870HQ, i7-4770HQ, i5-4210H processors

• Updated Table 24, Thermal Design Power (TDP) Specifications

• Updated Table 25, Junction Temperature Specification

• Updated Table 26, Idle Power Specifications

September 2013

April 2014

July 2014

Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron

Processor Family July 2014 Datasheet – Volume 1 of 2 Order No.: 328901-007 9

1.0 Introduction

Processor—Introduction

The 4th Generation Intel® Core™ processor based on Mobile M-Processor and HProcessor Lines, Mobile Intel® Pentium® processor family, and Mobile Intel® Celeron

processor family are 64-bit, multi-core processors built on 22-nanometer process technology.

The processors are designed for a two-chip platform consisting of a processor and Platform Controller Hub (PCH). The processors are designed to be used with the Mobile chipset. See the following figure for an example platform block diagram.

Throughout this document, the 4th Generation Intel® Core™ processor based on Mobile M-Processor and H-Processor Lines, Mobile Intel® Pentium® processor family, and Mobile Intel® Celeron® processor family may be referred to simply as "processor".

Throughout this document, the Intel® 8 Series chipset may be referred to simply as "PCH".

Throughout this document, the 4th Generation Intel® Core™ processor based on Mobile M-Processor and H-Processor Lines refers to the Mobile 4th Generation Intel

Core™ i7-4980HQ, i7-4960HQ, i7-4950HQ, i7-4930MX, i7-4900MQ, i7-4870HQ, i7-4850HQ, i7-4800MQ, i7-4770HQ, i7-4760HQ, i7-4712HQ, i7-4712MQ, i7-4710HQ, i7-4710MQ, i7-4702HQ, i7-4702MQ, i7-4700HQ, i7-4700MQ, i7-4750HQ, i7-4600M, i5-4330M, i5-4300M, i5-4210M, i5-4210H, i3-4110M, and i3-4100M processors.

Throughout this document, the Mobile Mobile Intel® Pentium® processor family refers to the Intel® Pentium® 3560M, 3550M processors.

Throughout this document, the Mobile Intel® Celeron® processor family refers to the Intel® Celeron® 2970M, 2950M processor.

Note: Some processor features are not available on all platforms. Refer to the processor

Specification Update document for details.

Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron Processor Family Datasheet – Volume 1 of 2 July 2014 10 Order No.: 328901-007

Processor

PCI Express* 3.0

Digital Display

Interface (DDI)

(3 interfaces)

Embedded

DisplayPort*

(x4)

System Memory

1333 / 1600 MT/s

2 DIMMs / CH

CH A CH B

Note: 2 DIMMs / CH is not supported on all SKUs.

Intel® Flexible Display

Interface (Intel® FDI)

(x2)

Direct Media Interface 2.0

(DMI 2.0) (x4)

Platform Controller

Hub (PCH)

SATA, 6 GB/s (up to 6 Ports)

Analog Display

(VGA)

SPI Flash

Super IO / EC

Trusted Platform

Module (TPM) 1.2

LPC

Intel® High

Definition Audio

(Intel® HD Audio)

Integrated LAN

USB 3.0

(up to 6 Ports)

USB 2.0 (8 Ports)

PCI Express* 2.0

(up to 8 Ports)

SPI

SMBus 2.0

GPIOs

Introduction—Processor

Figure 1. Platform Block Diagram

1.1

Supported Technologies

• Intel® Virtualization Technology (Intel® VT)

• Intel® Active Management Technology 9.5 (Intel® AMT 9.5 )

• Intel® Trusted Execution Technology (Intel® TXT)

• Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)

• Intel® Hyper-Threading Technology (Intel® HT Technology)

• Intel® 64 Architecture

• Execute Disable Bit

• Intel® Turbo Boost Technology 2.0

Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron

July 2014 Datasheet – Volume 1 of 2 Order No.: 328901-007 11

• Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)

Processor Family

• Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)

• PCLMULQDQ Instruction

• Intel® Secure Key

• Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSXNI)

• PAIR – Power Aware Interrupt Routing

• SMEP – Supervisor Mode Execution Protection

Note: The availability of the features may vary between processor SKUs.

Processor—Introduction

1.2

1.3

Interfaces

The processor supports the following interfaces:

• DDR3L/DDR3L-RS

• Direct Media Interface (DMI)

• Digital Display Interface (DDI)

• PCI Express*

Power Management Support

Processor Core

• Full support of ACPI C-states as implemented by the following processor C-states:

— C0, C1, C1E, C3, C6, C7

• Enhanced Intel SpeedStep® Technology

System

• S0, S3, S4, S5

Memory Controller

• Conditional self-refresh

• Dynamic power-down

PCI Express*

• L0s and L1 ASPM power management capability

DMI

• L0s and L1 ASPM power management capability

Processor Graphics Controller

• Intel® Rapid Memory Power Management (Intel® RMPM)

• Intel® Smart 2D Display Technology (Intel® S2DDT)

• Graphics Render C-state (RC6)

• Intel® Seamless Display Refresh Rate Switching with eDP port

• Intel® Display Power Saving Technology (Intel® DPST)

Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron Processor Family Datasheet – Volume 1 of 2 July 2014 12 Order No.: 328901-007

Introduction—Processor

1.4

1.5

1.6

Thermal Management Support

• Digital Thermal Sensor

• Adaptive Thermal Monitor

• THERMTRIP# and PROCHOT# support

• On-Demand Mode

• Memory Open and Closed Loop Throttling

• Memory Thermal Throttling

• External Thermal Sensor (TS-on-DIMM and TS-on-Board)

• Render Thermal Throttling

• Fan speed control with DTS

Package Support

The Mobile processor is available in two packages:

• A 37.5 mm x 37.5 mm rPGA package (rPGA946B/947)

• A 37.5 mm x 32 mm BGA package (BGA1364)

Processor Testability

The processor includes boundary-scan for board and system level testability.

1.7

Terminology

Table 1. Terminology

Term Description

APD Active Power-down

B/D/F Bus/Device/Function

BGA Ball Grid Array

BLC Backlight Compensation

BLT Block Level Transfer

BPP Bits per pixel

CKE Clock Enable

CLTM Closed Loop Thermal Management

DDI Digital Display Interface

DDR3 Third-generation Double Data Rate SDRAM memory technology

DDR3L DDR3 Low Voltage

DDR3L-RS DDR3 Low Voltage Reduced Standby Power

DLL Delay-Locked Loop

DMA Direct Memory Access

continued...

Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron

Processor Family July 2014 Datasheet – Volume 1 of 2 Order No.: 328901-007 13

Processor—Introduction

Term Description

DMI Direct Media Interface

DP DisplayPort*

DTS Digital Thermal Sensor

DVI*

Digital Visual Interface. DVI* is the interface specified by the DDWG (Digital Display Working Group)

EC Embedded Controller

ECC Error Correction Code

eDP* embedded DisplayPort*

EPG Electrical Power Gating

EU Execution Unit

FMA Floating-point fused Multiply Add instructions

FSC Fan Speed Control

HDCP High-bandwidth Digital Content Protection

HDMI* High Definition Multimedia Interface

HFM High Frequency Mode

iDCT Inverse Discrete

IHS Integrated Heat Spreader

GFX Graphics

GSA Graphics in System Agent

GUI Graphical User Interface

IMC Integrated Memory Controller

Intel® 64

64-bit memory extensions to the IA-32 architecture

Technology

Intel® DPST Intel Display Power Saving Technology

Intel® FDI Intel Flexible Display Interface

Intel® TSX-NI Intel Transactional Synchronization Extensions - New Instructions

Intel® TXT Intel Trusted Execution Technology

Intel Virtualization Technology. Processor virtualization, when used in conjunction

Intel® VT

with Virtual Machine Monitor software, enables multiple, robust independent software environments inside a single platform.

Intel Virtualization Technology (Intel VT) for Directed I/O. Intel VT-d is a hardware

Intel® VT-d

assist, under system software (Virtual Machine Manager or OS) control, for enabling I/O device virtualization. Intel VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel VT-d.

IOV I/O Virtualization

ISI Inter-Symbol Interference

ITPM Integrated Trusted Platform Module

LCD Liquid Crystal Display

LFM

Low Frequency Mode. LFM is Pn in the P-state table. It can be read at MSR CEh [47:40].

continued...

Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron

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Introduction—Processor

LFP Local Flat Panel

LPDDR3 Low-Power Third-generation Double Data Rate SDRAM memory technology

MCP Multi-Chip Package

MFM

MLE Measured Launched Environment

MLC Mid-Level Cache

MSI Message Signaled Interrupt

MSL Moisture Sensitive Labeling

MSR Model Specific Registers

NCTF

ODT On-Die Termination

OLTM Open Loop Thermal Management

PCG

PCH

PECI

PEG

PL1, PL2 Power Limit 1 and Power Limit 2

PPD Pre-charge Power-down

Processor The 64-bit multi-core component (package)

Processor Core

Processor Graphics Intel Processor Graphics

Rank

SCI System Control Interrupt. SCI is used in the ACPI protocol.

SF Strips and Fans

SMM System Management Mode

SMX Safer Mode Extensions

Term Description

Minimum Frequency Mode. MFM is the minimum ratio supported by the processor and can be read from MSR CEh [55:48].

Non-Critical to Function. NCTF locations are typically redundant ground or non-critical reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality.

Platform Compatibility Guide (PCG) (previously known as FMB) provides a design target for meeting all planned processor frequency requirements.

Platform Controller Hub. The chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity, audio features, power management, manageability, security, and storage features.

The Platform Environment Control Interface (PECI) is a one-wire interface that provides a communication channel between Intel processor and chipset components to external monitoring devices.

Case-to-ambient thermal characterization parameter (psi). A measure of thermal solution performance using total package power. Defined as (T Package Power. The heat source should always be specified for Y measurements.

PCI Express* Graphics. External Graphics using PCI Express* Architecture. It is a high-speed serial interface where configuration is software compatible with the existing PCI specifications.

The term “processor core” refers to Si die itself, which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache. All execution cores share the L3 cache.

A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a SO-DIMM.

- TLA ) / Total

CASE

continued...

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Processor Family July 2014 Datasheet – Volume 1 of 2 Order No.: 328901-007 15

Term Description

A non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have

Storage Conditions

any I/Os biased, or receive any clocks. Upon exposure to “free air” (that is, unsealed packaging or a device removed from packaging material), the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.

SVID Serial Voltage Identification

TAC Thermal Averaging Constant

TAP Test Access Point

CASE

The case temperature of the processor, measured at the geometric center of the topside of the TTV IHS.

TCC Thermal Control Circuit

is a static value that is below the TCC activation temperature and used as a

CONTROL

TDP

trigger point for fan speed control. When DTS > T to the TTV thermal profile.

Thermal Design Power: Thermal solution should be designed to dissipate this target power level. TDP is not the maximum power that the processor can dissipate.

TLB Translation Look-aside Buffer

TTV

DDQ

Thermal Test Vehicle. A mechanically equivalent package that contains a resistive heater in the die to evaluate thermal solutions.

Thermal Monitor. A power reduction feature designed to decrease temperature after the processor has reached its maximum operating temperature.

Processor core power supply

DDR3L power supply.

VF Vertex Fetch

VID Voltage Identification

VS Vertex Shader

VLD Variable Length Decoding

VMM Virtual Machine Monitor

VR Voltage Regulator

Processor ground

x1 Refers to a Link or Port with one Physical Lane

x2 Refers to a Link or Port with two Physical Lanes

x4 Refers to a Link or Port with four Physical Lanes

x8 Refers to a Link or Port with eight Physical Lanes

x16 Refers to a Link or Port with sixteen Physical Lanes

Processor—Introduction

, the processor must comply

CONTROL

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Introduction—Processor

1.8

2.0 Interfaces

Processor—Interfaces

2.1

System Memory Interface

• Two channels of DDR3L/DDR3L-RS memory with Unbuffered Small Outline Dual In-Line Memory Modules (SO-DIMM) with a maximum of two DIMMs per channel Two DIMMs per channel is only supported in Quad Core package

• Single-channel and dual-channel memory organization modes

• Data burst length of eight for all memory organization modes

• DDR3L/DDR3L-RS I/O Voltage of 1.35V

• 64-bit wide channels

• Non-ECC, Unbuffered DDR3L/DDR3L-RS SO-DIMMs only

• Theoretical maximum memory bandwidth of:

— 21.3 GB/s in dual-channel mode assuming DDR3L/DDR3L-RS 1333 MT/s

— 25.6 GB/s in dual-channel mode assuming DDR3L/DDR3L-RS 1600 MT/s

2.1.1

System Memory Technology Supported

The Integrated Memory Controller (IMC) supports DDR3L/DDR3L-RS protocols with two independent, 64-bit wide channels each accessing one or two DIMMs. The IMC supports one or two unbuffered non-ECC DDR3L/DDR3L-RS DIMM per channel; thus, allowing up to four device ranks per channel.

Note: 2 DIMMs per channel is only supported in Quad-Core package.

Table 3. Processor DIMM Support Summary by Product

Processors Package DIMM per channel DDR3L / DDR3L-RS

Quad Core rPGA, BGA

1 DPC 1333/1600

2 DPC 1333/1600

DDR3L/DDR3L-RS Data Transfer Rates:

• 1333 MT/s (PC3-10600)

• 1600 MT/s (PC3-12800)

DDR3L/DDR3L-RS SO-DIMM Modules:

• Raw Card B – Single Ranked x8 unbuffered non-ECC

• Raw Card F – Dual Ranked x8 (planar) unbuffered non-ECC

DRAM Device Technology:

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Interfaces—Processor

• Standard 1Gb, 2Gb, and 4Gb technologies and addressing are supported for x8 devices. There is no support for memory modules with different technologies or capacities on opposite sides of the same memory module. If one side of a memory module is populated, the other side is either identical or empty.

Table 4. Supported SO-DIMM Module Configurations

Raw Card

Version

DIMM

Capacity

1 GB 128 M x 8 8 14/10 8 8K

2 GB 256 M x 8 8 15/10 8 8K

4 GB 512 M x 8 8 16/10 8 8K

2 GB 128 M x 8 16 14/10 8 8K

4 GB 256 M x 8 16 15/10 8 8K

8 GB 512 M x 8 16 16/10 8 8K

DRAM

Organization

# of DRAM

Devices

# of Row/Col

Address Bits

# of Banks

Inside DRAM

Page Size

Table 5. Supported Maximum Memory Size Per DIMM

Platform Package Memory DDR3L

(note 1)

DDR3L-RS

(note 2)

SODIMM RC B

Mobile MProcessor / Mobile HProcessor

Notes: 1. The maximum High Density memory capacity is achieved using 4 Gigabit memory technology devices (1 and 2

2. DDR3L-RS is supported as a POR memory configuration as Intel expects these parts to be electrically and software

3. Raw Cards x16 SO-DIMM modules are not supported.

4. 1 DPC on 4SODIMM Board (2 total memory DIMMs populated) is supported.

5. Memory Down using DDR3L 2Rx8 and 1Rx32 (DDP) configurations are supported using a white paper design

rPGA, BGA

Gigabit devices are also supported).

identical to DDR3L. Actual validation checkout would depend on parts and vendor availability. PMO list for actual vendors and parts validated is available at https://www-ssl.intel.com/content/www/us/en/platform-memory/

platform-memory.html.

guidance.

(1Rx8) (note 3)

SODIMM RC F (2Rx8)

(note 3, 5)

Maximim Size

per DIMM

[GB]

4 4 8 8 16

8 8 16 16 32

Maximum Size Per Configuration [GB]

1 Ch

1 DPC

1 Ch

2 DPC

(note 4)

2 Ch

1 DPC

2 Ch

2 DPC

2.1.2

System Memory Timing Support

The IMC supports the following DDR3L/DDR3L-RS Speed Bin, CAS Write Latency (CWL), and command signal mode timings on the main memory interface:

• tCL = CAS Latency

• tRCD = Activate Command to READ or WRITE Command delay

• tRP = PRECHARGE Command Period

• CWL = CAS Write Latency

• Command Signal modes = 1N indicates a new command may be issued every clock and 2N indicates a new command may be issued every 2 clocks. Command launch mode programming depends on the transfer rate and memory configuration.

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Processor Family

Table 6. DDR3L / DDR3L-RS System Memory Timing Support

Processor—Interfaces

Segment Transfer

Quad Core BGA Processor with GT3/GT2 Graphics

(H-Processor) Quad Core rPGA Processor with

GT2 Graphics (M-Processor)

Rate

(MT/s)

1333 8/9 8/9 8/9 7

1600 10/11 10/11 10/11 8

tCL

(tCK)

tRCD

(tCK)

tRP

(tCK)

CWL

(tCK)

DPC CMD

1 1N/2N

2 2N

1 1N/2N

2 2N

Note: System memory timing support is based on availability and is subject to change

2.1.3

System Memory Organization Modes

The Integrated Memory Controller (IMC) supports two memory organization modes – single-channel and dual-channel. Depending upon how the DIMM Modules are populated in each memory channel, a number of different configurations can exist.

Single-Channel Mode

In this mode, all memory cycles are directed to a single-channel. Single-channel mode is used when either Channel A or Channel B DIMM connectors are populated in any order, but not both.

Dual-Channel Mode – Intel® Flex Memory Technology Mode

The IMC supports Intel Flex Memory Technology Mode. Memory is divided into symmetric and asymmetric zones. The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached. In this mode, the system runs with one zone of dual-channel mode and one zone of single-channel mode, simultaneously, across the whole memory array.

Mode

Note: Channels A and B can be mapped for physical channel 0 and 1 respectively or vice

versa; however, channel A size must be greater or equal to channel B size.

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CH BCH A

B B

Non interleaved access

Dual channel interleaved access

TOM

CH A and CH B can be configured to be physical channels 0 or 1 B – The largest physical memory amount of the smaller size memory module C – The remaining physical memory amount of the larger size memory module

Interfaces—Processor

Figure 2. Intel® Flex Memory Technology Operations

Dual-Channel Symmetric Mode

Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum performance on real world applications. Addresses are ping-ponged between the channels after each cache line (64-byte boundary). If there are two requests, and the second request is to an address on the opposite channel from the first, that request can be sent before data from the first request has returned. If two consecutive cache lines are requested, both may be retrieved simultaneously, since they are ensured to be on opposite channels. Use Dual-Channel Symmetric mode when both Channel A and Channel B DIMM connectors are populated in any order, with the total amount of memory in each channel being the same.

When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single channel zone is the top of memory, the IMC operates completely in Dual-Channel Symmetric mode.

Note: The DRAM device technology and width may vary from one channel to the other.

2.1.4

System Memory Frequency

In all modes, the frequency of system memory is the lowest frequency of all memory modules placed in the system, as determined through the SPD registers on the memory modules. The system memory controller supports up to two DIMM connectors per channel. If DIMMs with different latency are populated across the channels, the BIOS will use the slower of the two latencies for both channels. For dual-channel mode both channels must have a DIMM connector populated. For single-channel mode, only a single channel can have a DIMM connector populated.

2.1.5

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Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron

Intel® Fast Memory Access (Intel® FMA) Technology Enhancements

The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements.

Processor Family

Processor—Interfaces

Just-in-Time Command Scheduling

The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next. The most efficient request is picked from all pending requests and issued to system memory Just-in-Time to make optimal use of Command Overlapping. Thus, instead of having all memory access requests go individually through an arbitration mechanism forcing requests to be executed one at a time, the requests can be started without interfering with the current request allowing for concurrent issuing of requests. This allows for optimized bandwidth and reduced latency while maintaining appropriate command spacing to meet system memory protocol.

Command Overlap

Command Overlap allows the insertion of the DRAM commands between the Activate, Pre-charge, and Read/Write commands normally used, as long as the inserted commands do not affect the currently executing command. Multiple commands can be issued in an overlapping manner, increasing the efficiency of system memory protocol.

Out-of-Order Scheduling

While leveraging the Just-in-Time Scheduling and Command Overlap enhancements, the IMC continuously monitors pending requests to system memory for the best use of bandwidth and reduction of latency. If there are multiple requests to the same open page, these requests would be launched in a back-to-back manner to make optimum use of the open memory page. This ability to reorder requests on the fly allows the IMC to further reduce latency and increase bandwidth efficiency.

2.1.6

2.1.7

2.1.8

Data Scrambling

The system memory controller incorporates a Data Scrambling feature to minimize the impact of excessive di/dt on the platform system memory VRs due to successive 1s and 0s on the data bus. Past experience has demonstrated that traffic on the data bus is not random and can have energy concentrated at specific spectral harmonics creating high di/dt, which is generally limited by data patterns that excite resonance between the package inductance and on die capacitances. As a result, the system memory controller uses a data scrambling feature to create pseudo-random patterns on the system memory data bus to reduce the impact of any excessive di/dt.

DRAM Clock Generation

Every supported DIMM has two differential clock pairs. There are a total of four clock pairs driven directly by the processor to two DIMMs.

DRAM Reference Voltage Generation

The memory controller has the capability of generating the DDR3L/DDR3L-RS Reference Voltage (VREF) internally for both read (RDVREF) and write (VREFDQ) operations. The generated VREF can be changed in small steps, and an optimum VREF value is determined for both during a cold boot through advanced DDR3L/DDR3L-RS training procedures to provide the best voltage and signal margins.

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Interfaces—Processor

2.2

PCI Express* Interface

This section describes the PCI Express* interface capabilities of the processor. See the PCI Express Base* Specification 3.0 for details on PCI Express*.

2.2.1

PCI Express* Support

The PCI Express* lanes (PEG[15:0] TX and RX) are fully-compliant to the PCI Express Base Specification, Revision 3.0.

The 4th Generation Intel® Core™ processor based on Mobile M-Processor and HProcessor Lines with Mobile PCH supports the configurations shown in the following table (may vary depending on PCH SKUs).

Table 7. PCI Express* Supported Configurations in Mobile Products

Configuration Mobile

1x8, 2x4 GFX, I/O

2x8 GFX, I/O

1x16 GFX, I/O

• The port may negotiate down to narrower widths.

— Support for x16/x8/x4/x2/x1 widths for a single PCI Express* mode.

• 2.5 GT/s, 5.0 GT/s and 8 GT/s PCI Express* bit rates are supported.

• Gen1 Raw bit-rate on the data pins of 2.5 GT/s, resulting in a real bandwidth per pair of 250 MB/s given the 8b/10b encoding used to transmit data across this interface. This also does not account for packet overhead and link maintenance. Maximum theoretical bandwidth on the interface of 4 GB/s in each direction simultaneously, for an aggregate of 8 GB/s when x16 Gen 1.

• Gen 2 Raw bit-rate on the data pins of 5.0 GT/s, resulting in a real bandwidth per pair of 500 MB/s given the 8b/10b encoding used to transmit data across this interface. This also does not account for packet overhead and link maintenance. Maximum theoretical bandwidth on the interface of 8 GB/s in each direction simultaneously, for an aggregate of 16 GB/s when x16 Gen 2.

• Gen 3 raw bit-rate on the data pins of 8.0 GT/s, resulting in a real bandwidth per pair of 984 MB/s using 128b/130b encoding to transmit data across this interface. This also does not account for packet overhead and link maintenance. Maximum theoretical bandwidth on the interface of 16 GB/s in each direction simultaneously, for an aggregate of 32 GB/s when x16 Gen 3.

• Hierarchical PCI-compliant configuration mechanism for downstream devices.

• Traditional PCI style traffic (asynchronous snooped, PCI ordering).

• PCI Express* extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space.

• PCI Express* Enhanced Access Mechanism. Accessing the device configuration space in a flat memory mapped fashion.

• Automatic discovery, negotiation, and training of link out of reset.

• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering).

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Processor—Interfaces

• Peer segment destination posted write traffic (no peer-to-peer read traffic) in Virtual Channel 0:

— DMI -> PCI Express* Port 0

— DMI -> PCI Express* Port 1

— PCI Express* Port 0 -> DMI

— PCI Express* Port 1 -> DMI

• 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros).

• 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB (addresses where any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped.

• Re-issues Configuration cycles that have been previously completed with the Configuration Retry status.

• PCI Express* reference clock is 100-MHz differential clock.

• Power Management Event (PME) functions.

• Dynamic width capability.

• Message Signaled Interrupt (MSI and MSI-X) messages.

• Polarity inversion

• Dynamic lane numbering reversal as defined by the PCI Express Base Specification.

• Static lane numbering reversal. Does not support dynamic lane reversal, as defined (optional) by the PCI Express Base Specification.

• Supports Half Swing “low-power/low-voltage” mode.

Note: The processor does not support PCI Express* Hot-Plug.

2.2.2

PCI Express* Architecture

Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged.

The PCI Express* configuration uses standard mechanisms as defined in the PCI Plugand-Play specification. The processor PCI Express* ports support Gen 3. At 8 GT/s, Gen 3 operation results in twice as much bandwidth per lane as compared to Gen 2 operation. The 16 lanes PEG can operate at 2.5 GT/s, 5 GT/s, or 8 GT/s.

Gen 3 PCI Express* uses a 128b/130b encoding that is about 23% more efficient than the 8b/10b encoding used in Gen 1 and Gen 2.

The PCI Express* architecture is specified in three layers – Transaction Layer, Data Link Layer, and Physical Layer. See the PCI Express Base Specification 3.0 for details of PCI Express* architecture.

2.2.3

PCI Express* Configuration Mechanism

The PCI Express* (external graphics) link is mapped through a PCI-to-PCI bridge structure.

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PCI-PCI

Bridge

representing

root PCI Express ports (Device 1 and

Device 6)

PCI

Compatible

Host Bridge

Device

(Device 0)

PCI

Express*

Device

PEG0

DMI

Interfaces—Processor

Figure 3. PCI Express* Related Register Structures in the Processor

PCI Express* extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the conventional PCI specification. PCI Express* configuration space is divided into a PCI-compatible region (that consists of the first 256 bytes of a logical device's configuration space) and an extended PCI Express* region (that consists of the remaining configuration space). The PCI-compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express* configuration access mechanism described in the PCI Express* Enhanced Configuration Mechanism section.

The PCI Express* Host Bridge is required to translate the memory-mapped PCI Express* configuration space accesses from the host processor to PCI Express* configuration cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is recommended that system software access the enhanced configuration space using 32-bit operations (32-bit aligned) only. See the PCI Express Base Specification for details of both the PCI-compatible and PCI Express* Enhanced configuration mechanisms and transaction rules.

PCI Express* Graphics

The external graphics attach (PEG) on the processor is a single, 16-lane (x16) port. The PEG port is designed to be compliant with the PCI Express Base Specification, Revision 3.0.

PCI Express* Lanes Connection

The following figure demonstrates the PCIe* lane mapping.

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Processor Family

Figure 4. PCI Express* Typical Operation 16 Lanes Mapping

1 X 16

ntroller

Lane 0

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8

Lane 9

Lane 10

Lane 11

Lane 12

Lane 13

Lane 14

Lane 15

1 X 8 Controller

1 X 4 Cont

ller

Processor—Interfaces

2.3

Direct Media Interface (DMI)

Direct Media Interface (DMI) connects the processor and the PCH. Next generation DMI2 is supported.

Note: Only DMI x4 configuration is supported.

• DMI 2.0 support.

• Compliant to Direct Media Interface Second Generation (DMI2).

• Four lanes in each direction.

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Interfaces—Processor

• 5 GT/s point-to-point DMI interface to PCH is supported.

• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of

• Maximum theoretical bandwidth on interface of 2 GB/s in each direction

• Shares 100-MHz PCI Express* reference clock.

• 64-bit downstream address format, but the processor never generates an address

• 64-bit upstream address format, but the processor responds to upstream read

• Supports the following traffic types to or from the PCH:

• APIC and MSI interrupt messaging support:

• Downstream SMI, SCI and SERR error indication.

• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port

• DC coupling – no capacitors between the processor and the PCH.

• Polarity inversion.

• PCH end-to-end lane reversal across the link.

• Supports Half Swing “low-power/low-voltage”.

500 MB/s given the 8b/10b encoding used to transmit data across this interface. Does not account for packet overhead and link maintenance.

simultaneously, for an aggregate of 4 GB/s when DMI x4.

above 64 GB (Bits 63:36 will always be zeros).

transactions to addresses above 64 GB (addresses where any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped.

— DMI -> DRAM

— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs

only)

— Processor core -> DMI

— Message Signaled Interrupt (MSI and MSI-X) messages

DMA, floppy drive, and LPC bus masters.

DMI Error Flow

DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or GPE. Any DMI related SERR activity is associated with Device 0.

DMI Link Down

The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to data link down, after the link was up, then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption. This link behavior is controlled by the PCH.

Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal. No completions from downstream, non-posted transactions are returned upstream over the DMI link after a link down event.

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Processor—Interfaces

2.4

Processor Graphics

The processor graphics contains a generation 7.5 graphics core architecture. This enables substantial gains in performance and lower power consumption over previous generations. Up to 40 Execution Units are supported depending on the processor SKU.

• Next Generation Intel Clear Video Technology HD Support is a collection of video playback and enhancement features that improve the end user’s viewing experience

— Encode / transcode HD content

— Playback of high definition content including Blu-ray Disc*

— Superior image quality with sharper, more colorful images

— Playback of Blu-ray* disc S3D content using HDMI (1.4a specification

compliant with 3D)

• DirectX* Video Acceleration (DXVA) support for accelerating video processing

— Full AVC/VC1/MPEG2 HW Decode

• Advanced Scheduler 2.0, 1.0, XPDM support

• Windows* 8, Windows* 7, OSX, Linux* operating system support

• DirectX* 11.1, DirectX* 11, DirectX* 10.1, DirectX* 10, DirectX* 9 support.

• OpenGL* 4.0, support

• Switchable Graphics muxless support for mobile platforms

2.5

Processor Graphics Controller (GT)

The Graphics Engine Architecture includes 3D compute elements, Multi-format HW assisted decode/encode pipeline, and Mid-Level Cache (MLC) for superior high definition playback, video quality, and improved 3D performance and media.

The Display Engine handles delivering the pixels to the screen. GSA (Graphics in System Agent) is the primary channel interface for display memory accesses and “PCI-like” traffic in and out.

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Interfaces—Processor

Figure 5. Processor Graphics Controller Unit Block Diagram

2.5.1

3D and Video Engines for Graphics Processing

The Gen 7.5 3D engine provides the following performance and power-management enhancements.

3D Pipeline

The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive. All the cores are fully programmable, increasing the versatility of the 3D Engine.

3D Engine Execution Units

• Supports up to 40 EUs. . The EUs perform 128-bit wide execution per clock.

• Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing.

Vertex Fetch (VF) Stage

The VF stage executes 3DPRIMITIVE commands. Some enhancements have been included to better support legacy D3D APIs as well as SGI OpenGL*.

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Processor Family

Processor—Interfaces

Vertex Shader (VS) Stage

The VS stage performs shading of vertices output by the VF function. The VS unit produces an output vertex reference for every input vertex reference received from the VF unit, in the order received.

Geometry Shader (GS) Stage

The GS stage receives inputs from the VS stage. Compiled application-provided GS programs, specifying an algorithm to convert the vertices of an input object into some output primitives. For example, a GS shader may convert lines of a line strip into polygons representing a corresponding segment of a blade of grass centered on the line. Or it could use adjacency information to detect silhouette edges of triangles and output polygons extruding out from the edges.

Clip Stage

The Clip stage performs general processing on incoming 3D objects. However, it also includes specialized logic to perform a Clip Test function on incoming objects. The Clip Test optimizes generalized 3D Clipping. The Clip unit examines the position of incoming vertices, and accepts/rejects 3D objects based on its Clip algorithm.

Strips and Fans (SF) Stage

The SF stage performs setup operations required to rasterize 3D objects. The outputs from the SF stage to the Windower stage contain implementation-specific information required for the rasterization of objects and also supports clipping of primitives to some extent.

Windower / IZ (WIZ) Stage

The WIZ unit performs an early depth test, which removes failing pixels and eliminates unnecessary processing overhead.

The Windower uses the parameters provided by the SF unit in the object-specific rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of pixels. The Windower is also capable of performing dithering, whereby the illusion of a higher resolution when using low-bpp channels in color buffers is possible. Color dithering diffuses the sharp color bands seen on smooth-shaded objects.

Video Engine

The Video Engine handles the non-3D (media/video) applications. It includes support for VLD and MPEG2 decode in hardware.

2D Engine

The 2D Engine contains BLT (Block Level Transfer) functionality and an extensive set of 2D instructions. To take advantage of the 3D during engine’s functionality, some BLT functions make use of the 3D renderer.

Processor Graphics VGA Registers

The 2D registers consists of original VGA registers and others to support graphics modes that have color depths, resolutions, and hardware acceleration features that go beyond the original VGA standard.

Mobile 4th Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron Processor Family Datasheet – Volume 1 of 2 July 2014 30 Order No.: 328901-007

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