Intel I3-530, i5-680, i5-670, i5-661, i5-660 Documentation Update

...

Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium Desktop Processor 6000 Series

Specification Update

January 2011

Reference Number: 322911-013

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Specification Update

Contents

Revision History...............................................................................................................5

Preface ..............................................................................................................................6

Summary Tables of Changes..........................................................................................8

Identification Information..............................................................................................14

Errata...............................................................................................................................17

Specification Changes...................................................................................................49

Specification Clarifications...........................................................................................50

Documentation Changes...............................................................................................51

Specification Update

Contents

Specification Update

Revision History

Revision Description Date

-001 Initial Release January 2010

-002

-003

-004 Added Errataum AAU92. April 2010

-005

-006 Added Errata AAU93 - AAU97 April 2010

-007

-008 Added Errata AAU98-AAU102 July 2010

-009

-010

-011 Added Errata AAU103-AAU105 September 2010

-012

-013

Added Errata AAU85-AAU87. Corrected Extended Model and Model Number register values in Component Identification

table. Added Errata AAU88-AAU91.

Added Documentation Changes AAU1-AAU3.

Updated Processor Identification table to include the SKU information for the Intel® Core™ i5-680 processor.

Added processor K-0 stepping information.

Updated Processor Identification table to include the SKU information for the Intel® Core™ i5-655K and i3-550 processor.

Erratum AAU32 added to this product Specification Update in error, all erratum details removed from the specification update doc ument.

Updated Processor Identification table to include the SKU information for the Intel® Core™ i3-560 processor.

Added Errata AAU106 - AAU108 Updated problem statement for erratum AAU36

Changed document title to reflect introduction of G6960 processor Added Errata AAU109-AAU110 Erratum AAU98 added to this specification Update in error; all erratum details removed from the specification update document.

February 2010

March 2010

April 2010

June 2010

August 2010

November 2010

January 2011

Specification Update

Preface

This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.

This document may also contain information that was not previously published.

Affected Documents

Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop

Intel Processor 6000 Series Datasheet, Volume 1

Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor

Intel G6950 Datasheet, Volume 2

Nomenclature

Errata are design defects or errors. These may cause the processor behavior to

deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics such as, core speed, L2 cache size, package type, etc. as described in the processor identification information table. Read all notes associated with each S-Spec number.

Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in any new release of the specification.

Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification.

Note: Errata remain in the specification update throughout the product’s lifecycle, or until a

particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.).

Specification Update

Summary Tables of Changes

The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations:

Codes Used in Summary Tables

Stepping

Status

Row

X: Errata exists in the stepping indicated. Specification Change or

Clarification that applies to this stepping. (No mark) or (Blank box): This erratum is fixed in listed stepping or specification change

does not apply to listed stepping.

(Page): Page location of item in this document.

Doc: Document change or update will be implemented. Plan Fix: This erratum may be fixed in a future stepping of the product. Fixed: This erratum has been previously fixed. No Fix: There are no plans to fix this erratum.

Change bar to left of a table row indicates this erratum is either new or modified from the previous version of the document.

Specification Update

Errata (Sheet 1 of 5)

Number

AAU1

AAU2

AAU3

AAU4 AAU5 AAU6

AAU7

AAU8 AAU9

AAU10

AAU11

AAU12

AAU13

AAU14

AAU15

AAU16

AAU17

AAU18

AAU19

AAU20 AAU21

AAU22

AAU23

AAU24

AAU25

Steppings

C-2 K-0

Status ERRATA

XXNo FixThe Processor May Report a #TS Instead of a #GP Fault

REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page

XXNo Fix

Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations

XXNo Fix

Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher

Priority Interrupts/Exceptions and May Push the Wrong Address onto the Stack

XXNo FixPerformance Monitor SSE Retired Instructions May Return Incorrect Values XXNo FixPremature Execution of a Load Operation Prior to Exception Handler Invocation XXNo FixMOV To/From Debug Registers Causes Debug Exception

XXNo Fix

Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image Leads

to Partial Memory Update

XXNo FixValues for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM XXNo FixSingle Step Interrupts with Floating Point Exception Pending May Be Mishandled XXNo FixFault on ENTER Instruction May Result in Unexpected Values on Stack Frame

XXNo Fix

IRET under Certain Conditions May Cause an Unexpected Alignment Check

Exception

General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be

Preempted

General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit

Violation above 4-G Limit

LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt

Occurs in 64-bit Mode

MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB

Error

Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled

Breakpoints

XXNo FixMONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang XXNo Fix

XXNo Fix

Corruption of CS Segment Register During RSM While Transitioning From Real

Mode to Protected Mode

Performance Monitoring Events for Read Miss to Level 3 Cache Fill Occupancy

Counter may be Incorrect

XXNo FixA VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as Armed XXNo FixPerformance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately

XXNo Fix

#GP on Segment Selector Descriptor that Straddles Canonical Boundary May

Not Provide Correct Exception Error Code

Improper Parity Error Signaled in the IQ Following Reset When a Code

Breakpoint is Set on a #GP Instruction

An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/

XXNo Fix

POP SS Instruction if it is Followed by an Instruction That Signals a Floating

Point Exception

XXNo FixIA32_MPERF Counter Stops Counting During On-Demand TM1

Specification Update

Errata (Sheet 2 of 5)

Number

AAU26

AAU27

AAU28

AAU29

AAU30

AAU31

Steppings

Status ERRATA

C-2 K-0

XXNo Fix

AAU32 X X No Fix

AAU33

AAU34

AAU35

AAU36

AAU37

AAU38

AAU39

AAU40

AAU41

AAU42

AAU43

AAU44

AAU45

AAU46 AAU47

AAU48

AAU49

AAU50

XFixed

XXNo Fix XXNo FixTwo xAPIC Timer Event Interrupts May Unexpectedly Occur XXNo Fix

XXNo Fix XXNo FixAPIC Error “Received Illegal Vector” May be Lost XXNo Fix

XXNo Fix XXNo FixIA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized XXNo Fix

XXNo Fix XXNo FixFaulting Executions of FXRSTOR May Update State Inconsistently XXNo Fix XXNo FixMemory Aliasing of Code Pages May Cause Unpredictable System Behavior

XXNo FixPerformance Monitor Counters May Count Incorrectly XXNo Fix

XXNo Fix

Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does Not Work

Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio

Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt

xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While in Periodic Mode

Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures

Changing the Memory Type for an In-Use Page Translation May Lead to Memory-Ordering Violations

Erratum AAU32 added to this specification Update in error; all erratum details removed from the specification update document.

Delivery of Certain Events Immediately Following a VM Exit May Push a Corrupted RIP onto the Stack

Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is Received while All Cores in C6

EOI Transaction May Not be Sent if Software Enters Core C6 During an Interrupt Service Routine

FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM

DR6 May Contain Incorrect Information When the First Instruction After a MOV SS,r/m or POP SS is a Store

An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May Also Result in a System Hang

Performance Monitor Counter INST_RETIRED.STORES May Count Higher than Expected

Sleeping Cores May Not be Woken Up on Logical Cluster Mode Broadcast IPI Using Destination Field Instead of Shorthand

Performance Monitor Event EPT.EPDPE_MISS May be Counted While EPT is Disable

Performance Monitor Event Offcore_response_0 (B7H) Does Not Count NT Stores to Local DRAM Correctly

EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change

Back to Back Uncorrected Machine Check Errors May Overwrite IA32_MC3_STATUS.MSCOD

Specification Update

Errata (Sheet 3 of 5)

Number

AAU51

AAU52

AAU53 AAU54

AAU55

AAU56

AAU57

AAU58 AAU59

AAU60

AAU61

AAU62

AAU63

AAU64

AAU65

AAU66

AAU67

AAU68

AAU69

AAU70

AAU71

AAU72

AAU73

AAU74

AAU75 AAU76

Steppings

C-2 K-0

XXNo Fix

Status ERRATA

Corrected Errors With a Yellow Error Indication May be Overwritten by Other

Corrected Errors

Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST

May Overcount

XXNo FixRapid Core C3/C6 Transitions May Cause Unpredictable System Behavior XXNo FixAPIC Timer CCR May Report 0 in Periodic Mode

XXNo Fix

Performance Monitor Events INSTR_RETIRED and MEM_INST_RETIRED May

Count Inaccurately

A Page Fault May Not be Generated When the PS bit is set to "1" in a PML4E or

PDPTE

BIST Results May be Additionally Reported After a GETSEC[WAKEUP] or INIT-

SIPI Sequence

XXNo FixPending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected XXNo FixVM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction

XXNo Fix

The Memory Controller tTHROT_OPREF Timings May be Violated During Self

Refresh Entry

VM Exits Due to EPT Violations Do Not Record Information About Pre-IRET NMI

Blocking

Multiple Performance Monitor Interrupts are Possible on Overflow of

IA32_FIXED_CTR2

XXNo FixLBRs May Not be Initialized During Power-On Reset of the Processor XXNo Fix

LBR, BTM or BTS Records May have Incorrect Branch From Information After an

EIST Transition, T-states, C1E, or Adaptive Thermal Throttling

XXNo FixVMX-Preemption Timer Does Not Count Down at the Rate Specified XXNo Fix

Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed

Counter 0

XXNo FixVM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Correct Operand Size XXNo Fix

Performance Monitoring Events STORE_BLOCKS.NOT_STA and

STORE_BLOCKS.STA May Not Count Events Correctly

XXNo FixStorage of PEBS Record Delayed Following Execution of MOV SS or STI XXNo Fix

XXNo Fix

Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count

Some Transitions

INVLPG Following INVEPT or INVVPID May Fail to Flush All Translations for a

Large Page

Logical Processor May Use Incorrect VPID after VM Entry That Returns From

SMM

The Memory Controller May Hang Due to Uncorrectable ECC Errors or Parity

Errors Occurring on Both Channels in Mirror Channel Mode

MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology

Core Ratio Multipliers for Non-Existent Core Configurations

XFixedInternal Parity Error May Be Incorrectly Signaled during C6 Exit XXNo FixPMIs during Core C6 Transitions May Cause the System to Hang

Specification Update

Errata (Sheet 4 of 5)

Number

AAU77

AAU78

AAU79

AAU80

AAU82

AAU83 AAU84

AAU85

AAU86 AAU87

AAU88

AAU89

AAU90

AAU91

AAU92 AAU93 AAU94

AAU95

AAU96

AAU97

AAU98

AAU99

AAU100

AAU101

AAU102

AAU103

Steppings

C-2 K-0

XXNo Fix

Status ERRATA

2MB Page Split Lock Accesses Combined With Complex Internal Events May Cause Unpredictable System Behavior

If the APIC timer Divide Configuration Register (Offset 03E0H) is written at the

XXNo Fix

same time that the APIC timer Current Count Register (Offset 0390H) reads 1H, it is possible that the APIC timer will deliver two interrupts.

XFixedTXT.PUBLIC.KEY is Not Reliable XFixed

XXNo Fix

8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides With Interrupt Acknowledge Cycle From the Preceding Interrupt

The APIC Timer Current Count Register May Prematurely Read 0x0 While the

Timer is Still Running

XXNo FixSecondary PCIe Port May Not Train After A Warm Reset XXNo FixThe PECI Bus May Be Tri-stated after System Reset

XXNo Fix

The Combination of a Page-Split Lock Access And Data Accesses That Are Split

Across Cacheline Boundaries May Lead to Processor Livelock

XXNo FixProcessor Hangs on Package C6 State Exit XXNo FixA Synchronous SMI May be Delayed

FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access

XXNo Fix

Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-

bit Mode

XXPlan Fix

PCI Express x16 Port Links May Fail to Dynamically Switch From 5.0GT/s to

2.5GT/s

XXNo FixPCI Express Cards May Not Train to x16 Link Width XXNo Fix

Unexpected Graphics VID Transition During Warm Reset May Cause the System

to Hang

XXNo FixIO_SMI Indication in SMRAM State Save Area May Be Lost XFixedVM Entry to 64-Bit Mode May Fail if Bits 48 And 47 of Guest RIP Are Different XFixedVM Entry Loading an Unusable SS Might Not Set SS.B to 1

XFixed

XXNo Fix

FSW May Be Corrupted If an x87 Store Instruction Causes a Page Fault in VMX

Non-Root Operation

Under Certain Low Temperature Conditions, Some Uncore Performance

Monitoring Events May Report Incorrect Results

XXNo FixCKE May go Low Within tRFC(min) After a PD Exit XXNo Fix

XXNo Fix

Erratum AAU98 added to this specification Update in error; all erratum details

removed from the specification update document.

Performance Monitor Events for Hardware Prefetches Which Miss The L1 Data

Cache May be Over-Counted

XXNo FixVM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] XFixed

XXNo Fix

Correctable and Uncorrectable Cache Errors May be Reported Until the First

Core C6 Transition

Accesses to a VMCS May Not Operate Correctly If CR0.CD is Set on Any Logical

Processor of a Core

PCIe Port’s LTSSM May Not Transition Properly in the Presence of TS1 or TS2

Ordered Sets That Have Unexpected Symbols Within those Sets

Specification Update

Errata (Sheet 5 of 5)

Number

AAU104

AAU105

Steppings

C-2 K-0

Status ERRATA

XXNo FixNTB/RP Link Will Send Extra TS2 Ordered Set During Link Training XXNo Fix

PCIe Ports May Not Enter Slave Loopback Mode From the Configuration LTSSM State

USB Devices May Not Function Properly With Integrated Graphics While

AAU106

XXNo Fix

Running Targeted Stress Graphics Workloads With Non-Matching Memory Configurations

AAU107

AAU108

AAU109

AAU110

XXNo Fix

XNo Fix XFixedExecution of VMPTRLD May Corrupt Memory If Current-VMCS Pointer is Invalid XXNo Fix

VM Entry May Omit Consistency Checks Related to Bit 14 (BS) of the Pending Debug Exception Field in Guest-State Area of the VMCS

Intel Turbo Boost Technology Ratio Changes May Cause Unpredictable System Behavior

PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred

Specification Changes

Number SPECIFICATION CHANGES

None for this revision of this specification update.

Specification Clarifications

Number SPECIFICATION CLARIFICATIONS

None for this revision of this specification update.

Documentation Changes

Number DOCUMENTATION CHANGES

None for this revision of this specification update.

Specification Update

Identification Information

Component Identification using Programming Interface

The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series stepping can be identified by the following register contents:

Extended

Model

Reserved

31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0

Note:

1. The Extended Family , bits [27:20] are used in con junction with the F amily Code, specif ied in bits [11:8],

2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are

3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM

4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX

5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX

6. The Stepping ID in bits [3:0] indicates the revision number of that model. See Table 1 for the processor

Extended

Family

00000000b 0010b 00b 0110 0101b xxxxb

to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4,

or Intel used to identify the model of the processor within the processor’s family. processor, an OverDrive processor, or a dual processor (capable of being used in a dual processor

system). register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of

the Device ID register accessible through Boundary Scan. register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the

Device ID register accessible through Boundary Scan. stepping ID number in the CPUID information.

Core™ processor family.

Processor

Type

Family

Code

Model

Number

Stepping

When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family C ode, Mode l Number and Step ping ID

value in the EAX register. Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.

The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series can be identified by the following register contents:

Stepping Vendor ID

C-2 8086h 0040h 12h

Notes:

1. The Vendor ID corresponds to bits 15:0 of the Vendor ID Register located at offset 00–01h in the PCI

2. The Device ID corresponds to bits 15:0 of the Device ID Register located at Device 0 offset 02–03h in

3. The Revision Number corresponds to bits 7:0 of the Revision ID Register located at offset 08h in the PCI

function 0 configuration space. the PCI function 0 configuration space. function 0 configuration space.

Device ID

Revision ID

Specification Update

Component Marking Information

LOT NO S/N

The processor stepping can be identified by the following component markings.

Figure 1. Processor Production Top-side Markings (Example)

Table 1. Processor Identification (Sheet 1 of 2)

S-Spec

Number

SLBTM i5-680 K-0 20655h 3.60 / 1333 / 733

SLBLT i5-670 C-2 20652h 3.46 / 1333 / 733

SLBNE i5-661 C-2 20652h 3.33 / 1333 / 900

SLBLV i5-660 C-2 20652h 3.33 / 1333 / 733

SLBXL i5-655K K-0 20655h 3.20 / 1333 / 733

SLBLK i5-650 C-2 20652h 3.20 / 1333 / 733

SLBUD i3-550 K-0 2065 5h 3.20 / 1333 / 733 N/A 4 1, 3, 5, 8, 10

SLBY2 i3-560 K-0 20655h 3.33 / 1333 / 733 N/A 4

SLBMQ i3-540 C-2 20652h 3.06 / 1333 / 733 N/A 4

Processor

Number

Stepping

Processor Signature

Core Frequency

(GHz) /

DDR3 (MHz) /

Integrated

Graphics

Frequency

(GHz)

Max Intel

Turbo Boost

Technology

Frequency

2 core: 3.73 1 core: 3.86

2 core: 3.60 1 core: 3.73

2 core: 3.46 1 core: 3.60

2 core: 3.33 1 core: 3.46

Shared

L3 Cache

Size (MB)

Notes

1, 3, 4, 5, 6,

7, 8, 10

1, 3, 4, 5, 6,

7, 8, 10

3, 5, 7, 8, 9,

1, 3, 4, 5, 6,

7, 8, 10

1, 3, 4, 5, 6, 7,

8, 10

1, 3, 4,

5, 6, 7,

8, 10

1, 3, 5, 8,

Specification Update

Table 1. Processor Identification (Sheet 2 of 2)

S-Spec

Number

Processor

Number

Stepping

Processor Signature

Core Frequency

(GHz) /

DDR3 (MHz) /

Integrated

Graphics

Frequency

Max Intel

Turbo Boost

Technology

Frequency

SLBLR i3-530 C-2 20652h 2.93 / 1333 / 733 N/A 4

(GHz)

Shared

L3 Cache

Size (MB)

Notes

1, 3, 5, 8,

SLBMS G6950 C-2 20652h 2.80 / 1066 / 533 N/A 3 1, 5, 10

SLBT6 G6960 C-2 20652h 2.93 / 1066 / 533 N/A 3 1, 5, 10

Notes:

1. This processor has TDP of 73 W.

2. This column indicates maximum Intel

3. Intel

4. Intel

5. Intel

6. Intel

7. Intel

8. Intel SSE4.1 and SSE4.2 enabled.

9. This processor has TDP of 87 W.

10. The core frequency reported in the pro cessor brand string is rounded to 2 decimal digits. (F o r examp le,

respectively.

Hyper-Threading Technology enabled.

Trusted Execution Technology (Intel® TXT) enabled.

Virtualization Technology for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) enabled.

Virtualization Technology for Directed I/O (Intel® VT-d) enabled.

AES-NI enabled.

core frequency of 3.4666, repeating 6, is reported as @3.47 in brand stri ng. Core fr equency o f 3.3333, is reported as @3.33 in brand string.)

Turbo Boost Technology frequency (GHz) for 2 or 1 cores active

Specification Update

+ 35 hidden pages

Intel I3-530, i5-680, i5-670, i5-661, i5-660 Documentation Update

Specifications and Main Features

Frequently Asked Questions

User Manual

Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium Desktop Processor 6000 Series

Revision History

Preface

Affected Documents

Related Documents

Nomenclature

Summary Tables of Changes

Codes Used in Summary Tables

Stepping

Page

Status

Errata (Sheet 1 of 5)

Specification Clarifications

Documentation Changes

Identification Information

Component Identification using Programming Interface

Component Marking Information