2nd Generation Intel® Core™
Processor Family Desktop, Intel
®
Pentium
Processor Family Desktop,
®
and Intel
Celeron® Processor
Family Desktop
Datasheet, Volume 1
Supporting Intel® Core™ i7, i5, and i3 Desktop Processor Series
®
Supporting Intel
Supporting Intel
This is Volume 1 of 2
June 2013
Pentium® Processor G800 and G600 Series
®
Celeron® Processor G500 and G400 Series
®
Document Number: 324641-008
Page 2
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®
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Enhanced Intel
®
SpeedStep® Technology See the Processor Spec Finder or contact your Intel representative for more information.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family,
not across different processor families. See www.intel.com/products/processor_number for details.
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drivers and applications enabled for Intel
®
64 architecture. Performance will vary depending on your hardware and software
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Intel, Intel Core, Celeron, Pentium, Speedstep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other
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*Other names and brands may be claimed as the property of others.
Celeron® processor family desktop – Intel® Celeron
®
Pentium® G860, G630, and G630T processors
®
Celeron® G555, G550T, G465 processors
§ §
Revision
Date
January
2011
May 2011
September
2011
October
2011
December
2011
January
2012
September
2012
June 2013
8Datasheet, Volume 1
Page 9
Introduction
1Introduction
The 2nd Generation Intel® Core™ processor family desktop, Intel® Pentium® processor
family desktop, and Intel® Celeron® processor family desktop are the next generation
of 64-bit, multi-core desktop processor built on 32- nanometer process technology.
Based on a new micro-architecture, the processor is designed for a two-chip platform
consisting of a processor and Platform Controller Hub (PCH). The platform enables
higher performance, lower cost, easier validation, and improved x-y footprint. The
processor includes Integrated Display Engine, Processor Graphics, PCI Express* ports,
and Integrated Memory Controller. The processor is designed for desktop platforms. It
supports up to 12 Processor Graphics execution units (EUs). The processor is offered in
an 1155-land LGA package. Figure 1-1 shows an example desktop platform block
diagram.
This document provides DC electrical specifications, signal integrity, differential
signaling specifications, pinout and signal definitions, interface functional descriptions,
thermal specifications, and additional feature information pertinent to the
implementation and operation of the processor on its respective platform.
®
Note:Throughout this document, 2nd Generation Intel
®
Intel
Pentium® processor family desktop, and Intel® Celeron® processor family
Core™ processor family desktop,
desktop may be referred to as simply the processor.
Note:Throughout this document, the Intel
Note:Throughout this document, the Intel
®
Intel
Core™ i7-2700K, i7-2600K, i7-2600S, and i7-2600 processors.
• PCI Express* port(s) are fully-compliant with the PCI Express Base Specification,
Revision 2.0.
Table 1-1.PCI Express* Supported Configurations in Desktop Products
• Processor with desktop PCH supported configurations
ConfigurationOrganizationDesktop
12x8Graphics, I/O
21x16Graphics, I/O
Introduction
• The port may negotiate down to narrower widths
— Support for x16/x8/x4/x1 widths for a single PCI Express mode
• 2.5 GT/s and 5.0 GT/s PCI Express* frequencies are supported
• Gen1 Raw bit-rate on the data pins of 2.5 GT/s, resulting in a real bandwidth per
pair of 250 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on the interface of 4 GB/s in each direction
simultaneously, for an aggregate of 8 GB/s when x16 Gen 1
• Gen 2 Raw bit-rate on the data pins of 5.0 GT/s, resulting in a real bandwidth per
pair of 500 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on the interface of 8 GB/s in each direction
simultaneously, for an aggregate of 16 GB/s when x16 Gen 2
• Hierarchical PCI-compliant configuration mechanism for downstream devices
• Traditional PCI style traffic (asynchronous snooped, PCI ordering)
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express* Enhanced Access Mechanism; accessing the device configuration
space in a flat memory mapped fashion
• Automatic discovery, negotiation, and training of link out of reset
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0
— DMI -> PCI Express* Port 0
12Datasheet, Volume 1
Page 13
Introduction
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros)
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status
• PCI Express* reference clock is 100-MHz differential clock
• Power Management Event (PME) functions
• Dynamic width capability
• Message Signaled Interrupt (MSI and MSI-X) messages
• Polarity inversion
Note:The processor does not support PCI Express* Hot-Plug.
1.2.3Direct Media Interface (DMI)
• DMI 2.0 support
• Four lanes in each direction
• 5 GT/s point-to-point DMI interface to PCH is supported
• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of
500 MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 2 GB/s in each direction
simultaneously, for an aggregate of 4 GB/s when DMI x4
• Shares 100-MHz PCI Express* reference clock
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros)
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Supports the following traffic types to or from the PCH
— Message Signaled Interrupt (MSI and MSI-X) messages
• Downstream SMI, SCI and SERR error indication
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters
• DC coupling – no capacitors between the processor and the PCH
• Polarity inversion
• PCH end-to-end lane reversal across the link
• Supports Half Swing “low-power/low-voltage”
Datasheet, Volume 113
Page 14
1.2.4Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master. The processors support the PECI 3.0
Specification.
1.2.5Processor Graphics
• The Processor Graphics contains a refresh of the sixth generation graphics core
enabling substantial gains in performance and lower power consumption.
• Next Generation Intel Clear Video Technology HD support is a collection of video
playback and enhancement features that improve the end user’s viewing
experience.
— Encode/transcode HD content
— Playback of high definition content including Blu-ray Disc*
— Superior image quality with sharper, more colorful images
— Playback of Blu-ray disc S3D content using HDMI (V.1.4 with 3D)
• DirectX* Video Acceleration (DXVA) support for accelerating video processing
— Full AVC/VC1/MPEG2 HW Decode
• Advanced Scheduler 2.0, 1.0, XPDM support
• Windows* 7, XP, Windows Vista*, OSX, Linux OS Support
• DX10.1, DX10, DX9 support
•OGL 3.0 support
• Switchable graphics support on desktop AIO platforms with MxM solutions only
• External Thermal Sensor (TS-on-DIMM and TS-on-Board)
• Render Thermal Throttling
• Fan speed control with DTS
Datasheet, Volume 115
Page 16
1.5Package
• The processor socket type is noted as LGA 1155. The package is a 37.5 x 37.5 mm
Flip Chip Land Grid Array (FCLGA 1155).
Note:See the 2nd Generation Intel
®
Celeron® Processor, and LGA1155 Socket Thermal Mechanical Specifications and
Intel
Design Guidelines for complete details on package.
1.6Terminology
Table 1-2.Terminology (Sheet 1 of 2)
TermDescription
ACPIAdvanced Configuration and Power Interface
AIOAll In One
BLTBlock Level Transfer
CRTCathode Ray Tube
DDR3Third-generation Double Data Rate SDRAM memory technology
DMADirect Memory Access
DMIDirect Media Interface
DPDisplayPort*
DTSDigital Thermal Sensor
Enhanced Intel
SpeedStep
EUExecution Unit
Execute Disable Bit
IMCIntegrated Memory Controller
Intel
Intel
Intel
Intel
Technology
Intel
IOVI/O Virtualization
ITPMIntegrated Trusted Platform Module
LCDLiquid Crystal Display
LVD S
NCTF
®
Technology
®
64 Technology64-bit memory extensions to the IA-32 architecture
®
FDIIntel® Flexible Display Interface
®
TXTIntel® Trusted Execution Technology
®
Virtualization
®
VT-d
Technology that provides power management capabilities to laptops.
The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the IntelDeveloper's Manuals for more detailed information.
Processor virtualization which when used in conjunction with Virtual Machine
Monitor software enables multiple, robust independent software environments
inside a single platform.
®
Intel
Virtualization Technology (Intel® VT) for Directed I/O. Intel VT-d is a
hardware assist, under system software (Virtual Machine Manager or OS)
control, for enabling I/O device virtualization. Intel VT-d also brings robust
security by providing protection from errant DMAs by using DMA remapping, a
key feature of Intel VT-d.
Low Voltage Differential Signaling. A high speed, low power data transmission
standard used for display connections to LCD panels.
Non-Critical to Function. NCTF locations are typically redundant ground or noncritical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
Introduction
®
Core™ Processor, Intel® Pentium® Processor, and
®
64 and IA-32 Architectures Software
16Datasheet, Volume 1
Page 17
Introduction
Table 1-2.Terminology (Sheet 2 of 2)
TermDescription
Platform Controller Hub. The new, 2009 chipset with centralized platform
PCH
PECIPlatform Environment Control Interface
PEG
ProcessorThe 64-bit, single-core or multi-core component (package).
Processor Core
Processor GraphicsIntel
Rank
SCISystem Control Interrupt. Used in ACPI protocol.
Storage Conditions
TACThermal Averaging Constant.
TAPTest Access Point
TDPThermal Design Power.
V
AXG
V
CC
V
CCIO
V
CCPLL
V
CCSA
V
DDQ
VLDVariable Length Decoding.
V
SS
x1Refers to a Link or Port with one Physical Lane.
x16Refers to a Link or Port with sixteen Physical Lanes.
x4Refers to a Link or Port with four Physical Lanes.
x8Refers to a Link or Port with eight Physical Lanes.
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features.
PCI Express* Graphics. External Graphics using PCI Express* Architecture. A
high-speed serial interface whose configuration is software compatible with the
existing PCI specifications.
The term “processor core” refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
®
Processor Graphics
A unit of DRAM corresponding four to eight devices in parallel. These devices are
usually, but not always, mounted on a single side of a SO-DIMM.
A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to free air. Under
these conditions, processor landings should not be connected to any supply
voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air”
(that is, unsealed packaging or a device removed from packaging material) the
processor must be handled in accordance with moisture sensitivity labeling
(MSL) as indicated on the packaging material.
Graphics core power supply.
Processor core power supply.
High Frequency I/O logic power supply
PLL power supply
System Agent (memory controller, DMI, PCIe controllers, and display engine)
power supply
DDR3 power supply.
Processor ground.
Datasheet, Volume 117
Page 18
1.7Related Documents
Refer to Ta bl e 1 -3 for additional information.
Table 1-3.Related Documents
DocumentDocument Number/ Location
2nd Generation Intel
Processor Family Desktop, and Intel
Datasheet, Volume 2
2nd Generation Intel
Processor Family Desktop, and Intel
Specification Update
2nd Generation Intel
Processor Family Desktop, and Intel
and LGA1155 Socket Thermal Mechanical Specifications and Design
Guidelines
®
6 Series Chipset and Intel® C200 Series Chipset Datasheetwww.intel.com/Assets/PDF/datas
Intel
®
Intel
6 Series Chipset and Intel® C200 Series Chipset Thermal
Mechanical Specifications and Design Guidelines
Advanced Configuration and Power Interface Specification 3.0http://www.acpi.info/
PCI Local Bus Specification 3.0 http://www.pcisig.com/specifica-
PCI Express* Base Specification 2.0http://www.pcisig.com
DDR3 SDRAM Specificationhttp://www.jedec.org
DisplayPort* Specificationhttp://www.vesa.org
®
Intel
64 and IA-32 Architectures Software Developer's Manuals http://www.intel.com/products/pr
Volume 1: Basic Architecture253665
Volume 2A: Instruction Set Reference, A-M 253666
Volume 2B: Instruction Set Reference, N-Z 253667
Volume 3A: System Programming Guide 253668
Volume 3B: System Programming Guide 253669
®
Core™ Processor Family Desktop, Intel®Pentium®
®
Core™ Processor Family Desktop, Intel®Pentium®
®
Core™ Processor Family Desktop, Intel®Pentium®
®
Celeron® Processor Family Desktop
®
Celeron® Processor Family Desktop
®
Celeron® Processor Family Desktop,
Introduction
http://download.intel.com/design
/processor/datashts/324642.pdf
http://download.intel.com/design
/processor/specupdt/324643.pdf
http://download.intel.com/design
/processor/designex/324644.pdf
heet/324645.pdf
www.intel.com/Assets/PDF/desig
nguide/324647.pdf
tions
/security
ocessor/manuals/
ocessor/manuals/index.htm
§ §
18Datasheet, Volume 1
Page 19
Interfaces
2Interfaces
This chapter describes the interfaces supported by the processor.
2.1System Memory Interface
2.1.1System Memory Technology Supported
The Integrated Memory Controller (IMC) supports DDR3 protocols with two
independent, 64-bit wide channels each accessing one or two DIMMs. The type of
memory supported by the processor is dependant on the PCH SKU in the target
platform. Refer to Chapter 1 for supported memory configuration details.
It supports a maximum of two DDR3 DIMMs per-channel; thus, allowing up to four
device ranks per-channel.
• DDR3 Data Transfer Rates
— 1066 MT/s (PC3-8500), 1333 MT/s (PC3-10600)
• DDR3 SO-DIMM Modules
— Raw Card A – Dual Ranked x16 unbuffered non-ECC
— Raw Card B – Single Ranked x8 unbuffered non-ECC
— Raw Card C – Single Ranked x16 unbuffered non-ECC
— Raw Card F – Dual Ranked x8 (planar) unbuffered non-ECC
• Desktop PCH platform DDR3 DIMM Modules
— Raw Card A – Single Ranked x8 unbuffered non-ECC
— Raw Card B – Dual Ranked x8 unbuffered non-ECC
— Raw Card C – Single Ranked x16 unbuffered non-ECC
— Raw Card A – Single Ranked x8 unbuffered non-ECC
— Raw Card B – Dual Ranked x8 unbuffered non-ECC
— Raw Card C – Single Ranked x16 unbuffered non-ECC
— Raw Card D – Single Ranked x8 unbuffered ECC
— Raw Card E – Dual Ranked x8 unbuffered ECC
• Essential/Standard Server PCH platforms DDR3 DIMM Modules:
— Raw Card D – Single Ranked x8 unbuffered ECC
— Raw Card E – Dual Ranked x8 unbuffered ECC
DDR3 DRAM Device Technology: 1-Gb, 2-Gb, and 4 Gb DDR3 DRAM Device
technologies and addressing are supported.
1.System memory configurations are based on availability and are subject to change.
2.Interface does not support ULV/LV memory modules or ULV/LV DIMMs.
20Datasheet, Volume 1
Page 21
Interfaces
2.1.2System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
•tCL = CAS Latency
•t
•t
• CWL = CAS Write Latency
• Command Signal modes = 1n indicates a new command may be issued every clock
Table 2-3.DDR3 System Memory Timing Support
= Activate Command to READ or WRITE Command delay
RCD
= PRECHARGE Command Period
RP
and 2n indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.
Segment
All Desktop
segments
Notes:
1.System memory timing support is based on availability and is subject to change.
Transfer
Rate
(MT/s)
1066
13339997
tCL
(tCK)
7776
8886
tRCD
(tCK)
tRP
(tCK)
CWL
(tCK)DPC
CMD
Mode
11n/2n
22n
11n/2n
22n
11n/2n
22n
2.1.3System Memory Organization Modes
The IMC supports two memory organization modes—single-channel and dual-channel.
Depending upon how the DIMM Modules are populated in each memory channel, a
number of different configurations can exist.
2.1.3.1Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated in any
order, but not both.
The IMC supports Intel Flex Memory Technology Mode. Memory is divided into a
symmetric and an asymmetric zone. The symmetric zone starts at the lowest address
in each channel and is contiguous until the asymmetric zone begins or until the top
address of the channel with the smaller capacity is reached. In this mode, the system
runs with one zone of dual-channel mode and one zone of single-channel mode,
simultaneously, across the whole memory array.
Note:Channels A and B can be mapped for physical channels 0 and 1 respectively or vice
versa; however, channel A size must be greater or equal to channel B size.
Datasheet, Volume 121
Page 22
Figure 2-1. Intel
CH BCH A
BB
C
B
B
C
Non interleaved
access
Dual channel
interleaved access
TOM
B – The largest physical memory amount of the sm aller size memory module
C – The remaining physical mem ory amount of the larger size mem ory module
®
Flex Memory Technology Operation
Interfaces
2.1.3.2.1Dual-Channel Symmetric Mode
Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum
performance on real world applications. Addresses are ping-ponged between the
channels after each cache line (64-byte boundary). If there are two requests, and the
second request is to an address on the opposite channel from the first, that request can
be sent before data from the first request has returned. If two consecutive cache lines
are requested, both may be retrieved simultaneously since they are ensured to be on
opposite channels. Use Dual-Channel Symmetric mode when both Channel A and
Channel B DIMM connectors are populated in any order, with the total amount of
memory in each channel being the same.
When both channels are populated with the same memory capacity and the boundary
between the dual channel zone and the single channel zone is the top of memory, IMC
operates completely in Dual-Channel Symmetric mode.
Note:The DRAM device technology and width may vary from one channel to the other.
2.1.4Rules for Populating Memory Slots
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports one or two DIMM
connectors per channel. The usage of DIMM modules with different latencies is allowed,
but in that case, the worst latency (per channel) will be used. For dual-channel modes,
both channels must have a DIMM connector populated and for single-channel mode,
only a single-channel may have one or both DIMM connectors populated.
Note:In a 2 DIMM Per Channel (2DPC) daisy chain layout memory configuration, the furthest
DIMM from the processor of any given channel must always be populated first.
22Datasheet, Volume 1
Page 23
Interfaces
2.1.5Technology Enhancements of Intel® Fast Memory Access
(Intel® FMA)
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel FMA technology enhancements.
2.1.5.1Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
2.1.5.2Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Precharge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
2.1.5.3Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,
the IMC continuously monitors pending requests to system memory for the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back to back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the IMC
to further reduce latency and increase bandwidth efficiency.
2.1.6Memory Type Range Registers (MTRRs) Enhancement
The processor has 2 additional MTRRs (total 10 MTRRs). These additional MTRRs are
specially important in supporting larger system memory beyond 4 GB.
2.1.7Data Scrambling
The memory controller incorporates a DDR3 Data Scrambling feature to minimize the
impact of excessive di/dt on the platform DDR3 VRs due to successive 1s and 0s on the
data bus. Past experience has demonstrated that traffic on the data bus is not random
and can have energy concentrated at specific spectral harmonics creating high di/dt
that is generally limited by data patterns that excite resonance between the package
inductance and on-die capacitances. As a result, the memory controller uses a data
scrambling feature to create pseudo-random patterns on the DDR3 data bus to reduce
the impact of any excessive di/dt.
Datasheet, Volume 123
Page 24
2.2PCI Express* Interface
Transaction
Data Link
Physical
Logical Sub-block
Electrical Sub-block
RXTX
Transaction
Data Link
Physical
Logical Sub-block
Electrical Sub-block
RXTX
This section describes the PCI Express interface capabilities of the processor. See the
PCI Express Base Specification for details of PCI Express.
The number of PCI Express controllers is dependent on the platform. Refer to Chapter 1
for details.
2.2.1PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged.
The PCI Express configuration uses standard mechanisms as defined in the PCI
Plug-and-Play specification. The initial recovered clock speed of 1.25 GHz results in
2.5 Gb/s/direction that provides a 250 MB/s communications channel in each direction
(500 MB/s total). That is close to twice the data rate of classic PCI. The fact that
8b/10b encoding is used accounts for the 250 MB/s where quick calculations would
imply 300 MB/s. The external graphics ports support Gen2 speed as well. At 5.0 GT/s,
Gen 2 operation results in twice as much bandwidth per lane as compared to Gen 1
operation. When operating with two PCIe controllers, each controller can be operating
at either 2.5 GT/s or 5.0 GT/s.
Interfaces
Figure 2-2. PCI Express* Layering Diagram
The PCI Express architecture is specified in three layers—Transaction Layer, Data Link
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. Refer to Figure 2-2 for the PCI Express Layering Diagram.
24Datasheet, Volume 1
PCI Express uses packets to communicate information between components. Packets
are formed in the Transaction and Data Link Layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
through the other layers, they are extended with additional information necessary to
Page 25
Interfaces
Sequence
Number
FramingHeaderDataECRCLCRCFraming
Transaction Layer
Data Link Layer
Physical Layer
handle packets at those layers. At the receiving side, the reverse process occurs and
packets get transformed from their Physical Layer representation to the Data Link
Layer representation and finally (for Transaction Layer Packets) to the form that can be
processed by the Transaction Layer of the receiving device.
Figure 2-3. Packet Flow through the Layers
2.2.1.1Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The
Transaction Layer's primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also manages
flow control of TLPs.
2.2.1.2Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of Data Link Layer include link management, error detection, and error
correction.
The transmission side of the Data Link Layer accepts TLPs assembled by the
Transaction Layer, calculates and applies data protection code and TLP sequence
number, and submits them to Physical Layer for transmission across the Link. The
receiving Data Link Layer is responsible for checking the integrity of received TLPs and
for submitting them to the Transaction Layer for further processing. On detection of TLP
error(s), this layer is responsible for requesting retransmission of TLPs until information
is correctly received, or the Link is determined to have failed. The Data Link Layer also
generates and consumes packets that are used for Link management functions.
2.2.1.3Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance
matching circuitry. It also includes logical functions related to interface initialization and
maintenance. The Physical Layer exchanges data with the Data Link Layer in an
implementation-specific format, and is responsible for converting this to an appropriate
serialized format and transmitting it across the PCI Express Link at a frequency and
width compatible with the remote device.
Datasheet, Volume 125
Page 26
2.2.2PCI Express* Configuration Mechanism
PCI-PCI Bridge
representing
root PCI
Express* ports
(Device 1 and
Device 6)
PCI Compatible
Host Bridge
Device
(Device 0)
PCI
Express*
Device
PEG0
DMI
The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge
structure.
Figure 2-4. PCI Express* Related Register Structures in the Processor
Interfaces
PCI Express extends the configuration space to 4096 bytes per-device/function, as
compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express
configuration space is divided into a PCI-compatible region (that consists of the first
256 bytes of a logical device's configuration space) and an extended PCI Express region
(that consists of the remaining configuration space). The PCI-compatible region can be
accessed using either the mechanisms defined in the PCI specification or using the
enhanced PCI Express configuration access mechanism described in the PCI Express
Enhanced Configuration Mechanism section.
The PCI Express Host Bridge is required to translate the memory-mapped PCI Express
configuration space accesses from the host processor to PCI Express configuration
cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is
recommended that system software access the enhanced configuration space using
32-bit operations (32-bit aligned) only. See the PCI Express Base Specification for
details of both the PCI-compatible and PCI Express Enhanced configuration
mechanisms and transaction rules.
2.2.3PCI Express* Port
The PCI Express interface on the processor is a single, 16-lane (x16) port that can also
be configured at narrower widths. The PCI Express port is compliant with the PCI
Direct Media Interface (DMI) connects the processor and the PCH. Next generation
DMI2 is supported.
DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or
GPE. Any DMI related SERR activity is associated with Device 0.
The processor is compatible with the Intel
not compatible with any previous PCH products.
®
6 Series Chipset PCH. The processor is
Page 28
2.3.3DMI Link Down
Vertex
Fetch
VS/GS
Setup/Rasterize
Hierachical Z
Hardware Clipper
EUEU
EUEU
Unified Execution Unit Array
Texture
Unit
Pixel
Backend
Full MPEG2, VC1, AVC Decode
Fixed Function Post Processing
Full AVC Encode
Partial MPEG2, VC1 Encode
Multi-Format Decode/Encode
Additional Post Processing
The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to
data link down, after the link was up, then the DMI link hangs the system by not
allowing the link to retrain to prevent data corruption. This link behavior is controlled
by the PCH.
Downstream transactions that had been successfully transmitted across the link prior
to the link going down may be processed as normal. No completions from downstream,
non-posted transactions are returned upstream over the DMI link after a link down
event.
2.4Processor Graphics Controller (GT)
New Graphics Engine Architecture includes 3D compute elements, Multi-format
hardware-assisted decode/encode Pipeline, and Mid-Level Cache (MLC) for superior
high definition playback, video quality, and improved 3D performance and Media.
Display Engine in the Uncore handles delivering the pixels to the screen. GSA (Graphics
in System Agent) is the primary Channel interface for display memory accesses and
“PCI-like” traffic in and out.
Interfaces
Figure 2-6. Processor Graphics Controller Unit Block Diagram
28Datasheet, Volume 1
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Interfaces
2.4.13D and Video Engines for Graphics Processing
The 3D graphics pipeline architecture simultaneously operates on different primitives or
on different portions of the same primitive. All the cores are fully programmable,
increasing the versatility of the 3D Engine. The Gen 6.0 3D engine provides the
following performance and power-management enhancements:
• Up to 12 Execution units (EUs)
•Hierarchal-Z
• Video quality enhancements
2.4.1.13D Engine Execution Units
• Supports up to 12 EUs. The EUs perform 128-bit wide execution per clock.
• Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel
processing.
2.4.1.23D Pipeline
2.4.1.2.1Vertex Fetch (VF) Stage
The VF stage executes 3DPRIMITIVE commands. Some enhancements have been
included to better support legacy D3D APIs as well as SGI OpenGL*.
2.4.1.2.2Vertex Shader (VS) Stage
The VS stage performs shading of vertices output by the VF function. The VS unit
produces an output vertex reference for every input vertex reference received from the
VF unit, in the order received.
2.4.1.2.3Geometry Shader (GS) Stage
The GS stage receives inputs from the VS stage. Compiled application-provided GS
programs, specifying an algorithm to convert the vertices of an input object into some
output primitives. For example, a GS shader may convert lines of a line strip into
polygons representing a corresponding segment of a blade of grass centered on the
line. Or it could use adjacency information to detect silhouette edges of triangles and
output polygons extruding out from the edges.
2.4.1.2.4Clip Stage
The Clip stage performs general processing on incoming 3D objects. However, it also
includes specialized logic to perform a Clip Test function on incoming objects. The Clip
Test optimizes generalized 3D Clipping. The Clip unit examines the position of incoming
vertices, and accepts/rejects 3D objects based on its Clip algorithm.
2.4.1.2.5Strips and Fans (SF) Stage
The SF stage performs setup operations required to rasterize 3D objects. The outputs
from the SF stage to the Windower stage contain implementation-specific information
required for the rasterization of objects and also supports clipping of primitives to some
extent.
Datasheet, Volume 129
Page 30
2.4.1.2.6Windower/IZ (WIZ) Stage
The WIZ unit performs an early depth test, which removes failing pixels and eliminates
unnecessary processing overhead.
The Windower uses the parameters provided by the SF unit in the object-specific
rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of
pixels. The Windower is also capable of performing dithering, whereby the illusion of a
higher resolution when using low-bpp channels in color buffers is possible. Color
dithering diffuses the sharp color bands seen on smooth-shaded objects.
2.4.1.3Video Engine
The Video Engine handles the non-3D (media/video) applications. It includes support
for VLD and MPEG2 decode in hardware.
2.4.1.42D Engine
The 2D Engine contains BLT (Block Level Transfer) functionality and an extensive set of
2D instructions. To take advantage of the 3D during engine’s functionality, some BLT
functions make use of the 3D renderer.
Interfaces
2.4.1.4.1Processor Graphics VGA Registers
The 2D registers consists of original VGA registers and others to support graphics
modes that have color depths, resolutions, and hardware acceleration features that go
beyond the original VGA standard.
2.4.1.4.2Logical 128-Bit Fixed BLT and 256 Fill Engine
This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The
128-bit BLT engine provides hardware acceleration of block transfers of pixel data for
many common Windows operations. The BLT engine can be used for the following:
• Move rectangular blocks of data between memory locations
• Data alignment
• To perform logical operations (raster ops)
The rectangular block of data does not change, as it is transferred between memory
locations. The allowable memory transfers are between: cacheable system memory
and frame buffer memory, frame buffer memory and frame buffer memory, and within
system memory. Data to be transferred can consist of regions of memory, patterns, or
solid color fills. A pattern is always 8 x 8 pixels wide and may be 8, 16, or 32 bits per
pixel.
The BLT engine expands monochrome data into a color depth of 8, 16, or 32 bits. BLTs
can be either opaque or transparent. Opaque transfers move the data specified to the
destination. Transparent transfers compare destination color to source color and write
according to the mode of transparency selected.
Data is horizontally and vertically aligned at the destination. If the destination for the
BLT overlaps with the source memory location, the BLT engine specifies which area in
memory to begin the BLT transfer. Hardware is included for all 256 raster operations
(source, pattern, and destination) defined by Microsoft, including transparent BLT.
The BLT engine has instructions to invoke BLT and stretch BLT operations, permitting
software to set up instruction buffers and use batch processing. The BLT engine can
perform hardware clipping during BLTs.
30Datasheet, Volume 1
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Interfaces
Memory Host Interface
(Outside of Display Engine)
Display
Arbiter
Display
Planes
& VGA
Display
Pipe A
Display
Pipe B
Display
Port
Control
A
Display
Port
Control
B
Intel
FDI
(Tx
Side)
DMI
PCH Display Engine
2.4.2Processor Graphics Display
The Processor Graphics controller display pipe can be broken down into three
components:
• Display Planes
• Display Pipes
• DisplayPort and Intel FDI
Figure 2-7. Processor Display Block Diagram
2.4.2.1Display Planes
A display plane is a single displayed surface in memory and contains one image
(desktop, cursor, overlay). It is the portion of the display hardware logic that defines
the format and location of a rectangular region of memory that can be displayed on
display output device and delivers that data to a display pipe. This is clocked by the
Core Display Clock.
2.4.2.1.1Planes A and B
Planes A and B are the main display planes and are associated with Pipes A and B
respectively. The two display pipes are independent, allowing for support of two
independent display streams. They are both double-buffered, which minimizes latency
and improves visual quality.
2.4.2.1.2Sprite A and B
Sprite A and Sprite B are planes optimized for video decode, and are associated with
Planes A and B respectively. Sprite A and B are also double-buffered.
2.4.2.1.3Cursors A and B
Cursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration,
Datasheet, Volume 131
and are associated with Planes A and B respectively. These planes support resolutions
up to 256 x 256 each.
Page 32
2.4.2.1.4Video Graphics Array (VGA)
VGA is used for boot, safe mode, legacy games, etc. It can be changed by an
application without OS/driver notification, due to legacy requirements.
2.4.2.2Display Pipes
The display pipe blends and synchronizes pixel data received from one or more display
planes and adds the timing of the display output device upon which the image is
displayed. This is clocked by the Display Reference clock inputs.
The display pipes A and B operate independently of each other at the rate of 1 pixel per
clock. They can attach to any of the display ports. Each pipe sends display data to the
PCH over the Intel Flexible Display Interface (Intel FDI).
2.4.2.3Display Ports
The display ports consist of output logic and pins that transmit the display data to the
associated encoding logic and send the data to the display device (that is, LVDS,
HDMI*, DVI, SDVO, and so on). All display interfaces connecting external displays are
now repartitioned and driven from the PCH.
The Intel Flexible Display Interface (Intel® FDI) is a proprietary link for carrying display
traffic from the Processor Graphics controller to the PCH display I/Os. Intel® FDI
supports two independent channels—one for pipe A and one for pipe B.
• Each channel has four transmit (Tx) differential pairs used for transporting pixel
and framing data from the display engine.
• Each channel has one single-ended LineSync and one FrameSync input (1-V CMOS
signaling).
• One display interrupt line input (1-V CMOS signaling).
•Intel
• Common 100-MHz reference clock.
• Each channel transports at a rate of 2.7 Gbps.
• PCH supports end-to-end lane reversal across both channels (no reversal support
®
FDI may dynamically scalable down to 2X or 1X based on actual display
bandwidth requirements.
required in the processor).
2.4.4Multi-Graphics Controller Multi-Monitor Support
The processor supports simultaneous use of the Processor Graphics Controller (GT) and
a x16 PCI Express Graphics (PEG) device.
The processor supports a maximum of 2 displays connected to the PEG card in parallel
with up to 2 displays connected to the PCH.
Note:When supporting Multi Graphics controllers Multi-Monitors, “drag and drop” between
monitors and the 2x8 PEG is not supported.
32Datasheet, Volume 1
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Interfaces
2.5Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (processor) and a PECI master. The processor implements a PECI interface
to:
• Allow communication of processor thermal and other information to the PECI
master.
• Read averaged Digital Thermal Sensor (DTS) values for fan speed control.
This chapter provides a high-level description of Intel technologies implemented in the
processor.
The implementation of the features may vary between the processor SKUs.
Details on the different technologies of Intel processors and other relevant external
notes are located at the Intel technology web site: http://www.intel.com/technology/
3.1Intel® Virtualization Technology (Intel® VT)
Intel Virtualization Technology (Intel® VT) makes a single system appear as multiple
independent systems to software. This allows multiple, independent operating systems
to run simultaneously on a single system. Intel VT comprises technology components
to support virtualization of platforms based on Intel architecture microprocessors and
chipsets. Intel Virtualization Technology (Intel VT-x) added hardware support in the
processor to improve the virtualization performance and robustness. Intel Virtualization
Technology for Directed I/O (Intel VT-d) adds chipset hardware implementation to
support and improve I/O virtualization performance and robustness.
Intel VT-x specifications and functional descriptions are included in the IntelIA-32 Architectures Software Developer’s Manual, Volume 3B and is available at:
3.1.1Intel® Virtualization Technology (Intel® VT) for
IA-32, Intel® 64 and Intel® Architecture
®
(Intel
Intel VT-x provides hardware acceleration for virtualization of IA platforms. Virtual
Machine Monitor (VMM) can use Intel VT-x features to provide improved a reliable
virtualized platform. By using Intel VT-x, a VMM is:
• Robust: VMMs no longer need to use paravirtualization or binary translation. This
• Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA x86
• More reliable: Due to the hardware support, VMMs can now be smaller, less
• More secure: The use of hardware transitions in the VMM strengthens the isolation
VT-x) Objectives
means that they will be able to run off-the-shelf OSs and applications without any
special steps.
processors.
complex, and more efficient. This improves reliability and availability and reduces
the potential for software conflicts.
of VMs and further prevents corruption of one VM from affecting others on the
same system.
Datasheet, Volume 135
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3.1.2Intel® Virtualization Technology (Intel® VT) for
IA-32, Intel® 64 and Intel® Architecture
(Intel® VT-x) Features
The processor core supports the following Intel VT-x features:
• Extended Page Tables (EPT)
— EPT is hardware assisted page table virtualization
— It eliminates VM exits from guest OS to the VMM for shadow page-table
maintenance
• Virtual Processor IDs (VPID)
— Ability to assign a VM ID to tag processor core hardware structures (such as
TLBs)
— This avoids flushes on VM transitions to give a lower-cost VM transition time
and an overall reduction in virtualization overhead.
• Guest Preemption Timer
— Mechanism for a VMM to preempt the execution of a guest OS after an amount
of time specified by the VMM. The VMM sets a timer value before entering a
guest
— The feature aids VMM developers in flexibility and Quality of Service (QoS)
assurances
• Descriptor-Table Exiting
— Descriptor-table exiting allows a VMM to protect a guest OS from internal
(malicious software based) attack by preventing relocation of key system data
structures like IDT (interrupt descriptor table), GDT (global descriptor table),
LDT (local descriptor table), and TSS (task segment selector).
— A VMM using this feature can intercept (by a VM exit) attempts to relocate
these data structures and prevent them from being tampered by malicious
software.
The key Intel VT-d objectives are domain-based isolation and hardware-based
virtualization. A domain can be abstractly defined as an isolated environment in a
platform to which a subset of host physical memory is allocated. Virtualization allows
for the creation of one or more partitions on a single system. This could be multiple
partitions in the same operating system, or there can be multiple operating system
instances running on the same system – offering benefits such as system
consolidation, legacy migration, activity partitioning, or security.
36Datasheet, Volume 1
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Technologies
3.1.4Intel® Virtualization Technology (Intel® VT) for Directed
I/O (Intel® VT-d) Features
The processor supports the following Intel VT-d features:
• Memory controller and Processor Graphics comply with Intel® VT-d 1.2
specification.
•Two VT-d DMA remap engines.
— iGraphics DMA remap engine
—DMI/PEG
• Support for root entry, context entry, and default context
• 39-bit guest physical address and host physical address widths
• Support for 4K page sizes only
• Support for register-based fault recording only (for single entry only) and support
for MSI interrupts for faults
• Support for both leaf and non-leaf caching
• Support for boot protection of default page table
• Support for non-caching of invalid page table entries
• Support for hardware based flushing of translated but pending writes and pending
reads, on IOTLB invalidation
• Support for page-selective IOTLB invalidation
• MSI cycles (MemWr to address FEEx_xxxxh) not translated
— Translation faults result in cycle forwarding to VBIOS region (byte enables
masked for writes). Returned data may be bogus for internal agents, PEG/DMI
interfaces return unsupported request status
• Interrupt Remapping is supported
• Queued invalidation is supported.
• VT-d translation bypass address range is supported (Pass Through)
Note:Intel VT-d Technology may not be available on all SKUs.
3.1.5Intel® Virtualization Technology (Intel® VT) for Directed
I/O (Intel® VT-d) Features Not Supported
The following features are not supported by the processor with Intel VT-d:
• No support for PCISIG endpoint caching (ATS)
• No support for Intel VT-d read prefetching/snarfing (that is, translations within a
cacheline are not stored in an internal buffer for reuse for subsequent translations).
• No support for advance fault reporting
• No support for super pages
• No support for Intel VT-d translation bypass address range (such usage models
need to be resolved with VMM help in setting up the page tables correctly)
Intel Trusted Execution Technology (Intel TXT) defines platform-level enhancements
that provide the building blocks for creating trusted platforms.
The Intel TXT platform helps to provide the authenticity of the controlling environment
such that those wishing to rely on the platform can make an appropriate trust decision.
The Intel TXT platform determines the identity of the controlling environment by
accurately measuring and verifying the controlling software.
Another aspect of the trust decision is the ability of the platform to resist attempts to
change the controlling environment. The Intel TXT platform will resist attempts by
software processes to change the controlling environment or bypass the bounds set by
the controlling environment.
Intel TXT is a set of extensions designed to provide a measured and controlled launch
of system software that will then establish a protected environment for itself and any
additional software that it may execute.
These extensions enhance two areas:
• The launching of the Measured Launched Environment (MLE)
• The protection of the MLE from potential corruption
The enhanced platform provides these launch and control interfaces using Safer Mode
Extensions (SMX).
The SMX interface includes the following functions:
• Measured/Verified launch of the MLE
• Mechanisms to ensure the above measurement is protected and stored in a secure
location
• Protection mechanisms that allow the MLE to control attempts to modify itself
®
For more information, refer to the Intel
Developer’s Guide in http://www.intel.com/technology/security.
The processor supports Intel® Hyper-Threading Technology (Intel® HT Technology),
that allows an execution core to function as two logical processors. While some
execution resources (such as caches, execution units, and buses) are shared, each
logical processor has its own architectural state with its own set of general-purpose
registers and control registers. This feature must be enabled using the BIOS and
requires operating system support.
Intel recommends enabling Intel HT Technology with Microsoft Windows 7*, Microsoft
Windows Vista*, Microsoft Windows* XP Professional/Windows* XP Home, and
disabling Intel HT Technology using the BIOS for all previous versions of Windows
operating systems. For more information on Intel HT Technology, see
Intel® Turbo Boost Technology is a feature that allows the processor core to
opportunistically and automatically run faster than its rated operating frequency/render
clock if it is operating below power, temperature, and current limits. The Intel Turbo
Boost Technology feature is designed to increase performance of both multi-threaded
and single-threaded workloads. Maximum frequency is dependant on the SKU and
number of active cores. No special hardware support is necessary for Intel Turbo Boost
Technology. BIOS and the OS can enable or disable Intel Turbo Boost Technology.
Compared with previous generation products, Intel Turbo Boost Technology will
increase the ratio of application power to TDP. Thus, thermal solutions and platform
cooling that are designed to less than thermal design guidance might experience
thermal and performance issues since more applications will tend to run at the
maximum power limit for significant periods of time.
Note:Intel Turbo Boost Technology may not be available on all SKUs.
3.4.1Intel® Turbo Boost Technology Frequency
The processor’s rated frequency assumes that all execution cores are running an
application at the thermal design power (TDP). However, under typical operation, not
all cores are active. Therefore, most applications are consuming less than the TDP at
the rated frequency. To take advantage of the available thermal headroom, the active
cores can increase their operating frequency.
To determine the highest performance frequency amongst active cores, the processor
takes the following into consideration:
• The number of cores operating in the C0 state.
• The estimated current consumption.
• The estimated power consumption.
•The temperature.
Any of these factors can affect the maximum frequency for a given workload. If the
power, current, or thermal limit is reached, the processor will automatically reduce the
frequency to stay with its TDP limit.
Note:Intel Turbo Boost Technology processor frequencies are only active if the operating
system is requesting the P0 state. For more information on P-states and C-states, refer
to Chapter 4, “Power Management”.
3.4.2Intel® Turbo Boost Technology Graphics Frequency
Graphics render frequency is selected by the processor dynamically based on graphics
workload demand. The processor can optimize both processor and Processor Graphics
performance by managing power for the overall package. For the Processor Graphics,
this allows an increase in the render core frequency and increased graphics
performance for graphics intensive workloads. In addition, during processor intensive
workloads when the graphics power is low, the processor core can increase its
frequency higher within the package power limit. Enabling Intel Turbo Boost Technology
will maximize the performance of the processor core and the graphics render frequency
within the specified package power levels.
Datasheet, Volume 139
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Technologies
3.5Intel® Advanced Vector Extensions (Intel® AVX)
Intel Advanced Vector Extensions (Intel AVX) is the latest expansion of the Intel
instruction set. It extends the Intel Streaming SIMD Extensions (Intel SSE) from 128bit vectors into 256-bit vectors. Intel AVX addresses the continued need for vector
floating-point performance in mainstream scientific and engineering numerical
applications, visual processing, recognition, data-mining/synthesis, gaming, physics,
cryptography and other areas of applications. The enhancement in Intel AVX allows for
improved performance due to wider vectors, new extensible syntax, and rich
functionality including the ability to better manage, rearrange, and sort data. For more
information on Intel AVX, see http://www.intel.com/software/avx
3.6Intel® Advanced Encryption Standard New
®
Instructions (Intel
The processor supports Advanced Encryption Standard New Instructions (Intel AES-NI)
that are a set of Single Instruction Multiple Data (SIMD) instructions that enable fast
and secure data encryption and decryption based on the Advanced Encryption Standard
(AES). Intel AES-NI are valuable for a wide range of cryptographic applications; such
as, applications that perform bulk encryption/decryption, authentication, random
number generation, and authenticated encryption. AES is broadly accepted as the
standard for both government and industry applications, and is widely deployed in
various protocols.
Intel AES-NI consists of six Intel SSE instructions. Four instructions, AESENC,
AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption and
decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key
expansion procedure. Together, these instructions provide a full hardware for
supporting AES, offering security, high performance, and a great deal of flexibility.
3.6.1PCLMULQDQ Instruction
The processor supports the carry-less multiplication instruction, PCLMULQDQ.
PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the
128-bit carry-less multiplication of two, 64-bit operands without generating and
propagating carries. Carry-less multiplication is an essential processing component of
several cryptographic systems and standards. Hence, accelerating carry-less
multiplication can significantly contribute to achieving high speed secure computing
and communication.
AES-NI)
3.7Intel® 64 Architecture x2APIC
The x2APIC architecture extends the xAPIC architecture that provides a key mechanism
for interrupt delivery. This extension is intended primarily to increase processor
addressability.
Specifically, x2APIC:
• Retains all key elements of compatibility to the xAPIC architecture
— delivery modes
— interrupt and processor priorities
— interrupt sources
— interrupt destination types
40Datasheet, Volume 1
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Technologies
• Provides extensions to scale processor addressability for both the logical and
physical destination modes
• Adds new features to enhance performance of interrupt delivery
• Reduces complexity of logical destination mode interrupt delivery on link based
architectures
The key enhancements provided by the x2APIC architecture over xAPIC are the
following:
• Support for two modes of operation to provide backward compatibility and
extensibility for future platform innovations
— In xAPIC compatibility mode, APIC registers are accessed through a memory
mapped interface to a 4 KB page, identical to the xAPIC architecture.
— In x2APIC mode, APIC registers are accessed through Model Specific Register
(MSR) interfaces. In this mode, the x2APIC architecture provides significantly
increased processor addressability and some enhancements on interrupt
delivery.
• Increased range of processor addressability in x2APIC mode
— Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt
processor addressability up to 4G-1 processors in physical destination mode. A
processor implementation of x2APIC architecture can support fewer than 32bits in a software transparent fashion.
— Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical x2APIC
ID is partitioned into two sub-fields—a 16-bit cluster ID and a 16-bit logical ID
within the cluster. Consequently, ((2^20) -16) processors can be addressed in
logical destination mode. Processor implementations can support fewer than
16 bits in the cluster ID sub-field and logical ID sub-field in a software agnostic
fashion.
• More efficient MSR interface to access APIC registers
— To enhance inter-processor and self directed interrupt delivery as well as the
ability to virtualize the local APIC, the APIC register set can be accessed only
through MSR based interfaces in the x2APIC mode. The Memory Mapped IO
(MMIO) interface used by xAPIC is not supported in the x2APIC mode.
• The semantics for accessing APIC registers have been revised to simplify the
programming of frequently-used APIC registers by system software. Specifically,
the software semantics for using the Interrupt Command Register (ICR) and End Of
Interrupt (EOI) registers have been modified to allow for more efficient delivery
and dispatching of interrupts.
The x2APIC extensions are made available to system software by enabling the local
x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a new
Operating System and a new BIOS are both needed, with special support for the
x2APIC mode.
The x2APIC architecture provides backward compatibility to the xAPIC architecture and
forward extendibility for future Intel platform innovations.
Note:Intel x2APIC technology may not be available on all processor SKUs.
®
For more information, refer to the Intel
64 Architecture x2APIC Specification at
http://www.intel.com/products/processor/manuals/
§ §
Datasheet, Volume 141
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Technologies
42Datasheet, Volume 1
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Power Management
G0 – Working
S0 – CPU Fully powered on
C0 – Active mode
C1 – Auto halt
C1E – Auto h a lt, low freq, lo w voltag e
C3 – L1/L2 caches flush, clocks off
C6 – save core states before shutdown
C7 – similar to C6, L3 flush
G1 – Sleepin g
S3 cold – Sleep – Suspend To Ram (STR)
S4 – Hibernate – Suspend To Disk (STD),
Wakeup on PCH
S5 – Soft Off – no power,
Wakeup on PCH
G3 – Mechanical Off
P0
Pn
* Note: Power states availability may vary between the different SKUs
4Power Management
This chapter provides information on the following power management topics:
• Advanced Configuration and Power Interface (ACPI) States
• Processor Core
• Integrated Memory Controller (IMC)
• PCI Express*
• Direct Media Interface (DMI)
• Processor Graphics Controller
Figure 4-1. Power States
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Power Management
4.1Advanced Configuration and Power Interface
(ACPI) States Supported
The ACPI states supported by the processor are described in this section.
4.1.1System States
Table 4-1.System States
StateDescription
G0/S0Full On
G1/S3-Cold Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the processor).
G1/S4Suspend-to-Disk (STD). All power lost (except wakeup on PCH).
G2/S5Soft off. All power lost (except wakeup on PCH). Total reboot.
G3Mechanical off. All power removed from system.
4.1.2Processor Core / Package Idle States
Table 4-2.Processor Core / Package State Support
StateDescription
C0Active mode, processor executing code
C1AutoHALT state
C1EAutoHALT state with lowest frequency and voltage operating point
C3
C6Execution cores in this state save their architectural state before removing core voltage.
Execution cores in C3 flush their L1 instruction cache, L1 data cache, and L2 cache to the L3
shared cache. Clocks are shut off to each core.
4.1.3Integrated Memory Controller States
Table 4-3.Integrated Memory Controller States
StateDescription
Power upCKE asserted. Active mode
Pre-charge
Power-down
Active Power-
Down
Self-RefreshCKE de-asserted using device self-refresh
CKE de-asserted (not self-refresh) with all banks closed
CKE de-asserted (not self-refresh) with minimum one bank active
4.1.4PCI Express* Link States
Table 4-4.PCI Express* Link States
StateDescription
L0Full on – Active transfer state
L0sFirst Active Power Management low power state – Low exit latency
L1Lowest Active Power Management – Longer exit latency
L3Lowest power state (power-off) – Longest exit latency
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Power Management
4.1.5Direct Media Interface (DMI) States
Table 4-5.Direct Media Interface (DMI) States
StateDescription
L0Full on – Active transfer state
L0sFirst Active Power Management low power state – Low exit latency
L1Lowest Active Power Management – Longer exit latency
L3Lowest power state (power-off) – Longest exit latency
4.1.6Processor Graphics Controller States
Table 4-6.Processor Graphics Controller States
StateDescription
D0Full on, display active
D3 ColdPower-off
4.1.7Interface State Combinations
Table 4-7.G, S, and C State Combinations
Global
(G) State
G0S0C0 Full OnOn Full On
G0S0C1/C1EAuto-HaltOnAuto-Halt
G0S0C3Deep SleepOnDeep Sleep
G0S0C6Deep Power-downOnDeep Power-down
G1S3Power offOff, except RTC Suspend to RAM
G1S4Power offOff, except RTC Suspend to Disk
G2S5Power offOff, except RTC Soft Off
G3NAPower offPower offHard off
Sleep
(S) State
Processor
Package
(C) State
Processor State System ClocksDescription
Datasheet, Volume 145
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4.2Processor Core Power Management
While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s
frequency and core voltage based on workload. Each frequency and voltage operating
point is defined by ACPI as a P-state. When the processor is not executing code, it is
idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power
C-states have longer entry and exit latencies.
4.2.1Enhanced Intel® SpeedStep® Technology
The following are the key features of Enhanced Intel SpeedStep Technology:
• Multiple frequency and voltage points for optimal performance and power
efficiency. These operating points are known as P-states.
• Frequency selection is software controlled by writing to processor MSRs. The
voltage is optimized based on the selected frequency and the number of active
processor cores.
— If the target frequency is higher than the current frequency, V
in steps to an optimized voltage. This voltage is signaled by the SVID bus to the
voltage regulator. Once the voltage is established, the PLL locks on to the
target frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
target frequency, then transitions to a lower voltage by signaling the target
voltage on SVID bus.
— All active processor cores share the same frequency and voltage. In a multi-
core processor, the highest frequency P-state requested amongst all active
cores is selected.
— Software-requested transitions are accepted at any time. If a previous
transition is in progress, the new transition is deferred until the previous
transition is completed.
• The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
• Because there is low transition latency between P-states, a significant number of
transitions per-second are possible.
Power Management
is ramped up
CC
4.2.2Low-Power Idle States
When the processor is idle, low-power idle states (C-states) are used to save power.
More power savings actions are taken for numerically higher C-states. However, higher
C-states have longer exit and entry latencies. Resolution of C-states occur at the
thread, processor core, and processor package level. Thread-level C-states are
available if Intel HT Technology is enabled.
Caution:Long term reliability cannot be assured unless all the Low Power Idle States are
enabled.
46Datasheet, Volume 1
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Power Management
Processor Package State
Core 1 State
Thread 1Thread 0
Core 0 State
Thread 1Thread 0
C1C1EC6C3
C0
MWAIT(C1), HLT
C0
MWAIT(C6),
P_LVL3 I/O Read
MWAIT(C3),
P_LV2 I/O Read
MWAIT(C1), HLT
(C1E Enabled)
Figure 4-2. Idle Power Management Breakdown of the Processor Cores
Entry and exit of the C-States at the thread and core level are shown in Figure 4-3.
Figure 4-3. Thread and Core C-State Entry and Exit
While individual threads can request low power C-states, power saving actions only
take place once the core C-state is resolved. Core C-states are automatically resolved
by the processor. For thread and core C-states, a transition to and from C0 is required
before entering any other C-state.
Table 4-8.Coordination of Thread Power States at the Core Level
Processor Core
C-State
C0C0C0C0C0
Thread 0
Datasheet, Volume 147
Note:
1.If enabled, the core C-state will be C1E if all enabled cores have also resolved a core C1 state or higher.
C1C0C1
C3C0C1
C6C0C1
Thread 1
C0C1C3C6
1
1
1
1
C1
C3C3
C3C6
C1
1
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Power Management
4.2.3Requesting Low-Power Idle States
The primary software interfaces for requesting low power idle states are through the
MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).
However, software may make C-state requests using the legacy method of I/O reads
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This
method of requesting C-states provides legacy support for operating systems that
initiate C-state transitions using I/O reads.
For legacy operating systems, P_LVLx I/O reads are converted within the processor to
the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in
I/O reads to the system. The feature, known as I/O MWAIT redirection, must be
enabled in the BIOS.
Note:The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read
interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as shown in
Tab l e 4 -9 .
Table 4-9.P_LVLx to MWAIT Conversion
P_LVLxMWAIT(Cx)Notes
P_LVL2MWAIT(C3)
P_LVL3MWAIT(C6)C6. No sub-states allowed.
The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict
the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any
P_LVLx reads outside of this range does not cause an I/O redirection to MWAIT(Cx) like
request. They fall through like a normal I/O instruction.
Note:When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The
MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O
redirections enable the MWAIT 'break on EFLAGS.IF’ feature that triggers a wakeup on
an interrupt, even if interrupts are masked by EFLAGS.IF.
4.2.4Core C-states
The following are general rules for all core C-states, unless specified otherwise:
• A core C-State is determined by the lowest numerical thread state (such as Thread
0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See
Tab l e 4 -7 .
• A core transitions to C0 state when:
— An interrupt occurs
— There is an access to the monitored address if the state was entered using an
MWAIT instruction
• For core C1/C1E, core C3, and core C6, an interrupt directed toward a single thread
wakes only that thread. However, since both threads are no longer at the same
core C-state, the core resolves to C0.
• A system reset re-initializes all processor cores.
4.2.4.1Core C0 State
The normal operating state of a core where code is being executed.
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4.2.4.2Core C1/C1E State
C1/C1E is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1/C1E) instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal
state or the C1/C1E state. See the Intel
Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.
While a core is in C1/C1E state, it processes bus snoops and snoops from other
threads. For more information on C1E, see Section 4.2.5.2.
4.2.4.3Core C3 State
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while
maintaining its architectural state. All core clocks are stopped at this point. Because the
core’s caches are flushed, the processor does not wake any core that is in the C3 state
when either a snoop is detected or when another core accesses cacheable memory.
4.2.4.4Core C6 State
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an
MWAIT(C6) instruction. Before entering core C6, the core will save its architectural
state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero
volts. During exit, the core is powered on and its architectural state is restored.
4.2.4.5C-State Auto-Demotion
In general, deeper C-states such as C6 have long latencies and have higher energy
entry/exit costs. The resulting performance and energy penalties become significant
when the entry/exit frequency of a deeper C-state is high. Therefore, incorrect or
inefficient usage of deeper C-states have a negative impact on power. To increase
residency and improve power in deeper C-states, the processor supports C-state autodemotion.
®
64 and IA-32 Architecture Software
There are two C-State auto-demotion options:
•C6 to C3
• C6/C3 To C1
The decision to demote a core from C6 to C3 or C3/C6 to C1 is based on each core’s
immediate residency history. Upon each core C6 request, the core C-state is demoted
to C3 or C1 until a sufficient amount of residency has been established. At that point, a
core is allowed to go into C3/C6. Each option can be run concurrently or individually.
This feature is disabled by default. BIOS must enable it in the
PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by
this register.
Datasheet, Volume 149
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4.2.5Package C-States
The processor supports C0, C1/C1E, C3, and C6 power states. The following is a
summary of the general rules for package C-state entry. These apply to all package Cstates unless specified otherwise:
• A package C-state request is determined by the lowest numerical core C-state
amongst all cores.
• A package C-state is automatically resolved by the processor depending on the
core idle power states and the status of the platform components.
— Each core can be at a lower idle power state than the package if the platform
does not grant the processor permission to enter a requested package C-state.
— The platform may allow additional power savings to be realized in the
processor.
— For package C-states, the processor is not required to enter C0 before entering
any other C-state.
The processor exits a package C-state when a break event is detected. Depending on
the type of break event, the processor does the following:
• If a core break event is received, the target core is activated and the break event
message is forwarded to the target core.
— If the break event is not masked, the target core enters the core C0 state and
the processor enters package C0.
• If the break event was due to a memory access or snoop request.
— But the platform did not request to keep the processor in a higher package C-
state, the package returns to its previous C-state.
— And the platform requests a higher power C-state, the memory access or snoop
request is serviced and the package remains in the higher power C-state.
Power Management
Table 4-10. Coordination of Core Power States at the Package Level
1
1
1
Core 1
1
C1
C3C3
C3C6
Package C-State
C0C0C0C0C0
Core 0
Note:
1.If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher.
C1C0C1
C3C0C1
C6C0C1
C0C1C3C6
C1
1
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C0
C1
C6
C3
Figure 4-4. Package C-State Entry and Exit
4.2.5.1Package C0
This is the normal operating state for the processor. The processor remains in the
normal state when at least one of its cores is in the C0 or C1 state or when the platform
has not granted permission to the processor to go into a low power state. Individual
cores may be in lower power idle states while the package is in C0.
4.2.5.2Package C1/C1E
No additional power reduction actions are taken in the package C1 state. However, if
the C1E sub-state is enabled, the processor automatically transitions to the lowest
supported core clock frequency, followed by a reduction in voltage.
The package enters the C1 low power state when:
• At least one core is in the C1 state.
• The other cores are in a C1 or lower power state.
The package enters the C1E state when:
• All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint.
• All cores are in a power state lower that C1/C1E but the package low power state is
limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR.
• All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is
enabled in IA32_MISC_ENABLES.
No notification to the system occurs upon entry to C1/C1E.
Datasheet, Volume 151
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4.2.5.3Package C3 State
A processor enters the package C3 low power state when:
• At least one core is in the C3 state.
• The other cores are in a C3 or lower power state, and the processor has been
granted permission by the platform.
• The platform has not granted a request to a package C6 state but has allowed a
package C6 state.
In package C3-state, the L3 shared cache is valid.
4.2.5.4Package C6 State
A processor enters the package C6 low power state when:
• At least one core is in the C6 state.
• The other cores are in a C6 or lower power state, and the processor has been
granted permission by the platform.
In package C6 state, all cores have saved their architectural state and have had their
core voltages reduced to zero volts. The L3 shared cache is still powered and snoopable
in this state. The processor remains in package C6 state as long as any part of the L3
cache is active.
Power Management
4.3Integrated Memory Controller (IMC) Power
Management
The main memory is power managed during normal operation and in low-power ACPI
Cx states.
4.3.1Disabling Unused System Memory Outputs
Any system memory (SM) interface signal that goes to a memory module connector in
which it is not connected to any actual memory devices (such as DIMM connector is
unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM
signals are:
• Reduced power consumption.
• Reduced possible overshoot/undershoot signal quality issues seen by the processor
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.
When a given rank is not populated, the corresponding chip select and CKE signals are
not driven.
At reset, all rows must be assumed to be populated, until it can be proven that they are
not populated. This is due to the fact that when CKE is tristated with an DIMM present,
the DIMM is not ensured to maintain data integrity.
SCKE tri-state should be enabled by BIOS where appropriate, since at reset all rows
must be assumed to be populated.
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Power Management
4.3.2DRAM Power Management and Initialization
The processor implements extensive support for power management on the SDRAM
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals that the SDRAM controller supports. The processor drives four CKE pins to
perform these operations.
The CKE is one of the power-save means. When CKE is off the internal DDR clock is
disabled and the DDR power is reduced. The power-saving differs according the
selected mode and the DDR type used. For more information, please refer to the IDD
table in the DDR specification.
The DDR specification defines 3 levels of power-down that differ in power-saving and in
wakeup time:
1. Active power-down (APD): This mode is entered if there are open pages when
de-asserting CKE. In this mode the open pages are retained. Power-saving in this
mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this
mode is fined by tXP – small number of cycles.
2. Precharged power-down (PPD): This mode is entered if all banks in DDR are
precharged when de-asserting CKE. Power-saving in this mode is intermediate –
better than APD, but less than DLL-off. Power consumption is defined by IDD2P1.
Exiting this mode is defined by tXP. Difference from APD mode is that when wakingup all page-buffers are empty
3. DLL-off: In this mode the data-in DLLs on DDR are off. Power-saving in this mode
is the best among all power-modes. Power consumption is defined by IDD2P1.
Exiting this mode is defined by tXP, but also tXPDLL (10 – 20 according to DDR
type) cycles until first data transfer is allowed.
The processor supports 5 different types of power-down. The different modes are the
power-down modes supported by DDR3 and combinations of these. The type of CKE
power-down is defined by the configuration. The are options are:
1. No power-down
2. APD: The rank enters power-down as soon as idle-timer expires, no matter what is
the bank status
3. PPD: When idle timer expires the MC sends PRE-all to rank and then enters powerdown
4. DLL-off: same as option (2) but DDR is configured to DLL-off
5. APD, change to PPD (APD-PPD): Begins as option (1), and when all page-close
timers of the rank are expired, it wakes the rank, issues PRE-all, and returns to PPD
APD, change to DLL-off (APD_DLLoff) – Begins as option (1), and when all pageclose timers of the rank are expired, it wakes the rank, issues PRE-all and returns
to DLL-off power-down
The CKE is determined per rank when it is inactive. Each rank has an idle-counter. The
idle-counter starts counting as soon as the rank has no accesses, and if it expires, the
rank may enter power-down while no new transactions to the rank arrive to queues.
The idle-counter begins counting at the last incoming transaction arrival.
It is important to understand that since the power-down decision is per rank, the MC
can find many opportunities to power-down ranks even while running memory
intensive applications, and savings are significant (may be a few watts, according to
the DDR specification). This is significant when each channel is populated with more
ranks.
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Power Management
Selection of power modes should be according to power-performance or thermal tradeoffs of a given system:
• When trying to achieve maximum performance and power or thermal consideration
is not an issue: use no power-down.
• In a system that tries to minimize power-consumption, try to use the deepest
power-down mode possible – DLL-off or APD_DLLoff.
• In high-performance systems with dense packaging (that is, complex thermal
design) the power-down mode should be considered in order to reduce the heating
and avoid DDR throttling caused by the heating.
Control of the power-mode through CRB-BIOS: The BIOS selects by default no-powerdown. There are knobs to change the power-down selected mode.
Another control is the idle timer expiration count. This is set through PM_PDWN_config
bits 7:0 (MCHBAR +4CB0). As this timer is set to a shorter time, the MC will have more
opportunities to put DDR in power-down. The minimum recommended value for this
register is 15. There is no BIOS hook to set this register. Customers who choose to
change the value of this register can do it by changing the BIOS. For experiments, this
register can be modified in real time if BIOS did not lock the MC registers.
Note:In APD, APD-PPD, and APD-DLLoff there is no point in setting the idle-counter in the
same range of page-close idle timer.
Another option associated with CKE power-down is the S_DLL-off. When this option is
enabled, the SBR I/O slave DLLs go off when all channel ranks are in power-down. (Do
not confuse it with the DLL-off mode, in which the DDR DLLs are off). This mode
requires to define the I/O slave DLL wakeup time.
4.3.2.1Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM that has its level recognized
(other than the DDR3 reset pin) once power is applied. It must be driven LOW by the
DDR controller to make sure the SDRAM components float DQ and DQS during powerup. CKE signals remain LOW (while any reset is active) until the BIOS writes to a
configuration register. Using this method, CKE is ensured to remain inactive for much
longer than the specified 200 micro-seconds after power and clocks to SDRAM devices
are stable.
4.3.2.2Conditional Self-Refresh
Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory into
self-refresh in the package C3 and C6 low-power states. Intel RMPM functionality
depends on the graphics/display state (relevant only when processor graphics is being
used), as well as memory traffic patterns generated by other connected I/O devices.
The target behavior is to enter self-refresh as long as there are no memory requests to
service.
When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh, the
processor core flushes pending cycles and then enters all SDRAM ranks into selfrefresh. The CKE signals remain LOW so the SDRAM devices perform self-refresh.
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4.3.2.3Dynamic Power-down Operation
Dynamic power-down of memory is employed during normal operation. Based on idle
conditions, a given memory rank may be powered down. The IMC implements
aggressive CKE control to dynamically put the DRAM devices in a power-down state.
The processor core controller can be configured to put the devices in active power-down (CKE de-assertion with open pages) or precharge power-down (CKE de-assertion
with all pages closed). Precharge power-down provides greater power savings but has
a bigger performance impact, since all pages will first be closed before putting the
devices in power-down mode.
If dynamic power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
4.3.2.4DRAM I/O Power Management
Unused signals should be disabled to save power and reduce electromagnetic
interference. This includes all signals associated with an unused memory channel.
Clocks can be controlled on a per SO-DIMM basis. Exceptions are made for per SODIMM control signals such as CS#, CKE, and ODT for unpopulated SO-DIMM slots.
The I/O buffer for an unused signal should be tri-stated (output driver disabled), the
input receiver (differential sense-amp) should be disabled, and any DLL circuitry
related ONLY to unused signals should be disabled. The input path must be gated to
prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
4.4PCI Express* Power Management
• Active power management support using L0s, and L1 states.
• All inputs and outputs disabled in L2/L3 Ready state.
Note:PEG interface does not support Hot Plug.
Note:Power impact may be observed when PEG link disable power management state is
used.
4.5Direct Media Interface (DMI) Power Management
• Active power management support using L0s/L1 state.
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Power Management
4.6Graphics Power Management
4.6.1Intel® Rapid Memory Power Management (Intel® RMPM)
(also known as CxSR)
The Intel Rapid Memory Power Management puts rows of memory into self refresh
mode during C3/C6 to allow the system to remain in the lower power states longer.
Desktop processors routinely save power during runtime conditions by entering the C3,
C6 state. Intel RMPM is an indirect method of power saving that can have a significant
effect on the system as a whole.
Intel Graphics Power Modulation Technology (Intel GPMT) is a method for saving power
in the graphics adapter while continuing to display and process data in the adapter. This
method will switch the render frequency and/or render voltage dynamically between
higher and lower power states supported on the platform based on render engine
workload.
®
In products where Intel
Technology) is supported and enabled, the functionality of Intel GPMT will be
maintained by Intel
Tec h no l og y ).
Graphics Dynamic Frequency (also known as Turbo Boost
®
Graphics Dynamic Frequency (also known as Turbo Boost
4.6.3Graphics Render C-State
Render C-State (RC6) is a technique designed to optimize the average power to the
graphics render engine during times of idleness of the render engine. Render C-state is
entered when the graphics render engine, blitter engine and the video engine have no
workload being currently worked on and no outstanding graphics memory transactions.
When the idleness condition is met, the Integrated Graphics will program the VR into a
low voltage state (~0.4 V) through the SVID bus.
Intel S2DDT reduces display refresh memory traffic by reducing memory reads
required for display refresh. Power consumption is reduced by less accesses to the IMC.
S2DDT is only enabled in single pipe mode.
Intel S2DDT is most effective with:
• Display images well suited to compression, such as text windows, slide shows, and
so on. Poor examples are 3D games.
• Static screens such as screens with significant portions of the background showing
2D applications, processor benchmarks, and so on, or conditions when the
processor is idle. Poor examples are full-screen 3D games and benchmarks that flip
the display image at or near display refresh rates.
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4.6.5Intel® Graphics Dynamic Frequency
Intel® Graphics Dynamic Frequency Technology is the ability of the processor and
graphics cores to opportunistically increase frequency and/or voltage above the
ensured processor and graphics frequency for the given part. Intel® Graphics Dynamic
Frequency Technology is a performance feature that makes use of unused package
power and thermals to increase application performance. The increase in frequency is
determined by how much power and thermal budget is available in the package, and
the application demand for additional processor or graphics performance. The
processor core control is maintained by an embedded controller. The graphics driver
dynamically adjusts between P-States to maintain optimal performance, power, and
thermals. The graphics driver will always place the graphics engine in its lowest
possible P-State; thereby, acting in the same capacity as Intel GPMT.
4.7Thermal Power Management
See Section 4.6 for all graphics thermal power management-related features.
§ §
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58Datasheet, Volume 1
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5Thermal Management
For thermal specifications and design guidelines, refer to the 2nd Generation Intel®
Core™ Processor Family Desktop, Intel® Pentium® Processor Family Desktop, and
Intel® Celeron® Processor Family Desktop, and LGA1155 Socket Thermal and
Mechanical Specifications and Design Guidelines.
§ §
Datasheet, Volume 159
Page 60
Thermal Management
60Datasheet, Volume 1
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Signal Description
6Signal Description
This chapter describes the processor signals. They are arranged in functional groups
according to their associated interface or category. The following notations are used to
describe the signal type.
NotationsSignal Type
IInput Pin
OOutput Pin
I/OBi-directional Input/Output Pin
The signal description also includes the type of buffer used for the particular signal (see
Ta b le 6 -1 ).
Table 6-1.Signal Description Buffer Types
SignalDescription
PCI Express*
DMI
CMOSCMOS buffers. 1.1-V tolerant
DDR3DDR3 buffers: 1.5-V tolerant
A
RefVoltage reference signal
Asynchronous
PCI Express interface signals. These signals are compatible with PCI Express* 2.0
Signalling Environment AC Specifications and are AC coupled. The buffers are not
3.3-V tolerant. Refer to the PCIe specification.
Direct Media Interface signals. These signals are based on PCI Express* 2.0 Signaling
Environment AC Specifications (5 GT/s), but are DC coupled. The buffers are not
3.3-V tolerant.
Analog reference or output. May be used as a threshold voltage or for buffer
compensation
1
Signal has no timing relationship with any reference clock.
Notes:
1.Qualifier for a buffer type.
Datasheet, Volume 161
Page 62
6.1System Memory Interface Signals
Table 6-2.Memory Channel A Signals
Signal Description
Signal NameDescription
SA_BS[2:0]
SA_WE#
SA_RAS#
SA_CAS#
SA_DQS[8:0]
SA_DQS#[8:0]
SA_DQ[63:0]
SA_MA[15:0]
SA_CK[3:0]
SA_CK#[3:0]
SA_CKE[3:0]
SA_CS#[3:0]
SA_ODT[3:0]
Bank Select: These signals define which banks are selected within
each SDRAM rank.
Write Enable Control Signal: This signal is used with SA_RAS# and
SA_CAS# (along with SA_CS#) to define the SDRAM Commands.
RAS Control Signal: This signal is used with SA_CAS# and SA_WE#
(along with SA_CS#) to define the SRAM Commands.
CAS Control Signal: This signal is used with SA_RAS# and SA_WE#
(along with SA_CS#) to define the SRAM Commands.
Data Strobes: SA_DQS[8:0] and its complement signal group make
up a differential strobe pair. The data is captured at the crossing point
of SA_DQS[8:0] and its SA_DQS#[8:0] during read and write
transactions.
Data Bus: Channel A data signal interface to the SDRAM data bus.I/O
Memory Address: These signals are used to provide the multiplexed
row and column address to the SDRAM.
SDRAM Differential Clock: Channel A SDRAM Differential clock signal
pair. The crossing of the positive edge of SA_CK and the negative edge
of its complement SA_CK# are used to sample the command and
control signals on the SDRAM.
• Place all SDRAM ranks into and out of self-refresh during STR
Chip Select: (1 per rank). Used to select particular SDRAM
components during the active state. There is one Chip Select for each
SDRAM rank.
On Die Termination: Active Termination Control.O
Direction/
Buffer Type
O
DDR3
O
DDR3
O
DDR3
O
DDR3
I/O
DDR3
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
O
DDR3
DDR3
62Datasheet, Volume 1
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Signal Description
Table 6-3.Memory Channel B Signals
Signal NameDescription
SB_BS[2:0]
SB_WE#
SB_RAS#
SB_CAS#
SB_DQS[8:0]
SB_DQS#[8:0]
SB_DQ[63:0]
SB_MA[15:0]
SB_CK[3:0]
SB_CK#[3:0]
SB_CKE[3:0]
SB_CS#[3:0]
SB_ODT[3:0]
Bank Select: These signals define which banks are selected within
each SDRAM rank.
Write Enable Control Signal: This signal is used with SB_RAS# and
SB_CAS# (along with SB_CS#) to define the SDRAM Commands.
RAS Control Signal: This signal is used with SB_CAS# and SB_WE#
(along with SB_CS#) to define the SRAM Commands.
CAS Control Signal: This signal is used with SB_RAS# and SB_WE#
(along with SB_CS#) to define the SRAM Commands.
Data Strobes: SB_DQS[8:0] and its complement signal group make
up a differential strobe pair. The data is captured at the crossing point
of SB_DQS[8:0] and its SB_DQS#[8:0] during read and write
transactions.
Data Bus: Channel B data signal interface to the SDRAM data bus.I/O
Memory Address: These signals are used to provide the multiplexed
row and column address to the SDRAM.
SDRAM Differential Clock: Channel B SDRAM Differential clock signal
pair. The crossing of the positive edge of SB_CK and the negative edge
of its complement SB_CK# are used to sample the command and
control signals on the SDRAM.
Table 6-8.Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface
Signal NameDescription
DMI_RX[3:0]
DMI_RX#[3:0]
DMI_TX[3:0]
DMI_TX#[3:0]
DMI Input from PCH: Direct Media Interface receive differential pair.I
DMI Output to PCH: Direct Media Interface transmit differential pair.O
Direction/
Buffer Type
6.7Phase Lock Loop (PLL) Signals
Table 6-9.Phase Lock Loop (PLL) Signals
Signal NameDescription
BCLK
BCLK#
Differential bus clock input to the processorI
Direction/
Buffer Type
Diff Clk
6.8Test Access Points (TAP) Signals
DMI
DMI
Table 6-10. Test Access Points (TAP) Signals
Signal NameDescription
Breakpoint and Performance Monitor Signals: These signals are
BPM#[7:0]
BCLK_ITP
BCLK_ITP#
DBR#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
outputs from the processor that indicate the status of breakpoints
and programmable counters used for monitoring processor
performance.
These pins are connected in parallel to the top side debug probe to
enable debug capacities.
DBR# is used only in systems where no debug port is implemented
on the system board. DBR# is used by a debug port interposer so
that an in-target probe can drive system reset.
PRDY# is a processor output used by debug tools to determine
processor debug readiness.
PREQ# is used by debug tools to request debug operation of the
processor.
TCK (Test Clock): This signal provides the clock input for the
processor Test Bus (also known as the Test Access Port). TCK must be
driven low or allowed to float during power on Reset.
TDI (Test Data In): This signal transfers serial test data into the
processor. TDI provides the serial input needed for JTAG specification
support.
TDO (Test Data Out): This signal transfers serial test data out of the
processor. TDO provides the serial output needed for JTAG
specification support.
TMS (Test Mode Select): A JTAG specification support signal used by
debug tools.
TRST# (Test Reset): This signal resets the Test Access Port (TAP)
logic. TRST# must be driven low during power on Reset.
Direction/
Buffer Type
I/O
CMOS
I
O
O
Asynchronous
CMOS
I
Asynchronous
CMOS
I
CMOS
I
CMOS
O
Open Drain
I
CMOS
I
CMOS
66Datasheet, Volume 1
Page 67
Signal Description
6.9Error and Thermal Protection Signals
Table 6-11. Error and Thermal Protection Signals
Signal NameDescription
Catastrophic Error: This signal indicates that the system has
experienced a catastrophic error and cannot continue to operate. The
processor will set this for non-recoverable machine check errors or
other unrecoverable internal errors.
CATERR#
PECI
PROCHOT#
THERMTRIP#
On the processor, CATERR# is used for signaling the following types of
errors:
• Legacy MCERRs – CATERR# is asserted for 16 BCLKs.
• Legacy IERRs – CATERR# remains asserted until warm or cold
reset.
PECI (Platform Environment Control Interface): A serial sideband
interface to the processor, it is used primarily for thermal, power, and
error management.
Processor Hot: PROCHOT# goes active when the processor
temperature monitoring sensor(s) detects that the processor has
reached its maximum safe operating temperature. This indicates that
the processor Thermal Control Circuit (TCC) has been activated, if
enabled. This signal can also be driven to the processor to activate the
TCC.
Thermal Trip: The processor protects itself from catastrophic
overheating by use of an internal thermal sensor. This sensor is set
well above the normal operating temperature to ensure that there are
no false trips. The processor will stop all execution when the junction
temperature exceeds approximately 130 °C. This is signaled to the
system by the THERMTRIP# pin.
6.10Power Sequencing Signals
Table 6-12. Power Sequencing Signals
Direction/
Buffer Type
O
CMOS
I/O
Asynchronous
CMOS Input/
Open-Drain
Output
O
Asynchronous
CMOS
Signal NameDescription
SM_DRAMPWROK Processor Input: Connects to PCH
SM_DRAMPWROK
UNCOREPWRGOOD
SKTOCC#
Datasheet, Volume 167
DRAMPWROK.
The processor requires this input signal to be a clean indication that
the V
within specifications. This requirement applies, regardless of the Sstate of the processor. 'Clean' implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time
that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high
state. This is connected to the PCH PROCPWRGD signal.
SKTOCC# (Socket Occupied): Pulled down directly (0 Ohms) on
the processor package to ground. There is no connection to the
processor silicon for this signal. System board designers may use this
signal to determine if the processor is present.
CCSA
, V
CCIO
, V
AXG
, and V
, power supplies are stable and
DDQ
Direction/
Buffer Type
I
Asynchronous
CMOS
I
Asynchronous
CMOS
Page 68
6.11Processor Power Signals
Table 6-13. Processor Power Signals
Signal Description
Signal NameDescription
VCCProcessor core power railRef
VCCIOProcessor power for I/ORef
VDDQProcessor I/O supply voltage for DDR3Ref
VCCAXGGraphics core power supply.Ref
VCCPLLVCCPLL provides isolated power for internal processor PLLsRef
VCCSASystem Agent power supplyRef
VIDSOUT
VIDSCLK
VIDALERT#
VCCSA_VIDVoltage selection for VCCSA O
VIDALERT#, VIDSCLK, and VIDSCLK comprise a three signal serial
synchronous interface used to transfer power management information
between the processor and the voltage regulator controllers. This serial
VID interface replaces the parallel VID interface on previous
processors.
6.12Sense Signals
Table 6-14. Sense Signals
Signal NameDescription
VCC_SENSE
VSS_SENSE
VAXG_SENSE
VSSAXG_SENSE
VCCIO_SENSE
VSS_SENSE_VCCIO
VDDQ_SENSE
VSSD_SENSE
VCCSA_SENSE
VCC_SENSE and VSS_SENSE provide an isolated, low impedance
connection to the processor core voltage and ground. They can be
used to sense or measure voltage near the silicon.
VAXG_SENSE and VSSAXG_SENSE provide an isolated, low
impedance connection to the V
be used to sense or measure voltage near the silicon.
VCCIO_SENSE and VSS_SENSE_VCCIO provide an isolated, low
impedance connection to the processor V
They can be used to sense or measure voltage near the silicon.
VDDQ_SENSE and VSSD_SENSE provides an isolated, low
impedance connection to the V
be used to sense or measure voltage near the silicon.
VCCSA_SENSE provide an isolated, low impedance connection to
the processor system agent voltage. It can be used to sense or
measure voltage near the silicon.
voltage and ground. They can
AXG
voltage and ground.
CCIO
voltage and ground. They can
DDQ
Direction/
Buffer Type
I/O
O
I
CMOS
Direction/
Buffer Type
O
Analog
O
Analog
O
Analog
O
Analog
O
Analog
6.13Ground and Non-Critical to Function (NCTF)
Signals
Table 6-15. Ground and Non-Critical to Function (NCTF) Signals
Signal NameDescription
VSSProcessor ground nodeGND
VSS_NCTF
68Datasheet, Volume 1
Non-Critical to Function: These pins are for package mechanical
reliability.
The processor has VCC, VDDQ, VCCPLL, VCCSA, VCCAXG, VCCIO and VSS (ground)
inputs for on-chip power distribution. All power lands must be connected to their
respective processor power planes, while all VSS lands must be connected to the
system ground plane. Use of multiple power and ground planes is recommended to
reduce I*R drop. The VCC and VCCAXG lands must be supplied with the voltage
determined by the processor Serial Voltage IDentification (SVID) interface. A new
serial VID interface is implemented on the processor. Tab l e 7- 1 specifies the voltage
level for the various VIDs.
7.2Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings between low- and full-power states. This
may cause voltages on power planes to sag below their minimum values, if bulk
decoupling is not adequate. Larger bulk storage (C
supply current during longer lasting changes in current demand (for example, coming
out of an idle condition). Similarly, capacitors act as a storage well for current when
entering an idle condition from a running condition. To keep voltages within
specification, output decoupling must be properly designed.
), such as electrolytic capacitors,
BULK
Caution:Design the board to ensure that the voltage provided to the processor remains within
the specifications listed in Tab le 7 - 5. Failure to do so can result in timing violations or
reduced lifetime of the processor.
7.2.1Voltage Rail Decoupling
The voltage regulator solution needs to provide:
• bulk capacitance with low effective series resistance (ESR).
• a low interconnect resistance from the regulator to the socket.
• bulk decoupling to compensate for large current swings generated during poweron,
or low-power idle state entry/exit.
The power delivery solution must ensure that the voltage and current specifications are
met, as defined in Tab le 7 - 5.
Datasheet, Volume 171
Page 72
Electrical Specifications
7.3Processor Clocking (BCLK[0], BCLK#[0])
The processor uses a differential clock to generate the processor core operating
frequency, memory controller frequency, system agent frequencies, and other internal
clocks. The processor core frequency is determined by multiplying the processor core
ratio by the BCLK frequency. Clock multiplying within the processor is provided by an
internal phase locked loop (PLL) that requires a constant frequency input, with
exceptions for Spread Spectrum Clocking (SSC).
The processor’s maximum non-turbo core frequency is configured during power-on
reset by using its manufacturing default value. This value is the highest non-turbo core
multiplier at which the processor can operate. If lower maximum speeds are desired,
the appropriate ratio can be configured using the FLEX_RATIO MSR.
7.3.1Phase Lock Loop (PLL) Power Supply
An on-die PLL filter solution is implemented on the processor. Refer to Ta b le 7 - 6 for DC
specifications.
7.4VCC Voltage Identification (VID)
The processoruses three signals for the serial voltage identification interface to support
automatic selection of voltages. Tab l e 7 -1 specifies the voltage level corresponding to
the eight bit VID value transmitted over serial VID. A ‘1’ in this table refers to a high
voltage level and a ‘0’ refers to a low voltage level. If the voltage regulation circuit
cannot supply the voltage that is requested, the voltage regulator must disable itself.
VID signals are CMOS push/pull drivers. Refer to Tab l e 7 -9 for the DC specifications for
these signals. The VID codes will change due to temperature and/or current load
changes in order to minimize the power of the part. A voltage range is provided in
Tab l e 7 -5 . The specifications are set so that one voltage regulator can operate with all
supported frequencies.
Individual processor VID values may be set during manufacturing so that two devices
at the same core frequency may have different default VID settings. This is shown in
the VID range values in Tabl e 7 -5 . The processor
transitioning to an adjacent VID and its associated voltage. This will represent a DC
shift in the loadline.
See the VR12/IMVP7 SVID Protocol for further details.
provides the ability to operate while
72Datasheet, Volume 1
Page 73
Electrical Specifications
Table 7-1.VR 12.0 Voltage Identification Definition (Sheet 1 of 3)
VID7VID6VID5VID4VID3VID2VID1VID
0
HEX V
CC_MAX
000000000 0 0.00000100000008 0 0.88500
000000010 1 0.25000100000018 1 0.89000
000000100 2 0.25500100000108 2 0.89500
000000110 3 0.26000100000118 3 0.90000
000001000 4 0.26500100001008 4 0.90500
000001010 5 0.27000100001018 5 0.91000
000001100 6 0.27500100001108 6 0.91500
000001110 7 0.28000100001118 7 0.92000
000010000 8 0.28500100010008 8 0.92500
000010010 9 0.29000100010018 9 0.93000
000010100 A 0.29500100010108 A 0.93500
000010110 B 0.30000100010118 B 0.94000
000011000 C 0.30500100011008 C 0.94500
000011010 D 0.31000100011018 D 0.95000
000011100 E 0.31500100011108 E 0.95500
000011110F 0.32000100011118 F 0.96000
000100001 0 0.32500100100009 0 0.96500
000100011 1 0.33000100100019 1 0.97000
000100101 2 0.33500100100109 2 0.97500
000100111 3 0.34000100100119 3 0.98000
000101001 4 0.34500100101009 4 0.98500
000101011 5 0.35000100101019 5 0.99000
000101101 6 0.35500100101109 6 0.99500
000101111 7 0.36000100101119 7 1.00000
000110001 8 0.36500100110009 8 1.00500
000110011 9 0.37000100110019 9 1.01000
000110101 A 0.37500100110109 A 1.01500
000110111 B 0.38000100110119 B 1.02000
000111001 C 0.38500100111009 C 1.02500
000111011 D 0.39000100111019 D 1.03000
000111101 E 0.39500100111109 E 1.03500
000111111F 0.40000100111119 F 1.04000
001000002 0 0.4050010100000A 0 1.04500
001000012 1 0.4100010100001A 1 1.05000
001000102 2 0.4150010100010A 2 1.05500
001000112 3 0.4200010100011A 3 1.06000
001001002 4 0.4250010100100A 4 1.06500
001001012 5 0.4300010100101A 5 1.07000
001001102 6 0.4350010100110A 6 1.07500
001001112 7 0.4400010100111A 7 1.08000
001010002 8 0.4450010101000A 8 1.08500
001010012 9 0.4500010101001A 9 1.09000
001010102 A 0.4550010101010A A 1.09500
VID7VID6VID5VID4VID3VID2VID1VID
0
HEX V
CC_MAX
Datasheet, Volume 173
Page 74
Electrical Specifications
Table 7-1.VR 12.0 Voltage Identification Definition (Sheet 2 of 3)
VID7VID6VID5VID4VID3VID2VID1VID
001010112 B 0.4600010101011A B 1.10000
001011002 C 0.4650010101100A C 1.10500
001011012 D 0.4700010101101A D 1.11000
001011102 E 0.4750010101110A E 1.11500
001011112 F 0.4800010101111A F 1.12000
001100003 0 0.4850010110000B 0 1.12500
001100013 1 0.4900010110001B 1 1.13000
001100103 2 0.4950010110010B 2 1.13500
001100113 3 0.5000010110011B 3 1.14000
001101003 4 0.5050010110100B 4 1.14500
001101013 5 0.5100010110101B 5 1.15000
001101103 6 0.5150010110110B 6 1.15500
001101113 7 0.5200010110111B 7 1.16000
001110003 8 0.5250010111000B 8 1.16500
001110013 9 0.5300010111001B 9 1.17000
001110103 A 0.5350010111010B A 1.17500
001110113 B 0.5400010111011B B 1.18000
001111003 C 0.5450010111100B C 1.18500
001111013 D 0.5500010111101B D 1.19000
001111103 E 0.5550010111110B E 1.19500
001111113 F 0.5600010111111B F 1.20000
010000004 0 0.5650011000000C 0 1.20500
010000014 1 0.5700011000001C 1 1.21000
010000104 2 0.5750011000010C 2 1.21500
010000114 3 0.5800011000011C 3 1.22000
010001004 4 0.5850011000100C 4 1.22500
010001014 5 0.5900011000101C 5 1.23000
010001104 6 0.5950011000110C 6 1.23500
010001114 7 0.6000011000111C 7 1.24000
010010004 8 0.6050011001000C 8 1.24500
010010014 9 0.6100011001001C 9 1.25000
010010104 A 0.6150011001010C A 1.25500
010010114 B 0.6200011001011C B 1.26000
010011004 C 0.6250011001100C C 1.26500
010011014 D 0.6300011001101C D 1.27000
010011104 E 0.6350011001110C E 1.27500
010011114 F 0.6400011001111C F 1.28000
010100005 0 0.6450011010000D 0 1.28500
010100015 1 0.6500011010001D 1 1.29000
010100105 2 0.6550011010010D 2 1.29500
010100115 3 0.6600011010011D 3 1.30000
010101005 4 0.6650011010100D 4 1.30500
010101015 5 0.6700011010101D 5 1.31000
0
HEX V
CC_MAX
VID7VID6VID5VID4VID3VID2VID1VID
0
HEX V
CC_MAX
74Datasheet, Volume 1
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Electrical Specifications
Table 7-1.VR 12.0 Voltage Identification Definition (Sheet 3 of 3)
VID7VID6VID5VID4VID3VID2VID1VID
0
HEX V
CC_MAX
010101105 6 0.6750011010110D 6 1.31500
010101115 7 0.6800011010111D 7 1.32000
010110005 8 0.6850011011000D 8 1.32500
010110015 9 0.6900011011001D 9 1.33000
010110105 A 0.6950011011010D A 1.33500
010110115 B 0.7000011011011D B 1.34000
010111005 C 0.7050011011100D C 1.34500
010111015 D 0.7100011011101D D 1.35000
010111105 E 0.7150011011110D E 1.35500
010111115F 0.7200011011111D F 1.36000
011000006 0 0.7250011100000E 0 1.36500
011000016 1 0.7300011100001E 1 1.37000
011000106 2 0.7350011100010E 2 1.37500
011000116 3 0.7400011100011E 3 1.38000
011001006 4 0.7450011100100E 4 1.38500
011001016 5 0.7500011100101E 5 1.39000
011001106 6 0.7550011100110E 6 1.39500
011001116 7 0.7600011100111E 7 1.40000
011010006 8 0.7650011101000E 8 1.40500
011010016 9 0.7700011101001E 9 1.41000
011010106 A 0.7750011101010E A 1.41500
011010116 B 0.7800011101011E B 1.42000
011011006 C 0.7850011101100E C 1.42500
011011016 D 0.7900011101101E D 1.43000
011011106 E 0.7950011101110E E 1.43500
011011116F 0.8000011101111E F 1.44000
011100007 0 0.8050011110000F 0 1.44500
011100017 1 0.8100011110001F 1 1.45000
011100107 2 0.8150011110010F 2 1.45500
011100117 3 0.8200011110011F 3 1.46000
011101007 4 0.8250011110100F 4 1.46500
011101017 5 0.8300011110101F 5 1.47000
011101107 6 0.8350011110110F 6 1.47500
011101117 7 0.8400011110111F 7 1.48000
011110007 8 0.8450011111000F 8 1.48500
011110017 9 0.8500011111001F 9 1.49000
011110107 A 0.8550011111010F A 1.49500
011110117 B 0.8600011111011F B 1.50000
011111007 C 0.8650011111100F C 1.50500
011111017 D 0.8700011111101F D 1.51000
011111107 E 0.8750011111110F E 1.51500
011111117F 0.8800011111111F F 1.52000
VID7VID6VID5VID4VID3VID2VID1VID
0
HEX V
CC_MAX
Datasheet, Volume 175
Page 76
7.5System Agent (SA) VCC VID
The VCCSA is configured by the processor output pin VCCSA_VID.
VCCSA_VID output default logic state is low for the processors; logic high is reserved
for future compatibility.
Tab l e 7 -2 specifies the different VCCSA_VID configurations.
Table 7-2.VCCSA_VID configuration
Processor FamilyVCCSA_VIDSelected VCCSA
2nd Generation Intel
®
Pentium® processor family desktop,
Intel
®
Intel
Celeron® processor family desktop
Future Intel processors1Note 1
®
Core™ processor family desktop,
Electrical Specifications
00.925 V
Notes:
1.Some of V
configurations are reserved for future Intel processor families.
CCSA
7.6Reserved or Unused Signals
The following are the general types of reserved (RSVD) signals and connection
guidelines:
• RSVD – These signals should not be connected.
• RSVD_NCTF – These signals are non-critical to function and may be left unconnected
Arbitrary connection of these signals to VCC, V
to any other signal (including each other) may result in component malfunction or
incompatibility with future processors. See Chapter 8 for a land listing of the processor
and the location of all reserved signals.
For reliable operation, always connect unused inputs or bi-directional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (V
). Unused outputs maybe left unconnected; however, this may
SS
interfere with some Test Access Port (TAP) functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bi-directional
signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability. For details see Ta b le 7 - 9.
CCIO
, V
DDQ
, V
CCPLL
, V
CCSA, VCCAXG, VSS
, or
76Datasheet, Volume 1
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Electrical Specifications
7.7Signal Groups
Signals are grouped by buffer type and similar characteristics as listed in Tab l e 7 -3 . The
buffer type indicates which signaling technology and specifications apply to the signals.
All the differential signals, and selected DDR3 and Control Sideband signals have OnDie Termination (ODT) resistors. There are some signals that do not have ODT and
need to be terminated on the board.
Table 7-3.Signal Groups (Sheet 1 of 2)
Signal GroupTypeSi gnals
System Reference Clock
DifferentialCMOS InputBCLK[0], BCLK#[0]
DDR3 Reference Clocks
DifferentialDDR3 Output
DDR3 Command Signals
Single EndedDDR3 Output
DDR3 Data Signals
Single ended DDR3 Bi-directionalSA_DQ[63:0], SB_DQ[63:0]
DifferentialDDR3 Bi-directional
TAP (ITP/XDP)
Single EndedCMOS InputTCK, TDI, TMS, TRST#
Single EndedCMOS OutputTDO
Single EndedAsynchronous CMOS Output TAPPWRGOOD
Control Sideband
Single EndedCMOS InputCFG[17:0]
Single Ended
Single EndedAsynchronous CMOS Output THERMTRIP#, CATERR#
Single EndedAsynchronous CMOS Input
Single EndedAsynchronous Bi-directionalPECI
Single Ended
Power/Ground/Other
2
2
2
Asynchronous CMOS/Open
Drain Bi-directional
CMOS Input
Open Drain Output
Bi-directional CMOS Input
/Open Drain Output
PowerVCC, VCC_NCTF, VCCIO, VCCPLL, VDDQ, VCCAXG
GroundVSS
No Connect and test pointRSVD, RSVD_NCTF, RSVD_TP, FC_x
All Control Sideband Asynchronous signals are required to be asserted/de-asserted for
at least 10 BCLKs with a maximum Trise/Tfall of 6 ns for the processor to recognize
the proper signal state. See Section 7.10 for the DC specifications.
7.8Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, Intel recommends the processor be first in the TAP chain, followed by any other
components within the system. A translation buffer should be used to connect to the
rest of the chain unless one of the other components is capable of accepting an input of
the appropriate voltage. Two copies of each signal may be required with each driving a
different voltage level.
The processor supports Boundary Scan (JTAG) IEEE 1149.1-2001 and IEEE 1149.62003 standards. Some small portion of the I/O pins may support only one of these
standards.
78Datasheet, Volume 1
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Electrical Specifications
7.9Storage Conditions Specifications
Environmental storage condition limits define the temperature and relative humidity
that the device is exposed to while being stored in a moisture barrier bag. The specified
storage conditions are for component level prior to board attach.
Ta b le 7 -4 specifies absolute maximum and minimum storage temperature limits that
represent the maximum or minimum device condition beyond which damage, latent or
otherwise, may occur. The table also specifies sustained storage temperature, relative
humidity, and time-duration limits. These limits specify the maximum or minimum
device storage conditions for a sustained period of time. Failure to adhere to the
following specifications can affect long term reliability of the processor.
Table 7-4.Storage Condition Ratings
SymbolParameterMinMaxNotes
The non-operating device storage
T
absolute storage
T
sustained storage
T
short term storage
RH
sustained storage
Time
sustained storage
Time
short term storage
temperature. Damage (latent or otherwise)
may occur when exceeded for any length of
time.
The ambient storage temperature (in
shipping media) for a sustained period of time
The ambient storage temperature (in
shipping media) for a short period of time.
The maximum device storage relative
humidity for a sustained period of time.
A prolonged or extended period of time;
typically associated with customer shelf life.
A short-period of time.0 hours72 hours
-25 °C125 °C1, 2, 3, 4
-5 °C40 °C5, 6
-20°C85°C
60% at 24 °C6, 7
0 Months30 Months7
Notes:
1.Refers to a component device that is not assembled in a board or socket and is not electrically connected to
a voltage reference or I/O signal.
2.Specified temperatures are not to exceed values based on data collected. Exceptions for surface mount
reflow are specified by the applicable JEDEC standard. Non-adherence may affect processor reliability.
3.T
absolute storage
moisture barrier bags, or desiccant.
4.Component product device storage temperature qualification methods may follow JESD22-A119 (low temp)
and JESD22-A103 (high temp) standards when applicable for volatile memory.
5.Intel branded products are specified and certified to meet the following temperature and humidity limits
that are given as an example only (Non-Operating Temperature Limit: -40 °C to 70 °C and Humidity: 50%
to 90%, non-condensing with a maximum wet bulb of 28 °C.) Post board attach storage temperature limits
are not specified for non-Intel branded boards.
6.The JEDEC J-JSTD-020 moisture level rating and associated handling practices apply to all moisture
sensitive devices removed from the moisture barrier bag.
7.Nominal temperature and humidity conditions and durations are given and tested within the constraints
imposed by T
applies to the unassembled component only and does not apply to the shipping media,
sustained storage
and customer shelf life in applicable Intel boxes and bags.
Datasheet, Volume 179
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Electrical Specifications
7.10DC Specifications
The processor DC specifications in this section are defined at the processor
pads, unless noted otherwise. See Chapter 8 for the processor land listings and
Chapter 6 for signal definitions. Voltage and current specifications are detailed in
Tab l e 7 -5 , Tab le 7 - 6, and Ta bl e 7 -7 .
The DC specifications for the DDR3 signals are listed in Tab l e 7 -8 Control Sideband and
Test Access Port (TAP) are listed in Ta b le 7 -9 .
Tab l e 7 -5 through Tab le 7 - 7 list the DC specifications for the processor and are valid
only while meeting the thermal specifications (as specified in the Thermal / Mechanical
Specifications and Guidelines), clock frequency, and input voltages. Care should be
taken to read all notes associated with each parameter.
7.10.1Voltage and Current Specifications
Table 7-5.Processor Core Active and Idle Mode DC Voltage and Current Specifications
2011D, 2011C, 2011B (processors
with 95 W, 65 W, and 45 W TDPs)
TOB
VCC
TOB
PS0
PS1
PS2
Ripple:
2011D, 2011C, 2011B (processors
with 95 W, 65 W, and 45 W TDPs)
PS0
PS1
PS2
VCC Loadline Slope
2011A (processors with 35 W TDP)
V
Tolerance Band
CC
2011A (processors with 35 W TDP)
PS0
PS1
PS2
Ripple:
2011A (processors with 35 W TDP)
PS0
PS1
PS2
Default V
power up
2011D (processors with 95 W
TDPs) I
2011C (processors with 65 W TDP)
I
CC
voltage for initial
CC
CC
1.7mΩ3, 5, 6
3, 5, 6,
±16
±13
±11.5
±7
±10
-10/+25
2.9mΩ
19
19
11.5
±10
±10
-10/+25
—0 —V
——112A4
——75A4
mV
mV
mV
mV
3, 5, 6,
3, 5, 6,
3, 5, 6,
7, 8
3, 5, 6,
7, 8
1
7
7
8
80Datasheet, Volume 1
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Electrical Specifications
Table 7-5.Processor Core Active and Idle Mode DC Voltage and Current Specifications
(Sheet 2 of 2)
SymbolParameterMinTypMaxUnitNote
I
CC
I
CC
I
CC_TDC
I
CC_TDC
I
CC_TDC
I
CC_TDC
Notes:
1.Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical
data. These specifications will be updated with characterized data from silicon measurements at a later
date.
2.Each processor is programmed with a maximum valid voltage identification value (VID) that is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Adaptive
Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).
3.The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the
socket with a 20-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-MΩ minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external
noise from the system is not coupled into the oscilloscope probe.
4.ICC_MAX specification is based on the V
5.The V
6.The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and
VSS_SENSE lands.
7.PSx refers to the voltage regulator power state as set by the SVID protocol.
8.2011A (processors with 35 W TDP) loadline slope, TOB, and ripple specifications allow for a cost reduced
voltage regulator for boards supporting only the 2011A (processors with 35 W TDP). 2011A (processors
with 35 W TDP) processors may also use the loadline slope, TOB, and ripple specifications for the 2011D
(processors with 95 W TDP), 2011C (processors with 65 W TDP), and 2011B (processors with 45 W TDP).
2011B (processors with 45 W TDP)
I
CC
2011A (processors with 35 W TDP)
I
CC
2011D (processors with 95 W
TDPs) Sustained I
2011C (processors with 65 W TDP)
Sustained I
2011B (processors with 45 W TDP)
Sustained I
CC
CC
CC
2011A (processors with 35 W TDP)
Sustained I
specifications represent static and transient limits.
CC
CC
loadline at worst case (highest) tolerance and ripple.
CC
——60A4
——35A4
——85A4
——55A4
——40A4
——25A4
1
Datasheet, Volume 181
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Electrical Specifications
Table 7-6.Processor System Agent I/O Buffer Supply DC Voltage and Current
Specifications
SymbolParameterMinTypMaxUnitNote
V
CCSA
V
DDQ
V
CCPLL
V
CCIO
I
SA
I
SA_TDC
I
DDQ
I
DDQ_TDC
I
DDQ_STANDBY
I
CC_VCCPLL
I
CC_VCCPLL_TDC
I
CC_VCCIO
I
CC_VCCIO_TDC
Voltage for the system agent0.8790.9250.971V2
Processor I/O supply voltage for
DDR3
PLL supply voltage (DC + AC
specification)
Processor I/O supply voltage for
other than DDR3
1.4251.51.575V
1.711.81.89V
-2/-3%1.05+2/+3%V3
Current for the system agent——8.8A
Sustained current for the system
agent
Processor I/O supply current for
DDR3
Processor I/O supply sustained
current for DDR3
Processor I/O supply standby
current for DDR3
——8.2A
——4.75A
——4.75A
—— 1A
PLL supply current——1.5A
PLL sustained supply current——0.93A
Processor I/O supply current——8.5A
Processor I/O supply sustained
current
——8.5A
1
Notes:
1.Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical
data. These specifications will be updated with characterized data from silicon measurements at a later
date.
2.V
3.±5% total. Minimum of ±2% DC and 3% AC at the sense point. di/dt = 50 A/us with 150 ns step.
must be provided using a separate voltage source and not be connected to VCC. This specification is
CCSA
measured at VCCSA_SENSE.
82Datasheet, Volume 1
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Electrical Specifications
Table 7-7.Processor Graphics VID based (V
Specifications
SymbolParameterMinTypMaxUnitNote
V
GFX_VID
AXG
Range
LL
AXG
TOB
V
AXG
V
Ripple
AXG
I
AXG
I
AXG_TDC
Notes:
1.V
2.Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical
3.The V
4.The loadlines specify voltage limits at the die measured at the VAXG_SENSE and VSSAXG_SENSE lands.
5.PSx refers to the voltage regulator power state as set by the SVID protocol.
6.Each processor is programmed with a maximum valid voltage identification value (VID) that is set at
is VID based rail.
CCAXG
data. These specifications will be updated with characterized data from silicon measurements at a later
date.
AXG_MIN
Voltage regulation feedback for voltage regulator circuits must also be taken from processor VAXG_SENSE
and VSSAXG_SENSE lands.
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Adaptive
Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).
GFX_VID Range for V
V
Loadline Slope4.1mΩ3, 4
CCAXG
Tolerance Band
V
CC
CCAXG
PS0, PS1
PS2
Ripple:
PS0
PS1
PS2
Current for Processor Graphics
core
Sustained current for Processor
Graphics core
and V
loadlines represent static and transient limits.
AXG_MAX
) Supply DC Voltage and Current
AXG
0.2500—1.5200V1
19
11.5
±10
±10
-10/+15
——35 A
——25 A
2
mV3, 4, 5
mV3, 4, 5
Datasheet, Volume 183
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Electrical Specifications
Table 7-8.DDR3 Signal Group DC Specifications
SymbolParameterMinTypMaxUnits Notes
V
IL
V
IH
V
OL
V
OH
R
ON_UP(DQ)
R
ON_DN(DQ)
R
ODT(DQ)
V
ODT(DC)
R
ON_UP(CK)
R
ON_DN(CK)
R
ON_UP(CMD)
R
ON_DN(CMD)
R
ON_UP(CTL)
R
ON_DN(CTL)
V
IL_SM_DRAMP
WROK
V
IH_SM_DRAMP
WROK
I
LI
I
LI
Input Low Voltage——SM_VREF – 0.1V2,4
Input High VoltageSM_VREF + 0.1——V3
Output Low Voltage
Output High Voltage
—
—
(V
/ 2)* (R
DDQ
/(RON+R
V
– ((V
DDQ
(RON/(RON+R
DDQ
TERM
ON
))
/ 2)*
TERM
—6
))
—V4,6
DDR3 data buffer pull-up resistance24.3128.632.9Ω5
DDR3 data buffer pull-down
resistance
DDR3 on-die termination equivalent
resistance for data signals
22.8828.634.32Ω5
83
41.5
100
50
117
65
Ω7
DDR3 on-die termination DC
working point (driver set to receive
mode)
DDR3 clock buffer pull-up
resistance
DDR3 clock buffer pull-down
resistance
DDR3 command buffer pull-up
resistance
DDR3 command buffer pull-down
resistance
DDR3 control buffer pull-up
resistance
DDR3 control buffer pull-down
resistance
Input Low Voltage for
SM_DRAMPWROK
Input High Voltage for
SM_DRAMPWROK
0.43*V
DDQ
0.5*V
DDQ
20.82628.6Ω5
20.82631.2Ω5
162023Ω5
162024Ω5
162023Ω5
162024Ω5
——V
*.55 +0.1——V9
V
DDQ
0.56*V
CC
*.55 – 0.1V9
DDQ
V7
Input Leakage Current (DQ, CK)
0V
0.2*V
0.8*V
V
DDQ
DDQ
DDQ
——
± 0.75
± 0.55
± 0.9
± 1.4
mA
Input Leakage Current (CMD, CTL)
0V
0.2*V
0.8*V
V
DDQ
DDQ
DDQ
——
± 0.85
± 0.65
± 1.1
± 1.65
mA
1,9
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
2.V
IL
value.
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
3.V
IH
value.
4.V
and VOH may experience excursions above V
IH
signal quality specifications.
5.This is the pull up/down driver resistance.
6.R
7.The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.
8.DDR3 values are pre-silicon estimations and subject to change.
9.SM_DRAMPWROK must have a maximum of 15 ns rise or fall time over V
is the termination on the DIMM and in not controlled by the processor.
TERM
must be monotonic.
. However, input signal drivers must comply with the
DDQ
* 0.55 ±200 mV and edge
DDQ
84Datasheet, Volume 1
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Electrical Specifications
Table 7-9.Control Sideband and TAP Signal Group DC Specifications
SymbolParameterMinMaxUnitsNotes
V
V
V
V
R
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.The V
3.For V
4.V
Input Low Voltage—V
IL
Input High VoltageV
IH
Output Low Voltage—V
OL
Output High VoltageV
OH
Buffer on Resistance2373Ω
ON
I
Input Leakage Current—±200μA3
LI
referred to in these specifications refers to instantaneous V
CCIO
between “0” V and V
IN
and VOH may experience excursions above V
IH
signal quality specifications.
. Measured when the driver is tristated.
CCIO
* 0.7—V2, 4
CCIO
* 0.9—V2, 4
CCIO
CCIO
* 0.3V2
CCIO
* 0.1V2
CCIO
.
CCIO
. However, input signal drivers must comply with the
Table 7-10. PCI Express* DC Specifications
SymbolParameterMinTypMaxUnitsNotes
V
TX-DIFF-p-p Low
V
TX-DIFF-p-p
V
TX_CM-AC-p
V
TX_CM-AC-p-p
Z
TX-DIFF-DC
Z
RX-DC
Z
RX-DIFF-DC
V
RX-DIFFp-p
V
RX-DIFFp-p
V
RX_CM-AC-p
PEG_ICOMPOComp Resistance24.752525.25Ω4, 5
PEG_COMPIComp Resistance24.752525.25Ω4, 5
PEG_RCOMPOComp Resistance24.752525.25Ω4, 5
Notes:
1.Refer to the PCI Express Base Specification for more details.
2.V
TX-AC-CM-PP
at least 10^
3.As measured with compliance test load. Defined as 2*|V
4.COMP resistance must be provided on the system board with 1% resistors.
5.PEG_ICOMPO, PEG_COMPI, PEG_RCOMPO are the same resistor.
6.RMS value.
7.Measured at Rx pins into a pair of 50-Ω terminations into ground. Common mode peak voltage is defined by
the expression: max{|(Vd+ - Vd-) - V-CMDC|}.
8.DC impedance limits are needed to ensure Receiver detect.
9.The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to
ensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediately
and the 15 Rx Common Mode Impedance (constrained by RLRX-CM to 50 Ω ±20%) must be within the
specified range by the time Detect is entered.
10. Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.
11. These are pre-silicon estimates and are subject to change.
Low differential peak to peak Tx voltage
swing
0.40.50.6V3
Differential peak to peak Tx voltage swing0.811.2V3
Tx AC Peak Common Mode Output
Voltage (Gen1 only)
Tx AC Peak Common Mode Output
Voltage (Gen2 only)
——20mV1, 2, 6
——100mV1, 2
DC Differential Tx Impedance (Gen1 only)8090120Ω1, 10
DC Common Mode Rx Impedance404560Ω1, 8, 9
DC Differential Rx Impedance (Gen1 only)8090120Ω1
Differential Rx input Peak to Peak Voltage
(Gen1 only)
Differential Rx input Peak to Peak Voltage
(Gen2 only)
0.175—1.2V1
0.12—1.2V1
Rx AC peak Common Mode Input Voltage150——mV1, 7
and V
6
UI.
TX-AC-CM-P
are defined in the PCI Express Base Specification. Measurement is made over
– V
TXD+
TXD-
|.
1
1,11
Datasheet, Volume 185
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Electrical Specifications
7.11Platform Environmental Control Interface (PECI)
DC Specifications
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and chipset components to external thermal monitoring devices. The
processor contains a Digital Thermal Sensor (DTS) that reports a relative die
temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Temperature sensors located throughout the die are implemented as analog-to-digital
converters calibrated at the factory. PECI provides an interface for external devices to
read the DTS temperature for thermal management and fan speed control. More
detailed information is provided in the Platform Environment Control Interface (PECI) Specification.
7.11.1PECI Bus Architecture
The PECI architecture based on wired OR bus that the clients (as processor PECI) can
pull up high (with strong drive).
The idle state on the bus is near zero.
Figure 7-1 demonstrates PECI design and connectivity, while the host/originator can be
3rd party PECI host, and one of the PECI clients is the processor PECI device.
Figure 7-1. Example for PECI Host-clients Connection
86Datasheet, Volume 1
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Electrical Specifications
PECI High Range
PECI Low Range
Valid Input
Signal Range
Minimum
Hysteresis
V
TTD
Maximum V
P
Minimum V
P
Maximum V
N
Minimum V
N
PECI Ground
7.11.2DC Characteristics
The PECI interface operates at a nominal voltage set by V
specifications shown in Ta b le 7 - 11 is used with devices normally operating from a V
interface supply. V
nominal levels will vary between processor families. All PECI
CCIO
devices will operate at the V
system. For specific nominal V
Table 7-11. PECI DC Electrical Limits
SymbolDefinition and ConditionsM inMaxUnitsNotes
Rup
V
V
hysteresis
V
V
C
bus
Cpad
Ileak000leakage current at 0V—0.6mA2
Ileak025leakage current at 0.25*V
Ileak050leakage current at 0.50*V
Ileak075leakage current at 0.75*V
Ileak100leakage current at V
Notes:
1.V
CCIO
2.The leakage specification applies to powered devices on the PECI bus.
3.The PECI buffer internal pull up resistance measured at 0.75*V
Internal pull up resistance1545Ohm3
Input Voltage Range-0.15V
in
Hysteresis0.1 * V
Negative-Edge Threshold Voltage0.275 * V
n
Positive-Edge Threshold Voltage0.550 * V
p
Bus Capacitance per NodeN/A10pF
Pad Capacitance0.71.8pF
supplies the PECI interface. PECI behavior does not affect V
. The set of DC electrical
CCIO
level determined by the processor installed in the
CCIO
levels, refer to Tab l e 7 -6 .
CCIO
CCIO
N/AV
0.500 * V
0.725 * V
CCIO
CCIO
CCIO
CCIO
min/max specifications.
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
—0.4mA2
—0.2mA2
—0.13mA2
—0.10mA2
CCIO
1
V
V
V
7.11.3Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use Figure 7-2 as a guide for input buffer design.
Figure 7-2. Input Device Hysteresis
Datasheet, Volume 187
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Electrical Specifications
88Datasheet, Volume 1
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Processor Pin and Signal Information
8Processor Pin and Signal
Information
8.1Processor Pin Assignments
The processor pinmap quadrants are shown in Figure 8-1 through Figure 8-4. Tab le 8 - 1
provides a listing of all processor pins ordered alphabetically by pin name.