Intel Core i7-2600, Core i7-2700K, Core i5-2550K, Core i5-2500K, Core i5-2500S Datasheet
...
2nd Generation Intel® Core™
Processor Family Desktop, Intel
®
Pentium
Processor Family Desktop,
®
and Intel
Celeron® Processor
Family Desktop
Datasheet, Volume 1
Supporting Intel® Core™ i7, i5, and i3 Desktop Processor Series
®
Supporting Intel
Supporting Intel
This is Volume 1 of 2
June 2013
Pentium® Processor G800 and G600 Series
®
Celeron® Processor G500 and G400 Series
®
Document Number: 324641-008
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®
SpeedStep® Technology See the Processor Spec Finder or contact your Intel representative for more information.
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®
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2 Datasheet, Volume 1
Contents
1Introduction..............................................................................................................9
1.1 Processor Feature Details ................................................................................... 11
1.1.1 Supported Technologies .......................................................................... 11
1.2 Interfaces ........................................................................................................ 11
1.2.1 System Memory Support ......................................................................... 11
1.2.2 PCI Express* ......................................................................................... 12
1.2.3 Direct Media Interface (DMI).................................................................... 13
1.2.4 Platform Environment Control Interface (PECI)........................................... 14
1.2.5 Processor Graphics ................................................................................. 14
1.2.6 Intel
1.3 Power Management Support ............................................................................... 15
1.3.1 Processor Core....................................................................................... 15
1.3.2 System ................................................................................................. 15
1.3.3 Memory Controller.................................................................................. 15
1.3.4 PCI Express* ......................................................................................... 15
1.3.5 Direct Media Interface (DMI).................................................................... 15
1.3.6 Processor Graphics Controller................................................................... 15
1.4 Thermal Management Support ............................................................................ 15
1.5 Package ........................................................................................................... 16
1.6 Terminology ..................................................................................................... 16
1.7 Related Documents ........................................................................................... 18
2Interfaces................................................................................................................ 19
2.1 System Memory Interface .................................................................................. 19
2.1.1 System Memory Technology Supported ..................................................... 19
2.1.2 System Memory Timing Support............................................................... 21
2.1.3 System Memory Organization Modes......................................................... 21
2.1.4 Rules for Populating Memory Slots............................................................ 22
2.1.5 Technology Enhancements of Intel
2.1.6 Memory Type Range Registers (MTRRs) Enhancement................................. 23
2.1.7 Data Scrambling .................................................................................... 23
2.2 PCI Express* Interface....................................................................................... 24
2.2.1 PCI Express* Architecture ....................................................................... 24
2.2.2 PCI Express* Configuration Mechanism ..................................................... 26
2.2.3 PCI Express* Port................................................................................... 26
2.2.4 PCI Express* Lanes Connection................................................................ 27
2.3 Direct Media Interface (DMI)............................................................................... 27
2.3.1 DMI Error Flow....................................................................................... 27
2.3.2 Processor / PCH Compatibility Assumptions................................................ 27
2.3.3 DMI Link Down ...................................................................................... 28
2.4 Processor Graphics Controller (GT) ...................................................................... 28
2.4.1 3D and Video Engines for Graphics Processing............................................ 29
®
Flexible Display Interface (Intel® FDI) ............................................. 14
2.1.3.1 Single-Channel Mode................................................................. 21
2.1.3.2 Dual-Channel Mode – Intel
2.1.5.1 Just-in-Time Command Scheduling.............................................. 23
2.1.5.2 Command Overlap .................................................................... 23
2.1.5.3 Out-of-Order Scheduling............................................................ 23
2.2.1.1 Transaction Layer ..................................................................... 25
2.2.1.2 Data Link Layer ........................................................................ 25
2.2.1.3 Physical Layer .......................................................................... 25
2.4.1.1 3D Engine Execution Units ......................................................... 29
®
Flex Memory Technology Mode ........... 21
®
Fast Memory Access (Intel® FMA).......... 23
Datasheet, Volume 1 3
2.4.1.2 3D Pipeline...............................................................................29
2.4.1.3 Video Engine ............................................................................30
2.4.1.4 2D Engine ................................................................................30
2.4.2 Processor Graphics Display ......................................................................31
2.4.2.1 Display Planes ..........................................................................31
2.4.2.2 Display Pipes ............................................................................32
2.4.2.3 Display Ports ............................................................................32
2.4.3 Intel
®
Flexible Display Interface (Intel® FDI) .............................................32
2.4.4 Multi-Graphics Controller Multi-Monitor Support ..........................................32
2.5 Platform Environment Control Interface (PECI) ......................................................33
2.6 Interface Clocking..............................................................................................33
2.6.1 Internal Clocking Requirements ................................................................33
3 Technologies............................................................................................................35
3.1 Intel® Virtualization Technology (Intel® VT) ..........................................................35
3.1.1 Intel® Virtualization Technology (Intel® VT) for
3.1.2 Intel® Virtualization Technology (Intel® VT) for
3.1.3 Intel
3.1.4 Intel
3.1.5 Intel
3.2 Intel
IA-32, Intel
(Intel
IA-32, Intel
(Intel
®
I/O (Intel
®
I/O (Intel
®
I/O (Intel
®
Trusted Execution Technology (Intel® TXT) .................................................38
®
®
®
Virtualization Technology (Intel® VT) for Directed
Virtualization Technology (Intel® VT) for Directed
Virtualization Technology (Intel® VT) for Directed
64 and Intel® Architecture
VT-x) Objectives..........................................................................35
®
64 and Intel® Architecture
VT-x) Features ............................................................................36
®
VT-d) Objectives ....................................................................36
®
VT-d) Features.......................................................................37
®
VT-d) Features Not Supported..................................................37
3.3 Intel® Hyper-Threading Technology (Intel® HT Technology) ....................................38
3.4 Intel® Turbo Boost Technology ............................................................................39
3.4.1 Intel
®
Turbo Boost Technology Frequency..................................................39
3.4.2 Intel® Turbo Boost Technology Graphics Frequency.....................................39
3.5 Intel® Advanced Vector Extensions (Intel® AVX)....................................................40
3.6 Intel
®
Advanced Encryption Standard New Instructions (Intel® AES-NI) ...................40
3.6.1 PCLMULQDQ Instruction ..........................................................................40
3.7 Intel® 64 Architecture x2APIC .............................................................................40
4 Power Management .................................................................................................43
4.1 Advanced Configuration and Power Interface (ACPI) States Supported......................44
4.1.1 System States........................................................................................44
4.1.2 Processor Core / Package Idle States.........................................................44
4.1.3 Integrated Memory Controller States.........................................................44
4.1.4 PCI Express* Link States .........................................................................44
4.1.5 Direct Media Interface (DMI) States ..........................................................45
4.1.6 Processor Graphics Controller States .........................................................45
4.1.7 Interface State Combinations ...................................................................45
4.2 Processor Core Power Management......................................................................46
4.2.1 Enhanced Intel
®
SpeedStep® Technology ..................................................46
4.2.2 Low-Power Idle States.............................................................................46
4.2.3 Requesting Low-Power Idle States ............................................................48
4.2.4 Core C-states .........................................................................................48
4.2.4.1 Core C0 State ...........................................................................48
4.2.4.2 Core C1/C1E State ....................................................................49
4.2.4.3 Core C3 State ...........................................................................49
4.2.4.4 Core C6 State ...........................................................................49
4.2.4.5 C-State Auto-Demotion..............................................................49
4.2.5 Package C-States ...................................................................................50
4 Datasheet, Volume 1
4.2.5.1 Package C0.............................................................................. 51
4.2.5.2 Package C1/C1E ....................................................................... 51
4.2.5.3 Package C3 State...................................................................... 52
4.2.5.4 Package C6 State...................................................................... 52
4.3 Integrated Memory Controller (IMC) Power Management ........................................ 52
4.3.1 Disabling Unused System Memory Outputs ................................................ 52
4.3.2 DRAM Power Management and Initialization............................................... 53
4.3.2.1 Initialization Role of CKE............................................................ 54
4.3.2.2 Conditional Self-Refresh ............................................................ 54
4.3.2.3 Dynamic Power-down Operation ................................................. 55
4.3.2.4 DRAM I/O Power Management.................................................... 55
4.4 PCI Express* Power Management ........................................................................ 55
4.5 Direct Media Interface (DMI) Power Management .................................................. 55
4.6 Graphics Power Management .............................................................................. 56
4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM)
(also known as CxSR) ............................................................................. 56
4.6.2 Intel
4.6.3 Graphics Render C-State ......................................................................... 56
4.6.4 Intel
®
Graphics Performance Modulation Technology (Intel® GPMT) .............. 56
®
Smart 2D Display Technology (Intel® S2DDT) .................................. 56
4.6.5 Intel® Graphics Dynamic Frequency.......................................................... 57
4.7 Thermal Power Management............................................................................... 57
5 Thermal Management.............................................................................................. 59
6 Signal Description ................................................................................................... 61
6.1 System Memory Interface Signals........................................................................ 62
6.2 Memory Reference and Compensation Signals ....................................................... 63
6.3 Reset and Miscellaneous Signals.......................................................................... 64
6.4 PCI Express*-Based Interface Signals .................................................................. 65
6.5 Intel® Flexible Display Interface (Intel® FDI) Signals ............................................. 65
6.6 Direct Media Interface (DMI) Signals.................................................................... 66
6.7 Phase Lock Loop (PLL) Signals ............................................................................ 66
6.8 Test Access Points (TAP) Signals ......................................................................... 66
6.9 Error and Thermal Protection Signals ................................................................... 67
6.10 Power Sequencing Signals .................................................................................. 67
6.11 Processor Power Signals..................................................................................... 68
6.12 Sense Signals ................................................................................................... 68
6.13 Ground and Non-Critical to Function (NCTF) Signals............................................... 68
6.14 Processor Internal Pull-Up / Pull-Down Resistors.................................................... 69
7 Electrical Specifications........................................................................................... 71
7.1 Power and Ground Lands.................................................................................... 71
7.2 Decoupling Guidelines........................................................................................ 71
7.2.1 Voltage Rail Decoupling........................................................................... 71
7.3 Processor Clocking (BCLK[0], BCLK#[0]).............................................................. 72
7.3.1 Phase Lock Loop (PLL) Power Supply......................................................... 72
7.4 V
Voltage Identification (VID) .......................................................................... 72
CC
7.5 System Agent (SA) VCC VID............................................................................... 76
7.6 Reserved or Unused Signals................................................................................ 76
7.7 Signal Groups ................................................................................................... 77
7.8 Test Access Port (TAP) Connection....................................................................... 78
7.9 Storage Conditions Specifications ........................................................................ 79
7.10 DC Specifications .............................................................................................. 80
7.10.1 Voltage and Current Specifications............................................................ 80
7.11 Platform Environmental Control Interface (PECI) DC Specifications........................... 86
7.11.1 PECI Bus Architecture ............................................................................. 86
7.11.2 DC Characteristics .................................................................................. 87
Datasheet, Volume 1 5
7.11.3 Input Device Hysteresis...........................................................................87
8 Processor Pin and Signal Information ......................................................................89
8.1 Processor Pin Assignments..................................................................................89
9 DDR Data Swizzling................................................................................................109
Figures
1-1 Desktop Platform System Block Diagram Example .......................................................10
2-1 Intel® Flex Memory Technology Operation..................................................................22
2-2 PCI Express* Layering Diagram.................................................................................24
2-3 Packet Flow through the Layers.................................................................................25
2-4 PCI Express* Related Register Structures in the Processor............................................26
2-5 PCI Express* Typical Operation 16 lanes Mapping........................................................27
2-6 Processor Graphics Controller Unit Block Diagram ........................................................28
2-7 Processor Display Block Diagram ...............................................................................31
4-1 Power States ..........................................................................................................43
4-2 Idle Power Management Breakdown of the Processor Cores ..........................................47
4-3 Thread and Core C-State Entry and Exit .....................................................................47
4-4 Package C-State Entry and Exit.................................................................................51
7-1 Example for PECI Host-clients Connection...................................................................86
7-2 Input Device Hysteresis ...........................................................................................87
8-1 Socket Pinmap (Top View, Upper-Left Quadrant) .........................................................90
8-2 Socket Pinmap (Top View, Upper-Right Quadrant) .......................................................91
8-3 Socket Pinmap (Top View, Lower-Left Quadrant) .........................................................92
8-4 Socket Pinmap (Top View, Lower-Right Quadrant) .......................................................93
Tables
1-1 PCI Express* Supported Configurations in Desktop Products .........................................12
1-2 Terminology ...........................................................................................................16
1-3 Related Documents .................................................................................................18
2-1 Supported UDIMM Module Configurations ...................................................................20
2-2 Supported SO-DIMM Module Configurations (AIO Only) ................................................20
2-3 DDR3 System Memory Timing Support.......................................................................21
2-4 Reference Clock ......................................................................................................33
4-1 System States ........................................................................................................44
4-2 Processor Core / Package State Support.....................................................................44
4-3 Integrated Memory Controller States .........................................................................44
4-4 PCI Express* Link States..........................................................................................44
4-5 Direct Media Interface (DMI) States...........................................................................45
4-6 Processor Graphics Controller States..........................................................................45
4-7 G, S, and C State Combinations ................................................................................45
4-8 Coordination of Thread Power States at the Core Level.................................................47
4-9 P_LVLx to MWAIT Conversion....................................................................................48
4-10 Coordination of Core Power States at the Package Level ...............................................50
6-1 Signal Description Buffer Types.................................................................................61
6-2 Memory Channel A Signals .......................................................................................62
6-3 Memory Channel B Signals .......................................................................................63
6-4 Memory Reference and Compensation........................................................................63
6-5 Reset and Miscellaneous Signals................................................................................64
6-6 PCI Express* Graphics Interface Signals.....................................................................65
6-7 Intel
6-8 Direct Media Interface (DMI) Signals – Processor to PCH Serial Interface ........................66
6-9 Phase Lock Loop (PLL) Signals ..................................................................................66
6-10 Test Access Points (TAP) Signals ...............................................................................66
®
Flexible Display Interface (Intel® FDI) ..............................................................65
6 Datasheet, Volume 1
6-11 Error and Thermal Protection Signals......................................................................... 67
6-12 Power Sequencing Signals........................................................................................ 67
6-13 Processor Power Signals .......................................................................................... 68
6-14 Sense Signals......................................................................................................... 68
6-15 Ground and Non-Critical to Function (NCTF) Signals .................................................... 68
6-16 Processor Internal Pull-Up / Pull-Down Resistors ......................................................... 69
7-1 VR 12.0 Voltage Identification Definition .................................................................... 73
7-2 VCCSA_VID configuration ........................................................................................ 76
7-3 Signal Groups 1...................................................................................................... 77
7-4 Storage Condition Ratings........................................................................................ 79
7-5 Processor Core Active and Idle Mode DC Voltage and Current Specifications.................... 80
7-6 Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications ........... 82
7-7 Processor Graphics VID based (V
) Supply DC Voltage and Current Specifications ........ 83
AXG
7-8 DDR3 Signal Group DC Specifications ........................................................................ 84
7-9 Control Sideband and TAP Signal Group DC Specifications ............................................ 85
7-10 PCI Express* DC Specifications................................................................................. 85
7-11 PECI DC Electrical Limits.......................................................................................... 87
8-1 Processor Pin List by Pin Name ................................................................................. 94
9-1 DDR Data Swizzling Table – Channel A .................................................................... 110
9-2 DDR Data Swizzling Table – Channel B .................................................................... 111
Datasheet, Volume 1 7
Revision History
Revision
Number
001 Initial release
•Added Intel® Core™ i5-2405S, i5-2310, and i3-2105 processors
002
•Added Intel
Pentium
•Added Intel® Core™ i5-2320, i3-2125, i3-2130, and i3-2120T
processors
003
•Added Intel
G540, G530, G530T, and G440 processors
•Added Intel
004
005
006
007
008
•Added Intel® Core™ i7-2700K processor
•Added Intel® Celeron® G460 processor
•Added Intel® Core™ i5-2550K, i5-2450P, i5-2380P processors
•Added Intel® Pentium® G645, G645T processors
•Added Intel
•Added Intel® Celeron® G470 processors
Description
®
Pentium® processor family desktop – Intel®
®
G850, G840, G620, and G620T processors
®
Celeron® processor family desktop – Intel® Celeron
®
Pentium® G860, G630, and G630T processors
®
Celeron® G555, G550T, G465 processors
§ §
Revision
Date
January
2011
May 2011
September
2011
October
2011
December
2011
January
2012
September
2012
June 2013
8 Datasheet, Volume 1
Introduction
1 Introduction
The 2nd Generation Intel® Core™ processor family desktop, Intel® Pentium® processor
family desktop, and Intel® Celeron® processor family desktop are the next generation
of 64-bit, multi-core desktop processor built on 32- nanometer process technology.
Based on a new micro-architecture, the processor is designed for a two-chip platform
consisting of a processor and Platform Controller Hub (PCH). The platform enables
higher performance, lower cost, easier validation, and improved x-y footprint. The
processor includes Integrated Display Engine, Processor Graphics, PCI Express* ports,
and Integrated Memory Controller. The processor is designed for desktop platforms. It
supports up to 12 Processor Graphics execution units (EUs). The processor is offered in
an 1155-land LGA package. Figure 1-1 shows an example desktop platform block
diagram.
This document provides DC electrical specifications, signal integrity, differential
signaling specifications, pinout and signal definitions, interface functional descriptions,
thermal specifications, and additional feature information pertinent to the
implementation and operation of the processor on its respective platform.
®
Note: Throughout this document, 2nd Generation Intel
®
Intel
Pentium® processor family desktop, and Intel® Celeron® processor family
Core™ processor family desktop,
desktop may be referred to as simply the processor.
Note: Throughout this document, the Intel
Note: Throughout this document, the Intel
®
Intel
Core™ i7-2700K, i7-2600K, i7-2600S, and i7-2600 processors.
®
Intel
Core™ i5-2550K, i5-2500K, i5-2500S, i5-2500T, i5-2500, i5-2450P, i5-2400,
®
Core™ i7 desktop processor series refers to the
®
Core™ i5 desktop processor series refers to the
i5-2405S, i5-2400S, i5-2390T, i5-2380P, i5-2320, i5-2310, and i5-2300 processors.
Note: Throughout this document, the Intel
®
Intel
Core™ i3-2130, i3-2125, i3-2120, i3-2120T, i3-2105, i3-2100, and i3-2100T
®
Core™ i3 desktop processor series refers to the
processors.
Note: Throughout this document, the Intel
®
Pentium® G870, G860, G860T, G850, G840, G645, G645T, G640, G540T, G630,
Intel
®
Pentium® processor family desktop refers to the
G630T, G620, and G620T processors.
Throughout this document, the Intel
®
Intel
Celeron® G555, G550, G550T, G540, G540T, G530, G530T, G470, G465, G460,
®
Celeron® processor family desktop refers to the
and G440 processors.
®
Note: Throughout this document, the Intel
6 Series Chipset Platform Controller Hub may
also be referred to as “PCH”.
Note: Some processor features are not available on all platforms. Refer to the processor
specification update for details.
Datasheet, Volume 1 9
Figure 1-1. Desktop Platform System Block Diagram Example
I
n
t
e
l
®
F
l
e
x
i
b
l
e
Di
s
p
l
a
y
I
n
t
e
r
f
a
c
e
DMI2 x4
Discrete Graphics
(PEG)
Analog CRT
Gigabit
Network Connection
USB 2.0
Intel® HD Audio
FWH
Super I/O
Serial ATA
DDR3
PCI Express* 2.0
1 x16 or 2x8
8 PCI Express* 2.0 x1
Ports
(5 GT/s)
SPI
Digital Display x 3
PCI Express*
SPI Flash x 2
LPC
SMBUS 2.0
GPIO
LVDS Flat Panel
WiFi / WiMax
Controller Link 1
Processor
PECI
Platform
Controller
Hub (PCH)
Intel®
Management
Engine
PCI
Introduction
10 Datasheet, Volume 1
Introduction
1.1 Processor Feature Details
• Four or two execution cores
• A 32-KB instruction and 32-KB data first-level cache (L1) for each core
• A 256-KB shared instruction/data second-level cache (L2) for each core
• Up to 8-MB shared instruction/data third-level cache (L3), shared among all cores
1.1.1 Supported Technologies
•Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d)
•Intel
•Intel
•Intel
•Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1)
•Intel
•Intel
•Intel® 64 Architecture
• Execute Disable Bit
•Intel
•Intel® Advanced Vector Extensions (Intel® AVX)
•Intel
• PCLMULQDQ Instruction
®
Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel®
Architecture (Intel
®
Active Management Technology 7.0 (Intel® AMT 7.0)
®
Trusted Execution Technology (Intel® TXT)
®
Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
®
Hyper-Threading Technology (Intel® HT Technology)
®
Turbo Boost Technology
®
Advanced Encryption Standard New Instructions (Intel® AES-NI)
®
VT-x)
1.2 Interfaces
1.2.1 System Memory Support
• Two channels of unbuffered DDR3 memory with a maximum of two UDIMMs or SODIMMs (for AIO) per channel
• Single-channel and dual-channel memory organization modes
• Data burst length of eight for all memory organization modes
• Memory DDR3 data transfer rates of 1066 MT/s and 1333 MT/s
• 64-bit wide channels
• DDR3 I/O Voltage of 1.5 V
• The type of memory supported by the processor is dependent on the PCH SKU in
the target platform
— Desktop PCH platforms support non-ECC un-buffered DIMMs only
— All In One platforms (AIO) support SO-DIMMs
• Maximum memory bandwidth of 10.6 GB/s in single-channel mode or 21 GB/s in
dual-channel mode assuming DDR3 1333 MT/s
• 1Gb, 2Gb, and 4Gb DDR3 DRAM technologies are supported
— Using 4Gb device technologies, the largest memory capacity possible is 32 GB,
assuming Dual Channel Mode with four x8 dual ranked unbuffered DIMM
memory configuration.
Datasheet, Volume 1 11
• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank
devices)
• Command launch modes of 1n/2n
• On-Die Termination (ODT)
• Asynchronous ODT
•Intel
®
Fast Memory Access (Intel® FMA)
— Just-in-Time Command Scheduling
—Command Overlap
— Out-of-Order Scheduling
1.2.2 PCI Express*
• PCI Express* port(s) are fully-compliant with the PCI Express Base Specification,
Revision 2.0.
Table 1-1. PCI Express* Supported Configurations in Desktop Products
• Processor with desktop PCH supported configurations
Configuration Organization Desktop
12x8Graphics, I/O
2 1x16 Graphics, I/O
Introduction
• The port may negotiate down to narrower widths
— Support for x16/x8/x4/x1 widths for a single PCI Express mode
• 2.5 GT/s and 5.0 GT/s PCI Express* frequencies are supported
• Gen1 Raw bit-rate on the data pins of 2.5 GT/s, resulting in a real bandwidth per
pair of 250 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on the interface of 4 GB/s in each direction
simultaneously, for an aggregate of 8 GB/s when x16 Gen 1
• Gen 2 Raw bit-rate on the data pins of 5.0 GT/s, resulting in a real bandwidth per
pair of 500 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on the interface of 8 GB/s in each direction
simultaneously, for an aggregate of 16 GB/s when x16 Gen 2
• Hierarchical PCI-compliant configuration mechanism for downstream devices
• Traditional PCI style traffic (asynchronous snooped, PCI ordering)
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express* Enhanced Access Mechanism; accessing the device configuration
space in a flat memory mapped fashion
• Automatic discovery, negotiation, and training of link out of reset
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0
— DMI -> PCI Express* Port 0
12 Datasheet, Volume 1
Introduction
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros)
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status
• PCI Express* reference clock is 100-MHz differential clock
• Power Management Event (PME) functions
• Dynamic width capability
• Message Signaled Interrupt (MSI and MSI-X) messages
• Polarity inversion
Note: The processor does not support PCI Express* Hot-Plug.
1.2.3 Direct Media Interface (DMI)
• DMI 2.0 support
• Four lanes in each direction
• 5 GT/s point-to-point DMI interface to PCH is supported
• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of
500 MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 2 GB/s in each direction
simultaneously, for an aggregate of 4 GB/s when DMI x4
• Shares 100-MHz PCI Express* reference clock
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros)
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Supports the following traffic types to or from the PCH
—DMI -> DRAM
— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)
— Processor core -> DMI
• APIC and MSI interrupt messaging support
— Message Signaled Interrupt (MSI and MSI-X) messages
• Downstream SMI, SCI and SERR error indication
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters
• DC coupling – no capacitors between the processor and the PCH
• Polarity inversion
• PCH end-to-end lane reversal across the link
• Supports Half Swing “low-power/low-voltage”
Datasheet, Volume 1 13
1.2.4 Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master. The processors support the PECI 3.0
Specification.
1.2.5 Processor Graphics
• The Processor Graphics contains a refresh of the sixth generation graphics core
enabling substantial gains in performance and lower power consumption.
• Next Generation Intel Clear Video Technology HD support is a collection of video
playback and enhancement features that improve the end user’s viewing
experience.
— Encode/transcode HD content
— Playback of high definition content including Blu-ray Disc*
— Superior image quality with sharper, more colorful images
— Playback of Blu-ray disc S3D content using HDMI (V.1.4 with 3D)
• DirectX* Video Acceleration (DXVA) support for accelerating video processing
— Full AVC/VC1/MPEG2 HW Decode
• Advanced Scheduler 2.0, 1.0, XPDM support
• Windows* 7, XP, Windows Vista*, OSX, Linux OS Support
• DX10.1, DX10, DX9 support
•OGL 3.0 support
• Switchable graphics support on desktop AIO platforms with MxM solutions only
Introduction
1.2.6 Intel® Flexible Display Interface (Intel® FDI)
• For SKUs with graphics, Intel FDI carries display traffic from the Processor Graphics
in the processor to the legacy display connectors in the PCH
• Based on DisplayPort standard
• Two independent links – one for each display pipe
• Four unidirectional downstream differential transmitter pairs
— Scalable down to 3X, 2X, or 1X based on actual display bandwidth
requirements
— Fixed frequency 2.7 GT/s data rate
• Two sideband signals for Display synchronization
— FDI_FSYNC and FDI_LSYNC (Frame and Line Synchronization)
• One Interrupt signal used for various interrupts from the PCH
— FDI_INT signal shared by both Intel FDI Links
• PCH supports end-to-end lane reversal across both links
• Common 100-MHz reference clock
14 Datasheet, Volume 1
Introduction
1.3 Power Management Support
1.3.1 Processor Core
• Full support of Advanced Configuration and Power Interface (ACPI) C-states as
implemented by the following processor C-states
— C0, C1, C1E, C3, C6
®
• Enhanced Intel SpeedStep
1.3.2 System
• S0, S3, S4, S5
1.3.3 Memory Controller
• Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM))
• Dynamic power-down
1.3.4 PCI Express*
Tec h n ol o gy
• L0s and L1 ASPM power management capability
1.3.5 Direct Media Interface (DMI)
• L0s and L1 ASPM power management capability
1.3.6 Processor Graphics Controller
•Intel® Rapid Memory Power Management (Intel® RMPM) – CxSR
•Intel® Graphics Performance Modulation Technology (Intel® GPMT)
• Intel Smart 2D Display Technology (Intel S2DDT)
• Graphics Render C-State (RC6)
1.4 Thermal Management Support
• Digital Thermal Sensor
• Intel Adaptive Thermal Monitor
• THERMTRIP# and PROCHOT# support
• On-Demand Mode
• Memory Thermal Throttling
• External Thermal Sensor (TS-on-DIMM and TS-on-Board)
• Render Thermal Throttling
• Fan speed control with DTS
Datasheet, Volume 1 15
1.5 Package
• The processor socket type is noted as LGA 1155. The package is a 37.5 x 37.5 mm
Flip Chip Land Grid Array (FCLGA 1155).
Note: See the 2nd Generation Intel
®
Celeron® Processor, and LGA1155 Socket Thermal Mechanical Specifications and
Intel
Design Guidelines for complete details on package.
1.6 Terminology
Table 1-2. Terminology (Sheet 1 of 2)
Term Description
ACPI Advanced Configuration and Power Interface
AIO All In One
BLT Block Level Transfer
CRT Cathode Ray Tube
DDR3 Third-generation Double Data Rate SDRAM memory technology
DMA Direct Memory Access
DMI Direct Media Interface
DP DisplayPort*
DTS Digital Thermal Sensor
Enhanced Intel
SpeedStep
EU Execution Unit
Execute Disable Bit
IMC Integrated Memory Controller
Intel
Intel
Intel
Intel
Technology
Intel
IOV I/O Virtualization
ITPM Integrated Trusted Platform Module
LCD Liquid Crystal Display
LVD S
NCTF
®
Technology
®
64 Technology 64-bit memory extensions to the IA-32 architecture
®
FDI Intel® Flexible Display Interface
®
TXT Intel® Trusted Execution Technology
®
Virtualization
®
VT-d
Technology that provides power management capabilities to laptops.
The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the Intel
Developer's Manuals for more detailed information.
Processor virtualization which when used in conjunction with Virtual Machine
Monitor software enables multiple, robust independent software environments
inside a single platform.
®
Intel
Virtualization Technology (Intel® VT) for Directed I/O. Intel VT-d is a
hardware assist, under system software (Virtual Machine Manager or OS)
control, for enabling I/O device virtualization. Intel VT-d also brings robust
security by providing protection from errant DMAs by using DMA remapping, a
key feature of Intel VT-d.
Low Voltage Differential Signaling. A high speed, low power data transmission
standard used for display connections to LCD panels.
Non-Critical to Function. NCTF locations are typically redundant ground or noncritical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
Introduction
®
Core™ Processor, Intel® Pentium® Processor, and
®
64 and IA-32 Architectures Software
16 Datasheet, Volume 1
Introduction
Table 1-2. Terminology (Sheet 2 of 2)
Term Description
Platform Controller Hub. The new, 2009 chipset with centralized platform
PCH
PECI Platform Environment Control Interface
PEG
Processor The 64-bit, single-core or multi-core component (package).
Processor Core
Processor Graphics Intel
Rank
SCI System Control Interrupt. Used in ACPI protocol.
Storage Conditions
TAC Thermal Averaging Constant.
TAP Test Access Point
TDP Thermal Design Power.
V
AXG
V
CC
V
CCIO
V
CCPLL
V
CCSA
V
DDQ
VLD Variable Length Decoding.
V
SS
x1 Refers to a Link or Port with one Physical Lane.
x16 Refers to a Link or Port with sixteen Physical Lanes.
x4 Refers to a Link or Port with four Physical Lanes.
x8 Refers to a Link or Port with eight Physical Lanes.
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features.
PCI Express* Graphics. External Graphics using PCI Express* Architecture. A
high-speed serial interface whose configuration is software compatible with the
existing PCI specifications.
The term “processor core” refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
®
Processor Graphics
A unit of DRAM corresponding four to eight devices in parallel. These devices are
usually, but not always, mounted on a single side of a SO-DIMM.
A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to free air. Under
these conditions, processor landings should not be connected to any supply
voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air”
(that is, unsealed packaging or a device removed from packaging material) the
processor must be handled in accordance with moisture sensitivity labeling
(MSL) as indicated on the packaging material.
Graphics core power supply.
Processor core power supply.
High Frequency I/O logic power supply
PLL power supply
System Agent (memory controller, DMI, PCIe controllers, and display engine)
power supply
DDR3 power supply.
Processor ground.
Datasheet, Volume 1 17
1.7 Related Documents
Refer to Ta bl e 1 -3 for additional information.
Table 1-3. Related Documents
Document Document Number/ Location
2nd Generation Intel
Processor Family Desktop, and Intel
Datasheet, Volume 2
2nd Generation Intel
Processor Family Desktop, and Intel
Specification Update
2nd Generation Intel
Processor Family Desktop, and Intel
and LGA1155 Socket Thermal Mechanical Specifications and Design
Guidelines
®
6 Series Chipset and Intel® C200 Series Chipset Datasheet www.intel.com/Assets/PDF/datas
Intel
®
Intel
6 Series Chipset and Intel® C200 Series Chipset Thermal
Mechanical Specifications and Design Guidelines
Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info/
PCI Local Bus Specification 3.0 http://www.pcisig.com/specifica-
®
Intel
TXT Measured Launched Environment Developer’s Guide http://www.intel.com/technology
®
Intel
64 Architecture x2APIC Specification http://www.intel.com/products/pr
PCI Express* Base Specification 2.0 http://www.pcisig.com
DDR3 SDRAM Specification http://www.jedec.org
DisplayPort* Specification http://www.vesa.org
®
Intel
64 and IA-32 Architectures Software Developer's Manuals http://www.intel.com/products/pr
Volume 1: Basic Architecture 253665
Volume 2A: Instruction Set Reference, A-M 253666
Volume 2B: Instruction Set Reference, N-Z 253667
Volume 3A: System Programming Guide 253668
Volume 3B: System Programming Guide 253669
®
Core™ Processor Family Desktop, Intel®Pentium®
®
Core™ Processor Family Desktop, Intel®Pentium®
®
Core™ Processor Family Desktop, Intel®Pentium®
®
Celeron® Processor Family Desktop
®
Celeron® Processor Family Desktop
®
Celeron® Processor Family Desktop,
Introduction
http://download.intel.com/design
/processor/datashts/324642.pdf
http://download.intel.com/design
/processor/specupdt/324643.pdf
http://download.intel.com/design
/processor/designex/324644.pdf
heet/324645.pdf
www.intel.com/Assets/PDF/desig
nguide/324647.pdf
tions
/security
ocessor/manuals/
ocessor/manuals/index.htm
§ §
18 Datasheet, Volume 1
Interfaces
2 Interfaces
This chapter describes the interfaces supported by the processor.
2.1 System Memory Interface
2.1.1 System Memory Technology Supported
The Integrated Memory Controller (IMC) supports DDR3 protocols with two
independent, 64-bit wide channels each accessing one or two DIMMs. The type of
memory supported by the processor is dependant on the PCH SKU in the target
platform. Refer to Chapter 1 for supported memory configuration details.
It supports a maximum of two DDR3 DIMMs per-channel; thus, allowing up to four
device ranks per-channel.
• DDR3 Data Transfer Rates
— 1066 MT/s (PC3-8500), 1333 MT/s (PC3-10600)
• DDR3 SO-DIMM Modules
— Raw Card A – Dual Ranked x16 unbuffered non-ECC
— Raw Card B – Single Ranked x8 unbuffered non-ECC
— Raw Card C – Single Ranked x16 unbuffered non-ECC
— Raw Card F – Dual Ranked x8 (planar) unbuffered non-ECC
• Desktop PCH platform DDR3 DIMM Modules
— Raw Card A – Single Ranked x8 unbuffered non-ECC
— Raw Card B – Dual Ranked x8 unbuffered non-ECC
— Raw Card C – Single Ranked x16 unbuffered non-ECC
• Advanced Server/Workstation PCH platforms DDR3 DIMM Modules:
— Raw Card A – Single Ranked x8 unbuffered non-ECC
— Raw Card B – Dual Ranked x8 unbuffered non-ECC
— Raw Card C – Single Ranked x16 unbuffered non-ECC
— Raw Card D – Single Ranked x8 unbuffered ECC
— Raw Card E – Dual Ranked x8 unbuffered ECC
• Essential/Standard Server PCH platforms DDR3 DIMM Modules:
— Raw Card D – Single Ranked x8 unbuffered ECC
— Raw Card E – Dual Ranked x8 unbuffered ECC
DDR3 DRAM Device Technology: 1-Gb, 2-Gb, and 4 Gb DDR3 DRAM Device
technologies and addressing are supported.
Datasheet, Volume 1 19
Table 2-1. Supported UDIMM Module Configurations
Interfaces
Raw
Card
Version
A
B
C
DIMM
Capacity
1 GB 1 Gb 128 M X 8 8 2 14/10 8 8 K
2 GB 2 Gb 128 M X 16 8 2 14/10 8 16 K
2 GB 1 Gb 128 M X 8 16 2 14/10 8 8 K
4 GB 2 Gb 256 M X 8 16 2 15/10 8 8 K
8 GB 4 Gb 512 M X 8 16 2 16/10 8 8 K
512 MB 1 Gb 64 M X 16 4 1 13/10 8 16 K
1 GB 2 Gb 128 M X 16 4 1 14/10 8 16 K
DRAM Device
Technology
Unbuffered/Non-ECC Supported DIMM Module Configurations
Note: DIMM module support is based on availability and is subject to change.
DRAM
Organization
# of
DRAM
Devices
# of
Physical
Device
Ranks
# of
Row/Col
Address
Bits
Table 2-2. Supported SO-DIMM Module Configurations (AIO Only)
Raw
Card
Version
A
B
C
F
DIMM
Capacity
1 GB 1 Gb 64 M x 16 8 2 13/10 8 8K
2 GB 2 Gb 128 M x 16 8 2 14/10 8 8K
1 GB 1 Gb 128 M x 8 8 1 14/10 8 8K
2 GB 2 Gb 256 M x 8 8 1 15/10 8 8K
512 MB 1 Gb 64 M x 16 4 1 13/10 8 8K
1 GB 2 Gb 128 M x 16 4 1 14/10 8 8K
2 GB 1 Gb 128 M x 8 16 2 14/10 8 8K
4 GB 2 Gb 256 M x 8 16 2 15/10 8 8K
8 GB 4 Gb 512 M x 8 16 2 16/ 10 8 8K
DRAM Device
Technology
DRAM
Organization
# of
DRAM
Devices
# of
Physical
Device
Ranks
# of
Row/Col
Address Bits
1,2
# of
Banks
Inside
DRAM
# of Banks
Inside
DRAM
Page Size
Page Size
Notes:
1. System memory configurations are based on availability and are subject to change.
2. Interface does not support ULV/LV memory modules or ULV/LV DIMMs.
20 Datasheet, Volume 1
Interfaces
2.1.2 System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
•tCL = CAS Latency
•t
•t
• CWL = CAS Write Latency
• Command Signal modes = 1n indicates a new command may be issued every clock
Table 2-3. DDR3 System Memory Timing Support
= Activate Command to READ or WRITE Command delay
RCD
= PRECHARGE Command Period
RP
and 2n indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.
Segment
All Desktop
segments
Notes:
1. System memory timing support is based on availability and is subject to change.
Transfer
Rate
(MT/s)
1066
1333 9 9 9 7
tCL
(tCK)
7776
8886
tRCD
(tCK)
tRP
(tCK)
CWL
(tCK) DPC
CMD
Mode
11n/2n
22n
11n/2n
22n
11n/2n
22n
2.1.3 System Memory Organization Modes
The IMC supports two memory organization modes—single-channel and dual-channel.
Depending upon how the DIMM Modules are populated in each memory channel, a
number of different configurations can exist.
2.1.3.1 Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated in any
order, but not both.
2.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode
Notes
1
The IMC supports Intel Flex Memory Technology Mode. Memory is divided into a
symmetric and an asymmetric zone. The symmetric zone starts at the lowest address
in each channel and is contiguous until the asymmetric zone begins or until the top
address of the channel with the smaller capacity is reached. In this mode, the system
runs with one zone of dual-channel mode and one zone of single-channel mode,
simultaneously, across the whole memory array.
Note: Channels A and B can be mapped for physical channels 0 and 1 respectively or vice
versa; however, channel A size must be greater or equal to channel B size.
Datasheet, Volume 1 21
Figure 2-1. Intel
CH BCH A
B B
C
B
B
C
Non interleaved
access
Dual channel
interleaved access
TOM
B – The largest physical memory amount of the sm aller size memory module
C – The remaining physical mem ory amount of the larger size mem ory module
®
Flex Memory Technology Operation
Interfaces
2.1.3.2.1 Dual-Channel Symmetric Mode
Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum
performance on real world applications. Addresses are ping-ponged between the
channels after each cache line (64-byte boundary). If there are two requests, and the
second request is to an address on the opposite channel from the first, that request can
be sent before data from the first request has returned. If two consecutive cache lines
are requested, both may be retrieved simultaneously since they are ensured to be on
opposite channels. Use Dual-Channel Symmetric mode when both Channel A and
Channel B DIMM connectors are populated in any order, with the total amount of
memory in each channel being the same.
When both channels are populated with the same memory capacity and the boundary
between the dual channel zone and the single channel zone is the top of memory, IMC
operates completely in Dual-Channel Symmetric mode.
Note: The DRAM device technology and width may vary from one channel to the other.
2.1.4 Rules for Populating Memory Slots
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports one or two DIMM
connectors per channel. The usage of DIMM modules with different latencies is allowed,
but in that case, the worst latency (per channel) will be used. For dual-channel modes,
both channels must have a DIMM connector populated and for single-channel mode,
only a single-channel may have one or both DIMM connectors populated.
Note: In a 2 DIMM Per Channel (2DPC) daisy chain layout memory configuration, the furthest
DIMM from the processor of any given channel must always be populated first.
22 Datasheet, Volume 1
Interfaces
2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel FMA technology enhancements.
2.1.5.1 Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
2.1.5.2 Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Precharge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
2.1.5.3 Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,
the IMC continuously monitors pending requests to system memory for the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back to back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the IMC
to further reduce latency and increase bandwidth efficiency.
2.1.6 Memory Type Range Registers (MTRRs) Enhancement
The processor has 2 additional MTRRs (total 10 MTRRs). These additional MTRRs are
specially important in supporting larger system memory beyond 4 GB.
2.1.7 Data Scrambling
The memory controller incorporates a DDR3 Data Scrambling feature to minimize the
impact of excessive di/dt on the platform DDR3 VRs due to successive 1s and 0s on the
data bus. Past experience has demonstrated that traffic on the data bus is not random
and can have energy concentrated at specific spectral harmonics creating high di/dt
that is generally limited by data patterns that excite resonance between the package
inductance and on-die capacitances. As a result, the memory controller uses a data
scrambling feature to create pseudo-random patterns on the DDR3 data bus to reduce
the impact of any excessive di/dt.
Datasheet, Volume 1 23
2.2 PCI Express* Interface
Transaction
Data Link
Physical
Logical Sub-block
Electrical Sub-block
RX TX
Transaction
Data Link
Physical
Logical Sub-block
Electrical Sub-block
RX TX
This section describes the PCI Express interface capabilities of the processor. See the
PCI Express Base Specification for details of PCI Express.
The number of PCI Express controllers is dependent on the platform. Refer to Chapter 1
for details.
2.2.1 PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged.
The PCI Express configuration uses standard mechanisms as defined in the PCI
Plug-and-Play specification. The initial recovered clock speed of 1.25 GHz results in
2.5 Gb/s/direction that provides a 250 MB/s communications channel in each direction
(500 MB/s total). That is close to twice the data rate of classic PCI. The fact that
8b/10b encoding is used accounts for the 250 MB/s where quick calculations would
imply 300 MB/s. The external graphics ports support Gen2 speed as well. At 5.0 GT/s,
Gen 2 operation results in twice as much bandwidth per lane as compared to Gen 1
operation. When operating with two PCIe controllers, each controller can be operating
at either 2.5 GT/s or 5.0 GT/s.
Interfaces
Figure 2-2. PCI Express* Layering Diagram
The PCI Express architecture is specified in three layers—Transaction Layer, Data Link
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. Refer to Figure 2-2 for the PCI Express Layering Diagram.
24 Datasheet, Volume 1
PCI Express uses packets to communicate information between components. Packets
are formed in the Transaction and Data Link Layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
through the other layers, they are extended with additional information necessary to
Interfaces
Sequence
Number
Framing Header Data ECRC LCRC Framing
Transaction Layer
Data Link Layer
Physical Layer
handle packets at those layers. At the receiving side, the reverse process occurs and
packets get transformed from their Physical Layer representation to the Data Link
Layer representation and finally (for Transaction Layer Packets) to the form that can be
processed by the Transaction Layer of the receiving device.
Figure 2-3. Packet Flow through the Layers
2.2.1.1 Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The
Transaction Layer's primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also manages
flow control of TLPs.
2.2.1.2 Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of Data Link Layer include link management, error detection, and error
correction.
The transmission side of the Data Link Layer accepts TLPs assembled by the
Transaction Layer, calculates and applies data protection code and TLP sequence
number, and submits them to Physical Layer for transmission across the Link. The
receiving Data Link Layer is responsible for checking the integrity of received TLPs and
for submitting them to the Transaction Layer for further processing. On detection of TLP
error(s), this layer is responsible for requesting retransmission of TLPs until information
is correctly received, or the Link is determined to have failed. The Data Link Layer also
generates and consumes packets that are used for Link management functions.
2.2.1.3 Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance
matching circuitry. It also includes logical functions related to interface initialization and
maintenance. The Physical Layer exchanges data with the Data Link Layer in an
implementation-specific format, and is responsible for converting this to an appropriate
serialized format and transmitting it across the PCI Express Link at a frequency and
width compatible with the remote device.
Datasheet, Volume 1 25
2.2.2 PCI Express* Configuration Mechanism
PCI-PCI Bridge
representing
root PCI
Express* ports
(Device 1 and
Device 6)
PCI Compatible
Host Bridge
Device
(Device 0)
PCI
Express*
Device
PEG0
DMI
The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge
structure.
Figure 2-4. PCI Express* Related Register Structures in the Processor
Interfaces
PCI Express extends the configuration space to 4096 bytes per-device/function, as
compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express
configuration space is divided into a PCI-compatible region (that consists of the first
256 bytes of a logical device's configuration space) and an extended PCI Express region
(that consists of the remaining configuration space). The PCI-compatible region can be
accessed using either the mechanisms defined in the PCI specification or using the
enhanced PCI Express configuration access mechanism described in the PCI Express
Enhanced Configuration Mechanism section.
The PCI Express Host Bridge is required to translate the memory-mapped PCI Express
configuration space accesses from the host processor to PCI Express configuration
cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is
recommended that system software access the enhanced configuration space using
32-bit operations (32-bit aligned) only. See the PCI Express Base Specification for
details of both the PCI-compatible and PCI Express Enhanced configuration
mechanisms and transaction rules.
2.2.3 PCI Express* Port
The PCI Express interface on the processor is a single, 16-lane (x16) port that can also
be configured at narrower widths. The PCI Express port is compliant with the PCI
Express Base Specification, Revision 2.0.
26 Datasheet, Volume 1
Interfaces
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2.2.4 PCI Express* Lanes Connection
Figure 2-5 demonstrates the PCIe lanes mapping.
Figure 2-5. PCI Express* Typical Operation 16 lanes Mapping
2.3 Direct Media Interface (DMI)
Note: Only DMI x4 configuration is supported.
2.3.1 DMI Error Flow
2.3.2 Processor / PCH Compatibility Assumptions
Datasheet, Volume 1 27
Direct Media Interface (DMI) connects the processor and the PCH. Next generation
DMI2 is supported.
DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or
GPE. Any DMI related SERR activity is associated with Device 0.
The processor is compatible with the Intel
not compatible with any previous PCH products.
®
6 Series Chipset PCH. The processor is
2.3.3 DMI Link Down
Vertex
Fetch
VS/GS
Setup/Rasterize
Hierachical Z
Hardware Clipper
EU EU
EU EU
Unified Execution Unit Array
Texture
Unit
Pixel
Backend
Full MPEG2, VC1, AVC Decode
Fixed Function Post Processing
Full AVC Encode
Partial MPEG2, VC1 Encode
Multi-Format Decode/Encode
Additional Post Processing
The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to
data link down, after the link was up, then the DMI link hangs the system by not
allowing the link to retrain to prevent data corruption. This link behavior is controlled
by the PCH.
Downstream transactions that had been successfully transmitted across the link prior
to the link going down may be processed as normal. No completions from downstream,
non-posted transactions are returned upstream over the DMI link after a link down
event.
2.4 Processor Graphics Controller (GT)
New Graphics Engine Architecture includes 3D compute elements, Multi-format
hardware-assisted decode/encode Pipeline, and Mid-Level Cache (MLC) for superior
high definition playback, video quality, and improved 3D performance and Media.
Display Engine in the Uncore handles delivering the pixels to the screen. GSA (Graphics
in System Agent) is the primary Channel interface for display memory accesses and
“PCI-like” traffic in and out.
Interfaces
Figure 2-6. Processor Graphics Controller Unit Block Diagram
28 Datasheet, Volume 1
Interfaces
2.4.1 3D and Video Engines for Graphics Processing
The 3D graphics pipeline architecture simultaneously operates on different primitives or
on different portions of the same primitive. All the cores are fully programmable,
increasing the versatility of the 3D Engine. The Gen 6.0 3D engine provides the
following performance and power-management enhancements:
• Up to 12 Execution units (EUs)
•Hierarchal-Z
• Video quality enhancements
2.4.1.1 3D Engine Execution Units
• Supports up to 12 EUs. The EUs perform 128-bit wide execution per clock.
• Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel
processing.
2.4.1.2 3D Pipeline
2.4.1.2.1 Vertex Fetch (VF) Stage
The VF stage executes 3DPRIMITIVE commands. Some enhancements have been
included to better support legacy D3D APIs as well as SGI OpenGL*.
2.4.1.2.2 Vertex Shader (VS) Stage
The VS stage performs shading of vertices output by the VF function. The VS unit
produces an output vertex reference for every input vertex reference received from the
VF unit, in the order received.
2.4.1.2.3 Geometry Shader (GS) Stage
The GS stage receives inputs from the VS stage. Compiled application-provided GS
programs, specifying an algorithm to convert the vertices of an input object into some
output primitives. For example, a GS shader may convert lines of a line strip into
polygons representing a corresponding segment of a blade of grass centered on the
line. Or it could use adjacency information to detect silhouette edges of triangles and
output polygons extruding out from the edges.
2.4.1.2.4 Clip Stage
The Clip stage performs general processing on incoming 3D objects. However, it also
includes specialized logic to perform a Clip Test function on incoming objects. The Clip
Test optimizes generalized 3D Clipping. The Clip unit examines the position of incoming
vertices, and accepts/rejects 3D objects based on its Clip algorithm.
2.4.1.2.5 Strips and Fans (SF) Stage
The SF stage performs setup operations required to rasterize 3D objects. The outputs
from the SF stage to the Windower stage contain implementation-specific information
required for the rasterization of objects and also supports clipping of primitives to some
extent.
Datasheet, Volume 1 29
2.4.1.2.6 Windower/IZ (WIZ) Stage
The WIZ unit performs an early depth test, which removes failing pixels and eliminates
unnecessary processing overhead.
The Windower uses the parameters provided by the SF unit in the object-specific
rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of
pixels. The Windower is also capable of performing dithering, whereby the illusion of a
higher resolution when using low-bpp channels in color buffers is possible. Color
dithering diffuses the sharp color bands seen on smooth-shaded objects.
2.4.1.3 Video Engine
The Video Engine handles the non-3D (media/video) applications. It includes support
for VLD and MPEG2 decode in hardware.
2.4.1.4 2D Engine
The 2D Engine contains BLT (Block Level Transfer) functionality and an extensive set of
2D instructions. To take advantage of the 3D during engine’s functionality, some BLT
functions make use of the 3D renderer.
Interfaces
2.4.1.4.1 Processor Graphics VGA Registers
The 2D registers consists of original VGA registers and others to support graphics
modes that have color depths, resolutions, and hardware acceleration features that go
beyond the original VGA standard.
2.4.1.4.2 Logical 128-Bit Fixed BLT and 256 Fill Engine
This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The
128-bit BLT engine provides hardware acceleration of block transfers of pixel data for
many common Windows operations. The BLT engine can be used for the following:
• Move rectangular blocks of data between memory locations
• Data alignment
• To perform logical operations (raster ops)
The rectangular block of data does not change, as it is transferred between memory
locations. The allowable memory transfers are between: cacheable system memory
and frame buffer memory, frame buffer memory and frame buffer memory, and within
system memory. Data to be transferred can consist of regions of memory, patterns, or
solid color fills. A pattern is always 8 x 8 pixels wide and may be 8, 16, or 32 bits per
pixel.
The BLT engine expands monochrome data into a color depth of 8, 16, or 32 bits. BLTs
can be either opaque or transparent. Opaque transfers move the data specified to the
destination. Transparent transfers compare destination color to source color and write
according to the mode of transparency selected.
Data is horizontally and vertically aligned at the destination. If the destination for the
BLT overlaps with the source memory location, the BLT engine specifies which area in
memory to begin the BLT transfer. Hardware is included for all 256 raster operations
(source, pattern, and destination) defined by Microsoft, including transparent BLT.
The BLT engine has instructions to invoke BLT and stretch BLT operations, permitting
software to set up instruction buffers and use batch processing. The BLT engine can
perform hardware clipping during BLTs.
30 Datasheet, Volume 1
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