Intel BX80539T2500 - Core Duo 2 GHz Processor, BX80623I52550K, Core Duo Series User Manual

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Intel® Core™ 2 Duo Processor and Intel Intel

Core™ Duo Processor with

E7520 Chipset Development

Kit

User’s Manual

January 2007

Order Number: 316068-001US

Legal Lines and Disclaimers

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY , RELA TING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Intel may make changes to specifications and product descriptions at any time, without notice. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the

presented su bje ct matter. The furnishing of documents and other materials and information does not pr ovide an y license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details.

The Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

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products/ht/Hyperthreading_more.htm for additional information.

This User’s Manual as well as the software described in it is furnished under license and may only be used or copied in accordance with the terms of the license. The information in this manual is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility o r l ia b ility f or any err ors or inaccur acies that may appear in this document or any software that may be provided in association with this document.

Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Celeron, Intel, Intel Centrino, Intel logo, Intel NetBurst, Intel NetStructure, Intel Xeon, Intel XScale, Pentium, Pentium II Xeon, Pentium III Xeon and

VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007, Intel Corporation. All Rights Reserved.

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Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit

Contents

1.0 About This Manual

.....................................................................................................6

1.1 Content Overview................................................................................................6

1.2 Text Conventions ................................................................................................6

1.3 Technical Support................................................................................................7

1.4 Product Literature ............................................................................................... 8

1.5 Related Documents .............................................................................................8

2.0 Getting Started

.......................................................................................................... 9

2.1 Overview ........................................................................................................... 9

2.2 Evaluation Board Features..................................................................................10

2.3 Included Hardware ............................................................................................11

2.4 Software Key Features ....................................................................................... 11

2.5 Before You Begin...............................................................................................12

2.6 Configuring the BIOS.........................................................................................23

3.0 Theor y of Ope r a t i on

.................................................................................................25

3.1 Block Diagram .................................................................................................. 25

3.2 Thermal Management ........................................................................................ 25

3.3 System Features ...............................................................................................26

3.4 Battery Requirements........................................................................................38

4.0 Platform Management

.............................................................................................39

4.1 Power Button.................................................................................................... 39

4.2 Sleep States Supported...................................................................................... 39

4.3 PCI PM Support.................................................................................................41

4.4 Platform Management........................................................................................41

4.5 System Fan Operation........................................................................................41

5.0 Driver and Operating System Support

......................................................................42

5.1 Video Driver Issue............................................................................................. 42

6.0 Hardware Reference

................................................................................................43

6.1 Chipset Components.......................................................................................... 44

6.2 Expansion Slots and Sockets............................................................................... 44

6.3 On-Board Connectors......................................................................................... 51

6.4 Jumpers........................................................................................................... 54

6.5 SMBUS Headers ................................................................................................57

6.6 Back Panel Connectors....................................................................................... 57

7.0 Board Setup Checklist

8.0 Debug Procedure

..............................................................................................61

..................................................................................................... 62

8.1 Level 1 Debug (Port80/BIOS).............................................................................. 62

8.2 Level 2 Debug (Power Sequence) ........................................................................ 62

8.3 Level 3 Debug (Voltage References)..................................................................... 63

Figures

1 E val ua tio n Bo ard Befo re Insta llin g Ad ditio n al Hard wa re .... . .. . .. .. . .. . .. .. ... . .. . .. .. . .. . .. .. . .. . .. . .. . 13

2 Location for the Processor, MCH, and PXH for Heatsink Installation .................................15

3 Processor Heatsink Top and Bottom View ....................................................................16

4 Processor in Socket and Package Secured ...................................................................16

5 Clean Top of Processor Die........................................................................................17

6 Back Plate in Place ...................................................................................................18

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Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset

Development Kit

7 Heatsink Mounted on Processor ..................................................................................18

8 Screw Tightening Order.............................................................................................19

9 MCH Heatsink Top View.............................................................................................19

10 Clean Top of MCH Die ...............................................................................................20

11 Hook Heatsink Clip to Anchor.....................................................................................20

12 Heatsink Fan Connector.............................................................................................21

13 Block Diagram of Layout............................................................................................25

14 DDR2-400 Memory—DIMM Ordering ...........................................................................29

15 ITP location .............................................................................................................30

16 Power Distribution Block Diagram ...............................................................................31

17 Clock Block Diagram.................................................................................................32

18 Platform Reset Diagram.............................................................................................33

19 SMBus Block Diagram ...............................................................................................34

20 IRQ Routing Diagram ................................................................................................35

21 Evaluation Board......................................................................................................43

22 Key Jumper Locations ...............................................................................................56

23 Back Panel Connectors..............................................................................................57

Tables

1 Intel Literature Centers .............................................................................................. 8

2 Related Documents.................................................................................................... 8

3 Supported Processors................................................................................................10

4 Additional Hardware..................................................................................................12

5 Heatsink Information ................................................................................................15

6 Supported DIMM Module Types ..................................................................................29

7 Processor VRD Settings.............................................................................................37

8 Chipset Components.................................................................................................44

9 Expansion Slots and Socket .......................................................................................44

10 PCI Express* Port A (x8) Connector Pinout ..................................................................44

11 PCI Express* Port B (X4) Connector Pinout ..................................................................46

12 32-Bit 5 V PCI Connector Pinout.................................................................................47

13 PCI-X Connector Pinout.............................................................................................48

14 On-Board Connector .................................................................................................51

15 SATA Connector Pinout..............................................................................................52

16 IDE Connector Pinout................................................................................................52

17 Floppy Drive Connector Pinout....................................................................................53

18 Front Panel Connector Pinout .....................................................................................53

19 Jumpers and Descriptions..........................................................................................54

20 SMBUS 3.3 V STBY Pinout .........................................................................................57

21 PS/2* Mouse and Keyboard Pinout..............................................................................57

22 Parallel Port Connector Pinout ....................................................................................58

23 Serial Port Connector Pinout ......................................................................................58

24 USB Connector Pinout...............................................................................................59

25 Video Port Connector Pinout.......................................................................................59

26 Dual Gigabit Ethernet Port Connector Pinout.................................................................59

27 Level 1 Debug (Port80/BIOS) .....................................................................................62

28 Level 2 Debug (Power Sequence) ...............................................................................62

29 Level 3 Debug (Voltage Reference) .............................................................................63

Intel

Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit User’s Manual January 2007 4 Order Number: 316068-001US

Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit

Revision History

Date Revision Description

January 2007 001 Initial release.

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Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset

1.0 About This Manual

Development Kit

This manual describes how to set up and use the evaluation board and other components included in the Intel Processor with Intel

E7520 Chipset Development Kit.

1.1 Content Overview

Chapter 1.0, “About This Manual” – Description of conventions used in this manual and

instructions for obtaining literature and contacting customer support.

Chapter 2.0, “Gettin g Started ” – Complete instructions on how to configure the

evaluation board and processor assembly by setting jumpers, connecting peripherals, providing power, and configuring the BIOS.

Chapter 3.0, “Theory of Operation” – Information on the system design.

Chapter 4.0, “Platform Management” – Inform at i on on t he sy s t e m p owe r ma na ge me nt

operation.

Chapter 5.0, “Driver and Operating System Support” – List of supported drivers and

operating systems.

Chapter 6.0, “Hardware Reference” – R efe re nce in for mat ion on t he har dw are , inc ludi ng

locations of evaluation board components, connector pinout information, and jumper settings.

Chapter 7.0, “Board Setup Checklist” – Check lis t of it ems t o en sure pr oper func ti onal it y

of the evaluation board.

Chapter 8.0, “Debug Procedure” – Debug procedure to determine baseline functionality

for the Development Kit.

Core™ 2 Duo Processor and Intel® Core™ Duo

1.2 Text Conventions

The following notations may be used throughout this manual:

# -

The pound symbol (#) appended to a signal name indicates that the signal is active

low.

Variables -

values.

Instructions -

programming, instructions are not case-sensitive. You may use either upper- or lowercase.

Numbers -

followed by the character “h”. A zero prefix is added to numbers that begin with A through F. For example, FF is shown as 0FFh. Decimal and binary numbers are represented by their customary notations. That is, 255 is a decimal number and 1111 1111 is a binary number. In some cases, the character “b” is added for clarity.

Signal Names -

common name, an individual signal is represented by the signal name followed by a number, while the group is represented by the signal name followed by a variable (n). For example, the lower chip-select signals are named CS0#, CS1#, CS2#, and so on;

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Variables are shown in italics. Variables must be replaced with correct

Instruction mnemonics are shown in uppercase. When you are

Hexadecimal numbers are represented by a string of hexadecimal digits

Signal names are shown in uppercase. When several signals share a

Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit

they are collectively called CSn#. A pound symbol (#) appended to a signal name identifies an active-low signal. Port pins are represented by the port abbreviation, a period, and the pin number (e.g., P1.0).

Units of Measure -

The following abbreviations are used to represent units of

measure:

A amps, amperes

GB GByte, gigabytes

GHz gigahertz

KB KByte, kiloby tes

ΚΩ

kilo-ohms

mA milliamps, milliamperes

MB MByte, megabytes

MHz megahertz

ms milliseconds

mW milliwatts

ns nanoseconds

pF picofarads

W watts

V volts

A microamps, microamperes

F microfarads

s microseconds

W microwatts

1.3 Technical Support

Support Services for your hardware and software are provided through the secure

Intel

Premier Support Web site at https://premier.intel.com. After you log on, you can obtain technical support, review “What’s New,” and download any items required to maint ai n the pl atf orm . Sup por t i s pr ovi ded th roug h th e fo llow ing p rod uct :

Kit (Embedded/Core Duo/Core 2 Duo/E7520)

1.3.1 Additional Technical Support

If you require additional technical support, please contact your field sales representative or local distributor.

Development

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Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset

1.4 Product Literature

You can order product literature from the following Intel literature centers.

Table 1. Intel Literature Centers

U.S. and Canada 1-800-548-4725

U.S. (from overseas) 708-296-9333

Europe (U.K.) 44(0)1793-431155

Germany 44(0)1793-421333

France 44(0)1793-421777

Japan (fax only) 81(0)120-47-88-32

1.5 Related Documents

Tabl e 2 is a partial list of the available collateral. For the full lists, contact your local

Intel representative .

Table 2. Related Documents

Document Document Number

6300ESB I/O Controller Hub (ICH) Datasheet

Intel

E7520 Memory Controller Hub (MCH) Datasheet

Intel

E7520 Memory Controller Hub (MCH) Specification

Intel

E7520 Memory Controller Hub (MCH) Specifications Addendum

Intel

E7520 Memory Controller Hub (MCH) Specifications Embedded

Addendum

Intel

Intel Specification

Intel® Core™ 2 Duo and Intel® Core™ Duo Processor with Intel® E7520 Chipset Platform Design Guide

Intel

Intel Datasheet

Extended Debug Port Design Guide for UP and DP platforms

6700PXH PCI Hub Datasheet

82571EB Gigabit Ethernet Controller Datasheet

IMVP-6 Mobile Processor and Mobile Chipset Voltage Regulation

Core™ Duo Processoron 65nm Process Datasheet

Core™ 2 Duo Processor for Intel Centrino Mobile technology

Development Kit

Contact your Intel field representative for access.

Intel

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Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit

2.0 Getting Started

This chapter identifies the Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel specifications. It also describes how to set up the board for operation. Development software is included in the kit.

Note:

This manual assumes you are familiar with basic concepts involved with installing and configuring hardware for a PC or server system.

2.1 Overview

The development kit contains a baseboard with an Intel® Core™ 2 Duo Processor (2.16 GHz), Intel components and peripheral connectors.

Note:

The development kit also contains an additional processor, an Intel Processor (2 GHz), that can be installed in place of the Intel

The evaluation board is shipped as an open system allowing for maximum flexibility in changi ng h ar d wa r e co nf ig uration and p er i p he rals in a la b en v i r onm en t . Si nce the board is not in a protective chassis, the user is required to observe extra precautions when handling and operating the system. Some assembly is required before use.

Review the document provided with the Development Kit titled Important Safety and Re gula tor y I nfor mat io n. Thi s doc ument cont ai ns add it ion sa fet y war ning s and ca uti ons.

E7520 Chipset Development Kit key components, features and

E7520 MCH, Intel® 6300ESB ICH, and other system board

Core™ 2 Duo Processor.

Core™ Duo

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Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset

2.2 Evaluation Board Features

Tabl e 3 provides an overview of the supported processor pairing for the Intel® E7520

MCH.

Table 3. Supported Processors

Development Kit

Processor Brand Process Clock Speed

Core™ Duo Processor T2500

Intel

Core™ Duo Processor L2400 (BGA Only) 1.66 GHz 667 MHz 2 MB L2

65 nm

Note:

Intel

Core™ 2 Duo Processor T7400 2.16 GHz 667 MHz 4 MB L2

Intel

Core™ 2 Duo Processor L7400 1.5 GHz 667 MHz 4 MB L2

The Intel

Core™ Duo ProcessorL2400 is supported by the Intel® E7520 MCH platform, but a BGA part is not supported by the Customer Reference Board that is included in this Development Kit.

Note:

The Intel

Core™ 2 Duo Processor (T7400 and L7400) and the Intel® Core™ Duo Processor (T2500) are supported by the Customer Reference Board that is included in this Development kit. The Customer Reference Board comes with the Intel Duo Processor (T7400) installed at the factory . An Intel is included in the Development Kit and can be installed in place of Intel Processor. A separate BIOS flash chip is also included in this kit and must be installed when using the Intel

Core™ Duo Processor.

The evaluation board features are summarized below:

•Intel

Core™ 2 Duo Processor (2.16 GHz) or Intel® Core™ Duo Processor (2 GHz) — 667 MHz front side bus — On-board processor voltage regulator compatible with IMVP-6 Design Guide

•Intel

E7520 MCH — 1 PCI Express* x8 slot — 1 PCI Express x4 slot — 2 DDR2–400 DIMMs on two channels (4 slots total)

•Intel

6300ESB ICH — From Intel

6300ESB ICH 1 PCI 2.2 32/33 Slot 2 PCI-X 66 MHz slots 2 IDE connectors 2 Serial ATA connectors 2 Serial ports 4 USB 2.0 ports

Front Side Bus

2 GHz 667 MHz 2 MB L2

Core™ Duo Processor (T2500)

Cache

Core™ 2

Core™ 2 Duo

Intel

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Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit

— Super I/O via LPC bus from the Intel® 6300ESB ICH

1 Floppy port 1 Parallel port 1 Serial port 1 PS/2 port

• Intel

6700PXH PCI Hub — 2 PCI-X 100 MHz slots — 1 PCI-X 133 MHz slot

• Intel

82571EB Gigabit Ethernet Controller — 2 Gigabit Ethernet connections

• ITP-XDP debug port

• Port 80 7-segment LEDs

• Board Form Factor - 13” x 16” for benchtop use

2.3 Included Hardware

The following hardware is included in the development kit:

• Intel

• Processor heatsink

• Pre-installed jumpers

• Two 512 MB DDR2-400 DIMMs

• Unformatted IDE Hard Drive

• IDE cable

• CD with drivers

• FWH mounted and flashed with the BIOS, additional BIOS chip for the Intel

• Standoffs for benchtop use

Core™ 2 Duo Processor 2.16 GHz, 667 MHz FSB (installed)

Core™ Duo Processor 2 GHz, 667 MHz FSB (additional processor)

Core™ Duo Processor

2.4 Software Key Features

The software in the development kit was chosen to facilitate development of real-time appl ic ations based o n t he co mp on en t s us e d i n the evalua t i on b oa r d. T he sof t w a r e t o ol s includ ed are des crib ed in this sec tion .

Drivers included:

• Chipset INF Install Utili ty for Micro so ft Windo w s*

• Optional Intel

• Linux* driver packages

Note:

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Software in the kit is provided free by the vendor and is only licensed for evaluation purposes.

Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit

6300ESB ICH driver updates

Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset

Refer to the documentation in your kit for further details on any terms and conditions that may be applicable to the granted licenses. Customers using tools that work with other third party products must have licensed those products. Any targets created by those tools should also have appropriate licenses. Software included in the kit is subject to change.

Refer to http://developer.intel.com/design/intarch/devkits for details on additional software from other third party vendors.

2.4.1 AMIBIOS * fo r the D ev el op m en t Kit

The evaluation board is pre-installed and licensed with a copy of AMIBIOS* from American Megatrends*.

BIOS updates may be updated periodically. Please contact an field sales representative for BIOS updates.

2.5 Before You Begin

Tabl e 4 presents the additional hardware you may need for your kit.

Table 4. Additional Hardware

VGA Monitor You can use any standard VGA or greater resolution monitor.

Keyboard You can use a keyboard with a PS/2* connector or adapter as well as USB.

Mouse You can use a mouse with a PS/2* connector or adapter as well as USB.

Hard Drives You can connect up to four IDE and two SATA devices to the evaluation board.

Floppy Drive (optional)

Other Devices and Adapters

450 W or greater SSI 12 V external power supply

You can connect a floppy drive to the connector on the evaluation board. No floppy drives or cables are included in the development kit.

The evaluation board behaves much like a standard PC motherb oard. Many PC- compatible peripherals can be attached and configured to work with the evaluation board. For example, you may want to install a sound card or additional network adapters. You are responsible for procuring and installing any drivers required for additional devices.

Power supply for the Evaluation Board. No power supply is included in the development kit.

Development Kit

2.5.1 Setting up the Evaluation Board

Once you have gathered the hardware described in Section 2.5, follow the steps below to set up the development kit. This manual assumes you are familiar with basic concepts involved with installing and configuring hardware for a PC or server system.

Note:

Intel

Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit User’s Manual January 2007 12 Order Number: 316068-001US

Review the document provided with the Development Kit titled Important Safety and Re g ul at o r y I nf or m a t i on. T hi s do cum e nt con t ai ns add i t i on sa f ety warnings and ca ut i on s.

Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit

Figure 1. Evaluation Board Before Installing Additional Hardware

2.5.2 Safety

Ensure a safe work environment.

before removing any components from their anti-static packaging. The evaluation board is susceptible to electrostatic discharge, which may cause product failure or unpredictable operation.

Caution:

Warning:

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Connecting the wrong cable or reversing a cable may damage the evaluation board and may da mag e the dev ice bein g conne ct ed. Si nce t he bo ard is not in a pr ote ct iv e chas sis, use caution when connecting cables to this product.

Make sure AC cord of power supply is unplugged before performing the following steps in Section 2.6.

Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit

Make sure you are in a static-free environment

Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset

2.5.3 Packa g e Co nten ts

Development Kit

Veri f y ki t cont en ts.

Insp e ct t h e c ontents of yo ur k it and ensure that ever y t hi ng l i st e d in Section 2.3 is included. Check for damage that may have occurred during shipment. Contact your sales representative if any items are missing or damaged.

Check jumper settings.

Section 6.4 for detailed descriptions of all jumpers and their default settings indicated

in bold.

2.5.4 Installed Hardware

Verify installed hardware.

evaluation board:

•Intel

E7520 MCH heatsink

6700PXH PCI Hub heatsink

•BIOS FWH

• Battery in holder

Caution:

The above hardware should have been correctly installed at the factory. If components are not installed correctly, DO NOT power on the board. Correctly re-install the components before proceeding. If you suspect that any of the kit components have been damaged, contact your Intel field sales representative or local distributor for assistance.

2.5.5 Installing Standoffs

The evaluation board in this development kit is shipped as an open system allowing for maximum flexibility in changing hardware configuration and peripherals in the lab environment. Since the board is not in a protective chassis, the user is required to observe extra precautions when handling and operating the system.

Verify that the jumpers are set in their default state. Refer to

Make sure the following hardware is populated on your

The board is a standard ATX form factor and provides non-plated mounting holes with top and bottom ground rings. If the board is not going to be used in a chassis, standoffs are included for bench top use in the lab environment.

The development kit includes eight standoffs and eight screws that you can use to attach to the board for bench top use. Standoffs should be attached to board at the following mounting hole locations, A1, A4, A9, E1, E3, K1, J6, and J9.

1. Insert screw through top mounting hole.

2. Place standoff on back side of board and hand tighten to screw.

3. Repeat for additional standoffs on the board until all eight standoffs are installed.

2.5.6 Installing the Heatsinks for Processor and MCH

Heatsink Installation:

installed on the processor and on the Intel wit hou t a pr o ce ss or t he r m al sol ution. Heats i nk s ma y al r e ad y com e p r e- i n st a ll e d on the MCH. Please refer to this section if you need to remove or re-install the heatsinks.

Tools Needed:

Flat head screwdriver and Phillips head screwdriver

Consumable Items Needed:

Note:

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Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit User’s Manual January 2007 14 Order Number: 316068-001US

Processor heatsink may be silver or copper in color.

In ord er f or t he bo ar d t o op erate prop er l y, a heat s in k mus t be

E7520 MCH.

DO NOT

power on board

Disposable towels and isopropyl alcohol

Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit

Table 5. Heatsink Information

Component

Processor 1 Cooler Master* EEP-N41CS-0 1-G P

Intel

E7520 MCH 1 Cooler Master* ECB-00208-03-GP Active heatsink

Intel

6700PXH PCI

Hub

Quantity Per

Board

1Sunon*

Heatsink

Manufacturer

Part Number Comments

Acti ve he atsi nk and back plate

GC123506BH- 8DA.05.N.B515GN/ 2026GN

Active heatsink

Figure 2. Location for the Processor, MCH, and PXH for Heatsink Installation

Caution:

Note:

Applying excess pressure may cause damage to the processor.

Do not turn power on until the processor thermal solution has been installed.

2.5.7 Processor Heatsink Installation

This section details how to install the processor heatsink.

Note:

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If the Thermal Interface Material (TIM) is scratched, scrape it off and replace with new material. If a replacement is needed, use a TIM with high thermal conductivity such as thermal grease or a phase change material. The gasket ensures the heatsink is sitting flat on the package.

Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset Development Kit

Intel® Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520 Chipset

Figure 3. Processor Heatsink Top and Bottom View

1. Make certain that the processor is firmly seated in socket U6G1, and the package is secured using a flathead screwdriver.

Development Kit

Note:

The processor socket has a screw locking mechanism. The socket has an indication to show if the processor is locked in place. To remove the processor, turn the screw counter-clockwise all the way until it stops. The processor will be loose and will come out easily. To insert the processor, line up the socket and processor corners that do not have pins and insert the processor in the socket. Turn the screw clock-wise until it is tight and the processor is firmly held.

Figure 4. Processor in Socket and Package Secured

Intel

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2. Clean the top surface of the processor die with a clean towel and isopropyl alcohol (IPA).

Figure 5. Clean Top of Processor Die

Note:

3. Install the back plate to the bottom side of the PCB at the processor location. Align the standoffs to the four mounting holes in the board.

There is a non-electrically conductive tape to hold the back plate in place until the heatsink is completely installed.

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Figure 6. Back Plate in Place

Development Kit

4. Mount the heatsink to the processor. Ensure the TIM and die have contact.

Figure 7. Heatsink Mounted on Processor

5. Align the screws (4x at corners) to the threaded holes of the standoffs on the back plate. Using the Phillips head screwdriver, tighten the four screws in a diagonal manner (as shown in the diagram). Tighten each screw half of the screw length for A to B and follow by ¼ for C to D. Then tighten A to B until the screw hard stops and repeat for C to D. The screws are designed to compress the springs a predetermined amount.

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Figure 8. Screw Tightening Order

6. Plug the fan connector to the fan pin header J7J1 on the board.

Note:

The heatsink removal process is the reverse of the installation procedure.

2.5.8 MCH Heatsink Installation

This section may not apply if the MCH heatsink is pre-installed on the board. However, you may want to briefly look over the procedure to verify that the heatsink is properly installed and it has not been damaged in the packaging.

Note:

Figure 9. MCH Heatsink Top View

If the Thermal Interface Material (TIM) is scratched, scrape it off and replace with new material. Use a TIM with high thermal conductivity, such as thermal grease or phase change material.

1. Clean t he t op sur f ac e of t he MC H di e wi t h a cl ea n t ow el and is op r op y l al c oho l ( I P A ) .

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Figure 10. Clean Top of MCH Die

Development Kit

2. Hook one end of the heatsink clip to one of the anchors located near the corner of the MCH. Securely hold the other end of the heatsink clip.

Figure 11. Hook Heatsink Clip to Anchor

3. Hold the clip firmly to the anchor to prevent the heatsink from moving. Attach the other end of the clip to the other anchor. Ensure that the heatsink is level with the MCH package.

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Figure 12. Heatsink Fan Connector

4. Plug the fan connector to the fan pin header J5D2 on the board.

Note:

The heatsink removal process is the reverse of the installation procedure.

2.5.9 Installing Memory

The kit includes two 512 MByte registered ECC DIMMs. To install, ensure the tabs on the slot are open, or rotated outward from the slot. Line up the DIMM above the slot (the DIMM is keyed so that it only fits in the slot in one orientation). Firmly but carefully insert the DIMM into the slot until the tabs close. Repeat for all other DIMM and slots.

Note:

Caution:

When populating both channels, always place identical DIMMs in sockets that have the same position on channel A and channel B (i.e., DIMM A2 should be identical to DIMM B2).

Populate DIMMs starting with the sockets farthest away from the MCH (DIMM slots A2 and B2).

Do NOT bend the board when installing memory. There are a large number of components near the memory slots and excessive board flex can lead to solder joint failure.

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2.5.10 Installing Storage Devices

There is two IDE connectors on the evaluation board, which supports an IDE devices. For a correct boot-up of the system, ensure that a hard drive is installed as the primary master . (Master/slave settings are determined by a jumper on each IDE device. Consult the device label/documentation to verify that the jumper is set correctly for any configuration you choose.) A CD-ROM drive or additional hard drive may be installed as a primary slave device. Follow this procedure to install a hard drive on the evaluation board:

1. Verify that the jumper on the hard drive is set correctly for single or master, depending on your configuration.

2. Install the hard drive. This can be done using either the IDE or SATA.

IDE Installation:

a. Connect the long end of the IDE cable to the IDE connector J2J2 on the board.

Ensure that the red line (pin one on the cable) is aligned with pin one of the connector indicated by an arrow.

b. Co nne ct the midd l e co nne ctor of the c ab l e t o the hard drive. Agai n, e ns ur e t ha t

the red line, pin one on the cable, is aligned with pin one on the hard drive.

Development Kit

Note:

Failure to properly align the IDE cable may damage the evaluation board and/or the hard drive.

SATA Installation:

a. Connect one end of the SATA cable to the hard drive connection. Connect the

other end to the SATA0 or SATA1 connector (J3F1 or J3F2, respectively) on the board.

3. Connect a power connector from the power supply to the hard drive. The power connector on the SATA drive may have a plastic cover that will need to be removed. (Old style power connector is supported.)

4. Install the CD-ROM drive (optional). A CD-ROM drive is not included in the kit and is not required, but you may find it useful in loading additional software. To install it on the evaluation board:

a. Verify that the jumper on the CD-ROM drive is set for slave. b. Co nne ct the unus ed en d of t h e I D E cab l e t o t he CD-ROM dri v e. Ens ur e t ha t t he

red line, pin one on the cable, is aligned with pin one of the CD-ROM drive connector, indicated by an arrow.

c. Connect a large 4-pin power connector from the power supply to the CD-ROM

drive.

5. Install the floppy drive (optional). A floppy disk drive is not included in your kit and is not required, but you may find it useful in loading additional software. To install a floppy drive on the evaluation board:

a. Connect the floppy cable to the floppy connector J1J1. Ensure that the red line

(pin one on the cable) is aligned with pin one of the connector, indicated by an

arrow. b. Connect the other end of the floppy cable to the floppy drive. c. Connect a power cable to the floppy drive. Ensure that the red line (pin one on

the cable) is aligned with pin one on the floppy drive.

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2.5.11 Connect the Monitor Cable

Connect the monitor cable to J6A1 on the evaluation board. If using a video card disable onboard video by removing jumper J4A1, insert video card and connect monitor cable to video connector on card.

Note:

Monitor is not included in this development kit.

2.5.1 2 Co nn ec t the Ke y b oa rd a nd Mo use

Connect a PS/2* mouse and keyboard to the stacked PS/2* connector on the evaluation board. The bottom connector, often purple, is the keyboard connector and the top, often green, is the mouse connector. Alternatively, you may plug a USB keyboard and a USB mouse into the USB connectors on the evaluation board.

Note:

Keyboard and mouse are not included in this development kit.

2.5.13 Connect the Power Supply

Make sure the power supply is turned off and unplugged. Connect the two ATX power supply cables to connectors J5K1 and J8K1 on the evaluation board. Next, plug the power cord into the power supply and the wall. Then turn on the switch on the back of the power supply.

Note:

Power Supply is not included in this development kit. Use power supply described in

Section 2.5.

2.5.14 Power the System

Turn on the monitor and then turn on the evaluation board.

Note:

Caution:

Do not turn power on until the processor thermal solutions have been installed.

Ensure that fan heatsink on the processor is operational. If not, turn off the power immediately and verify that the fan heatsink is connected to the board correctly (see

Section 2.5.6). If the fan heatsink is not operating, contact your Intel field sales

representative or local distributor.

2.6 Configuring the BIOS

An AMI* BIOS is pre-loaded on the evaluation board. You may need to make changes to the BIOS to enable hard disks, floppy disks and other supported features. You may use the setup program to modify BIOS settings and control the special features of the system. Setup options are configured through a menu-driven user interface.

On first boot-up of the system, you may want to use the BIOS setup program to verify the date/time and boot device. BIOS updates may periodically be posted to the Intel Developer web site at http://developer.intel.com/design/intarch. Pressing the Delete key during boot causes the system to enter into the BIOS setup program.

The development kit contains an additional BIOS chip for use with the Intel Duo Processor. To replace the BIOS chip, follow the following steps:

• Remove power from the CRB

• Remove FWH from U2H3

• Install new FWH in U2H3

• Apply power to the CRB

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• Move CMOS clear jumper J5H2 to position 2-3 (Configure) for 15 seconds

• Move CMOS clear jumper J5H2 back to position 1-2 (Normal)

• Apply power to the system

• Enter BIOS setup program to set date/time

Note:

To avoid damaging the FWH, use an extraction tool such as the AMP822154-1. This tool is not provided with the DEV KIT.

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3.0 Theory of Operation

3.1 Block Diagram

Figure 13. Block Diagram of Layout

3.2 Thermal Management

The objective of thermal management is to ensure that the temperature of each component is maintained within specified functional limits. The functional temperature limit is the range within which the electrical circuits may be expected to meet their specified performance requirements. Operation outside the functional limit may degrade system performance and cause reliability problems. The development kit shipped with heatsink thermal solution to be installed on the processor. This thermal solution has been tested in an open air environment at room temperature and is sufficient for evaluation purposes. The designer must ensure that adequate thermal management is provided for any customer-derived designs.

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3.3 System Features

Processor

• Supports the Intel

• On-board proce ss or volta ge regu la tors com patib le with IMVP -6 Design Guide.

Chipset

•Intel

E7520 MCH

6300ESB ICH

6700PXH PCI Hub

82571EB Gigabit Ethernet Controller

Clocking

• CK409B clock synthesizer that generates all host clock and the PCI Express* interface clock for the MCH PHY layer

• DB800 generates the PCI Express differential pair clocks to the onboard PCI Express components and the dedicated PCI Express slots

Memory

• Registered ECC DDR2-400 DIMMs

• Each of the two memory channels on the Intel board supports a maximum of two DDR2-400 DIMMs per channel

• 3.2 Gbytes/s bus per channel bandwidth with DDR2-400

Development Kit

Core™ 2 Duo Processor and the Intel® Core™ Duo Processor

E7520 MCH on this evaluation

Graphics

• ATI Rage Mobility-M graphics controller

I/O

• From Intel

6300ESB ICH — 1 PCI 2.2 32/33 Slot — 2 PCI-X 66 MHz slots — 2 IDE connectors — 2 Serial ATA connectors — 2 Serial ports — 4 USB 2.0 ports

Two on rear panel I/O Two on front panel header

— Super I/O via LPC bus from the 6300ESB

One Floppy port One Parallel port One Serial port (10-pin header) Tw o PS 2 port

•Intel

6700PXH PCI Hub — 2 PCI-X 100 MHz slots — 1 PCI-X 133 MHz slot

•Intel

82571EB Gigabit Ethernet Controller — 2 Gigabit Ethernet connections

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— X4 PCIe interface with MCH providing bandwidth up to 2 GB/s per direction — Integrated PHY layer for 10/100/1000 Mbps operation

Low Pin Count Bus

• Super I/O IC

• Firmware hub

Board Form Factor

• 13” x 16” for bench top use

• ATX SSI 12 V Power supply

3.3.1 Intel® Core™ 2 D u o Pr o c esso r

• 2 high performance execution cores at 2.16 GHz on 65nm process technology

• 667 MHz FSB

3.3.2 Intel® Core™ D u o Pr oc e ssor

• 2 high performance execution cores at 2 GHz on 65nm process technology

• 667 MHz FSB

3.3.3 Intel® E7520 MCH

The architecture of the MCH provides the performance and feature set required for

Intel

Core™ Duo Processor and Intel® Core™ 2 Duo Processor-based volume to performance servers. Configuration options facilitate optimization of the platform for workloads characteristic of communication, presentation, storage, performance computation, or database applications. Coverage includes the MCH interface units (system bus, system memory, PCI Express, Hub Interface (HI), SMBus, power management, MCH clocking, MCH system reset and power sequencing) as well as RASUM (Reliability, Availability, Serviceability, Usability, and Manageability) features.

Features:

• Registered ECC DDR2-400 DIMM support

• Integrated four-channel DMA engine with IOxAPIC functionality

• High speed seri al PCI Expre ss interfa ce

• Hub interface to Intel

• Intel

6700PXH PCI Hub is a PCIe to PCI-X Hub interface

3.3.4 Intel® 6300ESB ICH

The Intel® 6300ESB ICH is designed for a variety of processors/memory controller hubs. The Intel required to ensure that system interfaces operate efficiently and provide the bandwidth necessary to enable the system to obtain peak performance.

Features:

• Upstream HI for access to the MCH

• Two port Serial ATA controllers

• Two IDE connectors

• PCI-X 1.0 Interface

6300ESB ICH provides the data buffering and interface arbitration

6300ESB ICH

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• PCI 2.2 Interface

• Tw o seri al I/O ports

• Two-stage WDT (Watch Dog Timer)

• LPC Interface

• EPLD for Port 80 decode and display

• FWH Interface

• SMBus 2.0 controller

• I/O APIC

• Four USB 2.0 Ports

3.3.5 Intel® 6700PXH PCI Hub

The 6700PXH provides a connection between the E7520 and PCI or PCI-X interfaces via a PCIe channel. The 6700PXH PCI Hub contains two PCI bus interfaces that have been configured to PCI-X 133 MHz and the other to PCI-X 100 MHz, for either 32-bit or 64- bit PCI devices.

• Two PCI-X 100 MHz slots

• One PCI-X 133 MHz slot

Development Kit

3.3.6 Intel® 82571EB Gigabit Ethernet Controller

The Intel 82571EB Gigabit Ethernet Controller is a single, compact component with two fully integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) ports. Uses the PCI Express X4 connection to the Intel

E7520 MCH. The Intel 82571EB provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE- TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). In addition to managing MAC and PHY Ethernet layer functions, the controller manages PCI Express packet traffic across its transaction, link, and physical/logical layers.

3.3.7 Memory Subsystem

The memory subsystem is designed to support Double Data Rate 2 (DDR2) Synchronous Dynamic Random Access Memory (SDRAM) using the Intel The MCH provides two independent DDR channels, which support DDR2-400 DIMMs. The peak bandwidth of each DDR2 branch channel is 3.2 GByte/s (8 bytes x 400 MT/s) with DDR2-400. When the two DDR2 channels from the MCH operate in lock step, the effective overall peak bandwidth of the DDR2 memory subsystem is 6.4 GByte/s for DDR2-400.

E7520 MCH.

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3.3.8 Supported DIMM Module Types

Table 6 shows all DIMM technology validated by Intel on the evaluation board.

Table 6. Supported DIMM Module Types

Size 1G 1 G 1G2G4 G

Channels Dual Single Single Single Dual

Note:

SR = Single Rank; DR = Dual Rank

256 M

512 M

3.3.9 Memory Population Rules and Configurations

The system supports two DDR2-400 DIMM slots for Channel A and two DDR2-400 DIMM slots for Channel B. The four slots are interleaved and placed in a row in the following order: A1, B1, A2, B2 with A1 being closest to the MCH. This design supports only registered ECC-enabled DIMMs.

When populating both channels, always place identical DIMMs in sockets that have the same position on Channel A and Channel B (i.e., DIMM A2 should be identical to DIMM B2). Refer to datasheet for definition of identical DIMMs.

In addition, single-rank DIMMs should be populated furthest from the MCH when a combination of single-rank and double-rank DIMMs are used. This recommendation is based on the signal integrity requirements of the DDR2 interface.

Figure 14. DDR2-400 Memory—DIMM Ordering

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3.3.10 Firmware Hub (FWH)

Development Kit

A socketed FLASH device is used to store system BIOS as well as an Inte Number Generator (RNG). A bootblock locking jumper is provided to allow a mechanical means of protecting the bootblock BIOS firmware. All BIOS programming is controlled via software.

FWH Features:

• 32-pin PLCC package

• Symmetrically-blocked flash memory array (64 Kbyte)

• Pin and register-based block locking

• Integrated hardware RNG

• Single-byte read/write

•Five GPIs

3.3.11 Boot RO M

The system boot ROM is installed on a FWH device. The FWH is addressable on the LPC bus off the Intel

6300ESB ICH.

3.3.12 In-Targ et Pr ob e (IT P)

The evaluation board contains an in-target probe (ITP) connector for an ITP-XDP connector. Other ITPs will not work and if installed, could damage the platform and/or the IT P. Figure 15 shows the ITP connector which is located at location J9G1.

Figure 15. ITP location

l®

Random

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3.3.13 Power Diagram

Figure 16 shows the p ower dis tr ib uti on for t he ev al uat ion b oar d. R ef er to t he e v alua ti on

board schematics for details on the power distribution logic (contact your Intel field sales representative to obtain the schematics).

Figure 16. Power Distribution Block Diagram

-6

ccA

1.5 V

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3.3.14 Clock Ge ne ra ti on

The evaluation board uses one CK409B Clock Synthesizer to generate the host differential pair clocks and the 100 MHz differential clock to the DB800. The DB800 then generates the 100 MHz diff eren tial pair clo ck for the PCI Expre ss devic es.

Figure 17 shows the evaluation board clock configuration.

Figure 17. Clock Block Diagram

Development Kit

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3.3.15 Platform Resets

Figure 18 depicts the reset logic for the evaluation board. The 6300ESB provides most

of the reset, following assertion of power good and system reset.

Figure 18. Platform Reset Diagram

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3.3.16 SMBus

Figure 19 below illustrates the routing of the SMBus signal among the components.

Figure 19. SMBus Block Diagram

Development Kit

SMBUS

HEADER

ITP

SMBus

E7520

6700PXH

CK409B

SIO

SMBUS

REPEATER

MCH SMB

ICH SMB

PCA9515

SMBus

Repeater

6300ESB

82571EB

AMD1023

PCI-X 133MHZ

SLOT #1

PCI-X 100MHZ

SLOT #2

ICH SMBALERT

PCI SMB

PCI-X 100MHZ

SLOT #3

PCI Express

SLOT #4

PCI Express

SLOT #5

PCI-X 66MHZ

SLOT #6

DB800

PCI-X 66MHZ

SLOT #7

DIMMS A1 & A2 DIMMS B1 & B2

PCI 33MHZ

SLOT #8

DDR SMB

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3.3.17 Platform IRQ Routing

Figure 20 shows how the Intel® 6300ESB ICH uses these segments:

• IRQ 14 and 15 for IDE segment

• SERIRQ for SIOPIXRQ segment

• PCRIRQ for the PCI-X segment

• PIRQ for the PCI 32/33 segment

Figure 20. IRQ Routing Diagram

CPU0

CPU

PCI-E

Dual Northway

MSI

I-

PCI-E

MSI

PCI-E

I MSI

MCH

MSI

FSB

MCH

NMI

SMI NMI

MSI

HI PCI-E

MI MSI

SMI

PCI-E

MSI

PCI-E

IRQ14/15

MSI

NMISMI

SERIRQ

IDE

ICH

PCI- X Slot

PCI -X Slot

REQ/GNT: 0

IDSEL: AD17

A B C D

2 X

PAIRQPBIRQ

PCI-X 64/133

PXH

MSI

E PCI-

PCI-

A B

B C

C D

PIRQPXIRQ

E F

F G

G H

H A

A B

B C

C D

0 1

4/1

C P

6 7

PCI Slot

PCI Slot REQ/GNT: 0

REQ/GNT: 0

IDSEL: AD16

A B C D A

PCI-X 64/66 PCI 32/33

REQ/GNT: 1

IDSEL: AD17

PCI- X Slot

PCI-X Slot

REQ/GNT: 0

IDSEL: AD17

A B C D

REQ/GNT: 0

IDSEL: AD17

Video

REQ/GNT: 1

PCI-X Slot

PCI- X Slot PCI-X Slot

PCI- X Slot

REQ/GNT: 0

A B C D

PCI-X Slot

REQ/GNT: 1

IDSEL: AD18

A B C D

PCI-X Slot

PCI -X Slot

REQ/GNT: 1

IDSEL: AD18

A B C D

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3.3.18 VRD VID Headers

VID headers provide for manual control of the processor core voltage regulator output level(s). Normally, the processor should be run at its default VID (voltage identification) value as set during manufacturing. However, in the event the user needs to set a different VID value from the default value, it can be accomplished through a jumper block found on the board.

Development Kit

Note:

These headers are not populated by default. IMVP-6 Controller VID input 0 and 6 are tied low. Initial boards will not have the VID Header populated, processor must have VID override enabled for the initial Intel Duo Processor samples. The, VID override enable, jumper controls whether or not the VID header jumpers control the VID to the regulator or not.

Core™ Duo Processor and Intel® Core™ 2

1. For the table below 1 means the jumper is installed.

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Table 7. Processor VRD Settings

VID2 VID1 VID0 Vcc-coreVID6 VID5 VID4 VID3VID2 VID1 VID0 Vcc-coreVID6 VID5 VID4 VID3

00000001.5000V 10000000.7000V

00000011.4875V 10000010.6875V

00000101.4750V 10000100.6750V

00000111.4625V 10000110.6625V

00001001.4500V 10001000.6500V

00001011.4375V 10001010.6375V

00001101.4250V 10001100.6250V

00001111.4125V 10001110.6125V

00010001.4000V 10010000.6000V

00010011.3875V 10010010.5875V

00010101.3750V 10010100.5750V

00010111.3625V 10010110.5625V

00011001.3500V 10011000.5500V

00011011.3375V 10011010.5375V

00011101.3250V 10011100.5250V

00011111.3125V 10011110.5125V

00100001.3000V 10100000.5000V

00100011.2875V 10100010.4875V

00100101.2750V 10100100.4750V

00100111.2625V 10100110.4625V

00101001.2500V 10101000.4500V

00101011.2375V 10101010.4375V

00101101.2250V 10101100.4250V

00101111.2125V 10101110.4125V

00110001.2000V 10110000.4000V

00110011.1875V 10110010.3875V

00110101.1750V 10110100.3750V

00110111.1625V 10110110.3625V

00111001.1500V 10111000.3500V

00111011.1375V 10111010.3375V

00111101.1250V 10111100.3250V

00111111.1125V 10111110.3125V

01000001.1000V 11000000.3000V

01000011.0875V 11000010.2875V

01000101.0750V 11000100.2750V

01000111.0625V 11000110.2625V

01001001.0500V 11001000.2500V

01001011.0375V 11001010.2375V

01001101.0250V 11001100.2250V

01001111.0125V 11001110.2125V

01010001.0000V 11010000.2000V

01010010.9875V 11010010.1875V

01010100.9750V 11010100.1750V

01010110.9625V 11010110.1625V

01011000.9500V 11011000.1500V

01011010.9375V 11011010.1375V

01011100.9250V 11011100.1250V

01011110.9125V 11011110.1125V

01100000.9000V 11100000.1000V

01100010.8875V 11100010.0875V

01100100.8750V 11100100.0

01100110.8625V 11100110.0625V

01101000.8500V 11101000.0500V

01101010.8375V 11101010.0375V

01101100.8250V 11101100.0250V

01101110.8125V 11101110.0125V

01110000.8000V 11110000.0000V

01110010.7875V 11110010.0000V

01110100.7750V 11110100.0000V

01110110.7625V 11110110.0000V

01111000.7500V 11111000.0000V

01111010.7375V 11111010.0000V

01111100.7250V 11111100.0000V

01111110.7125V 11111110.0000V

750V

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3.4 Battery Requirements

A type 2032 3 V lithium coin cell battery is required and included in the evaluation board kit.

Development Kit

Warning:

Risk of explosion if the lithium battery is replaced by an incorrect type. Ensure the correct type of battery is selected and installed correctly before turning power on to the board.

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4.0 Platform Management

The following sections describe how the system power management operates, and how the different ACPI states are implemented. Platform management involves:

• ACPI implementation-specific details

• Sy stem monitor i ng , con t r ol , an d r e sp ons e t o th er m a l, vo ltage, and int r us io n ev e nts

• BIOS secu rity

4.1 Power Button

The system power button is connected to the I/O controller component. When the button is pressed, the I/O controller receives the signal and transitions the system to the proper sleep state as determined by the operating system and software. If the power button is pressed and held for four seconds, the system powers off (S 5 state). This fe a t ur e i s c al l ed p ow er b utton over r i de a nd is p ar t i c ul ar l y he l pf ul i n c as e of sy s t em hang and system lock. The power button is located at location SW3E1on the board.

4.2 Sleep States Supported

The I/O controller controls the system sleep states. States S0, S1, S3, and S5 are supported. The platform enters sleep states in response to BIOS, operating system, or user actions. Normally the operating system determines which sleep state to transition into. However, a four second power button override event places the system immediately into S5. When transitioning into a software-invoked sleep state, the I/O controller attempts to gracefully put the system to sleep by first going into the processor C2 state.

4.2.1 S0 State

This is the normal operating state, even though there are some power savings modes in this state using processor Halt and Stop Clock (processor C1 and C2 states). S0 affords the fastest wake-up response time of any sleep state because the system remains fully powered and memory is intact.

4.2.2 S1 State

This state is entered via a processor Sleep signal from the I/O controller (processor C3 state). The system remains fully powered with memory contents intact but the processors enter their lowest power state. Wake-up latency is slightly longer in this state than in S0; however, power savings are improved from S0.

4.2.3 S2 State

This state is not sup po rted.

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4.2.4 S3 State

This state is called Suspend to RAM (STR). The system context is maintained in system DRAM, but power is shut off to non-critical circuits. Memory is retained, and refreshes continue. All clocks stop except the RTC. S3 is entered when the I/O controller asserts the SLP_S3# signal to downstream circuitry to control 1.8 V power plane switching. Power must be switched from the normal 1.8 V rail to standby 1.8 V, because the 450 W SSI 12 V power supply does not directly supply a standby 1.8 V rail. The sequence to enter Suspend to RAM is as follows:

1. The OS and BIOS prepare for S3 sleep state.

2. The OS sets the appropriate sleep bits in the I/O controller.

3. The I/O controller drives STPCLK to the processor.

4. The processor respond with a Stop-Grant cycle, passed over hub interface by MCH.

5. The I/O controller indicates an S3 (STR) sleep mode to the MCH via Hub Interface A.

6. The MCH puts DDR memory into the self-refresh mode.

7. The MCH drives DDR CMDCLK differential pairs and all DDR outputs low.

8. The MCH drives a completion message via Hub Interface A to the I/O controller.

9. The I/O controller turns off all voltage rails (except Standby 5 V) from the main power supply by asserting the SLP_S3_N signal.

When in the S3 state, only the standby 5 V rail is available from the power supply. The board uses this standby source to generate 1.8 V standby rail to power the DIMMs.

Development Kit

The asserted SLP_S3_N signal also controls the logic to switch the DIMM power source from main 1.8 V to standby 1.8 V.

4.2.5 S4 State

This state is not supported.

4.2.6 S5 State

This state is the normal off state whether entered through the power button or soft off. All power is shut off except for the logic required to restart. The system remains in the S5 state only while the power supply is plugged into the electrical outlet. If the power supply is unplugged, this is considered a mechanical off or G3.

4.2.7 Wake-Up Events

The types of wake-up events and wake-up latencies are related to the actual power rails available to the system in a particular sleep state, as well as to the location in which the system context is stored. Regardless of the sleep state, wake on the power button is always supported except in a mechanical off situation. When in a sleep state, the system complies with the PCI specification by supplying the optional 3.3 V standby voltage to each PCI slot as well as the PME# signal. This enables any compliant PCI card to wake up the system from any supported sleep state except mechanical off.

4.2.8 Wake from S1 Sleep State

During S1 the system is fully powered, permitting support for PCI Express* Wake and Wake on PCI PME#.

4.2.9 Wake from S3 State

Keyboard press or mouse movement is used to wake from S3.

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4.2.10 Wake from S5 State

The power button is used to wake from S5.

4.3 PCI PM Support

This design holds the system reset signal low when in a sleep state. The system supports the PCI PME# signal and provides 3.3 V standby to the PCI and PCI Express slot s. T hi s su pp or t allows an y co mp l ia nt PC I or P C I Ex p r e ss c ar d t o w ak e up t he s y stem from any sleep state except mechanical off. Because of the limited amount of power available on 3.3 V standby, the user and the operating system must configure the system carefully following the PCI power management interface specification.

4.4 Platform Management

The ADM1023 monitors the majority of the system voltages. All voltage levels can be read via the SMBus.

4.4.1 Processor Thermal Management

Each processor monitors its own core temperature and thermally manages itself when it reaches a certain temperature. The system also uses the internal processor diode to monitor the die temperature. The diode pins are routed to the diode input pins in the ADM1023. The ADM1023 will use its A/D converter to determine the CPU temperature. When the CPU temperature reaches its threshold, System Management will react accordingly to lower the overall system temperature.

4.5 System Fan Operation

Power consumption can be adjusted by controlling the fan speed. The fan can be off, running on 5 V, or running on 12 V. The system can adjust the fan speed depending on the CPU temperature. If a system gets too hot, an alert will be sent to the System Management controller. The administrator may then want to turn the system off but keep the fan running to cool the system faster.

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5.0 Driver and Operating System Support

The development kit supports the following operating systems:

• Red Hat* EL 3.0 AS and WS

• QNX Neutrino*

• Microsoft Windows Server 2003*

• Microsoft Windows XP* and embedded XP*

Development Kit

Note:

Operating systems are not included in the development kit.

5.1 Video Driver Issue

The ATI video software driver included with this development kit does not fully comply with the new guidelines set forth in the software developer’s manual (SDM), chapter

10. This section outlines the utilization of memory cache control. You may experience infrequent issue when resuming from a S3 state. There should be no other issues with this software video driver.

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6.0 Hardware Reference

This section provides reference information on the hardware, including locations of evaluation board components, connector pinout information, and jumper settings.

Figure 21 shows the evaluation board.

Figure 21. Evaluation Board

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6.1 Chipset Components

Tabl e 8 lists the chipset and other major components on the evaluation board.

Table 8. Chipset Components

Component Designator Component Description

U6E1 Intel

U4F1 Intel

U2F1 Intel

U6B1 Intel

U2H3 Firmware Hub (FWH)

E7520 Memory Controller Hub (MCH)

6300ESB I/O Controller Hub (ICH)

6700PXH PCI Hub

82571EB Gigabit Ethernet Controller

6.2 Expansion Slots and Sockets

Tabl e 9 lists the expansion slots and sockets on the evaluation board.

Table 9. Expansion Slots and Socket

Slot/Socket Reference Designator Slot/Socket Description

J3B2 PCI Express* Port A (x8)

J4B2 PCI Express* Port B (x4)

J4B1 PCI Slot

J1B1 PCI-X Slot (PXH)

J1B2 PCI-X Slot (PXH)

J2B1 PCI-X Slot (PXH)

J2B2 PCI-X Slot (ICH)

J3B1 PCI-X Slot (ICH)

U6G1 Processor

XB5G1 Battery

Development Kit

6.2.1 PCI Expr ess* Con ne c tor

Tabl e 10 lists the signals assigned to the PCI Express port A slot connector found at

J3B2.

Table 10. PCI Express* Port A (x8) Connector Pinout (Sheet 1 of 2)

Pin Signal Pin Signal

A1 PRSNT1# B1 12 V

A2 12 V B2 12 V

A3 12 V B3 12 V

A4 GND B4 GND

A5 JTAG2 B5 SMCLK

A6 JTAG3 B6 SMDAT

A7 JTAG4 B7 GND

A8 JTAG5 B8 3.3 V

A9 3.3 V B9 JTAG1

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Table 10. PCI Express* Port A (x8) Connector Pinout (Sheet 2 of 2)

Pin Signal Pin Signal

A10 3.3 V B10 3.3 V

A11 PWRGD B11 WAKE#

A12 GND B12 Reserved

A13 Refclk+ B13 GND

A14 Refclk - B14 HSOP_0

A15 GND B15 HSON_0

A16 HSIP_0 B16 GND

A17 HSIN_0 B17 PRSNT2_1#

A18 GND B18 GND

A19 Reserved B19 HSOP_1

A20 GND B20 HSON_1

A21 HSIP_1 B21 GND

A22 HSIN_1 B22 GND

A23 GND B23 HSOP_2

A24 GND B24 HSON_2

A25 HSIP_2 B25 GND

A26 HSIN_2 B26 GND

A27 GND B27 HSOP_3

A28 GND B28 HSON_3

A29 HSIP_3 B29 GND

A30 HSIN_3 B30 Reserved

A31 GND B31 PRSNT2_2#

A32 Reserved B32 GND

A33 Reserved B33 HSOP_4

A34 GND B34 HSON_4

A35 HSIP_4 B35 GND

A36 HSIN_4 B36 GND

A37 GND B37 HSOP_5

A38 GND B38 HSON_5

A39 HSIP_5 B39 GND

A40 HSIN_5 B40 GND

A41 GND B41 HSOP_6

A42 GND B42 HSON_6

A43 HSIP_6 B43 GND

A44 HSIN_6 B44 GND

A45 GND B45 HSOP_7

A46 GND B46 HSON_7

A47 HSIP_7 B47 GND

A48 HSIN_7 B48 PRSNT2_3#

A49 GND B49 GND

AUX

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Tabl e 11 lists the signals assigned to the PCI Express Port B slot connector found at

J4B2.

Table 11. PCI Express* Port B (X4) Connector Pinout

Pin Signal Pin Signal

A1 PRSNT1# B1 12 V

A2 12 V B2 12 V

A3 12 V B3 12 V

A4 GND B4 GND

A5 JTAG2 B5 SMCLK

A6 JTAG3 B6 SMDAT

A7 JTAG4 B7 GND

A8 JTAG5 B8 3.3 V

A9 3.3 V B9 JTAG1

A10 3.3 V B10 3.3 V

A11 PWRGD B11 WAKE#

A12 GND B12 Reserved

A13 Refclk+ B13 GND

A14 Refclk - B14 HSOP_0

A15 GND B15 HSON_0

A16 HSIP_0 B16 GND

A17 HSIN_0 B17 PRSNT2_1#

A18 GND B18 GND

A19 Reserved B19 HSOP_1

A20 GND B20 HSON_1

A21 HSIP_1 B21 GND

A22 HSIN_1 B22 GND

A23 GND B23 HSOP_2

A24 GND B24 HSON_2

A25 HSIP_2 B25 GND

A26 HSIN_2 B26 GND

A27 GND B27 HSOP_3

A28 GND B28 HSON_3

A29 HSIP_3 B29 GND

A30 HSIN_3 B30 Reserved

A31 GND B31 PRSNT2_2#

A32 Reserved B32 GND

AUX

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6.2.2 32-Bit PCI Connector

Table 12 presents the signals assigned to the 32-bit PCI slot connector found at J4B1.

Table 12. 32-Bit 5 V PCI Connector Pinout (Sheet 1 of 2)

Pin Signal Pin Signal

A1 TRST# B1 -12 V

A2 +12 V B2 TCK

A3 TMS B3 GND

A4 TDI B4 TDO

A5 5 V B5 5 V

A6 INTA# B6 5 V

A7 INTC# B7 INTB#

A8 5 V B8 INTD#

A9 RSVD1 B9 PRSNT1#

A10 5 V B10 Rese rve d

A11 RSVD3 B11 PRSNT2#

A12 GND B12 GND

A13 GND B13 GND

A14 3.3 V

A15 RST# B15 GND

A16 5 V B16 C LK

A17 GNT# B17 GND

A18 GND B18 REQ#

A19 PME# B19 5 V

A20 AD30 B20 AD31

A21 3.3 V B21 AD29

A22 AD28 B22 GND

A23 AD26 B23 AD27

A24 GND B24 AD25

A25 AD24 B25 3.3 V

A26 IDSEL B26 C/BE3#

A27 3.3 V B27 AD23

A28 AD22 B28 GND

A29 AD20 B29 AD21

A30 GND B30 AD19

A31 AD18 B31 3.3 V

A32 AD16 B32 AD17

A33 3.3 V B33 C/BE2#

A34 FRAME# B34 GND

A35 GND B35 IRDY#

A36 TRDY# B36 3.3 V

A37 GND B37 DEVSEL#

AUX

B14 Reserved

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Table 12. 32-Bit 5 V PCI Connector Pinout (Sheet 2 of 2)

Pin Signal Pin Signal

A38 STOP# B38 GND

A39 3.3 V B39 LOCK#

A40 SDONE B40 PERR#

A41 SBO# B41 3.3 V

A42 GND B42 SERR#

A43 PAR B43 3.3 V

A44 AD15 B44 C/BE1#

A45 3.3 V B45 AD14

A46 AD13 B46 GND

A47 AD11 B47 AD12

A48 GND B48 AD10

A49 AD9 B49 GND

A50 KEY B50 KEY

A51 KEY B51 KEY

A52 CBEO# B52 AD8

A53 3.3 V B53 AD7

A54 AD6 B54 3.3 V

A55 AD4 B55 AD5

A56 GND B56 AD3

A57 AD2 B57 GND

A58 AD0 B58 AD1

A59 5 V B59 5 V

A60 REQ64# B60 ACK64#

A61 5 V B61 5 V

A62 5 V B62 5 V

Development Kit

6.2.3 PCI-X Conn ec tor

Tabl e 13 presents the PCI-X connector pinout for J1B1, J1B2, J2B1, J2B2, and J3B1.

Table 13. PCI-X Connector Pinout (Sheet 1 of 4)

Pin Signal Pin Signal

A1 TRST# B1 -12 V

A2 +12 V B2 TCK

A3 TMS B3 GND

A4 TDI B4 TDO

A5 5 V B5 5 V

A6 INTA# B6 5 V

A7 INTC# B7 INTB#

A8 5 V B8 INTD#

A9 Reserved B9 PRSNT1#

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Tabl e 13. PCI- X C onnector Pinout (Sheet 2 of 4)

Pin Signal Pin Signal

A10 3.3 V B10 Reserved

A11 Reserved B11 PRSNT2#

A12 KEY B12 KEY

A13 KEY B13 KEY

A14 3.3 V

A15 RST# B15 GND

A16 3.3 V B16 CLK

A17 GNT# B17 GND

A18 GND B18 REQ#

A19 PME# B19 3.3 V

A20 AD30 B20 AD31

A21 3.3 V B21 AD29

A22 AD28 B22 GND

A23 AD26 B23 AD27

A24 GND B24 AD25

A25 AD24 B25 3.3 V

A26 IDSEL B26 C/BE3#

A27 3.3 V B27 AD23

A28 AD22 B28 GND

A29 AD20 B29 AD21

A30 GND B30 AD19

A31 AD18 B31 3.3 V

A32 AD16 B32 AD17

A33 3.3 V B33 C/BE2#

A34 FRAME# B34 GND

A35 GND B35 IRDY#

A36 TRDY# B36 3.3 V

A37 GND B37 DEVSEL#

A38 STOP# B38 PCIXCAP

A39 3.3 V B3 9 LOCK #

A40 SDONE B40 PERR#

A41 SBO# B41 3.3 V

A42 GND B42 SERR#

A43 PAR B43 3.3 V

A44 AD15 B44 CBE1#

A45 3.3 V B4 5 AD 14

A46 AD13 B46 GND

A47 AD11 B47 AD12

A48 GND B48 AD10

A49 AD9 B49 M66EN

AUX

B14 Reserved

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Table 13. PCI-X Connector Pinout (Sheet 3 of 4)

Pin Signal Pin Signal

A50 GND B50 GND

A51 GND B51 GND

A52 CBEO# B52 AD8

A53 3.3 V B53 AD7

A54 AD6 B54 3.3 V

A55 AD4 B55 AD5

A56 GND B56 AD3

A57 AD2 B57 GND

A58 AD0 B58 AD1

A59 3.3 V B59 3.3 V

A60 REQ64# B60 ACK64#

A61 5 V B61 5 V

A62 5 V B62 5 V

A63 GND B63 Reserved

A64 C/BE7# B64 GND

A65 C/BE5# B65 C/BE6#

A66 3.3 V B66 C/BE4#

A67 PAR64 B67 GND

A68 AD62 B68 AD63

A69 GND B69 AD61

A70 AD60 B70 3.3 V

A71 AD58 B71 AD59

A72 GND B72 AD57

A73 AD56 B73 GND

A74 AD54 B74 AD55

A75 3.3 V B75 AD53

A76 AD52 B76 GND

A77 AD50 B77 AD51

A78 GND B78 AD49

A79 AD48 B79 3.3 V

A80 AD46 B80 AD47

A81 GND B81 AD45

A82 AD44 B82 GND

A83 AD42 B83 AD43

A84 3.3 V B84 AD41

A85 AD40 B85 GND

A86 AD38 B86 AD39

A87 GND B87 AD37

A88 AD36 B88 3.3V

A89 AD34 B89 AD35

Development Kit

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Tabl e 13. PCI- X C onnector Pinout (Sheet 4 of 4)

Pin Signal Pin Signal

A90 GND B90 AD33

A91 AD32 B91 GND

A92 Reserved B92 Reserved

A93 GND B93 Reserved

A94 Reserved B94 GND

6.2.4 Processor Sockets

The processor is keyed so that it fits into the socket in one particular orientation.

6.2.5 Firmware Hub (FWH) BIOS Socket

The system boot ROM is installed on the ATMEL AT49LW080 or SST ST49LF008A Firmware Hub device. The FWH is addressable on the LPC bus off the Intel ICH.

The FWH or BIOS flash memory fits into the 32-pin socket U2H3, giving you the option to remove and reprogram it without the use of soldering equipment. There is also a flas h utility that is sup pl i e d w i t h the BIOS t hat can be used to progra m t he F W H. T hi s is the recommended way to program the FWH.

There is only one correct orientation for the FWH to be placed into its socket. Line up the circular marking on the FWH, denoting pin one, with the arrow marking on the evaluation board socket.

Note:

An additional BIOS flash memory is included in the development kit. This BIOS chip must be installed in the platform when the Intel section 2.6 for more details on how to replace the BIOS chip.

6.2.6 Battery

A type 2032, 3 V lithium coin cell battery is used in socket XB5G1 on the evaluation board. The battery is held in place by a metal arm. To remove the battery, gently push the metal arm and remove the battery.

Warning:

Risk of explosion if the lithium battery is replaced by an incorrect type. Ensure the correct type of battery is selected and installed correctly before turning power on to the board.

6.3 On-Board Connectors

6300ESB

Core™ Duo Processor is used. See

Table 14. On-Board Connector

Connector Reference Designator Connector Description

J3F1, J3F2 SATA Connector

J2J2, J2K2 IDE Connectors

J1J1 Floppy Connector

J9G1 ITP Connector

J1H3 Front Panel Connector

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6.3.1 SATA Conn ec tor

Table 15. SATA Connector Pinout

Pin Connector Description

1 GND

2A+

3A-

4 GND

5B-

6B+

7 GND

6.3.2 IDE Conne c tor

The evaluation board has two 40-pin connectors for the IDE controllers present in the

6300ESB ICH. Tab l e 16 lists the signals assigned to the IDE connectors.

Intel

Table 16. IDE Connector Pinout

Development Kit

Pin Connector Description Pin Connector Description

1Reset IDE 21PDDREQ

2 GND 22 GND

3 Host Data 23 I/O Write#

4 Host Data 24 GND

5 Host Data 25 I/O Read#

6 Host Data 26 GND

7 Host Data 27 I/O CHRDY

8 Host Data 28 GND

9 Host Data 29 DACK#

10 Host Data 30 GND

11 Host Data 31 IRQ14

12 Host Data 32 Reserved

13 Host Data 33 Addr1

14 Host Data 34 Primary IDE Cable Detect

15 Host Data 35 Addr0

16 Host Data 36 Addr2

17 Host Data 37 Chip Select 1#

18 Host Data 38 Chip Select 3#

19 GND 39 Activity

20 Key 40 GND

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6.3.3 Floppy Drive Connector

The evaluation board provides one 34-pin floppy connector, which is located at J1J1.

Table 17. Floppy Drive Connector Pinout

Pin Signal Pin Signal

1 GND 18 DIR#

2 Drive Enable 0 19 GND

3 GND 20 STEP#

4 Reserved 21 GND

5Key 22Write Data#

6 Drive Enable 1 23 GND

7 GND 24 Write Gate#

8 Index 25 GND

9 GND 26 Track 00#

10 Motor Enable A# 27 G ND

11 GND 28 Write Protect#

12 Reserved 29 GND

13 GND 30 Read Data#

14 Drive Select 0# 31 GND

15 GND 32 Side 1 Select#

16 Reserved 33 GND

17 GND 34 Diskette Change#

6.3.4 Front Panel Connector

The development kit is not shipped with a chassis, so the front panel connector is unused by default. However, if you want to place your evaluation board in a chassis, refer to Ta b l e 18 for the pinout of the front panel connector J1H3.

Table 18. Front Panel Connector Pinout

Pin Connector Description Pin Connector Description

3 No connect 4 FPNTPNL_PWR_LED

5 GND 6 FP_PWR_BTN_N

7 FP_RST_BTN_N 8 GND

9 No connect 10 No Pin

2 HD_ACT_LED_N

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6.4 Jumpers

The evaluation board has a number of jumpers that control various functions of the system.

Tabl e 19 presents the descriptions of the jumpers and their settings.

Figure 22 illustrates the locations of key jumpers on the board.

Table 19. Jumpers and Descriptions

Jumper Description / Settings Default Position

Enable PXH

J2G3

J2H2

J2J1

J5H2

J7J2

J8H3

J4A1

J4H2 (BSEL1), J4J2 (BSEL0)

J5F6 (PLLSEL1 ), J5E3 (PLLSEL0)

J9G4 (DIMCH), J9G3 (MCH_2)

J1A1

J2G1 For validation only Ope n

J2H1

1-2: Enable (LH) Open: Disable (LH-VS)

Processor socket occupy signal routing Short: Processor present Open: Processor not present

Enable Super IO chip 1-2: Enable Open: Disable

CMOS clear 1-2: Normal 2-3: Configure

Processor VID override 1-2: Manu al select Open: Processor select

Processor VID VID[5]: 11-12 VID[4]: 1-2 VID[3]: 3-4 VID[2]: 5-6 VID[1]: 7-8 VID[0]: 9-10

Enable on-board video 1-2: Enable Open: Disable

FSB clock frequency override (J4H2/J4J2/Speed) Open/Open/166 MHz 1-2/1-2/Auto

DIMM speed configuration (J5F6/J5E3/FSB Freq) Open/Short/667 Open/Short/533

ITP Processor access (J9G3/J9G4/Mode) 1-2/Open/Processor Access Only 2-3/1-2/Chain Test

3.3V AUX switch @ 1.7A 1-2: Enable AUX voltage Open: Disable

Speaker pull-up routing 1-2: Enable Open: Disable

Development Kit

1-2

Open

(1.212 V) 1-2 Open 3-4 Open 5-6 Short 7-8 Open 9-10 Open 11-12 Short

1-2

J4H2: 1-2 J4J2: 1-2

J5E3: 1-2 J5F6: Open

J9G3: 1-2 J9G4: Open

1-2

Open

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Table 19. Jumpers and Descriptions

Jumper Description / Settings Default Position

J3A1

J3D1

J3J1 For validation only Open

J3J2 For validation only Open

J4G1 For validation only Open

J4G4 For validation only Open

J4G5 For validation only Open

J4H1

J5H1

J5H3

J4H3 For validation only Open

J4J1 For validation only Open

J5A1

J5D3

J5F1

J5F3

J5F5 For validation only Open

5V AUX switch @ 1.7A 1-2: Enable Open: Disable

Front panel sleep button Open: (For external access only)

PCI SMB Clock and PCI SMB Data ground 1-2: SMBData grounded 2-3: SMBClk grounded Open: IDLE

LAN SMB Clock and LAN SMB Data ground 1-2: SMBData grounded 2-3: SMBClk grounded Open: IDLE

DIMM SMB Clock and DIMM SMB Data ground 1-2: SMBData grounded 2-3: SMBClk grounded Open: IDLE

To manually control LAN_AUXPWR_STRAP either pulled up to 3.3V or pulled down to GND

1-2: Disable 2-3: Enable Open: IDLE

MCH SMB Clock and MCH SMB Data ground 1-2: SMBData grounded 2-3: SMBClk grounded Open: IDLE

Enable A16 ICH swap override Short: Top Swap Open: Normal

Enable ICH run at safe mode Short: Safe Mode Open: Normal

1-2

Open

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Table 19. Jumpers and Descriptions

Jumper Description / Settings Default Position

J5A1 (3.3V Supply), J5A2 (LAN_AUXPWR_STRAP), J6B1 (ICH_Wake)

J8H2

J7J2

LAN Wake On Control (J5A1/J5A2/J6B1/Lan Wake On Status)

1-2/1-2/1-2/Wake On 2-3/2-3/1-2/No Wake On

DDR S3 Enable BCKFD_CT_LTCH Short: Enable DIMM S3 Open: Disable DIMM S3

Processor ThermDA and ThermDC External connection 2: Thermal DA connection 3: Ground

Figure 22. Key Jumper Locations

Development Kit

J5A1: 2-3 J5A2: 2-3 J6B1: 1-2

1-2

Open

J1A1

J3A1

J2G3

J2J1

J4H2/J4J2

J4A1

J5E3/J5F6

J5H2

J8H2

J9G3/J9G4

J8H3

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6.5 SMBUS Headers

The SMBUS headers are used to connect the SMBUS. Refer to the following tables for pinout information.

Table 20 describes the SMBUS 3.3 V STBY pinout.

Tabl e 20. SMBUS 3.3 V STBY Pinout

Pin Connector Description

1SMBDAT

2GND

3SMB CLK

6.6 Back Panel Connectors

The evaluation b oa r d co nt a in s a nu mb e r of c onne c t or s for e x t e r nal sy s t e m de v i ce s a nd peripherals. Figure 23 shows the peripheral connectors.

The following sections provide pinouts for each connector.

Figure 23. Back Panel Connectors

6.6.1 PS/2* Mouse and Keyboard Connectors

Table 21 lists the signals assigned to the PS/2* keyboard and mouse connectors. The

keyboard port is on the top and the mouse port is on the bottom.

Table 21. PS/2* Mouse and Keyboard Pinout

Pin Connector Description

1,7 Data

2,8 Reserved

3,9, 13-17 Ground

4,10 +5 V (fused)

5,11 Clock

6, 12 Reserved

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6.6.2 Parallel Port

Tabl e 22 lists the signals assigned to the parallel port connector.

Table 22. Parallel Port Connector Pinout

Pin Connector Description Pin Connector Description

1 Strobe# 14 Auto Feed#

2 Data Bit 0 15 Fault#

3 Data Bit 1 16 INIT#

4 Data Bit 2 17 SLC IN#

5 Data Bit 3 18 Ground

6 Data Bit 4 19 Ground

7 Data Bit 5 20 Ground

8 Data Bit 6 21 Ground

9 Data Bit 7 22 Ground

10 ACK# 23 Ground

11 Busy 24 Ground

12 Paper end 25 Ground

13 SLCT

Development Kit

6.6.3 Serial Po r ts

Tabl e 23 lists the signals assigned to the serial port connector.

Table 23. Serial Port Connector Pinout

Pin Connector Description

1DCD

2 Serial In - RXD

3 Serial Out - TXD

4DTR

5Ground

6DSR

7RTS

8CTS

9RI

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6.6.4 Dual Stacked USB Connectors

Table 24 lists the signals assigned to the dual stacked USB connector.

Table 24. USB Connector Pinout

Pin Connector Description

1,5 Power (fused)

2,6 USBP1 # [USBP2#]

3,7 USBP1 [USBP2]

4,8 Ground

6.6.5 Video Port

Table 25 lists the signals assigned to the video port connector.

Table 25. Video Port Connector Pinout

Pin Connector Description

1VGA Red

2 VGA Green

3VGA Blue

4 Monitor ID

5GND

6GND

7GND

8GND

9GND

10 GND

11 Monitor ID

12 DDCDA

13 HSYNC

14 YSYNC

15 DDCLK

6.6.6 Dual Gigabit Ethernet Ports

Table 26 lists the signals assigned to the dual gigabit ethernet ports connector.

Table 26. Dual Gigabit Ethernet Port Connector Pinout (Sheet 1 of 2)

Pin Connector Description

1/20 TERM

2/19 D4N

3/18 D3P

4/17 TD3

5/16 D2N

6/15 D1P

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Table 26. Dual Gigabit Ethernet Port Connector Pinout (Sheet 2 of 2)

Pin Connector Description

7/14 TD1

8/26 D4P

9/25 TD4

10/24 D3N

11/23 D2P

12/22 TD2

13/21 D1N

27/31 GRN_A

28/32 GRN_C

29/33 GRN_YEL_A

30/34 GRN_YEL_C

35/36/ 37/38

GND

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7.0 Board Setup Checklist

The following is a checklist of items to ensure proper functionality of the development kit.

• All cables are properly plugged in: — Hard drives — SATA and/or IDE — Monitor, keyboard, mouse — Additional peripherals such as CD, DVD, floppy, etc. — Power

• Fans are securely in pla ce and plu gge d into the appro pria te jumpe rs.

• Memory, PCI, and PCI Express* cards are secured in slots.

• RTC battery is install ed.

• Jumpers are configured correctly (refer to Section 6.4, “Jumpers” on page 54).

• Proper standoffs for benchtop use.

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8.0 Debug Procedure

The debug procedure in this section is used to determine baseline functionality for the

Core™ 2 Duo Processor and Intel® Core™ Duo Processor with Intel® E7520

Intel Chipset Development Kit. This is a cursory set of tests designed to provide a level of confidence in the platform operation.

8.1 Level 1 Debug (Port80/BIOS)

Refer to the steps in Tab le 27 when debugging a board that does not boot.

Table 27. Level 1 Debug (Port80/BIOS)

Step Test Passing Criteria Cause of Failure

1 Verify “SYSTEM PWRGD” LED Green

2 Is “PCI Reset” LED illuminated?

3 Verify CPURST LED is off Off

4 Verify Port 80 posting

5 Verify BIOS settings Latest BIOS installed

6 Verify default jumper settings See default settings Improper jumper settings

Decimal on Port 80 display RED

Port 80 LEDs are posting boot codes and stopping

Development Kit

Power sequence failure – go immediately to Level 2 debug

PCI reset stuck – go to Level 3 debug

CPU reset stu ck – go to Level 3 debug

System Hang – Check BIOS go to level 3 debug. Refer to AMI* BIOS documentation for details.

Contact Intel representative for the latest BIOS image

8.2 Level 2 Debug (Power Sequence)

Table 28. Level 2 Debug (Power Sequence)

Step Test Passing Criteria Cause of Failure

Measure voltages across:

3.3 V

1 Primary power supply voltages

2 1.8V 1.8 V DDR2 power supply failure

3 1.5V 1.5 V MCH/ICH core power supply failure

4 1.8V VSBY 1.8 V DDR2 standby power supply failure

5 CPU VTT Power Supply 1.05 V CPU_VTT power supply failure

6 CPU0 VRD 1.2 V–1.4 V CPU0 VRD failure

7 CPU1 VRD 1.2 V–1 .4 V CPU1 VRD failure

8 Verify “SYSTEM PWRGD” LED Green Power sequence failure

-12 V 5V 5V 12 V

External power supply failure

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8.3 Level 3 Debug (Voltage References)

Table 29 includes the first items to look at when debugging a board that is not booting.

Table 29. Level 3 Debug (Voltage Reference)

Step Test Passing Criteria Cause of Failure

1 MCH DDR2 Channel A Vref 0.9 V Vref incorrect: check resistor values

2 MCH DDR2 Channel B Vref 0.9 V Vref incorrect: check resistor values

3 MCH Hublink Vref 0.354 V Vref incorrect: check resistor values

4 MCH Hublink Vswing 0.804 V Vswing incorrect: check resistor values

5 ICH Hublink Vref 0.347 V Vref incorrect: check resistor values

6 ICH Hublink Vswing 0.696 V Vswing incorrect: check resistor values

CPU0 VTT Vref

(back side of board)

CPU1 VTT Vref

(back side of board)

9 MCH VTT Vref 0.775 V Vref incorrect: check resistor values

0.775 V Vref incorrect: check resistor values

0.754 V Vref incorrect: check resistor values

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Development Kit

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Intel BX80539T2500 - Core Duo 2 GHz Processor, BX80623I52550K, Core Duo Series User Manual

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