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24 Port 80h POST Code Ranges...................................................................................... 55
25 Typical Port 80h POST Sequence................................................................................55
June 2007User’s Manual
Order Nu mber: 316639 - 00 25
Revision History
DateRevision Description
June 2007002Added support for Intel® Core
March 2007001I nitial public release.
Revision History
TM
2 Duo Processor L7400 to this Customer Reference Board design.
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Product Description
1.0Product Description
1.1Overview
1.1.1Feature Summary
Table 1 summarizes the major features of the Customer Reference Board (CRB).
Table 1.Feature Summar y
FeatureDescription
Form FactorATX (12.00 inches by 10.75 inches)
ProcessorsRefer to Table 4, “Supported Micropro ces sors” on page 11.
Support for 400 MHz DDR2 Registered ECC
Memory
ChipsetIntel
VideoOn-board PCI ATI Rage* Mobility Video Chip
I/O ControlLow Pin Count (LPC) B us I/O Controller
USB
Per ipheral Inte rfaces
BIOS
LAN SupportSupports Dual Port PCI Express* Gigabit NIC
Expansion Capabilities
Hardware Mo ni t or Sub sys t em
2 Angled DIMM Sockets which support up to 4 GB RAM
Support for registered ECC only
®
3100 Chip se t
Support for USB 1.1 and 2.0 devices
T otal of four USB ports UHCI or EHCI configurations
Two serial ports
One parallel port
Total of six SATA Ports (two available modes):
• Enhanced IDE mode- Utilizes four SATA ports
• AHCI mode- Utilizes Six SATA ports
One floppy drive interface
PS/2* keyboard and mouse ports
Support for Advanced Configuration and Power Interface (ACPI), Plug and
Play, SMBIOS, and In tel® Active Management Technology (Intel® AMT)
Three PCI Express* x4 bus add-in card connectors
One PCI 32/33 bus add in card connector compliant with Specification 2.2
Hardware monitoring and fan control ASI
Voltage sense to detect out of range power supply voltages
Thermal sense to detect out of range thermal values
Four fan connectors
Four fan s ense inputs use to moni tor fan activity
Fan speed control
June 2007User’s Manual
Order Nu mber: 316639 - 00 27
Table 2 describes what is included in the Development Kit.
Table 2.Development Kit Contents
FeatureDescription
PCB
Processor
MemoryTwo 1 GB DDR2 DIMMs
ChipsetIntel® 3100 Chipset
Processor HeatsinkCoolermaster* Active Heatsink
Network CardIntel PC I Express* Gigabit NIC
Firmwa re HubSocket ed Fir m ware Hub (BIOS)
SoftwareDriver CD
Additional Peripherals
Product Description
®
CRB, Intel
Intel
Intel® CoreTM 2 Duo Pr ocessor L 7400, 1.50 GHz (installed)
Intel
Standoffs (with installation hardware) for Benchtop use
Warning:
Core™ 2 Duo Processor and Intel® Core™ Duo Processor an d
®
3100 Chipset
®
CoreTM Duo Proce s sor ULV U2500, 1.2 Ghz (s up pl i e d )
Placing the board on an unknown surface without standoffs may
short the CRB and result in damage. If CRB is not mounted in a
chassis, Intel recommends using provided Standoffs to prevent
risk of the bottom of the CRB shorting on a conductive surf ace.
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Product Description
1.1.2Board Lay out
Figure 1 shows the location of the major components.
Figure 1.Board Components
213
9
8
6
5
4
7
10
11
131415
12
16
19
20
33
34
35
33
32
31
30
36
37
38
Table 3 lists the components shown in Figure 1.
Table 3.Component Layout Description (Sheet 1 of 2)
CalloutDescription
132-bit/33 MHz PCI connector
2Port B x4 on l y PC I E xp r e ss* using x 8 c o nn e c to r
3Port A x4 only PCI Express* using x8 connector (A1)
4
5Port A x4 only PCI Express* using x8 connector (A0)
6CMOS battery
7Power button
8Reset button
9On-board speaker
10Back panel 15 Pin VGA connector
11USB ports (2) 3 top / 2 bottom
12USB ports (2) 0 top / 1 bottom
13Serial com port 2
14Parallel port
On-board PCI ATI Rage* Mobility Video Chip if available (if not on-board a
PCI add-in Card is supplied)
21
22
23
24
2526272829
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Table 3.Component Layout Description (Sheet 2 of 2)
CalloutDescription
15Serial com port 1
16PS/2* top = mouse / bottom = keyboard
17DIMM0 (Not used in This angled DIMM Design, two DIMMS only)
18DIMM1 (Not used in This angled DIMM Design, two DIMMS only)
19DIMM2
20DIMM3 (closest to edge of board)
21AUX FAN 1
22XDP connector
23JTAG connector
24AUX FAN 0
®
25Intel
26Processor with active fan plugged into processor FAN
27ATX 12 V for SATA power
28ATX power connector
29Floppy drive connector
30Port 80 seven segme nt displays
31Port 80 chip
32Firmw ar e hub (BI OS )
33Plug For validation only
34SATA port 0
35SATA port 1
36SATA port 2
37SATA port 3
38SATA port 4
39SATA port 5
3100 Chipset with active fan Connected to FAN1
Product Description
User’s ManualJune 2007
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Product Description
1.2Processors
The CRB is designed to support the following processors with a 533 and 667 MHz FSB
speed.
Use only the processors listed below in Table 4. Use of unsupported processors can
damage the CRB, the process or, and the power supp ly.
Note:In this document Processor refers to all processor SKUs listed in Table 4.
Table 4.Supported Microprocessors
MicroprocessorCores
Intel® Core™ 2 Duo Processor L7400Dual1.50GHz667MHz4MB17W
Intel® Core™ Duo proces sor ULV U2500Dual1.20GHz533MHz2MB9W
Intel® Celeron® M Processor ULV 423Single1.06GHz533MHz1MB5.5W
1.3System Memory
The CRB has two DIMM sockets and supports the following memory features:
• DDR2-400 MHz registered ECC
•SEC/DED
• Up to four ranks of memory
• Minimum total system memory: 512 MB, maximum of 4 GB
• ECC DIMMs, 8 bits ECC
• Single ch ann el op erati on on ly
• Supports x4 and x8 DDR2- 512 Mb and DDR2 -1 Gb t echno l ogies a nd x4 DDR 2-2 Gb
technologies
1.3.1DDR2-400 DIMM Slot Populations
Table 5 shows the supported DDR2-400 DIMM populations.
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1.3.2DDR2 DIMM Ordering Overview
Figure 2 shows the DIMM ordering and location.
Figure 2.Two-DIMM Implementation
Product Description
Fill SecondFill First
Can use two Dual-
Intel® 3100
Chipset
Rank DIMMs, One
Dual Rank and a
Single , or two single
rank DIMMS
The platform requires DDR2-400 DIMMs to be populated in order, starting with the
DIMM furthest from Intel
addition, dual-rank DIMMs must be populated farthest from Intel
a combination of single-rank and dual-rank DIMMs are used. This recommendation is
based on the chip select and on-die termination signals routing requirements of the
DDR2-400 interface. Intel recommends that you check for correct DIMM placement
during BIOS initialization and that all designs follow the DIMM ordering, clock enable
routing, command clock routing, and chip select routing shown in Figure 2. This
addressing must be maintained to be compliant with the BIOS code.
The two DIMMs that are provided with the development kit are 1 Gb singl e-rank
DIMMs. If other memory is used follow the illustrations in Figure 3, Figure 4, and
Figure 5. Figure 3 shows how to populate two single-rank DIMMs. Figure 4 shows how
to po pu la t e one du a l -r a nk and one single - r a nk DI MM s. Figure 5 shows how to populate
two dual-rank DIMMs.
®
3100 Chipset in a “fill-farthest” approach (see Figure 2). In
D
I
M
M
2
®
3100 Chipset when
D
I
M
M
3
User’s ManualJune 2007
12Order Nu mber: 316639 - 00 2
Product Description
Figure 3.Example of Single-Rank DIMM Population
Single Rank DIMM 2
Intel® 3100
Chipset
Figure 4.Example of Single-Rank and Dual-Rank DIMM Mixing Population
Single Rank DIMM 2
Intel® 3100
Chipset
Figure 5.Example of Dual-Rank DIMM Population
Single Rank DIMM 3
Dual Rank DIMM 3
Dual Rank DIMM 2
Intel® 3100
Chipset
June 2007User’s Manual
Order Nu mber: 316639 - 00 213
Dual Rank DIMM 3
1.4Intel® 3100 Chipset
Product Description
Figure 6.Inte l
®
3100 Chipset Block Diagram
Processor
WDT
Serial ATA
6 Drives
SM Bus x2
PCI 32/33
2 UART
4 USB-2 .0
38 GPIOs
LPC
Intel®3100 Chipset
IICHIMCH
Port B
PCI Express*
1x4 or 4x1
* Other names and brands may be claimed as the property of others.
FSB
Single-Me m ory
Channel
EDMA
Port A
PCI Exp ress*
1x8 configurable as 2x4 or 2x1
Registered ECC
DDR2 400
B5990-01
1.4.1On-Board Peripherals
Super I/O and PCI Video are included as on-board peripherals.
1.4.1.1Super I/O
Super I/O includes a Low Pin Count (LPC) driven Super I/O device that can be disabled
by removing a resistor.
1.4.1.2PCI Video
An ATI Rage* Mobility-M integrated video controller is located on the 32-bit, 33 MHz
PCI bus. Figure 7, “PCI On-Board Video Chip” on page 15 is a picture of the on board
chip.
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Product Description
Figure 7.PCI On-Board Video Chip
1.4.2On-Board I/O
The following sections include all of the on-board I/O.
1.4.2.1Serial ATA (SATA)
The CRB provides a total of six SATA interface connectors.
• Four usable SATA connectors in a SATA mode (BIOS setting) (SATA 0-3)
• Six SATA ports available in an AHCI mode (BIOS setting) (SATA 0-5)
• There are no RAID Capabilities on the chipset. Of course SW RAID is always and
option.
1.4.2.2Serial Connector
The CRB has one 10-pin, dual-row header.
• Provides the COM3 port from the Super I/O
1.4.2.3Floppy Drive
The CRB supplies a 34-pin, dual-row header.
• Floppy drive support comes from Super I/O
• The BIOS setup program configures the floppy drive interface
Figure 8.Floppy Drive Connector
1.4.2.4LPC Debug Port
The CRB includes one 60-pin card edge connector for LPC.
• Aligned with PCI connector (used for Intel Validation Only)
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1.4.2.5Front Panel Control Pins
1
The CRB includes a 10-pin, dual-row header.
• Provides Power Switch pins
• Provides Reset Switch pins
• Provides LED Power-On pins
• Provides LED HD Status pins
Figure 9.Front Panel Header
Product Description
Front Panel Heade r
1.4.2.6XDP Connector
The CRB includes one 60-pin XDP connector. XDP stands for Extended Debug Port and
can be used for debugging and testing components of the board.
Figure 10.XDP Connector
B5786- 0
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16Order Nu mber: 316639 - 00 2
Product Description
1.4.2.7USB
The CRB has a 10-pin, dual-row header to route two USB Ports to an external USB
connector.
• Allows two USB 1.1 or 2.0 ports to be routed to the dual-stack rear I/O or
optionally to the 10-pin header from the internal I/O. These USB ports are Port 2
and Port 3. Rear panel ports 2 and 3 are not simultaneously functional.
• By default, routing for USB is to the dual-stack header on the rear panel I/O.
• In conjunction with the rear panel USB Ports there are only a total of four USB
ports.
More information is available in Section 1.4.4.3, “USB Ports” on page 18.
1.4.3I/O Slots for Expansion Capabilities
1.4.3.1PCI Express*
The CRB provides a total of 3 x4 PCI Express* ports.
• Port A provides two x4 connections through two x8 connectors
• Port B provides one x4 connection through one x8 connector
• 32-bit ECRC (Port A only) stays with packet ensuring correct data at destination
• 256 opportunistic combining for read completions to improve performance
• ONLY Port A provides posted writes between each x4 port
• ONLY Port A provides memory-to-I/O DMA
Note:The PCI Express* Ports are x8 connectors, but ONLY have the functionality of a x4
connector. This enables you to use a x8 card on the CRB but it has the bandwidth and
functionality of the x4.
Warning:Hot-Plug is NOT supported on this platform.
1.4.3.2PCI
The CRB provides one PCI slot. It has the following characteristics:
• Specification 2.2 compliant
• 32-bit
• 33 MHz
• 12 0 MB / s th ro ughput
• 64-bit addressing through the DAC protocol
June 2007User’s Manual
Order Nu mber: 316639 - 00 217
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