The Intel® Desktop Board D915PLWD may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current
characterized errata are documented in the Intel Desktop Board D915PLWD Specification Update.
June 2005
Order Number: D23930-001US
Revision History
Revision Revision History Date
-001 First release of the Intel® Desktop Board D915PLWD Technical Product
Specification.
This product specification applies to only standard Intel Desktop Board D915PLWD with BIOS
identifier VG91510A.86A.
Changes to this specification will be published in the Intel Desktop Board D915PLWD
Specification Update before being incorporated into a revision of this document.
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June 2005
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.”
Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising
from future changes to them.
®
Intel
desktop boards may contain design defects or errors known as errata, which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
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Germany 44-0-1793-421-333, other Countries 708-296-9333.
Intel, Pentium, and Celeron are registered trademarks of Intel Corporation or its subsidiaries in the United States and other
countries.
This Technical Product Specification (TPS) specifies the board layout, components, connectors,
power and environmental requirements, and the BIOS for the Intel
It describes the standard product and available manufacturing options.
Intended Audience
The TPS is intended to provide detailed, technical information about the Desktop Board
D915PLWD and its components to the vendors, system integrators, and other engineers and
technicians who need this level of information. It is specifically not intended for general audiences.
What This Document Contains
Chapter Description
1 A description of the hardware used on the Desktop Board D915PLWD
2 A map of the resources of the Desktop Board
3 The features supported by the BIOS Setup program
4 A description of the BIOS error messages, beep codes, and POST codes
®
Desktop Board D915PLWD.
Typographical Conventions
This section contains information about the conventions used in this specification. Not all of these
symbols and abbreviations appear in all specifications of this type.
Notes, Cautions, and Warnings
NOTE
Notes call attention to important information.
INTEGRATOR’S NOTES
#
Integrator’s notes are used to call attention to information that may be useful to system integrators.
CAUTION
Cautions are included to help you avoid damaging hardware or losing data.
WARNING
Warnings indicate conditions, which if not observed, can cause personal injury.
# Used after a signal name to identify an active-low signal (such as USBP0#)
(NxnX) When used in the description of a component, N indicates component type, xn are the relative
coordinates of its location on the board, and X is the instance of the particular part at that
general location. For example, J5J1 is a connector, located at 5J. It is the first connector in
the 5J area.
GB Gigabyte (1,073,741,824 bytes)
GB/sec Gigabytes per second
KB Kilobyte (1024 bytes)
Kbit Kilobit (1024 bits)
kbits/sec 1000 bits per second
MB Megabyte (1,048,576 bytes)
MB/sec Megabytes per second
Mbit Megabit (1,048,576 bits)
Mbit/sec Megabits per second
xxh An address or data value ending with a lowercase h indicates a hexadecimal value.
x.x V Volts. Voltages are DC unless otherwise specified.
* This symbol is used to indicate third-party brands and names that are the property of their
The board is designed to support Intel Pentium 4 processors in an LGA775 processor socket with an
800 or 533 MHz system bus. See the Intel web site listed below for the most up-to-date list of
supported processors.
The board has two DIMM sockets and support the following memory features:
• 2.5 V (only) DDR SDRAM DIMMs with gold-plated contacts
• Unbuffered, single-sided or double-sided DIMMs with the following restriction:
Double-sided DIMMS with x16 organization are not supported.
• 2 GB maximum total system memory
• Minimum total system memory: 128 MB
• Non-ECC DIMMs
• Serial Presence Detect
• DDR 400 MHz and DDR 333 MHz SDRAM DIMMs
Table 3 lists the supported system bus frequency and memory speed combinations.
Table 3. Supported System Bus Frequency and Memory Speed Combinations
To use this type of DIMM… The processor's system bus frequency must be…
DDR 400 800 MHz
DDR 333
Note: When using an 800 MHz system bus frequency processor, DDR 333 memory is clocked at 320 MHz. This minimizes
(Note)
800 or 533 MHz
system latencies to optimize system throughput.
NOTES
To be fully compliant with all applicable DDR SDRAM memory specifications, the board should be
populated with DIMMs that support the Serial Presence Detect (SPD) data structure. This allows
the BIOS to read the SPD data and program the chipset to accurately configure memory settings
for optimum performance. If non-SPD memory is installed, the BIOS will attempt to correctly
configure the memory settings, but performance and reliability may be impacted or the DIMMs
may not function under the determined frequency.
Table 4 lists the supported DIMM configurations.
Table 4. Supported Memory Configurations
DIMM
Capacity
128 MB SS 256 Mbit 16 M x 16/empty 4
256 MB SS 256 Mbit 32 M x 8/empty 8
256 MB SS 512 Mbit 32 M x 16/empty 4
512 MB DS 256 Mbit 32 M x 8/32 M x 8 16
512 MB SS 512 Mbit 64 M x 8/empty 8
512 MB SS 1 Gbit 64 M x 16/empty 4
1024 MB SS 1 Gbit 128 M x 8/empty 8
Note: In the second column, “DS” refers to double-sided memory modules (containing two rows of SDRAM) and “SS” refers
to single-sided memory modules (containing one row of SDRAM).
Configuration
SDRAM
Density
SDRAM Organization
Front-side/Back-side
Number of SDRAM
Devices
16
Product Description
1.4.1 Memory Configurations
The Intel 82915PL MCH supports two types of memory organization:
•Dual channel (Interleaved) mode. This mode offers the highest throughput for real world
applications. Dual channel mode is enabled when the installed memory capacities of both
DIMM channels are equal. Technology and device width can vary from one channel to the
other but the installed memory capacity for each channel must be equal. If different speed
DIMMs are used between channels, the slowest memory timing will be used.
•Single channel (Asymmetric) mode. This mode is equivalent to single channel bandwidth
operation for real world applications. This mode is used when only a single DIMM is installed
or the memory capacities are unequal. Technology and device width can vary from one
channel to the other. If different speed DIMMs are used between channels, the slowest
memory timing will be used.
Figure 3 illustrates the memory channel and DIMM configuration.
Figure 4 shows a dual channel configuration using two DIMMs. In this example, the DIMM
sockets are populated with identical DIMMs.
1 GB
1 GB
Channel A, DIMM 0
Channel B, DIMM 0
OM17974
Figure 4. Dual Channel (Interleaved) Mode Configuration with Two DIMMs
18
Product Description
1.4.1.2 Single Channel (Asymmetric) Mode Configurations
NOTE
Dual channel (Interleaved) mode configurations provide the highest memory throughput.
Figure 5 shows a single channel configuration using one DIMM. In this example, only Channel A
is populated. Channel B is not populated.
256 MB
Figure 5. Single Channel (Asymmetric) Mode Configuration with One DIMM
Channel A, DIMM 0
Channel B, DIMM 0
OM17975
Figure 6 shows a single channel configuration using two DIMMs. In this example, the capacity of
the DIMM in Channel A does not equal the capacity of the DIMM in Channel B.
256 MB
512 MB
Channel A, DIMM 0
Channel B, DIMM 0
Figure 6. Single Channel (Asymmetric) Mode Configuration with Two DIMMs
The Intel 915PL chipset consists of the following devices:
• Intel 82915PL Memory Controller Hub (MCH) with Direct Media Interface (DMI) interconnect
• Intel 82801FB I/O Controller Hub (ICH6) with DMI interconnect
• Firmware Hub (FWH)
The MCH is a centralized controller for the system bus, the memory bus, the PCI Express bus, and
the DMI interconnect. The ICH6 is a centralized controller for the board’s I/O paths. The FWH
provides the nonvolatile storage of the BIOS.
For information about Refer to
The Intel 915PL chipset http://developer.intel.com/
Resources used by the chipset Chapter 2
1.5.1 USB
The board supports up to eight USB 2.0 ports, supports UHCI and EHCI, and uses UHCI- and
EHCI-compatible drivers.
The ICH6 provides the USB controller for all ports. The port arrangement is as follows:
• Four ports are implemented with dual stacked back panel connectors adjacent to the audio
connectors
• Four ports are routed to two separate front panel USB connectors
NOTE
Computer systems that have an unshielded cable attached to a USB port may not meet FCC
Class B requirements, even if no device is attached to the cable. Use shielded cable that meets the
requirements for full-speed devices.
For information about Refer to
The location of the USB connectors on the back panel Figure 12, page 43
The location of the front panel USB connectors Figure 13, page 44
1.5.2 IDE Support
The board providess five IDE interface connectors:
• One parallel ATA IDE connector that supports two devices
• Four serial ATA IDE connectors that support one device per connector
20
Product Description
1.5.2.1 Parallel ATA IDE Interface
The ICH6’s Parallel ATA IDE controller has one bus-mastering Parallel ATA IDE interface. The
Parallel ATA IDE interface supports the following modes:
• Programmed I/O (PIO): processor controls data transfer.
• 8237-style DMA: DMA offloads the processor, supporting transfer rates of up to 16 MB/sec.
• Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates
of up to 33 MB/sec.
• ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of
up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible.
• ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH6’s ATA-100
logic can achieve read transfer rates up to 100 MB/sec and write transfer rates up to 88 MB/sec.
NOTE
ATA-66 and ATA-100 are faster timings and require a specialized cable to reduce reflections,
noise, and inductive coupling.
The Parallel ATA IDE interface also supports ATAPI devices (such as CD-ROM drives) and ATA
devices using the transfer modes.
The BIOS supports Logical Block Addressing (LBA) and Extended Cylinder Head Sector (ECHS)
translation modes. The drive reports the transfer rate and translation mode to the BIOS.
For information about Refer to
The location of the Parallel ATA IDE connector Figure 13, page 44
1.5.2.2 Serial ATA Interfaces
The ICH6’s Serial ATA controller offers four independent Serial ATA ports with a theoretical
maximum transfer rate of 150 MB/s per port. One device can be installed on each port for a
maximum of four Serial ATA devices. A point-to-point interface is used for host to device
connections, unlike Parallel ATA IDE which supports a master/slave configuration and two devices
per channel.
For compatibility, the underlying Serial ATA functionality is transparent to the operating system.
The Serial ATA controller can operate in both legacy and native modes. In legacy mode, standard
IDE I/O and IRQ resources are assigned (IRQ 14 and 15). In Native mode, standard PCI
Conventional bus resource steering is used. Native mode is the preferred mode for configurations
using the Windows* XP and Windows 2000 operating systems.
NOTE
Many Serial ATA drives use new low-voltage power connectors and require adaptors or power
supplies equipped with low-voltage power connectors.
For more information, see: http://www.serialata.org/
For information about Refer to
The location of the Serial ATA IDE connectors Figure 13, page 44
A coin-cell battery (CR2032) powers the real-time clock and CMOS memory. When the computer
is not plugged into a wall socket, the battery has an estimated life of three years. When the
computer is plugged in, the standby current from the power supply extends the life of the battery.
The clock is accurate to ± 13 minutes/year at 25 ºC with 3.3 VSB applied.
NOTE
If the battery and AC power fail, custom defaults, if previously saved, will be loaded into CMOS
RAM at power-on.
1.6 PCI Express* Connectors
The board provides the following PCI Express connectors:
• One PCI Express x16 connector supporting simultaneous transfer speeds up to 8 GBytes/sec
• Two PCI Express x1 connectors. The x1 interfaces support simultaneous transfer speeds up to
500 MBytes/sec
The PCI Express interface supports the PCI Conventional bus configuration mechanism so that the
underlying PCI Express architecture is compatible with PCI Conventional compliant operating
systems. Additional features of the PCI Express interface include the following:
• Support for the PCI Express enhanced configuration mechanism
• Automatic discovery, link training, and initialization
• Support for Active State Power Management (ASPM)
• SMBus 2.0 support
• Wake# signal supporting wake events from ACPI S1, S3, S4, or S5
• Software compatible with the PCI Power Management Event (PME) mechanism defined in the
PCI Power Management Specification Rev. 1.1
22
Product Description
1.7 Legacy I/O Controller
The legacy I/O controller provides the following features:
• One serial port
• One parallel port with Extended Capabilities Port (ECP) and Enhanced Parallel Port
(EPP) support
• Serial IRQ interface compatible with serialized IRQ support for PCI Conventional bus systems
• PS/2-style mouse and keyboard interfaces
• Interface for one 1.44 MB or 2.88 MB diskette drive
• Intelligent power management, including a programmable wake-up event interface
• PCI Conventional bus power management support
The BIOS Setup program provides configuration options for the legacy I/O controller.
1.7.1 Serial Port
The Serial port A connector is located on the back panel. The serial port supports data transfers at
speeds up to 115.2 kbits/sec with BIOS support.
For information about Refer to
The location of the serial port A connector Figure 12, page 43
1.7.2 Parallel Port
The 25-pin D-Sub parallel port connector is located on the back panel. Use the BIOS Setup
program to set the parallel port mode.
For information about Refer to
The location of the parallel port connector Figure 12, page 43
1.7.3 Diskette Drive Controller
The legacy I/O controller supports one diskette drive. Use the BIOS Setup program to configure
the diskette drive interface.
For information about Refer to
The location of the diskette drive connector Figure 13, page 44
1.7.4 Keyboard and Mouse Interface
PS/2 keyboard and mouse connectors are located on the back panel.
NOTE
The keyboard is supported in the bottom PS/2 connector and the mouse is supported in the top PS/2
connector. Power to the computer should be turned off before a keyboard or mouse is connected or
disconnected.
For information about Refer to
The location of the keyboard and mouse connectors Figure 12, page 43
The board supports the Intel High Definition audio subsystem based on the Realtek ALC860VU
codec. The audio subsystem supports the following features:
• Advanced jack sense (front and rear panel) that enables the audio codec to recognize the device
that is connected to an audio port. All jacks are capable of retasking according to user’s
definition, or can be automatically switched depending on the recognized device type.
• Stereo input and output for all jacks
• A signal-to-noise (S/N) ratio of 90 dB
INTEGRATOR’S NOTE
#
For the front panel jack sensing and automatic retasking feature to function, a front panel daughter
card that is designed for Intel High Definition Audio must be used. Otherwise, an AC ’97 style
audio front panel connector will be assumed and the Line Out and Mic In functions will be
permanent.
1.8.1 Audio Subsystem Software
Audio software and drivers are available from Intel’s World Wide Web site.
For information about Refer to
Obtaining audio software and drivers Section 1.2, page 15
1.8.2 Audio Connectors
The board contains audio connector on both the back panel and the component side of the board.
The front panel audio connector is a 2 x 5-pin connector that provides mic in and line out signals
for front panel audio connectors.
For information about Refer to
The location of the front panel audio connector Figure 13, page 44
The signal names of the front panel audio connector Table 17, page 46
24
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