Intel BFCBASE - Motherboard - 7300, Xeon 7300 Series, Xeon 7200 Series Datasheet

Intel® Xeon® Processor 7200 Series and 7300 Series

Datasheet

September 2008

Notice: The Intel® Xeon® Processor 7200 Series and 7300 Series may contain design defects or errors known as errata which may cause the product t o deviate from published specifications. Current characterized errata are available on request.

Document Number: 318080-002

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING T O SALE AND/OR USE OF INTEL PRODUC TS INCLUDING LIABILITY OR WARRANTIES RELA TING T O FITNES S FOR A PARTICULAR PURPOSE, MERCHANT ABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel

reserves these for future definition and shall have no responsibility whatsoev er for conflicts or incompatibilities arising from future changes to them.

The Intel

Xeon® Processor 7200 Series and 7300 Series may contain design defects or errors known as errata which may cause

the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be

obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com Intel, Pentium, Intel Xeon, Intel SpeedStep, Intel Core, and Intel Virtualization Technology, are trademarks or registered

trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Intel® 64 requires a computer system with a processor, chipset, BIOS, OS, device drivers and applications enabled for Intel® 64.

Processor will not operate (including 32-bit operation) without an Intel® 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. Intel® 64-enabled OS, BIOS, device drivers and applications may not be available.

2 Document Number: 318080-002

Contents

1Introduction..............................................................................................................9

1.1 Terminology .....................................................................................................11

1.2 State of Data........................ .......................... .. .. ......................... .. ...................13

1.3 References.......................................................................................................13

2 Electrical Specifications...........................................................................................15

2.1 Front Side Bus and GTLREF ......................... ... .. .. ........................... .....................15

2.2 Decoupling Guidelines ........................................................................................15

2.2.1 VCC

2.2.2 VTT

2.2.3 Front Side Bus AGTL+ Decoupling ......................................... .. ... .. ............16

2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking.......................................16

2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])..................................17

2.3.2 PLL Power Supply...................................................................................17

2.4 Voltage Identification (VID) ................................................................................17

2.5 Reserved, Unused, or Test Signals.......................................................................20

2.6 Front Side Bus Signal Groups............. .. ........................... ....................................20

2.7 CMOS Asynchronous and Open Drain Asynchronous Signals....................................22

2.8 Test Access Port (TAP) Connection.......................................................................22

2.9 Mixing Processors..............................................................................................23

2.10 Absolute Maximum and Minimum Ratings........................................ .. .. ... ..............23

2.11 Processor DC Specifications................................................................................24

2.11.1 Flexible Motherboard Guidelines (FMB)......................................................25

2.11.2 Platform Environmental Control Interface (PECI) DC Specifications................35

2.11.3 VCC Overshoot Specification....................................................................37

2.11.4 AGTL+ FSB Specifications........................................................................38

2.12 Front Side Bus AC Specifications .................................................. .......................40

2.13 Processor AC Timing Waveforms .........................................................................45

3 Mechanical Specifications........................................................................................57

3.1 Package Mechanical Drawing...................... .........................................................57

3.2 Processor Component Keepout Zones....................... .. ............................ .. ............60

3.3 Package Loading Specifications .......................................... .. .. ........................... ..66

3.4 Package Handling Guidelines............................. .. .. .. ........................... .................67

3.5 Package Insertion Specifications................................................... .. .. .. ... ..............67

3.6 Processor Mass Specifications .............................................................................67

3.7 Processor Materials............................................................................................67

3.8 Processor Markings............................................................................................68

3.9 Processor Pin-Out Coordinates ............................................................................69

4 Pin Listing ...............................................................................................................71

4.1 Pin Assignments................................................................................................71

4.1.1 Pin Listing by Pin Name...........................................................................71

4.1.2 Pin Listing by Pin Number........................................................................79

5 Signal Definitions ....................................................................................................87

5.1 Signal Definitions. ............................ .. ........................... ....................................87

6 Thermal Specifications ............................................................................................95

6.1 Package Thermal Specifications.... ........................... ............................................95

6.1.1 Thermal Specifications............................................................................95

6.1.2 Thermal Metrology ............................................................................... 102

6.2 Processor Thermal Features.............................................................................. 103

6.2.1 Thermal Monitor Features...................................................................... 103

6.2.2 Thermal Monitor................................................................................... 103

Decoupling......................................................................................16

Document Number: 318080-002 3

6.2.3 Thermal Monitor 2 ....................................................... .. .......................104

6.2.4 On-Demand Mode.................................................................................105

6.2.5 PROCHOT# Signal .............................................. .. .......................... .. .. ..106

6.2.6 FORCEPR# Signal.................................................................................106

6.2.7 THERMTRIP# Signal......... .. .. ......................... .. .. .......................... .. .. ......106

6.3 Platform Environment Control Interface (PECI)....................................................107

6.3.1 Introduction.........................................................................................107

6.3.2 PECI Specifications ...............................................................................108

7Features................................................................................................................111

7.1 Power-On Configuration Options........................................................................111

7.2 Clock Control and Low Power States...... .. ................................................... .. .. .. ..111

7.2.1 Normal State .......................................................................................112

7.2.2 HALT or Extended HALT State.................................................................112

7.2.3 Stop-Grant State..................................................................................114

7.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant

Snoop State.........................................................................................115

7.3 Enhanced Intel SpeedStep® Technology............................................................. 115

7.4 System Management Bus (SMBus) Interface .......................................................116

7.4.1 SMBus Device Addressing ......................................................................117

7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions.......................118

7.4.3 Processor Information ROM (PIROM).......................................................119

7.4.4 Checksums..........................................................................................137

7.4.5 Scratch EEPROM...................................................................................137

8 Boxed Processor Specifications.............................................................................. 139

8.1 Introduction....................................................................................................139

8.2 Thermal Specifications........................... .. .. ..................................................... ..139

8.2.1 Boxed Processor Cooling Requirements....................................................139

9 Debug Tools Specifications ....................................................................................141

9.1 Debug Port System Requirements........... ........................... ................................141

9.2 Logic Analyzer Interface (LAI) ...........................................................................141

9.2.1 Mechanical Considerations .....................................................................141

9.2.2 Electrical Considerations........................................................................142

4 Document Number: 318080-002

Figures

2-1 Quad-Core Intel® Xeon® L7345 Processor Load Current versus Time .....................27

2-2 Dual-Core Dual-Core Intel® Xeon® Processor 7200 Series Load Current

versus Time.......................... ... ......................... .. .. ......................... .. .................28

2-3 Quad-Core Intel

Time28

2-4 Quad-Core Intel® Xeon® X7350 Processor Load Current versus Time .................29

2-5 Quad-Core Intel

Tolerance Load Lines ....................................... ......................... .. .. .....................31

2-6 Quad-Core Intel® Xeon® X7350 Processor VCC Static and Transient Tolerance

Load Lines......................................... .. ......................... .......................... .. ........32

2-7 Quad-Core Intel® Xeon® L7345 Processor V

Load Lines......................................... .. ......................... .......................... .. ........33

2-8 Dual-Core Intel® Xeon® Processor 7200 Series VCC Static and Transient

Tolerance Load Lines ....................................... ......................... .. .. .....................34

2-9 Input Device Hysteresis .....................................................................................37

2-10 VCC Overshoot Example Waveform......................................................................38

2-11 Electrical Test Circuit .........................................................................................46

2-12 TCK Clock Waveform .........................................................................................46

2-13 Differential Clock Waveform................................................................................47

2-14 Differential Clock Crosspoint Specification.............................................................47

2-15 BCLK Waveform at Processor Pad and Pin.............................................................48

2-16 FSB Common Clock Valid Delay Timing Waveform ............................ .. .. ... .. .. .. .. .. .. ..48

2-17 FSB Source Synchronous 2X (Address) Timing Waveform .......................................49

2-18 FSB Source Synchronous 4X (Data) Timing Waveform............................................50

2-19 TAP Valid Delay Timing Waveform.......................................................................51

2-20 Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform............... 51

2-21 THERMTRIP# Power Down Sequence ...................................................................51

2-22 SMBus Timing Waveform....................................................................................52

2-23 SMBus Valid Delay Timing Waveform...................................................................52

2-24 Voltage Sequence Timing Requirements ...............................................................53

2-25 FERR#/PBE# Valid Delay Timing .............................................. .. .........................54

2-26 VID Step Timings..............................................................................................54

2-27 VID Step Times and Vcc Waveforms ....................................................................55

3-1 Processor Package Assembly Sketch ....................................................................57

3-2 Processor Package Drawing (Sheet 1 of 2)............................................................58

3-3 Processor Package Drawing (Sheet 2 of 2)............................................................59

3-4 Top Side Board Keepout Zones (Part 1)................................................................61

3-5 Top Side Board Keepout Zones (Part 2)................................................................62

3-6 Bottom Side Board Keepout Zones.......................................................................63

3-7 Board Mounting-Hole Keepout Zones ...................................................................64

3-8 Volumetric Height Keep-Ins................................................................................65

3-9 Processor Topside Markings................................................................................68

3-10 Processor Bottom-Side Markings .........................................................................68

3-11 Processor Pin-Out Coordinates, Top View..............................................................69

6-1 Quad-Core Intel® Xeon® E7300 Processor Thermal Profile.....................................97

6-2 Quad-Core Intel® Xeon® X7350 Processor Thermal Profile.....................................98

6-3 Quad-Core Intel® Xeon® L7345 Processor Thermal Profile................................... 100

6-4 Dual-Core Intel® Xeon® Processor 7200 Series Thermal Profile ........................... 101

6-5 Case Temperature (TCASE) Measurement Location.............................................. 103

6-6 Thermal Monitor 2 Frequency and Voltage Ordering ............................................. 105

6-7 PECI Topology ................................................................................................ 107

Xeon® Processor 7200 Series and 7300 Series Load Current versus

Xeon® Processor 7200 Series and 7300 Series VCC Static and Transient

Static and Transient Tolerance

Document Number: 318080-002 5

6-8 Conceptual Fan Control Diagram For a PECI-Based Platform ..................... ... .. .. ......108

7-1 Stop Clock State Machine..................................................................................114

7-2 Logical Schematic of SMBus Circuitry..................................................................117

Tables

1-1 Quad-Core Intel® Xeon® Processor 7300 Series Processor Features ........................10

1-2 Dual-Core Intel® Xeon® Processor 7200 Series Processor Features .........................10

2-1 Core Frequency to FSB Multiplier Configuration......................................................17

2-2 BSEL[2:0] Frequency Table.................................................................................17

2-3 Voltage Identification Definition ...........................................................................19

2-4 FSB Signal Groups.............................................................................................21

2-5 AGTL+ Signal Description Table...........................................................................22

2-6 Non AGTL+ Signal Description Table.....................................................................22

2-7 Signal Reference Voltages...................................................................................22

2-8 Processor Absolute Maximum Ratings............................. .. .. ..................................23

2-9 Voltage and Current Specifications.......................................................................25

2-10 VCC Static and Transient Tolerance......................................................................30

2-11 AGTL+ Signal Group DC Specifications............................................. .....................34

2-12 CMOS Signal Input/Output Group DC Specifications................................................35

2-13 Open Drain Signal Group DC Specifications ...........................................................35

2-14 SMBus Signal Group DC Specifications..................................................................35

2-15 PECI DC Electrical Limits.....................................................................................36

2-16 VCC Overshoot Specifications..............................................................................37

2-17 AGTL+ Bus Voltage Definitions ............................................................................39

2-18 FSB Differential BCLK Specifications.....................................................................39

2-19 Front Side Bus Differential Clock AC Specifications .................................................40

2-20 Front Side Bus Common Clock AC Specifications ....................................................40

2-21 FSB Source Synchronous AC Specifications............................................................41

2-22 Miscellaneous GTL+ AC Specifications...................................................................42

2-23 Front Side Bus AC Specifications (Reset Conditions) ...............................................42

2-24 TAP Signal Group AC Specifications ......................................................................42

2-25 VID Signal Group AC Specifications ......................................................................44

2-26 SMBus Signal Group AC Specifications ..................................................................44

3-1 Processor Loading Specifications..........................................................................66

3-2 Package Handling Guidelines...............................................................................67

3-3 Processor Materials............................................................................................67

4-1 Pin Listing by Pin Name ......................................................................................71

4-2 Pin Listing by Pin Number ...................................................................................79

5-1 Signal Definitions...............................................................................................87

6-1 Quad-Core Intel® Xeon® E7300 Processor Thermal Specifications ...........................96

6-2 Quad-Core Intel® Xeon® E7300 Processor Thermal Profile Table............... ..............97

6-3 Quad-Core Intel® Xeon® X7350 Processor Thermal Specifications........................ .. .98

6-4 Quad-Core Intel® Xeon® X7350 Processor Thermal Profile Table.............................99

6-5 Quad-Core Intel® Xeon® L7345 Processor Thermal Specifications ................ .... .. .. ...99

6-6 Quad-Core Intel® Xeon® L7345 Processor Thermal Profile....................................100

6-7 Dual-Core Intel® Xeon® Processor 7200 Series Thermal Specifications ..................101

6-8 Dual-Core Intel® Xeon® Processor 7200 Series Thermal Profile................. ............102

6-9 BREQ# signal assertion during power on.............................................................109

6-10 PECI Address assigned to processor ...................................................................109

6-11 GetTemp0() and GetTemp1() Error Codes........... .. .. .. .. ........................... ... .. .. .. ....110

7-1 Power-On Configuration Option pins...................................................................111

6 Document Number: 318080-002

7-2 Extended HALT Maximum Power......... .. ......................... .. .......................... ........ 113

7-3 Memory Device SMBus Addressing..................................................................... 118

7-4 Read Byte SMBus Packet.................................................................................. 118

7-5 Write Byte SMBus Packet ................................................................................. 118

7-6 Processor Information ROM Data Sections .......................................................... 119

7-7 128 Byte ROM Checksum Values ....................................................................... 137

Document Number: 318080-002 7

Revision History

Document

Number

318080 -001 • Initial Release September 2007 318080 -002 • Changed Product Name to Intel

Revision Description Date

7300 Series

• Updated Power Specifications

• The character byte ordering was reversed for the following fields: SQNUM: S-Spec QDF Number PREV: Package Revision PPN: Processor Part Number

• Updated the Processor Mechanical drawings to add an optional small shallow depression in the top right-hand side corner of the integrated heat spreader (IHS). This feature, which supports anti-mixing, may be seen on some processor packages. There are no major electrical, mechanical, or thermal differences in the form, fit or function of the processors with or without this feature.

• Update d PROC_ID[1:0] Definition

Xeon® Processor 7200 Series and

September 2008

8 Document Number: 318080-002

Introduction

1 Introduction

ALL INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE. The Intel® Xeon® Processor 7200 Series and 7300 Series are multi-processor servers

utilizing four Intel® CoreTM microarchitecture cores. These processors are based on Intel’s 65 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. The Quad-Core Intel Series consists of two die, each die containing two processor cores. The Dual-Core

Xeon® 7200 Series consists of two die, each die containing one processor core.

Intel All processors maintain the tradition of compatibility with IA-32 software. Some key features include on-die, 64 KB Level 1 instruction data caches per die and 2x4MB shared Level 2 cache with Advanced Transfer Cache Architecture. The processor’s Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting in reduced bus cycle penalties and improved performance. The 1066 MHz Front Side Bus (FSB) is a quad-pumped bus running off a 266 MHz system clock making 8.5 GBytes per second data transfer rates possible. The Quad-Core Intel Xeon® X7350 processor offers higher clock frequencies than the other Quad-Core

Xeon® Processor 7300 Series for platforms that are targeted for the

Intel performance optimized segment. The Quad-Core Intel® Xeon® L7345 Processor is a lower voltage, lower power processor.

Xeon® 7300

Enhanced thermal and power management capabilities are implemented including Thermal Monitor (TM1), Thermal Monitor 2 (TM2) and Enhanced Intel SpeedStep

Technology. TM1 and TM2 provide efficient and effective cooling in high temperature situations. Enhanced Intel SpeedStep Technology allows trade-offs to be made between performance and power consumption. This may lower average power consumption (in conjunction with OS support).

The Intel

Xeon® Processor 7200 Series and 7300 Series features include Advanced Dynamic Execution, enhanced floating point and multi-media units, Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3). Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor. The floating point and multi-media units include 128-bit wide registers and a separate register for data movement. SSE3 instructions provide highly efficient doubleprecision floating point, SIMD integer, and memory management operations.

The Intel

Xeon® Processor 7200 Series and 7300 Series support Intel® 64 as an enhancement to Intel's IA-32 architecture. This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64-bit extension technology. Further details on Intel model can be found in the Intel

64 and IA-32 Architectures Software Developer's

64 Technology and its programming

Manual.

In addition, the Intel

Xeon® Processor 7200 Series and 7300 Series support the Execute Disable Bit functionality. When used in conjunction with a supporting operating system, Execute Disable allows memory to be marked as executable or non executable. This feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. Further details on Execute Disable can be found at

http://www.intel.com/cd/ids/developer/asmo-na/eng/149308.htm.

Document Number: 318080-002 9

The Intel® Xeon® Processor 7200 Series and 7300 Series support Intel® Virtualization Te chnology for hardware-assisted virtualization within the processor. Intel Virtualization Technology is a set of hardware enhancements that can improve virtualization solutions. Intel Virtualization Technology is used in conjunction with Virtual Machine Monitor software enabling multiple, independent software environments inside a single platform. Further details on Intel Virtualization T echnology can be found at http://developer.intel.com/technology/vt.

The Intel

Xeon® Processor 7200 Series and 7300 Series are intended for high performance multi-processor server systems. The processors support a Multi Independent Bus (MIB) architecture with one processor on each bus. The MIB architecture provides improved performance by allowing increased FSB speeds and bandwidth. All versions of the Intel

Xeon® Processor 7200 Series and 7300 Series will include manageability features. Components of the manageability features include an OEM EEPROM and Processor Information ROM which are accessed through an SMBus interface and contain information relevant to the particular processor and system in which it is installed. The Intel packaged in a 604-pin Flip Chip Micro Pin Grid Array (FC-mPGA6) package and utilizes a surface-mount Zero Insertion Force (ZIF) mPGA604 socket. The Intel

Xeon® Processor 7200 Series and 7300 Series is

Xeon®

Processor 7200 Series and 7300 Series support 40-bit addressing.

Table 1-1. Quad-Core Intel® Xeon® Processor 7300 Series Processor Features

Introduction

# of Processor

Cores

4 32 KB instruction

L1 Cache per core

32 KB data

L2 Advanced

Transfer Cache

4M Shared L2 Cache per die

8M Total Cache

Front Side Bus

Frequency

1066 MHz FC-mPGA6

Table 1-2. Dual-Core Intel® Xeon® Processor 7200 Series Processor Features

# of Processor

Cores

2 32 KB instruction

Xeon® Processor 7200 Series and 7300 Series-based platforms implement

Intel independent core voltage (V voltage (V

L1 Cache per core

32 KB data

) power planes for each processor. FSB termination

) is shared and must connect to all FSB agents. The processor core voltage

L2 Advanced

Transfer Cache

4M L2 Cache per die

8M Total Cache

Front Side Bus

Frequency

1066 MHz FC-mPGA6

utilizes power delivery guidelines specified by VRM/EVRD 11.0 and its associated load line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details). VRM/EVRD 11.0 will support the power requirements of all frequencies of the processors including Flexible Motherboard Guidelines (FMB) (see Section 2.11.1). Refer to the appropriate platform design guidelines for implementation details.

The Intel

Xeon® Processor 7200 Series and 7300 Series supports 1066 MHz Front Side Bus operation. The FSB utilizes a split-transaction, deferred reply protocol and Source-Synchronous Transfer (SST) of address and data to improve performance. The processor transfers data four times per bus clock (4X data transfer r ate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a ‘double-clocked’ or a 2X address bus. In addition, the Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 8.5 GBytes per second. The FSB is also used to deliver interrupts.

Package

10 Document Number: 318080-002

Introduction

Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages.

Section 2.1 contains the electrical specifications of the FSB while implementation

details are fully described in the appropriate platform design guidelines (refer to

Section 1.3).

1.1 Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

Commonly used terms are explained here for clarification:

• Enhanced Intel SpeedStep Technology is the next generation implementation of the Geyserville technology which extends power management capabilities of servers.

• FC-mPGA6 — The Intel available in a Flip-Chip Micro Pin Grid Array 6 package, consisting of a processor core mounted on a pinned substrate with an integrated heat spreader (IHS). This packaging technology employs a 1.27 mm [0.05 in] pitch for the substrate pins.

• mPGA604 — The Intel® Xeon® Processor 7200 Series and 7300 Series package mates with the system board through this surface mount, 604-pin, zero insertion force (ZIF) socket.

• Processor core – Processor core with integrated L1 cache. L2 cache and system bus interface are shared between the two cores on the die. All AC timing and signal integrity specifications are at the pads of the processor die.

• FSB (Front Side Bus) – The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB.

• Multi Independent Bus (MIB) – A front side bus architecture with one processor on each bus, rather than a FSB shared between multiple processor agents. The MIB architecture provides improved performance by allowing increased FSB speeds and bandwidth.

• Flexible Motherboard Guidelines (FMB) – Are estimates of the maximum values the Intel® Xeon® Processor 7200, 7300 Series will have over certain time periods. The values are only estimates and actual specifications for future processors may differ.

• Functional Operation – Refers to the normal operating conditions in which all processor specifications, including DC, AC, FSB, signal quality, mechanical and thermal are satisfied.

• Storage Conditions – Refers to a non-operational state. The processor may be installed in a platform, in a tray , or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor pins should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (that is, unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.

Technology — Enhanced Intel SpeedStep®

Xeon® Processor 7200 Series and 7300 Series package is

Document Number: 318080-002 11

Introduction

• Processor Information ROM (PIROM) — A memory device located on the processor and accessible via the System Management Bus (SMBus) which contains information regarding the processor’s features. This device is shared with the Scratch EEPROM, is programmed during manufacturing, and is write-protected.

• Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory) — A memory device located on the processor and addressable via the SMBus which can be used by the OEM to store information useful for system management.

• SMBus — System Management Bus. A two-wire interface through which simple system and power management related devices can communicate with the rest of the system. It is based on the principals of the operation of the I

C* two-wire serial

bus from Phillips Semiconductor. Note: I2C is a two-wire communications bus/protocol developed by Phillips.

SMBus is a subset of the I Implementations of the I

C bus/protocol and was developed by Intel.

C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Phillips Electronics N.V. and North American Phillips Corporation.

• Priority Agent – The priority agent is the host bridge to the processor and is typically known as the chipset.

• Symmetric Agent – A symmetric agent is a processor which shares the same I/O subsystem and memory array, and runs the same operating system as another processor in a system. Systems using symmetric agents are known as Symmetric Multiprocessing (SMP) systems.

• Integrated Heat Spreader (IHS) – A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.

• Thermal Design Power – Processor thermal solutions should be designed to meet this target. It is the highest expected sustainable power while running known power intensive real applications. TDP is not the maximum power that the processor can dissipate.

•Intel® 64 – Instruction set architecture and programming environment of Intel’s 64-bit processors, which are a superset of and compatible with IA-32. This 64-bit instruction set architecture was formerly known as IA-32 with EM64T or Intel

EM64T.

• Platform Environment Control Interface (PECI) – A proprietary one-wire bus interface that provides a communication channel between Intel processor and chipset components to external thermal monitoring devices, for use in fan speed control. PECI communicates readings from the processor’s Digital Thermal Sensors (DTS). The DTS replaces the thermal diode available in previous processors.

• Intel

Virtualization Technology – Processor virtualization which when used in

conjunction with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform.

• VRM (Voltage Regulator Module) – DC-DC converter built onto a module that interfaces with a card edge socket and supplies the correct voltage and current to the processor based on the logic state of the processor VID bits.

• EVRD (Enterprise Voltage Regulator Down) – DC-DC converter integrated onto the system board that provides the correct voltage and current to the processor based on the logic state of the processor VID bits.

• V

– The processor core power supply.

– The processor ground.

– FSB termination voltage.

12 Document Number: 318080-002

Introduction

1.2 State of Data

This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design

1.3 References

Material and concepts available in the following documents may be beneficial when reading this document:

Document

AP-485, Intel

Intel

64 and IA-32 Architectures Software Developer's Manual

Processor Identification and the CPUID Instruction 241618 1

• Volume 1: Basic Architecture

• Volume 2A: Instruction Set Reference, A-M

• Volume 2B: Instruction Set Reference, N-Z

• Volume 3A: System Programming Guide Part 1

• Volume 3B: System Programming Guide, Part 2

IA-32 Intel Documentation Changes

IA-32 Intel Intel

Architecture and Intel® 64 Software Developer's Manual

Architecture Optimization Reference Manual 248966 1

Extended Memory 64 Technology

• Volume I

• Volume 2

Intel

Virtualization Technology for IA-32 Processors (VT-x) Preliminary

Specification Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon®

Processor 7300 Series Specification Update

Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD)

11.0 Design Guidelines EPS12V Power Supply Design Guide: A Server system Infrastructure (SSI)

Specification for Entry Chassis Power Supplies

Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series Thermal / Mechanical Design Guide

Intel

Xeon® Processor 7200 Series and 7300 Series Package Mechanical Models 1

mPGA604 Socket Design Guide 254239 1

Intel

Xeon® Processor 7200 Series and 7300 Series Enabled Components (CEK)

Thermal Models

Xeon® Processor 7200 Series and 7300 Series Enabled Components (CEK)

Intel Mechanical Models

Document

Number

253665 253666 253667 253668 253669

252046

300834 300835

C97063 1

318081 1

315889 1

318086 1

Notes

Intel® Xeon® Processor 7200 Series and 7300 Series Boundary Scan Descriptive Language (BSDL) Model

Notes:

1. Document is available publicly at http://developer.intel.com.

2. Document available on www.ssiforum.org.

Document Number: 318080-002 13

Introduction

14 Document Number: 318080-002

Electrical Specifications

2 Electrical Specifications

2.1 Front Side Bus and GTLREF

Most Intel® Xeon® Processor 7200 Series and 7300 Series FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high logic level and termination. AGTL+ output buffers differ from GTL+ buffers with the addition of an active PMOS pull-up transistor to “assist” the pull-up resistors during the first clock of a low-to-high voltage transition. Platforms implement a termination voltage level for AGTL+ signals defined as V power planes for each processor (and chipset), separate V necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address buses have made signal integrity considerations and platform design methods even more critical than with previous processor families. Design guidelines for the processor FSB are detailed in the appropriate platform design guidelines (refer to Section 1.3).

The AGTL+ inputs require reference voltages (GTLREF_DATA_MID, GTLREF_DAT A_END , GTLREF_ADD_MID and GTLREF_ADD_END) which are used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF_DATA_MID and GTLREF_DATA_END are used for the 4X front side bus signaling group and GTLREF_ADD_MID and GTLREF_ADD_END are used for the 2X and common clock front side bus signaling groups. GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END must be generated on the baseboard (See

Table 2-17 for GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID and

GTLREF_ADD_END specifications). Refer to the applicable platform design guidelines for details. Termination resistors (R silicon and are terminated to VTT. The on-die termination resistors are always enabled on the processor to control reflections on the transmission line. Intel chipsets also provide on-die termination, thus eliminating the need to terminate the bus on the baseboard for most AGTL+ signals.

) for AGTL+ signals are provided on the processor

. Because platforms implement separate

and VTT supplies are

Some FSB signals do not include on-die termination (R the baseboard. See Table 2-4 and Table 2-6 for details regarding these signals.

The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the FSB, including trace lengths, is highly recommended when designing a system. Contact your Intel Field Representative to obtain the processor signal integrity models, which includes buffer and package models.

2.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. Care must be taken in the baseboard design to ensure that the voltage provided to the processor

Document Number: 318080-002 15

) and must be terminated on

Electrical Specifications

remains within the specifications listed in Table 2-9. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and guidelines, refer to the appropriate platform design guidelines.

2.2.1 V

2.2.2 V

Decoupling

Vcc regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR). Bulk decoupling must be provided on the baseboard to handle large current swings. The power delivery solution must ensure the voltage and current specifications are met (as defined in Table 2-9). For further information regarding power delivery, decoupling and layout guidelines, refer to the appropriate platform design guidelines.

Decoupling

Bulk decoupling must be provided on the baseboard. Decoupling solutions must be sized to meet the expected load. To ensure optimal performance, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution consists of a combination of low ESR bulk capacitors and high frequency ceramic capacitors. For further information regarding power delivery, decoupling and layout guidelines, refer to the appropriate platform design guidelines.

2.2.3 Front Side Bus AGTL+ Decoupling

The processor integrates signal termination on the die, as well as a portion of the required high frequency decoupling capacitance on the processor package. However, additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the FSB. Bulk decoupling must also be provided by the baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in the appropriate platform design guidelines.

2.3 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous processor generations, the processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is set during manufacturing. The default setting is for the maximum speed of the processor.

The processor core frequency is configured during reset by using values stored internally during manufacturing. The stored value sets the highest bus fraction at which the particular processor can operate. If lower speeds are desired, the appropriate ratio can be configured via the CLOCK_FLEX_MAX Model Specific Register (MSR).

Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread spectrum clocking. Processor DC and AC specifications for the BCLK[1:0] inputs are provided in Table 2-18 and Table 2-19, respectively. These specifications must be met while also meeting signal integrity requirements as outlined in Table 2-18. The processor utilizes differential clocks. Table 2-1 contains processor core frequency to FSB multipliers and their corresponding core frequencies.

16 Document Number: 318080-002

Electrical Specifications

Table 2-1. Core Frequency to FSB Multiplier Configuration

Core Frequency to FSB

Multiplier

1/6 1.60 GHz 1, 2, 3, 4 1/7 1.86 GHz 1, 2, 3 1/8 2.13 GHz 1, 2, 3

1/9 2.40 GHz 1, 2, 3 1/10 2.66 GHz 1, 2, 3 1/11 2.93 GHz 1, 2, 3

Notes:

1. Individual processors operate only at or below the frequency marked on the package.

2. Listed frequencies are not necessarily committed production frequencies.

3. For valid processor core frequencies, refer to the Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series Specification Update.

4. The lowest bus ratio supported is 1/6.

Core Frequency with

266 MHz FSB Clock

Notes

2.3.1 Front Side Bus Frequency Select Signals (BSEL[2:0])

Upon power up, the FSB frequency is set to the maximum supported by the individual processor. BSEL[2:0] are CMOS outputs that are used to select the FSB frequency. Please refer to Table 2-11 for DC specifications. Table 2-2 defines the possible combinations of the signals and the frequency associated with each combination. The frequency is determined by the processor(s), chipset, and clock synthesizer. All FSB agents must operate at the same core and FSB frequency. See the appropriate platform design guidelines for further details.

Table 2-2. BSEL[2:0] Frequency Tab le

BSEL2 BSEL1 BSEL0 Bus Clock Frequency

000 266 MHz 001 Reserved 010 Reserved 011 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Reserved

2.3.2 PLL Power Supply

An on-die PLL filter solution is implemented on the processor. The V to provide power to the on chip PLL of the processor. Please refer to Table 2-9 for DC specifications. Refer to the appropriate platform design guidelines for decoupling and routing guidelines.

2.4 Voltage Identification (VID)

The Voltage Identification (VID) specification for the processor is defined by the

Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines. The voltage set by the VID signals is the reference VR output

voltage to be delivered to the processor Vcc pins. VID signals are asynchronous CMOS

input is used

CCPLL

Document Number: 318080-002 17

Electrical Specifications

outputs. Please refer to Table 2-12 for the DC specifications for these signals. A voltage range is provided in Table 2-3 and changes with frequency. The specifications have been set such that one voltage regulator can operate with all supported frequencies.

Individual processor VID values may be calibrated during manufacturing such that two devices at the same core frequency may have different default VID settings. This is reflected by the VID range values provided in Table 2-3.

The processor uses six voltage identification signals, VID[6:1], to support automatic selection of power supply voltages. Table 2-3 specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. The definition provided in Table 2-3 is not related in any way to previous Intel

Xeon® processors or voltage regulator designs. If the processor socket is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply the voltage that is requested, the voltage regulator must disable itself. See the Voltage

Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details.

Although the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines defines VID [7:0], VID 7 and VID 0 are not used on the

Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series.

The Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (V

). This will represent a DC shift in

the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted. Table 2-10 includes VID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 2-2 and Table 2-3.

The VRM or EVRD utilized must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 2-9 and Table 2-10, while AC specifications are included in Table 2-25. Refer to the Voltage

Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details.

Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable.

18 Document Number: 318080-002

Electrical Specifications

Table 2-3. Voltage Identification Definition

VID5

VID4

VID3

VID2

HEX

VID6

400

200

100 mV

VID1

12.5 mV

CC_MAX

HEX

7A111101 0.8500 3C 0 1 1 1 1 0 1.2375 7811110 7611101 7411101 7211100 7011100 6E11011 6C11011 6A11010

0 0.8625 3A 0 1 1 1 0 1 1.2500 1 0.8750 38 0 1 1 1 0 0 1.2625 0 0.8875 36 0 1 1 0 1 1 1.2750 1 0.9000 34 0 1 1 0 1 0 1.2875 0 0.9125 32 0 1 1 0 0 1 1.3000 1 0.9250 30 0 1 1 0 0 0 1.3125 0 0.9375 2E 0 1 0 1 1 1 1.3250

1 0.9500 2C 0 1 0 1 1 0 1.3375 68 1 1 0 1 0 0 0.9625 2A 0 1 0 1 0 1 1.3500 66 1 1 0 0 1 1 0.9750 28 0 1 0 1 0 0 1.3625 64 1 1 0 0 1 0 0.9875 26 0 1 0 0 1 1 1.3750 62 1 1 0 0 0 1 1.0000 24 0 1 0 0 1 0 1.3875 60 1 1 0 0 0 0 1.0125 22 0 1 0 0 0 1 1.4000 5E 1 0 1 1 1 1 1.0250 20 0 1 0 0 0 0 1.4125 5C 1 0 1 1 1 0 1.0375 1E 0 0 1 1 1 1 1.4250 5A 1 0 1 1 0 1 1.0500 1C 0 0 1 1 1 0 1.4375 58 1 0 1 1 0 0 1.0625 1A 0 0 1 1 0 1 1.4500 56 1 0 1 0 1 1 1.0750 18 0 0 1 1 0 0 1.4625 54 1 0 1 0 1 0 1.0875 16 0 0 1 0 1 1 1.4750 52 1 0 1 0 0 1 1.1000 14 0 0 1 0 1 0 1.4875 50 1 0 1 0 0 0 1.1125 12 0 0 1 0 0 1 1.5000 4E 1 0 0 1 1 1 1.1250 100010001.5125 4C 1 0 0 1 1 0 1.1375 0E0001111.5250 4A 1 0 0 1 0 1 1.1500 0C0001101.5375 48 1 0 0 1 0 0 1.1625 0A0001011.5500 46 1 0 0 0 1 1 1.1750 080001001.5625 44 1 0 0 0 1 0 1.1875 060000111.5750 42 1 0 0 0 0 1 1.2000 040000101.5875 40 1 0 0 0 0 0 1.2125 020000011.6000 3E 0 1 1 1 1 1 1.2250 00000000OFF

VID6

400

VID5

200

VID4

100

VID3

VID2

VID1

12.5 mV

CC_MAX

Notes:

1. When this VID pattern is observed, the voltage regulator output should be disabled.

2. Shading denotes the expected VID range of the Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series.

3. The VID range includes VID transitions that may be initiated by thermal events, assertion of the FORCEPR# signal (see

Section 6.2.3), Extended HALT state transitions (see Section 7.2.2), or Enhanced Intel SpeedStep

(see Section 7.3). The Extended HALT state must be enabled for the processor to remain within its specifications.

4. Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a specifi c VID o ff code i s received, the VRM/EVRD must turn off its output (the output should go to high impedance) within 500 ms and latch off until power is cycled. Refer to Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines.

Document Number: 318080-002 19

Technology transitions

2.5 Reserved, Unused, or Test Signals

All Reserved signals must remain unconnected. Connection of these signals to VCC, VTT,

, or to any other signal (including each other) can result in component malfunction

or incompatibility with future processors. See Section 4 for a pin listing of the processor and the location of all Reserved signals.

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active high inputs, should be connected through a resistor to ground (V interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the baseboard trace for FSB signals, unless otherwise noticed in the appropriate platform design guidelines. For unused AGTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (R

TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include ondie termination. Inputs and utilized outputs must be terminated on the baseboard. Unused outputs may be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. Signal termination for these signal types is discussed in the appropriate platform design guidelines.

). Unused outputs can be left unconnected; however, this may

). For details see Table 2-24.

Electrical Specifications

For each processor socket, connect the TESTIN1 and TESTIN2 signals together, then terminate the net with a 51 Ω resistor to V

The TESTHI signal must be tied to the processor VTT using a matched resistor, where a matched resistor has a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω is required.

The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group:

• TESTHI[1:0] - can be grouped together with a single pull-up to V

2.6 Front Side Bus Signal Groups

The FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END as reference levels. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly , “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. AGTL+ asynchronous outputs can become active anytime and include an active PMOS pull-up transistor to assist during the first clock of a low-to-high voltage transition.

With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals whose timings are specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 2-4 identifies which signals are common clock, source synchronous and asynchronous.

20 Document Number: 318080-002

Electrical Specifications

Table 2-4. FSB Signal Groups

Signal Group Type Signals

AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#,

AGTL+ Common Clock Output Synchronous to BCLK[1:0] BPM4#, BPM[2:1]#, BPMb[2:1]# AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, AP[1:0]#, BINIT#

AGTL+ Source Synchronous I/O

Synchronous to assoc. strobe

TRDY#;

BPM3#, BPM0#, BPMb3#, BPMb0#, BR[1:0]#, DBSY#, DP[3:0]#, DRDY#, HIT#

, LOCK#, MCERR#

HITM#

, BNR#2, BPM5#,

Signals Associated Strobe

REQ[4:0]# A[37:36,16:3]#

ADSTB0#

A[39:38, 35:17]# ADSTB1# D[15:0]#, DBI0# DSTBP0#, DSTBN0# D[31:16]#, DBI1# DSTBP1#, DSTBN1# D[47:32]#, DBI2# DSTBP2#, DSTBN2# D[63:48]#, DBI3# DSTBP3#, DSTBN3#

AGTL+ Strobes I/O Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# Open Drain Output Asynchronous FERR#/PBE#, IERR#, PROCHOT#,

THERMTRIP#, TDO

CMOS Asynchronous Input Asynchronous A20M#, FORCEPR#, IGNNE#, INIT#,

LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#,

STPCLK#, TCK, TDI, TMS TRST# CMOS Asynchronous Output Asynchronous BSEL[2:0], VID[6:1] FSB Clock Clock BCLK[1:0] SMBus Synchronous to SM_CLK SM_CLK, SM_DAT, SM_EP_A[2:0], SM_WP Power/Other Power/Other COMP[3:0], GTLREF_ADD_MID,

Notes:

1. Refer to Section 5 for signal descriptions.

2. These signals may be driven simultaneously by multiple agents (Wired-OR).

GTLREF_ADD_END, GTLREF_DATA_MID,

GTLREF_DATA_END, LL_ID[1:0],

PROC_ID[1:0], PECI, RESERVED,

SKTOCC#,SM_VCC, TESTHI[1:0], TESTIN1,

TESTIN2, VCC, VCC_SENSE, VCC_SENSE2,

VCCPLL, VSS_SENSE, VSS_SENSE2, VSS,

VTT, VTT_SEL

Document Number: 318080-002 21

Table 2-5 outlines the signals which include on-die termination (RTT). Table 2-6

outlines non AGTL+ signals including open drain signals. Table 2-7 provides signal reference voltages.

Table 2-5. AGTL+ Signal Description Table

AGTL+ signals with R

A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

Electrical Specifications

AGTL+ signals with no R

BPM[5:0]#, BPMb[3:0]#, RESET#, BR[1:0]

Note:

1. Signals that have RTT in the package with 50 Ω pullup to V

Table 2-6. Non AGTL+ Signal Description Table

Signals with R

A20M#, BCLK[1:0], BSEL[2:0], COMP[3:0], FERR#/PBE#, FORCEPR#, GTLREF_ADD_MID, GTLREF_ADD_END, GTLREF_DATA_MID, GTLREF_DATA_END, IERR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, LL_ID[1:0], PROC_ID[1:0], PECI, PROCHOT#, PWRGOOD, SKTOCC#, SMI#, STPCLK#, TCK, TDI, TDO, TESTHI[1:0], TESTIN1, TESTIN2, THERMTRIP#, TMS, TRST#, VCC_SENSE, VCC_SENSE2, VID[6:1], VSS_SENSE, VSS_SENSE2, VTT_SEL

Signals with no R

Table 2-7. Signal Reference Voltages

GTLREF CMOS

A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BPM[5:0]#, BPMb[3:0]#, BPRI#, BR[1:0]#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#, HIT#, HITM#, LOCK#, MCERR#, RESET#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#

A20M#, LINT0/INTR, LINT1/NMI, IGNNE#, INIT#, PWRGOOD, SMI#, STPCLK#, TCK, TDI, TMS, TRST#

2.7 CMOS Asynchronous and Open Drain Asynchronous Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#, THERMTRIP#, and TDO utilize open drain output buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state. See Section 2.11 and

Section 2.12 for the DC and AC specifications. See Section 7 for additional timing

requirements for entering and leaving the low power states.

2.8 Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the processor(s) be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage. Similar considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be required with each driving a different voltage level.

22 Document Number: 318080-002

Electrical Specifications

2.9 Mixing Processors

Intel supports and validates multi-processor configurations only in which all processors operate with the same FSB frequency, core frequency, number of cores, and have the same internal cache sizes. Mixing components operating at different internal clock frequencies or number of cores is not supported and will not be validated by Intel.

Note: Processors within a system must operate at the same frequency per bits [12:8] of the

CLOCK_FLEX_MAX MSR; however this does not apply to frequency transitions initiated due to thermal events, Extended HALT, Enhanced Intel SpeedStep technology transitions, or assertion of the FORCEPR# signal (See Section 6).

Mixing processors of different steppings but the same model (as per CPUID instruction) is supported. Details regarding the CPUID instruction are provided in the AP-485 Intel® Processor Identification and the CPUID Instruction application note.

2.10 Absolute Maximum and Minimum Ratings

Table 2-8 specifies absolute maximum and minimum r atings only, which lie outside the

functional limits of the processor. Only within specified operation limits, can functionality and long-term reliability be expected.

At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function or its reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.

Table 2-8. Processor Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes

CASE

STORAGE

Notes:

1. For functional operation, all processor electri cal, signal quality, mechanical and thermal specifications must be satisfied.

2. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no pins can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, please refer to the processor case temperature specifications.

3. This rating applies to the processor and does not include any tray or packaging.

4. Failure to adhere to this specification can affect the long-term reliability of the processor.

Core voltage with respect to V FSB termination voltage with respect to

Processor case temperature See Section 6 See Section 6 °C Storage temperature -40 85 ° C 2, 3, 4

-0.30 1.55 V

Document Number: 318080-002 23

2.11 Processor DC Specifications

The following notes apply:

• The processor DC specifications in this section are defined at the processor die and not at the package pins unless noted otherwise.

• The notes associated with each parameter are part of the specification for that parameter.

• Unless otherwise noted, all specifications in the tables apply to all frequencies and cache sizes.

See Section 5 for the pin signal definitions. Most of the signals on the processor FSB are in the AGTL+ signal group. The DC specifications for these signals are listed in

Table 2-11. Table 2-9 through Table 2-17 list the DC specifications and are valid only while meeting

specifications for case temperature (Tcase as specified in Section 6), clock frequency, and input voltages.

Electrical Specifications

24 Document Number: 318080-002

Electrical Specifications

2.11.1 Flexible Motherboard Guidelines (FMB)

The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series will have over certain time periods. The values are only estimates and actual specifications for future processors may differ. Processors may or may not have specifications equal to the FMB value in the foreseeable future. System designers should meet the FMB values to ensure their systems will be compatible with future processors.

Table 2-9. Voltage and Current Specifications (Sheet 1 of 2)

Symbol Parameter Min Typ Max Unit

VID VID range 1.0000 1.5000 V V

CC_BOOT

VID_STEP

VID_SHIFT

CCPLL

VCC for processor core Launch - FMB

See Table 2-10, Figure 2-5,

Figure 2-6 and Figure 2-7

Default VCC Voltage for initial power up 1.10 V 2 VID step size during a transition ± 12.5 mV Total allowable DC load line shift from

VID steps FSB termination voltage (DC + AC

1.14 1.20 1.26 V 8, 13

450 mV 10

specification) PLL supply voltage (DC + AC

specification)

1.425 1.50 1.605 V

SM_VCC SMBus supply voltage 3.135 3.300 3.465 V I

ICC for Quad-Core Intel® Xeon® L7345 Processor with multiple VID

60 A 4, 5, 6, 9

Launch - FMB

CC_RESET

I L7345 Processor with multiple VID

for Quad-Core Intel® Xeon®

CC_RESET

60 A 17

Launch - FMB

ICC for Dual-Core Intel® Xeon® Processor 7200 Series with multiple VID

90 A 4, 5, 6, 9

Launch - FMB

CC_RESET

I Processor 7200 Series with multiple VID

for Dual-Core Intel® Xeon®

CC_RESET

90 A 17

Launch - FMB

ICC for Intel® Xeon® Processor 7200 Series and 7300 Series with multiple VID

90 A 4, 5, 6, 9

Launch - FMB

CC_RESET

I 7200 Series and 7300 Series with

for Intel® Xeon® Processor

CC_RESET

90 A 17

multiple VID Launch - FMB

ICC for Intel® Xeon® X7350 Processor with multiple VID

130 A 4, 5, 6, 9

Launch - FMB

CC_RESET

Processor with multiple VID

for Intel® Xeon® X7350

130 A 17

Launch - FMB

SM_VCC

Icc for SMBus supply 100 122.5 mA

Notes

1,17

V 2, 3, 4, 6,

Document Number: 318080-002 25

Table 2-9. Voltage and Current Specifications (Sheet 2 of 2)

Electrical Specifications

Symbol Parameter Min Typ Max Unit

CC_TDC

ICC for VTT supply before VCC stable I

for VTT supply after VCC stable

Thermal Design Current (TDC) QuadCore Intel® Xeon® L7345 Processor

8.0

7.0 50 A 6,14

Launch - FMB

CC_TDC

Thermal Design Current (TDC) DualCore Intel® Xeon® Processor 7200 Series

75 A 6,14

Launch - FMB

CC_TDC

Thermal Design Current (TDC) Intel®

Processor 7200 Series and 7300

Xeon

75 A 6,14

Series Launch - FMB

CC_TDC

Thermal Design Current (TDC) Intel® Xeon® X7350 Processor

110 A 6,14

Launch - FMB

CC_VTT_OUT

CC_GTLREF

CC_VCCPLL

TCC

DC current that may be drawn from

per pin

TT_OUT

ICC for GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END

ICC for PLL supply 260 mA 12 ICC for Quad-Core Intel® Xeon® L7345

Processor during active thermal control circuit (TCC)

ICC for Dual-Core Intel® Xeon® Processor 7200 Series during active thermal control circuit (TCC)

ICC for Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series during active thermal control circuit (TCC)

ICC for Intel® Xeon® X7350 Processor during active thermal control circuit (TCC)

580 mA 16

200 µA 7

60 A

90 A

130 A

Notes

1,17

A15

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processors and are based on estimates and simulations, not empirical data. These specifications will be updated with characterized data from silicon measurements at a later date.

2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.4 for more information.

3. The voltage specification requirements are measured across the VCC_SENSE and VSS_SENSE pins and across the VCC_SENSE2 and VSS_SENSE2 pins with an oscilloscope set to 100 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope pr obe.

4. The processor must not be subjected to any static V particular current. Failure to adhere to this specification can shorten processor lifetime.

5. I

6. FMB is the flexible motherboard guideline. These guidelines are fo r estimation purposes only. See

7. This specification represents the total current for GTLREF_DATA_MID, GTLREF_DATA_END,

8. V

specification is based on maximum V

CC_MAX

capable of drawing I current draw over various time durations.

Section 2.11.1 for further details on FMB guidelines.

GTLREF_ADD_MID, and GTLREF_ADD_END.

must be provided via a separate voltage source and must not be connected to VCC. This specification is

measured at the pin.

26 Document Number: 318080-002

level that exceeds the V

loadline Refer to Figure 2-10 for details. The processor is

for up to 10 ms. Refer to Figure 2-9 for further details on the average processor

CC_MAX

associated with any

CC_MAX

Electrical Specifications

9. Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE) shown in Figure 6-2.

10. This specification refers to the total reduction of the load line due to VID transitions below the specified VID.

11. Individual processor VID values may be calibrated during man ufacturing such that two devices at the same frequency may have different VID settings.

12. This specification applies to the VCCPLL pin.

13. Baseboard bandwidth is limited to 20 MHz.

14. I

15. This is the maximum total current drawn from the V

16. I

17. I

is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and

CC_TDC

should be used for the voltage regulator temperature assessment. The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion. Please see the applicable design guidelines for further details. The processor is capable of drawing I over various time durations. This parameter is based on design characterization and is not tested.

specification does not include the current coming from on-board termination (R Refer to the appropriate platform design guide and the Voltage Regulator Design Guidelines to determine the total I

CC_VTT_OUT

CC_RESET

RESET# de-assertion time specification and Table 2-23 for the RESET# Pulse Width specification.

indefinitely. Refer to Figure 2-9 for further details on the average processor current draw

CC_TDC

plane by only one processor with RTT enabled. This

drawn by the system. This parameter is based on design characterization and is not tested.

is specified at 1.2 V.

is specified while PWRGOOD and RESET# are asserted. Refer to Table 2- 22 for the PWRGOOD to

), through the signal line.

Figure 2-1. Quad-Core Intel® Xeon® L7345 Processor Load Current versus Time

Sustained Current (A)

0.01 0.1 1 10 100 1000

Time Dur ation (s)

Notes:

1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than

2. Not 100% tested. Specified by design characterization.

CC_TDC

Document Number: 318080-002 27

Electrical Specifications

Figure 2-2. Dual-Core Dual-Core Intel® Xeon® Processor 7200 Series Load Current

versus Time

10 0

75 70

Sustained Current (A)

0.01 0.1 1 10 100 1000

Time Duration (s)

Notes:

1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than I

CC_TDC

2. Not 100% tested. Specified by design characterization

Figure 2-3. Quad-Core Intel® Xeon® Processor 7200 Series and 7300 Series Load Current

versus Time

10 0

75 70

Sustained Current (A)

0.01 0.1 1 10 100 1000

Time Duration (s)

Notes:

1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than

2. Not 100% tested. Specified by design characterization.

CC_TDC

28 Document Number: 318080-002

Electrical Specifications

Figure 2-4. Quad-Core Intel® Xeon® X7350 Processor Load Current versus Time

13 0

12 5

12 0

115

110

10 5

Sustained Current (A)

10 0

0.01 0.1 1 10 100 1000

Time Duration (s)

Notes:

1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than

2. Not 100% tested. Specified by design characterization.

CC_TDC

Document Number: 318080-002 29

Table 2-10. VCC Static and Transient Tolerance

Electrical Specifications

ICC (A) V

(V) V

CC_Max

(V) V

CC_Typ

(V) Notes

CC_Min

0 VID - 0.000 VID - 0.015 VID - 0.030 1, 2, 3

5 VID - 0.006 VID - 0.021 VID - 0.036 1, 2, 3 10 VID - 0.013 VID - 0.028 VID - 0.043 1, 2, 3 15 VID - 0.019 VID - 0.034 VID - 0.049 1, 2, 3 20 VID - 0.025 VID - 0.040 VID - 0.055 1, 2, 3 25 VID - 0.031 VID - 0.046 VID - 0.061 1, 2, 3 30 VID - 0.038 VID - 0.053 VID - 0.068 1, 2, 3 35 VID - 0.044 VID - 0.059 VID - 0.074 1, 2, 3 40 VID - 0.050 VID - 0.065 VID - 0.080 1, 2, 3 45 VID - 0.056 VID - 0.071 VID - 0.086 1, 2, 3 50 VID - 0.069 VID - 0.084 VID - 0.099 1, 2, 3 55 VID - 0.069 VID - 0.077 VID - 0.093 1, 2, 3 60 VID - 0.075 VID - 0.090 VID - 0.105 1, 2, 3 65 VID - 0.081 VID - 0.096 VID - 0.111 1, 2, 3, 4 70 VID - 0.087 VID - 0.103 VID - 0.118 1, 2, 3, 4 75 VID - 0.094 VID - 0.109 VID - 0.124 1, 2, 3, 4 80 VID - 0.100 VID - 0.115 VID - 0.130 1, 2, 3, 4 85 VID - 0.106 VID - 0.121 VID - 0.136 1, 2, 3, 4 90 VID - 0.113 VID - 0.128 VID - 0.143 1, 2, 3, 4 95 VID - 0.119 VID - 0.134 VID - 0.149 1, 2, 3, 4, 5

100 VID - 0.125 VID - 0.140 VID - 0.155 1, 2, 3, 4, 5 105 VID - 0.131 VID - 0.146 VID - 0.161 1, 2, 3, 4, 5 110 VID - 0.138 VID - 0.153 VID - 0.168 1, 2, 3, 4, 5 115 VID - 0.144 VID - 0.159 VID - 0.174 1, 2, 3, 4, 5 120 VID - 0.150 VID - 0.165 VID - 0.180 1, 2, 3, 4, 5 125 VID - 0.156 VID - 0.171 VID - 0.186 1, 2, 3, 4, 5 130 VID - 0.163 VID - 0.178 VID - 0.193 1, 2, 3, 4, 5

Notes:

1. The V

2. This table is intended to aid in reading discrete points on Figure 2-5 for Intel

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins and

4. I

5. I

overshoot specifications.

Series and 7300 Series, Figure 2-6 for Intel® Xeon® X7350 Processor , Figure 2-7 for Quad-Core Intel® Xeon® L7345 Processor and Figure 2-8 for Dual-Core Intel® Xeon® Processor 7200 Series

across the VCC_SENSE2 and VSS_SENSE2 pins. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE2 and VSS_SENSE2 pins. Refer to the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR implementation. Please refer to the appropriate platform design guide for details on VR implementation.

values greater than 60 A are not applicable for the Quad-Core Intel® Xeon® L7345 Processor.

values greater than 90 A are not applicable for the Intel® Xeon® Processor 7200 Series and 7300

Series and Dual-Core Intel® Xeon® Processor 7200 Series.

CC_MIN

and V

loadlines represent static and transient limits. Please see Section 2.11.3 for

CC_MAX

Xeon® Processor 7200

30 Document Number: 318080-002

Electrical Specifications

Figure 2-5. Quad-Core Intel® Xeon® Processor 7200 Series and 7300 Series VCC Static and

Transient Tolerance Load Lines

Icc [A]

VID - 0.000

VID - 0.020

VID - 0.040

VID - 0.060

VID - 0.080

Vcc [V]

VID - 0.100

VID - 0.120

VID - 0.140

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90

Maximum

Typical

Minimum

VID - 0.160

Notes:

1. The V overshoot specifications.

2. Refer to Table 2-9 for processor VID information.

3. Refer to Table 2-10 for V

4. The load lines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins and the VCC_SENSE2 and VSS_SENSE2 pins. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE2 and VSS_SENSE2 pins. Refer to the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR implementation. Please refer to the appropriate platform design guide for details on VR

CC_MIN

and V

loadlines represent static and transient limits. Please see Section 2.11.3 for VCC

CC_MAX

Static and Transient Tolerance

implementation.

Document Number: 318080-002 31

Electrical Specifications

Figure 2-6. Quad-Core Intel® Xeon® X7350 Processor VCC Static and Transient Tolerance

Load Lines

VID - 0.000

VID - 0.050

VID - 0.100

Vcc [V]

VID - 0.150

VID - 0.200

VID - 0.250

Notes:

1. The V overshoot specifications.

2. Refer to Table 2-9 for processor VID information.

3. Refer to Table 2-10 for V

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 12 0 1 25 130

Typical

Minimum

CC_MIN

and V

loadlines represent static and transient limits. Please see Section 2.11.3 for VCC

CC_MAX

Static and Transient Tolerance

implementation.

Icc [A]

Maximum

32 Document Number: 318080-002

Electrical Specifications

Figure 2-7. Quad-Core Intel® Xeon® L7345 Processor VCC Static and Transient Tolerance

Load Lines

Min im um

Icc [A ]

Maxi mu m

0 5 10 15 20 25 30 35 40 45 50 55 60

VI D - 0.000

VI D - 0.010

VI D - 0.020

VI D - 0.030

VI D - 0.040

VI D - 0.050

Vcc [V]

VI D - 0.060

VI D - 0.070

VI D - 0.080

VI D - 0.090

VI D - 0.100

Notes:

1. The V overshoot specifications.

2. Refer to Table 2-9 for processor VID information.

3. Refer to Table 2-10 for V

CC_MIN

and V

CC_MAX

Typical

loadlines represent static and transient limits. Please see Section 2.11.3 for VCC

Static and Transient Tolerance

implementation

Document Number: 318080-002 33

Electrical Specifications

Figure 2-8. Dual-Core Intel® Xeon® Processor 7200 Series VCC Static and Transient

Tolerance Load Lines

Icc [A]

VID - 0.000

VID - 0.020

VID - 0.040

VID - 0.060

VID - 0.080

Vcc [V]

VID - 0.100

VID - 0.120

VID - 0.140

VID - 0.160

Notes:

1. The V overshoot specifications.

2. Refer to Table 2-9 for processor VID information.

3. Refer to Table 2-10 for V

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90

Maximum

Typical

Minimum

CC_MIN

and V

loadlines represent static and transient limits. Please see Section 2.11.3 for VCC

CC_MAX

Static and Transient Tolerance

Table 2-11. AGTL+ Signal Group DC Specifications

Symbol Parameter Min Typ Max Units Notes

Input Low Voltage -0.10 0 GTLREF-0.10 V 2,4,6

Input High Voltage GTLREF+0.10 V

Output High Voltage V

- 0.10 N/A V

VTT+0.10 V 3,6

V4,6

Buffer On Resistance 10.00 11.50 13.00 Ω 5

Input Leakage Current N/A N/A +/-100 μA7,8

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low

2. V

value.

3. V

is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high

value.

4. V

and VOH may experience excursions above VTT. However, input signal drivers must comply with the

signal quality specifications.

5. This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics. Measured at 0.31*V

6. GTLREF should be generated from VTT with a 1% tolerance resistor divider. The VTT referred to in these specifications is the instantaneous V

7. Specified when on-die R

8. This is the measurement at the pin.

. RON (min) = 0.225*RTT. RON (typ) = 0.250*RTT. RON (max) = 0.275*R

and RON are turned off. VIN between 0 and VTT.

34 Document Number: 318080-002

Electrical Specifications

Table 2-12. CMOS Signal Input/Output Group DC Specifications

Symbol Parameter Min Typ Max Units Notes

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. The V

3. Refer to the processor I/O Buffer Models for I/V characteristics.

4. Measured at 0.1*V

5. Measured at 0.9*V

6. For Vin between 0 V and VTT. Measured when the driver is tristated.

7. This is the measurement at the pin.

Input Low Voltage -0.10 0.00 0.3*V

Input High Voltage 0.7*V

Output Low Voltage -0.10 0 0.1*V

Output High Voltage 0.9*V

Output Low Current 1.70 N/A 4.70 mA 4

Output High Current 1.70 N/A 4.70 mA 5

Input Leakage Current N/A N/A +/- 100 μA6,7

referred to in these specifications refers to instantaneous VTT.

Table 2-13. Open Drain Signal Group DC Specifications

Symbol Parameter Min Typ Max Units Notes

Output Low Voltage N/A 0.20 V 3

Output High Voltage V

-5% V

Output Low Current 16 N/A 50 mA 2

Leakage Current N/A N/A +/- 200 μA4,5

V2,3

VTT+0.1 V 2

+5% V

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Measured at 0.2*V

3. V

4. For V

5. This is the measurement at the pin.

is determined by value of the external pullup resistor to VTT. Please refer to platform design guide for

details.

between 0 V and VOH.

Table 2-14. SMBus Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

SMB

Notes:

1. These parameters are based on design characterization and are not tested.

2. All DC specifications for the SMBus signal group are measured at the processor pins.

3. Platform designers may need this value to calculate the maximum loading of the SMBus and to determine maximum rise and fall times for SMBus signals.

Input Low Voltage -0.30 0.30 * SM_VCC V Input High Voltage 0.70 * SM_VCC 3.465 V Output Low Voltage 0 0.400 V Output Low Current N/A 3.0 mA Input Leakage Current N/A ± 10 µA Output Leakage Current N/A ± 10 µA SMBus Pin Capacita nce 15.0 pF 3

2.11.2 Platform Environmental Control Interface (PECI) DC Specifications

PECI is an Intel proprietary one-wire bus interface that provides a communication channel between Intel processor and external thermal monitoring devices. The DualCore Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor

1, 2

Document Number: 318080-002 35

7300 Series contains Digital Thermal Sensors (DTS) distributed throughout the die. These sensors are implemented as analog-to-digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature. PECI provides an interface to relay the highest DT S temperature within a die to external management devices for thermal/fan speed control.

2.11.2.1 DC Characteristics

A PECI device interface operates at a nominal voltage set by VTT. The set of DC electrical specifications shown in Table 2-15 is used with devices normally operating from a V PECI devices will operate at the VTT level determined by the processor installed in the system. For specific nominal V

Table 2-15. PECI DC Electrical Limits

hysteresis

source

sink

leak+

leak-

bus

noise

interface supply . VTT nominal levels will vary between processor families. All

Symbol Definition and Conditions Min Max Units Notes

Input Voltage Range Hysteresis Negative-edge threshold voltage Positive-edge threshold voltage High level output source

= 0.75 * VTT)

Low level output sink

= 0.25 * VTT)

High impedance state leakage to VTT

= VOL)

leak

High impedance leakage to GND

= VOH)

leak

Bus capacitance Signal noise immunity above 300 MHz

levels, refer to Table 2-11.

-0.150 VTT V

0.1 * V

0.275 * VTT0.500 * V

0.550 * VTT0.762 * V

-6.0 N/A mA

0.5 1.0 mA

N/A 50 µA 2

N/A 10 µA 2 N/A 10 pF 3

0.1 * V

Electrical Specifications

N/A V

TT TT

N/A V

V V

p-p

Note:

1. V

2. The leakage specification applies to powered devices on the PECI bus.

3. One node is counted for each client and one node for the system host. Extended trace lengths might

supplies the PECI interface. PECI behavior does not affect VTT min/max specifications.

appear as additional nodes.

2.11.2.2 Input Device Hysteresis

The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 2-9 as a guide for input buffer design.

36 Document Number: 318080-002

Electrical Specifications

Figure 2-9. Input Device Hysteresis

Maximum V

Minimum V

Maximum V

Minimum V

PECI High Range

PECI Low Range

PECI Ground

2.11.3 VCC Overshoot Specification

Processors can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high-to-low current load condition. This overshoot cannot exceed VID + V

OS_MAX

VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE pins and across the VCC_SENSE2 and VSS_SENSE2 pins.

Table 2-16. VCC Overshoot Specifications

Symbol Parameter Min Max Units Figure Notes

OS_MAX

Magnitude of VCC overshoot above VID 50 mV 2-10 Time duration of VCC overshoot above VID 25 µs 2-10

OS_MAX

Minimum Hysteresis

Valid Input Signal Range

is the maximum allowable overshoot above

Document Number: 318080-002 37

Electrical Specifications

Figure 2-10. V

Overshoot Example Waveform

Example Overshoot Waveform

VID + 0.050

Voltage [V]

VID - 0.000

0 5 10 15 20 25

TOS: Overshoot time abo ve VID

: Overshoot above VID

Notes:

1. VOS is the measured overshoot voltage.

2. TOS is the measured time duration above VID.

Time [us]

2.11.3.1 Die Voltage Validation

Core voltage (VCC) overshoot events at the processor must meet the specifications in

Table 2-16 when measured across the VCC_SENSE and VSS_SENSE pins and across

the VCC_SENSE2 and VSS_SENSE2 pins. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope.

2.11.4 AGTL+ FSB Specifications

Routing topologies are dependent on the processors supported and the chipset used in the design. Please refer to the appropriate platform design guidelines for specific implementation details. In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 2-6 for details on which signals do not include on-die termination. Please refer to Table 2-17 for R

Valid high and low levels are determined by the input buffers via comparing with a reference voltage called GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END. GTLREF_DATA_MID and GTLREF_DATA_END are the reference voltage for the FSB 4X data signals, GTLREF_ADD_MID and GTLREF_ADD_END are the reference voltage for the FSB 2X address signals and common clock signals. Table 2-17 lists the GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END specifications.

The AGTL+ reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END) must be generated on the baseboard using high precision voltage divider circuits. Refer to the appropriate platform design guidelines for implementation details.

values.

38 Document Number: 318080-002

Electrical Specifications

Table 2-17. AGTL+ Bus Voltage Definitions

Symbol Parameter Min Typ Max Units Notes

GTLREF_DATA_MID GTLREF_DATA_END

GTLREF_ADD_MID GTLREF_ADD_END

COMP COMP Resistance 49.4 49.9 50.4

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values

across the range of V

3. GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END is generated from V

baseboard by a voltage divider of 1% resistors. The minimum and maximum specifications account for this resistor toler ance. Refer to the appropriate platform design guidelines for implementation details. The V the instantaneous V

is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at 0.31*VTT. RTT is connected

4. R

to VTT on die. Refer to processor I/O Buffer Models for I/V characteristics.

5. COMP resistance must be provided on the system board with +/- 1% resistors. See the applicable platform design guide for

implementation details.

Data Bus Reference Voltage

Address Bus Refer ence Voltage

Termination Resistance (pull up)

0.98 * 0.67 * V

0.67 * V

45 50 55

1.02 * 0.67 * V

V2, 3

on the

referred to in these specifications is

Table 2-18. FSB Differential BCLK Specifications

Symbol Parameter Min Typ Max Unit Figure Notes

CROSS(abs)

CROSS(rel)

Δ V

CROSS

MAX (Absolute

Overshoot)

MIN (Absolute

Undershoot)

RBM

Single-ended Input Low Voltage

Single-ended Input

-0.150 0.0 0.15 V 2-13

0.660 0.710 0.850 V 2-13

High Voltage Absolute Crossing

Point Relative Crossing

Point

0.250 0.350 0.550 V 2-13,

0.5 * (V

0.250 +

- 0.700)

Havg

N/A 0.550 +

0.5 * (V

Havg

- 0.700)

2-14

V 2-13,

2-14

Vcross variation N/A N/A 0.140 V 2-13,

2-14

Single-ended

N/A N/A 1.15 V 2-13 4

maximum voltage Single-ended

minimum voltage Single-ended

Ringback Margin Single-ended

Threshold Region Input Leakage

Current

-0.300 N/A N/A V 2-13 5

0.200 N/A N/A V 2-13 6

- 0.100 N/A V

CROSS

+ 0.100 V 2-13 7

CROSS

N/A N/A +/- 100 μA10

1,2

2,8

3,8,9, 11

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to the falling edge of

BCLK1.

3. V

4. Overshoot is defined as the absolute value of the maximum voltage.

5. Undershoot is defined as the absolute value of the minimum voltage.

6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum

7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches.

8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.

9. V

10. For V

is the statistical average of the VH measured by the oscilloscope.

Havg

Falling Edge Ringback. It includes input threshold hysteresis.

can be measured directly using “Vtop” on Agilent and “High” on Tektronix oscilloscopes.

Havg

between 0 V and VHΔV

CROSS

Document Number: 318080-002 39

is defined as the total variation of all crossing voltages as defined in note 2.

Electrical Specifications

2.12 Front Side Bus AC Specifications

The processor FSB timings specified in this section are defined at the processor core (pads). Therefore, proper simulation of the FSB is the only means to verify proper timing and signal quality.

See Table 4-1 for the pin listing and Table 5-1 for signal definitions. Table 2-19 through

Table 2-24 list the AC specifications associated with the processor FSB.

All AGTL+ timings are referenced to GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END for both ‘0’ and ‘1’ logic levels unless otherwise specified.

The timings specified in this section should be used in conjunction with the processor signal integrity models provided by Intel. AGTL+ layout guidelines are also available in the appropriate platform design guidelines.

Note: Care should be taken to read all notes associated with a particular timing parameter.

Table 2-19. Front Side Bus Differential Clock AC Specifications

T# Parameter Min Max Unit Figure N otes

FSB Clock Frequency 265.247 266.745 MHz 2 T1: BCLK[1:0] Period 3.7489 3.7700 ns 2-13 3 T2: BCLK[1:0] Period Stability N/A 150 ps 4 T3: BCLK[1:0] Rise Time 175 700 ps 5 T4: BCLK[1:0] Fall Time 175 700 ps 5 Differential Rising and Falling Edge Rates 0.6 4 V/ns 7

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. The processor core clock frequency is derived from BCLK. The bus clock to processor core clock ratio is determined during initialization as described in Section 2.3. Table 2-1 includes core frequency to FSB multipliers.

3. The period specified here is the average period. A given period may vary from this specification as governed by the period stability specification (T2).

4. In this context, period stability is defined as the worst case timing difference between successive crossover voltages. In other words, the largest absolute differe nce b etween adjacent clo ck periods must be l ess than the period stability.

5. Rise and fall times are measured single ended between 245 mV and 455 mV of the clock swing.

6. Measured from -200 mV to +200 mV. The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero.

Table 2-20. Front Side Bus Common Clock AC Specifications

T# Parameter Min Max Unit Figure Notes

T10: Common Clock Output Valid Delay 0.22 1.10 ns 2-16 4 T11: Common Clock Input Setup Time 0.650 N/A ns 2-16 5 T12: Common Clock Input Hold Time 0.150 N/A ns 2-16 5 T13: RESET# Pulse Width 1 10 ms 2-24 6, 7, 8

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Not 100% tested. Specified by design characterization.

3. All common clock AC timings for AGTL+ s i gnals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at nominal GTLREF_DAT A_MID , GTLREF_DA TA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor core (pads).

4. Valid delay timings for these signals are specified into the test circuit described in Figure 2-11 and with GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at 0.67 * V

1, 2, 3

40 Document Number: 318080-002

Electrical Specifications

5. Specification is for a minimum swing is specified into the test circuit described in Figure 2-11 and defined between AGTL+ V

6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.

7. This should be measured after V

8. Maximum specification applies only while PWRGOOD is asserted.

IL_MAX

to V

. This assumes an edge rate of 2.0 V/ns to 3.0 V/ns.

IH_MIN

and BCLK[1:0] become stable.

Table 2-21. FSB Source Synchronous AC Specifications

T# Parameter Min Max Unit Figure Notes

T20: Source Sync. Output Valid Delay (first data/address only)

T21: T Valid Before Data Strobe

T22: T Valid After Data Strobe

T23: T Valid Before Address Strobe

T24: T Valid After Address Strobe

T25: T T25: T

T26: T

T27: Source Synchronous Address Strobe Setup Time to BCLK[1:0]

Source Sync. Data Output

VBD

Source Sync. Data Output

VAD

Source Sync. Address Output

VBA

Source Sync. Address Output

VAA

Data Input Setup Time 0.190 ns 2-17 2-18 6

SUSS

Address Input Setup Time 0.300 n s 2-17,

SUSS

Data Input Hold Time 0.190 ns 2-17,

HSS

Address Input Hold Time 0.300 ns 2-17,

HSS

T28: Source Synchronous Data Strobe Setup Time to BCLK[1:0]

T30: Data Strobe ‘n’ (DSTBN#) Output Valid Delay

T31: Address Strobe Output Valid Delay 2.81 3.91 ns 2-17

0.00 1.10 ns 2-17,

0.270 ns 2-18 5,8

0.270 ns 2-18 5,9

0.660 ns 2-17 5,8

0.660 ns 2-17 5,9

3.5 -

(1.875 * n)

4.15 -

(0.9375 * n)

3.28 4.38 ns 2-18 13

1, 2, 3, 4

2-18

ns 2-17 12, 14, 15

ns 2-18 11,14

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Not 100% tested. Specified by design characterization.

3. All source synchronous AC timings are referenced to their associated strobe at nominal GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe. All source synchronous AGTL+ signal timings are referenced at nominal GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor core (pads).

4. Unless otherwise noted, these specifications apply to both data and address timings.

5. Valid delay timings for these signals are specified into the test circuit described in Figure 2-11 and with GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at 0.67 * V

6. Specification is for a minimum swing into the test circuit described in Figure 2-11 and defined between AGTL+ V

7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each respective strobe.

8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the appropriate platform design guidelines for more information on the definitions and use of these specifications.

9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the appropriate platform design guidelines for more information on the definitions and use of these specifications.

10. The rising edge of ADSTB# must come approximately 1/2 BCLK period after the falling edge of ADSTB#.

11. For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.

12. The address strobe setup time is measured with respect to T2. Calculation of the setup time is as follows.:

a. If T27 > BCLK period, then the setup time calculated is positive. The value calculated indicates b. If T27 < BCLK period, then the setup time calculated is negative. The value calculated indicates

13. This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.

14. This specification reflects a typical value, not a minimum or maximum.

15. For this timing parameter, n = 0 to 1.

IL_MAX

to V

. This assumes an edge rate of 3.0 V/ns to 5.5 V/ns.

IH_MIN

setup time before T1. setup time after T1. Refer to Figure 2-17.

Document Number: 318080-002 41

Table 2-22. Miscellaneous GTL+ AC Specifications

Electrical Specifications

T# Parameter Min Max Unit Figure

Notes

1, 2, 3, 4

T35: Asynchronous GTL+ input pulse width 30 ns 5 T36: PWRGOOD assertion to RESET# de-assertion 1 10 ms 2-24 T37: BCLK stable to PWRGOOD assertion 10 BCLKs 2-24 6,12 T38: PROCHOT# pulse width 500 µs 2-20 7 T39: THERMTRIP# assertion until V

removed 500 ms 2-21 8

T40: FERR# valid delay from STPCLK# deassertion 0 5 BCLKs 2-25 T41: V

stable to PWRGOOD assertion 0.05 500 ms 2-24 10

T42: PWRGOOD rise time 20 ns 11 T43: V T44: VID / BSEL valid to V T48: V T49: V

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. All AC timings for the Asynchronous GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage (V

3. These signals may be driven asynchronously.

4. Refer to Section 7.2 for additional timing requirements for entering and leaving low power states.

5. A minimum pulse width of 500 µs is recommended when FORCEPR# is asserted by the system

6. Refer to the PWRGOOD signal definition in Section 5 for more details information on behavior of the signal.

7. Length of assertion for PROCHOT# does not equal TCC activation time. Time is required after the assertion and before the deassertion of PROCHOT# for the processor to enable or disable the TCC.

8. Intel recommends the V

9. This specification requires that the VID and BSEL signals be sampled no earlier than 10 μs after V V

CC_BOOT

10. Parameter must be measured after applicable voltage level is stable. “Stable” means that the power supply is in regulation as defined by the minimum and maximum DC/AC specifications for all components being powered by it.

11. The maximum PWRGOOD rise time specification denotes the slowest allowable rise time for the processor. Measured between (0.3* V

12. See Table 2-19 for BCLK specifications.

stable to VID / BSEL valid 10 µs 2-24 9,10

CC_BOOT

stable 100 µs 2-24 10

stable to VID / BSEL valid 10 µs 2-24 10

stable to PWRGOOD assertion 1 ms 2-24 10

CCPLL

). PWRGOOD is referenced to BCLK0 rising edge at 0.5 * VTT.

CROSS

power supply also be removed upon assertion of THERMTRIP#.

voltage) and VTT are stable.

) and (0.7*VTT).

(at

Table 2-23. Front Side Bus AC Specifications (Reset Conditions)

T# Parameter Min Max Unit Figure Notes

T45: Reset Configuration Signals (A[39:3]#, BR[1:0]#, INIT#, SMI#) Setup Time

T46: Reset Configuration Signals (A[39:3]#, INIT#, SMI#) Hold Time

T47: Reset Configuration Signals BR[1:0]# Hold Time

Notes:

1. Before the clock that de-asserts RESET#

2. After the clock that de-asserts RESET#.

Table 2-24. TAP Signal Group AC Specifications (Sheet 1 of 2)

T# Parameter Min Max Unit Figure

T55: TCK Period 30 ns 2-12 3 T56: TDI, TMS Setup Time 7.5 ns 2-19 4,7

42 Document Number: 318080-002

480 µs 2-24 1

220BCLKs2-24 2

22BCLKs2-24 2

Notes

1, 2, 8

Electrical Specifications

Table 2-24. TAP Signal Group AC Specifications (Sheet 2 of 2)

T# Parameter Min Max Unit Figure

T57: TDI, TMS Hold Time 7.5 ns 2-19 4,7 T58: TDO Clock to Output Delay 0 7.5 ns 2-19 5 T59: TRST# Assert Time 2 T

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Not 100% tested. Specified by design characterization.

3. This specification is based on the capabilities of the ITP debug port, not on processor silicon.

4. Referenced to the rising edge of TCK.

5. Referenced to the falling edge of TCK.

6. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.

7. Specification for a minimum swing defined between TAP V

0.5 V/ns.

8. It is recommended that TMS be asserted while TRST# is being deasserted.

to Vt+. This assumes a minimum edge rate of

TCK

2-20 6

Notes

1, 2, 8

Document Number: 318080-002 43

Table 2-25. VID Signal Group AC Specifications

T # Parameter Min Max Unit Figure Notes

T80: VID Step Time 5 µs 2-27 T81: VID Dwell Time at 266.666 MHz FSB 500 µs 2-27 T82: VID Down Transition to Valid V T83: VID Up Transition to Valid V T84: VID Down Transition to Valid V T85: VID Up Transition to Valid V

Notes:

1. See Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for addition information.

2. Platform support for VID transitions is required for the processor to operate within specifications.

(min) 0 µs 2-26,2-27

(min) 50 µs 2-26,2-27

(max) 50 µs 2-26,2-27

(max) 0 µs 2-26,2-27

Table 2-26. SMBus Signal Group AC Specifications

T# Parameter Min Max Unit Figure Notes 1, 2

T90: SM_CLK Frequency 10 100 KHz T91: SM_CLK Period 10 100 µs T92: SM_CLK High Time 4.0 N/A µs 2-22 T93: SM_CLK Low Time 4.7 N/A µs 2-22 T94: SMBus Rise Time 0.02 1.0 µs 2-22 3 T95: SMBus Fall Time 0.02 0.3 µs 2-22 3 T96: SMBus Output Valid Delay 0.1 4.5 µs 2-23 T97: SMBus Input Setup Time 250 N/A ns 2-22 T98: SMBus Input Hold Time 300 N/A ns 2-22 T99: Bus Free Time 4.7 N/A µs 2-22 4, 5 T100: Hold Time after Repeated Start Condition 4.0 N/A µs 2-22 T101: Repeated Start Condition Setup Time 4.7 N/A µs 2-22 T102: Stop Condition Setup Time 4.0 N/A µs 2-22

Notes:

1. These parameters are based on design characterization and are not tested.

2. All AC timings for the SMBus signals are referenced at V processor pins. Refer to Figure 2-23.

3. Rise time is measured from (V from (0.9 * SM_VCC) to (V

4. Minimum time allowed between request cycles.

5. Following a write transaction, an internal write cycle time of 10ms must be allowed before

starting the next transaction.

IL_MAX

- 0.15V) to (V

IL_MAX

- 0.15V). DC parameters are specified in Table 2-26.

Electrical Specifications

or V

IL_MAX

+ 0.15V). Fall time is measured

IH_MIN

and measured at the

IL_MIN

1, 2

44 Document Number: 318080-002

Electrical Specifications

2.13 Processor AC Timing Waveforms

The following figures are used in conjunction with the AC timing tables, Table 2-19 through Table 2-25.

Note: For Figure 2-12 through Figure 2-25, the following apply:

1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (V AGTL+ signal timings are referenced at nominal GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor core (pads).

2. All source synchronous AC timings for AGTL+ signals are referenced to their associated strobe (address or data) at nominal GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe. All source synchronous AGTL+ signal timings are referenced at nominal GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor core (pads).

3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at V AGTL+ strobe signal timings are referenced at nominal GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor core (pads).

4. All AC timings for the TAP signals are referenced to the TCK at 0.5 * V processor pins. All TAP signal timings (TMS , TDI, etc...) are referenced at 0.5 * VTT at the processor core (pads).

5. All CMOS signal timings are referenced at 0.5 * VTT at the processor pins.

6. All AC timings for the SMBus signals are referenced to the SM_CLK at 0.5 * SM_VCC at the processor pins. All SMBus signal timings (SM_DAT, SM_CLK, etc.) are referenced at

) of the BCLK[1:0] at rising edge of BCLK0. All common clock

CROSS

at the

. All

The circuit used to test the AC specification is shown in Figure 2-11.

Document Number: 318080-002 45

Figure 2-11. Electrical Test Circuit

Electrical Specifications

Figure 2-12. TCK Clock Waveform

TCK

= T55: Period

V1, V2: For rise and fall times, TCK is measured betwee n 20% and 80% points on the waveform. V3: TCK is referenced to 0.5 * V

46 Document Number: 318080-002

Electrical Specifications

Figure 2-13. Differential Clock Waveform

BCLK1

Crossing

Threshold

Region

BCLK0

Voltage

Tp = T1: BCLK[1:0] period

Figure 2-14. Differential Clock Crosspoint Specification

Crossing

Voltage

Overshoot

Rising Edge

Ringback

Margin

Falling Edge

Ringback,

Undershoot

650

600 550 500 450 400 350

Crossin g Point (mV)

300 250 200

550 + 0.5 (VHavg - 700)

250 + 0.5 (VHavg - 700)

250 mV

660 670 6 80 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850

550 mV

VHavg (mV)

Document Number: 318080-002 47

Figure 2-15. BCLK Waveform at Processor Pad and Pin

Electrical Specifications

Notes:

1. Waveform at pin is non-monotonic. Waveform at pad is monotonic.

2. Differential Edge Rate (DER) measured zero +/- 200mv.

3. g indicates V/ns units and meg indicates mv/ns units.

4. Waveform at pad has faster edge rate than at pin.

Figure 2-16. FSB Common Clock Valid Delay Timing Waveform

T1 T2

BCLK1 BCLK0

Common Clock

Signal (@ driver)

valid valid

Common Clock

Signal (@ receiver)

TP = T10: Common Clock Output Valid Delay T

= T11: Common Clock Input Setup

= T12: Common Clock Input Hold Time

valid

48 Document Number: 318080-002

Electrical Specifications

Figure 2-17. FSB Source Synchronous 2X (Address) Timing Waveform

BCLK1

BCLK0

ADSTB# (@ driver)

A# (@ driver)

ADSTB# (@ receiver)

A# (@

receiver)

Tp/4 Tp/2 3Tp/4

valid valid

valid

= T1: BCLK[1:0] Period

TH= T23: Source Sync. Address Output Valid Before Address Strobe

= T24: Source Sync. Address Output Valid After Address Strobe

= T27: Source Sync. Address Strobe Se tup Tim e to B CLK

= T25: Source Sync. Input Setup Time

= T26: Source Sync. Input Hold Time

= T20: Source Sync. Output Valid Delay

TR= T31: Address Strobe Output Valid Delay

valid

Document Number: 318080-002 49

Figure 2-18. FSB Source Synchronous 4X (Data) Timing Waveform

Electrical Specifications

BCLK1

BCLK0

DSTBp# (@ driver)

DSTBn# (@ driver)

D# (@ driver)

DSTBp# (@ receive r )

DSTBn# (@ receiv e r )

D# (@ receiver)

Tp/4

A T

BTA

= T1: BCLK[1:0] Period

/2 3Tp/4

T1 T2

TET

TA= T21: Source Sync. Data Out put V alid Delay Before Data Strobe

= T22: Source Sync. Data Output V a lid De lay A fter Data Strobe

= T28: Source Sync. Data Strobe Se tup Time to BCLK

= T30: Data Strobe ‘n’ (DSTBN#) Output Valid Delay

= T25: Source Sync. Input Setup Time

= T26: Source Sync. Input Hold Time

= T20: Source Sync. Data Output V alid Dela y

50 Document Number: 318080-002

Electrical Specifications

T q

Figure 2-19. TAP Valid Delay Timing Waveform

TCK

Tx Ts Th

Signal

V Valid

Tx = T58: TDO Clock to Output Delay Ts = T56: TDI, TMS Setup Time

Note: Please refer to Table 2-12 for TAP Signal Group DC specifications and Table 2-24 for TAP Signal Group

AC specifications.

Th = T57: TDI, TMS Hold Time

V = 0.5 * V

Figure 2-20. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Tim i ng Waveform

T59 (TRST# Pulse Width), V = 0.5 * VTT T38 (PROCHOT# Pulse Width), V = GTLREF

Figure 2-21. THERMTRIP# Power Down Sequence

THERMTRIP#

Document Number: 318080-002 51

Vcc

TA = T39 (THERMTRIP# to removal of power)

Figure 2-22. SMBus Timing Waveform

Electrical Specifications

HD;STA

LOW

HD;DAT

LOW

HIGH

Clk

Data

BUF

P P

STOP STOPSTART START

HIGH

T93

T92

T94

T95

Figure 2-23. SMBus Valid Delay Timing Waveform

SM_CLK

TAA

HD;STA

HD;DAT

BUF

SU;DAT

HD;STA

SU;STA

T100

T98

T99

T97

SU;STA

SU;STD

T101

T102

SU;STO

SM_DAT

DATA VALID

DATA OUTPUT

TAA = T96

52 Document Number: 318080-002

Electrical Specifications

Figure 2-24. Voltage Sequence Timing Requirements

VID[6:1] / BSEL[2:0]

CCPLL

Vcc

PWRGOOD

BCLK

CC_BOOT

Ta Tb

Reset Configuration

Signals(A[35:3]#,

INIT#, SMI#)

Reset Configuration

Signals BR[1:0]#

RESET#

Ta= T43 (V Tb= T44 (VID[6:1] / BSEL[2 :0] valid to Vcc stable) Tc= T48 (V Td= T36 (PWRGOOD assertion to RESET# de-assertion) Te= T41 (V Tf = T37 (BCLK stable to PWRGOOD assertion) Tg = T49 (V Th = T45 Reset Configuration Signals (A[35:3]#, BR[1:0]#, INIT#, SMI#) Setup Time Ti= T46 Reset Configuration Signals (A[35:3]#, INIT#, SMI#) Hold Time Tj= T47 Reset Configuration Signals (BR[1:0]#) Hold Time

stable to VID[6:1] / BSEL[2:0] valid)

CC_BOOT

stable to VID[6:1] / BSEL[2:0] valid)

stable to PWRGOOD assertion)

CCPLL

Th Ti

Document Number: 318080-002 53

Figure 2-25. FERR#/PBE# Valid Delay Timing

BCLK

Electrical Specifications

System bus

STPCLK#

FERR#/PBE#

Notes:

1. Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion).

2. FERR# / PBE# is undefined from STPCLK# assertion until the Stop-Grant acknowledge is driven on the FSB. FERR# / PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined regions, the PBE# signal is driven. FERR# is driven at all other times.

Figure 2-26. VID Step Timings

VID

VCC(max)

SG Ack

FERR# undefined FERR#

n n-1 m+1m

PBE# undefined

...

(min)

Ta = T84: VID Down to Valid VCC(max) Tb = T82: VID Down to Valid V Tc = T85: VID Up to Valid V Td = T83: VID Up to Valid V

54 Document Number: 318080-002

CC CC

(min)

(max) (min)

Electrical Specifications

Figure 2-27. VID Step Times and Vcc Waveforms

Ta Tb

n-1

n-2

n-3

n-4

n-5

VCC(min,n-3)

Ta = T80: VID Step Time Tb = T81: Thermal Monitor 2 Dwell Time Tc = T84: VID Down to Valid V Td = T82: VID Down to Valid V Te = T85: VID Up to Valid V Tf = T83: VID Up to Valid V

Note: This waveform illustrates an example of an Intel Thermal Monitor 2 transition or an Intel Enhanced SpeedStep Technology transition that is six VID steps down from the current state and six steps back up. Any arbitrary up or down transition can be generalized from this waveform.

VID

(max)

(min)

CC CC

(max) (min)

n-6 = VID

TM2

VCC(max,n-3)

n-4

n-5

VCC(min,n-4)

n-1

n-2

n-3

VCC(max,n-4)

Document Number: 318080-002 55

Electrical Specifications

56 Document Number: 318080-002

Mechanical Specifications

3 Mechanical Specifications

The Intel® Xeon® Processor 7200 Series and 7300 Series is packaged in a FC-mPGA6 package that interfaces with the motherboard via a mPGA604 socket. The package consists of two processor dies mounted on a substrate pin-carrier. An IHS is attached to the package substrate and die and serves as the mating surface for processor component thermal solutions, such as a heatsink. Figure 3-1 shows a sketch of the processor package components and how they are assembled together. Refer to the mPGA604 Socket Design Guidelines for complete details on the mPGA604 socket.

The package components shown in Figure 3-1 include the following:

1. IHS

2. Processor die

3. FC-m PGA 6 pack age

4. Pin-side capacitors

5. Package pin

Figure 3-1. Processor Package Assembly Sketch

Note: Figure 3-1 is not to scale and is for reference only. The mPGA604 socket is not shown.

3.1 Package Mechanical Drawing

The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include:

1. Package reference with tolerances (total height, length, width, etc.)

2. IHS parallelism and tilt

3. Pin dimensions

4. Top-side and back-side component keepout dimensions

5. Reference datums

All drawing dimension are in mm [in].

Document Number: 318080-002 57

Figure 3-2.Processor Package Drawing (Sheet 1 of 2)

Mechanical Specifications

58 Document Number: 318080-002

Mechanical Specifications

Figure 3-3.Processor Package Drawing (Sheet 2 of 2)

Document Number: 318080-002 59

3.2 Processor Component Keepout Zones

The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the package substrate. See Figure 3-4 and

Figure 3-5 for keepout zones.

Mechanical Specifications

60 Document Number: 318080-002

Mechanical Specifications

Figure 3-4.Top Side Board Keepout Zones (Part 1)

Document Number: 318080-002 61

Figure 3-5.Top Side Board Keepout Zones (Part 2)

Mechanical Specifications

62 Document Number: 318080-002

Mechanical Specifications

Figure 3-6.Bottom Side Board Keepout Zones

Document Number: 318080-002 63

Figure 3-7.Board Mounting-Hole Keepout Zones

Mechanical Specifications

64 Document Number: 318080-002

Mechanical Specifications

Figure 3-8.Volumetric Height Keep-Ins

Document Number: 318080-002 65

3.3 Package Loading Specifications

Table 3-1 provides dynamic and static load specifications for the processor package.

These mechanical load limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Also, any mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solutions. The minimum loading specification must be maintained by any thermal and mechanical solution.

Table 3-1. Processor Loading Specifications

Parameter Minimum Maximum Unit Notes

Static Compressive Load

Dynamic Compressive Load

Transient 445

Notes:

1. These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface.

2. This is the minimum and maximum static force that can be applied by the heatsink and retention solution to

maintain the heatsink and processor interface.

3. These parameters are based on limited testing for design characterization. Loading limits are for the package

only and do not include the limits of the processor socket.

4. This specification applies for thermal retention solutions that allow baseboard deflection.

5. This specification applies either for thermal retention solutions that prevent baseboard deflection or for the

Intel enabled reference solution (CEK).

6. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement.

7. Experimentally validated test condition used a heatsink mass of 1 lbm (~0.45 kg) with 100 G acceleration

measured at heatsink mass. The dynamic portion of this specification in the product application can have flexibility in specific values, but the ultimate product of mass times acceleration should not exceed this validated dynamic load (1 lbm x 100 G = 100 lb).

8. Transient loading is defined as a 2 sec ond duration peak load superimposed on the static load requirement,

representative of loads experienced by the package during heatsink installation.

44 10

222

288

222 N + 0.45 kg * 100 G

50 lbf (static) + 1 lbm * 100 G

288 N + 0.45 kg * 100 G

65 lbf (static) + 1 lbm * 100 G

100

Mechanical Specifications

1, 2, 3, 4

1, 2, 3, 5

1, 3, 4, 6, 7

1, 3, 5, 6, 7

1, 3, 8

lbf

66 Document Number: 318080-002

Mechanical Specifications

3.4 Package Handling Guidelines

Table 3-2 includes a list of guidelines on package handling in terms of recommended

maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal.

Table 3-2. Package Handling Guidelines

Parameter Maximum Recommended Notes

Shear 356 N [80 lbf] Tensile 156 N [35 lbf] Torque 8 N-m [70 lbf-in]

Notes:

1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.

2. These guidelines are based on limited testing for design characterization.

3. A tensile load is defined as a pulling load applied to the IHS in the direction normal to the IHS surface.

4. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface.

3.5 Package Insertion Specifications

The Intel® Xeon® Processor 7200 Series and 7300 Series can be inserted into and removed from a mPGA604 socket 15 times. The socket should meet the mPGA604 requirements detailed in the mPGA604 Socket Design Guidelines.

1, 2

3, 2

4, 2

3.6 Processor Mass Specifications

The typical mass of the Intel® Xeon® Processor 7200 Series and 7300 Series is 37.6 g (1.5oz). This mass [weight] includes all the components that are included in the package.

3.7 Processor Materials

Table 3-3 lists some of the package components and associated materials.

Table 3-3. Processor Materials

Component Material

Integrated Heat Spreader (IHS) Nickel Plated Copper

Substrate Fiber-Reinforced Resin

Substrate Pins Gold Plated Copper

Document Number: 318080-002 67

3.8 Processor Markings

Mechanical Specifications

Figure 3-9 shows the topside markings and Figure 3-10 shows the bottom-side

markings on the processor. These diagrams are to aid in the identification of the Intel Xeon® Processor 7200 Series and 7300 Series. Please note that the figures in this section are not to scale.

Figure 3-9. Processor Topside Markings

INTEL® X EON®

INTEL® X EON® i{M}©’YY {PbFree symbol}

i{M}©’YY {PbFree symbol}

Pin 1 Indicator

2D Matrix

2D Matrix FPO – Serial #

FPO – Serial #

Notes:

1. Character size for laser markings is: 17 Point, height 1.27 mm (50 mils), width 0.81 mm (32 mils)

2. All characters will be in upper case.

Figure 3-10. Processor Bottom-Side Markings

Pin 1 Indicator

Pin Field

Cavity

with

Components

Text Line1

Text Line1 Text Line2

Text Line2 Text Line3

Text Line3

Notes:

1. Character size for laser markings is: 21 Point, height 1.43 mm (56 mils), width 0.95 mm (37.5 mils)

2D Matrix

2D Matrix FPO – Se ria l #

FPO – Se ria l #

Processor/Speed/Cache/Bus

Processor/Speed/Cache/Bus Number

Number

X7350 2933MP/8M/1066

X7350 2933MP/8M/1066 SLA67 COSTA RIC A

SLA67 COSTA RIC A C0096109-0021

C0096109-0021

FPO – Serial #

(13 Cha racters)

S-Spec

Country of Assy

68 Document Number: 318080-002

Mechanical Specifications

3.9 Processor Pin-Out Coordinates

Figure 3-11 shows the top view of the processor pin coordinates. The coordinates are

referred to throughout the document to identify processor pins.

Figure 3-11. Processor Pin-Out Coordinates, Top View

COMMON

A B C

D E

Vcc/Vss

P R

U V

AB AC AD

COMMON

CLOCK

ADDRESS

3 5 7 9 11 13 15 17 19 21 23 25 27 29 311

Processor

Top View

2 4 6 8 10 12 14 16 18 20 22 24 26 28

CLOCKS

DATA

Async /

JTAG

A B

C D

E F

G H

J K

L M

N P R

T U V W Y

Vcc/Vss

AA AB

Document Number: 318080-002 69

= Signal

= VCC

= G round

= VTT = Rese rved/No Connect

Mechanical Specifications

70 Document Number: 318080-002

Pin Listing

4 Pin Listing

4.1 Pin Assignments

Section 2.6 contains the front side bus signal groups for the Intel® Xeon® Processor

7200 Series and 7300 Series (see Table 2-4). This section provides a sorted pin lists in

Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor pins ordered alphabetically by pin name. Table 4-2

is a listing of all processor pins ordered by pin number.

4.1.1 Pin Listing by Pin Name

Table 4-1. Pin Listing by Pin Name (Sheet 1

of 16)

Pin Name Pin No.

A3# A22 Source Sync Input/Output A4# A20 Source Sync Input/Output A5# B18 Source Sync Input/Output A6# C18 Source Sync Input/Output A7# A19 Source Sync Input/Output A8# C17 Source Sync Input/Output A9# D17 Source Sync Input/Output A10# A13 Source Sync Input/Output A11# B16 Source Sync Input/Output A12# B14 Source Sync Input/Output A13# B13 Source Sync Input/Output A14# A12 Source Sync Input/Output A15# C15 Source Sync Input/Output A16# C14 Source Sync Input/Output A17# D16 Source Sync Input/Output A18# D15 Source Sync Input/Output A19# F15 Source Sync Input/Output A20# A10 Source Sync Input/Output A21# B10 Source Sync Input/Output A22# B11 Source Sync Input/Output A23# C12 Source Sync Input/Output A24# E14 Source Sync Input/Output A25# D13 Source Sync Input/Output A26# A9 Source Sync Input/Output A27# B8 Source Sync Input/Output A28# E13 Source Sync Input/Output A29# D12 Source Sync Input/Output A30# C11 Source Sync Input/Output

Signal

Buffer Type

Direction

Table 4-1. Pin Listing by Pin Name (Sheet 2

of 16)

Pin Name Pin No.

A31# B7 Source Sync Input/Output A32# A6 Source Sync Input/Outp ut A33# A7 Source Sync Input/Outp ut A34# C9 Source Sync Input/Output A35# C8 Source Sync Input/Output A36# F16 Source Sync Input/ Output A37# F22 Source Sync Input/ Output A38# B6 Source Sync Input/Output A39# C16 Source Sync Input/Output A20M# F27 Async GTL+ Input ADS# D19 Common Clk Input/Output ADSTB0# F17 Source Sync Input/Output ADSTB1# F14 Source Sync Input/Output AP0# E10 Common Clk Input/Output AP1# D9 Common Clk Input/Output BCLK0 Y4 FSB Clk Input BCLK1 W5 FSB Clk Input BINIT# F11 Common Clk Input/Output BNR# F20 Common Clk Input/Output BPM0# F6 Common Clk Input/Output BPM1# F8 Common Clk Output BPM2# E7 Common Clk Output BPM3# F5 Common Clk Input/Output BPM4# E8 Common Clk Output BPM5# E4 Common Clk Input/Output BPMb0# AA4 Common Clk Input/Output BPMb1# AC1 Common Clk Output BPMb2# AE2 Common Clk Output

Signal

Buffer Type

Direction

Document Number: 318080-002 71

Pin Listing

Table 4-1. Pin Listing by Pin Name (Sheet 3

of 16)

Pin Name Pin No.

BPMb3# AE3 Common Clk Input/Output BPRI# D23 Common Clk Input BR0# D20 Common Clk Input/Output BR1# F12 Common Clk Input/Output BSEL0 AA3 Power/Other Output BSEL1 AB3 Power/Other Output BSEL2 Y31 Power/Other Output COMP0 D25 Power/Other Input COMP1 E16 Power/Other Input COMP2 AE15 Power/Other Input COMP3 AE16 Power/Other Input D0# Y26 Source Sync Input/Output D1# AA27 Source Sync Input/Output D2# Y24 Source Sync Input/Output D3# AA25 Source Sync Input/Output D4# AD27 Source Sync Input/Output D5# Y23 Source Sync Input/Output D6# AA24 Source Sync Input/Output D7# AB26 Source Sync Input/Output D8# AB25 Source Sync Input/Output D9# AB23 Source Sync Input/Output D10# AA22 Source Sync Input/Output D11# AA21 Source Sync Input/Output D12# AB20 Source Sync Input/Output D13# AB22 Source Sync Input/Output D14# AB19 Source Sync Input/Output D15# AA19 Source Sync Input/Output D16# AE26 Source Sync Input/Output D17# AC26 Source Sync Input/Output D18# AD25 Source Sync Input/Output D19# AE25 Source Sync Input/Output D20# AC24 Source Sync Input/Output D21# AD24 Source Sync Input/Output D22# AE23 Source Sync Input/Output D23# AC23 Source Sync Input/Output D24# AA18 Source Sync Input/Output D25# AC20 Source Sync Input/Output D26# AC21 Source Sync Input/Output D27# AE22 Source Sync Input/Output D28# AE20 Source Sync Input/Output

Signal

Buffer Type

Direction

Table 4-1. Pin Listing by Pin Name (Sheet 4

of 16)

Pin Name Pin No.

D29# AD21 Source Sync Input/Output D30# AD19 Source Sync Input/Output D31# AB17 Source Sync Input/Output D32# AB16 Source Sync Input/Output D33# AA16 Source Sync Input/Output D34# AC17 Source Sync Input/Output D35# AE13 Source Sync Input/Output D36# AD18 Source Sync Input/Output D37# AB15 Source Sync Input/Output D38# AD13 Source Sync Input/Output D39# AD14 Source Sync Input/Output D40# AD11 Source Sync Input/Output D41# AC12 Source Sync Input/Output D42# AE10 Source Sync Input/Output D43# AC11 Source Sync Input/Output D44# AE9 Source Sync Input/Output D45# AD10 Source Sync Input/Output D46# AD8 Source Sync Input/Output D47# AC9 Source Sync Input/Output D48# AA13 Source Sync Input/Output D49# AA14 Source Sync Input/Output D50# AC14 Source Sync Input/Output D51# AB12 Source Sync Input/Output D52# AB13 Source Sync Input/Output D53# AA11 Source Sync Input/Output D54# AA10 Source Sync Input/Output D55# AB10 Source Sync Input/Output D56# AC8 Source Sync Input/Output D57# AD7 Source Sync Input/Output D58# AE7 Source Sync Input/Output D59# AC6 Source Sync Input/Output D60# AC5 Source Sync Input/Output D61# AA8 Source Sync Input/Output D62# Y9 Source Sync Input/Output D63# AB6 Source Sync Input/Output DBI0# AC27 Source Sync Input/Output DBI1# AD22 Source Sync Input/Output DBI2# AE12 Source Sync Input/Output DBI3# AB9 Source Sync Input/Output DBSY# F18 Common Clk Input/Output

Signal

Buffer Type

Direction

72 Document Number: 318080-002

Pin Listing

Table 4-1. Pin Listing by Pin Name (Sheet 5

of 16)

Pin Name Pin No.

DEFER# C23 Common Clk Input DP0# AC18 Common Clk Input/Output DP1# AE19 Common Clk Input/Output DP2# AC15 Common Clk Input/Output DP3# AE17 Common Clk Input/Output DRDY# E18 Common Clk Input/Output DSTBN0# Y21 Source Sync Input/Output DSTBN1# Y18 Source Sync Input/Output DSTBN2# Y15 Source Sync Input/Output DSTBN3# Y12 Source Sync Input/Output DSTBP0# Y20 Source Sync Input/Output DSTBP1# Y17 Source Sync Input/Output DSTBP2# Y14 Source Sync Input/Output DSTBP3# Y11 Source Sync Input/Output FERR#/PBE# E27 Async GTL+ Output FORCEPR# A15 Async GTL+ Input GTLREF_ADD_E

ND GTLREF_ADD_MIDF23 Power/Other Input

GTLREF_DATA_ENDW9 Power/Other Input

GTLREF_DATA_MIDW23 Power/Other Input

HIT# E22 Common Clk Input/Output HITM# A23 Common Clk Input/Output IERR# E5 Async GTL+ Output IGNNE# C26 Async GTL+ Input INIT# D6 Async GTL+ Input LINT0 B24 Async GTL+ Input LINT1 G23 Async GTL+ Input LL_IDO B31 Power/Other Output LL_ID1 B28 Power/Other Output LOCK# A17 Common Clk Input/Output MCERR# D7 Common Clk Input/Output PECI C28 Power/Other Input/Output PROC_ID0 A30 Power/Other Output PROC_ID1 B29 Power/Other Output PROCHOT# B25 Async GTL+ Output PWRGOOD AB7 Async GTL+ Input REQ0# B19 Source Sync Input/Output REQ1# B21 Source Sync Input/Output

F9 Power/Other Input

Signal

Buffer Type

Direction

Table 4-1. Pin Listing by Pin Name (Sheet 6

of 16)

Pin Name Pin No.

REQ2# C21 Source Sync Input/Output REQ3# C20 Source Sync Input/Output REQ4# B22 Source Sync Input/Output Reserved A28 Reserved A31 Reserved B1 Reserved B4 Reserved B30 Reserved C31 Reserved D27 Reserved D29 Reserved E2 Reserved Y27 Reserved Y28 Reserved Y29 Reserved AA5 Reserved AA28 Reserved AB4 Reserved AC30 Reserved AD4 Reserved AD6 Reserved AD16 Reserved AD28 Reserved AD30 Reserved AD31 Reserved AE8 Reserved AE30 RESET# Y8 Common Clk Input RS0# E21 Common Clk Input RS1# D22 Common Clk Input RS2# F21 Common Clk Input RSP# C6 Common Clk Input SKTOCC# A3 Power/Other Output SM_CLK AC28 SMBus Input SM_DAT AC29 SMBus Input/Output SM_EP_A0 AA29 SMBus Input SM_EP_A1 AB29 SMBus Input SM_EP_A2 AB28 SMBus Input SM_VCC AE28 Power/Other SM_VCC AE29 Power/Other

Signal

Buffer Type

Direction

Document Number: 318080-002 73

Pin Listing

Table 4-1. Pin Listing by Pin Name (Sheet 7

of 16)

Pin Name Pin No.

SM_WP AD29 SMBus Input SMI# C27 Async GTL+ Input STPCLK# D4 Async GTL+ Input TCK E24 TAP Input TDI C24 TAP Input TDO E25 TAP Output TESTHI0 A16 Power/Other Input TESTHI1 W3 Power/Other Input TESTIN1 D1 Power/Other Input TESTIN2 C2 Power/Other Input THERMTRIP# F26 Async GTL+ Output TMS A25 TAP Input TRDY# E19 Common Clk Input TRST# F24 TAP Input V

A8 Power/Other A14 Power/Other A18 Power/Other A24 Power/Other B20 Power/Other

C4 Power/Other C22 Power/Other C30 Power/Other

D8 Power/Other D14 Power/Other D18 Power/Other D24 Power/Other D31 Power/Other

E6 Power/Other E20 Power/Other E26 Power/Other E28 Power/Other E30 Power/Other

F1 Power/Other

F4 Power/Other

F29 Power/Other F31 Power/Other

G2 Power/Other G4 Power/Other G6 Power/Other G8 Power/Other

Signal

Buffer Type

Direction

Table 4-1. Pin Listing by Pin Name (Sheet 8

of 16)

Pin Name Pin No.

G24 Power/Other G26 Power/Other G28 Power/Other G30 Power/Other

H1 Power/Other H3 Power/Other H5 Power/Other H7 Power/Other

H9 Power/Other H23 Power/Other H25 Power/Other H27 Power/Other H29 Power/Other H31 Power/Other

J2 Power/Other J4 Power/Other J6 Power/Other

J8 Power/Other J24 Power/Other J26 Power/Other J28 Power/Other J30 Power/Other

K1 Power/Other K3 Power/Other K5 Power/Other K7 Power/Other

K9 Power/Other K23 Power/Other K25 Power/Other K27 Power/Other K29 Power/Other K31 Power/Other

L2 Power/Other L4 Power/Other L6 Power/Other

L8 Power/Other L24 Power/Other L26 Power/Other L28 Power/Other L30 Power/Other

Signal

Buffer Type

Direction

74 Document Number: 318080-002

Pin Listing

Table 4-1. Pin Listing by Pin Name (Sheet 9

of 16)

Pin Name Pin No.

M1 Power/Other M3 Power/Other M5 Power/Other M7 Power/Other

M9 Power/Other M23 Power/Other M25 Power/Other M27 Power/Other M29 Power/Other M31 Power/Other

N1 Power/Other

N3 Power/Other

N5 Power/Other

N7 Power/Other

N9 Power/Other

N23 Power/Other N25 Power/Other N27 Power/Other N29 Power/Other N31 Power/Other

P2 Power/Other P4 Power/Other P6 Power/Other

P8 Power/Other P24 Power/Other P26 Power/Other P28 Power/Other P30 Power/Other

R1 Power/Other R3 Power/Other R5 Power/Other R7 Power/Other

R9 Power/Other R23 Power/Other R25 Power/Other R27 Power/Other R29 Power/Other R31 Power/Other

T2 Power/Other T4 Power/Other

Signal

Buffer Type

Direction

Table 4-1. Pin Listing by Pin Name (Sheet

10 of 16)

Pin Name Pin No.

T6 Power/Other

T8 Power/Other T24 Power/Other T26 Power/Other T28 Power/Other T30 Power/Other

U1 Power/Other U3 Power/Other U5 Power/Other U7 Power/Other

U9 Power/Other U23 Power/Other U25 Power/Other U27 Power/Other U29 Power/Other U31 Power/Other

V2 Power/Other

V4 Power/Other

V6 Power/Other

V8 Power/Other V24 Power/Other V26 Power/Other V28 Power/Other V30 Power/Other

W1 Power/Other

W25 Power/Other W27 Power/Other W29 Power/Other W31 Power/Other

Y2 Power/Other Y16 Power/Other Y22 Power/Other Y30 Power/Other

AA1 Power/Other

AA6 Power/Other AA20 Power/Other AA26 Power/Other AA31 Power/Other

AB2 Power/Other

AB8 Power/Other

Signal

Buffer Type

Direction

Document Number: 318080-002 75

Pin Listing

Table 4-1. Pin Listing by Pin Name (Sheet

11 of 16)

Pin Name Pin No.

CCPLL

CC_SENSE

CC_SENSE2

AB14 Power/Other AB18 Power/Other AB24 Power/Other AB30 Power/Other

AC3 Power/Other AC16 Power/Other AC22 Power/Other AC31 Power/Other

AD2 Power/Other

AD20 Power/Other AD26 Power/Other

AE14 Power/Other AE18 Power/Other AE24 Power/Other

AD1 Power/Other Input

B27 Power/Other Output

A26 Power/Other Output

VID1 E3 Power/Other Output VID2 D3 Power/Other Output VID3 C3 Power/Other Output VID4 B3 Power/Other Output VID5 A1 Power/Other Output VID6 C1 Power/Other Output V

A5 Power/Other A11 Power/Other A21 Power/Other A27 Power/Other A29 Power/Other

B2 Power/Other

B9 Power/Other B15 Power/Other B17 Power/Other B23 Power/Other

C7 Power/Other C13 Power/Other C19 Power/Other C25 Power/Other C29 Power/Other

D2 Power/Other

D5 Power/Other

Signal

Buffer Type

Direction

Table 4-1. Pin Listing by Pin Name (Sheet

12 of 16)

Pin Name Pin No.

D11 Power/Other D21 Power/Other D28 Power/Other D30 Power/Other

E1 Power/Other

E9 Power/Other E15 Power/Other E17 Power/Other E23 Power/Other E29 Power/Other E31 Power/Other

F2 Power/Other

F3 Power/Other

F7 Power/Other F13 Power/Other F19 Power/Other F25 Power/Other F28 Power/Other F30 Power/Other

G1 Power/Other

G3 Power/Other

G5 Power/Other

G7 Power/Other

G9 Power/Other

G25 Power/Other G27 Power/Other G29 Power/Other G31 Power/Other

H2 Power/Other

H4 Power/Other

H6 Power/Other

H8 Power/Other H24 Power/Other H26 Power/Other H28 Power/Other H30 Power/Other

J1 Power/Other J3 Power/Other J5 Power/Other J7 Power/Other

Signal

Buffer Type

Direction

76 Document Number: 318080-002

Pin Listing

Table 4-1. Pin Listing by Pin Name (Sheet

13 of 16)

Pin Name Pin No.

J9 Power/Other J23 Power/Other J25 Power/Other J27 Power/Other J29 Power/Other J31 Power/Other

K2 Power/Other K4 Power/Other K6 Power/Other

K8 Power/Other K24 Power/Other K26 Power/Other K28 Power/Other K30 Power/Other

L1 Power/Other L3 Power/Other L5 Power/Other L7 Power/Other

L9 Power/Other L23 Power/Other L25 Power/Other L27 Power/Other L29 Power/Other L31 Power/Other

M2 Power/Other M4 Power/Other M6 Power/Other

M8 Power/Other M24 Power/Other M26 Power/Other M28 Power/Other M30 Power/Other

N2 Power/Other

N4 Power/Other

N6 Power/Other

N8 Power/Other

N24 Power/Other N26 Power/Other N28 Power/Other N30 Power/Other

Signal

Buffer Type

Direction

Table 4-1. Pin Listing by Pin Name (Sheet

14 of 16)

Pin Name Pin No.

P1 Power/Other P3 Power/Other P5 Power/Other P7 Power/Other

P9 Power/Other P23 Power/Other P25 Power/Other P27 Power/Other P29 Power/Other P31 Power/Other

R2 Power/Other R4 Power/Other R6 Power/Other

R8 Power/Other R24 Power/Other R26 Power/Other R28 Power/Other R30 Power/Other

T1 Power/Other T3 Power/Other T5 Power/Other T7 Power/Other

T9 Power/Other T23 Power/Other T25 Power/Other T27 Power/Other T29 Power/Other T31 Power/Other

U2 Power/Other U4 Power/Other U6 Power/Other

U8 Power/Other U24 Power/Other U26 Power/Other U28 Power/Other U30 Power/Other

V1 Power/Other

V3 Power/Other

V5 Power/Other

V7 Power/Other

Signal

Buffer Type

Direction

Document Number: 318080-002 77

Pin Listing

Table 4-1. Pin Listing by Pin Name (Sheet

15 of 16)

Pin Name Pin No.

V9 Power/Other V23 Power/Other V25 Power/Other V27 Power/Other V29 Power/Other V31 Power/Other

W2 Power/Other

W4 Power/Other W24 Power/Other W26 Power/Other W28 Power/Other W30 Power/Other

Y1 Power/Other Y3 Power/Other Y5 Power/Other

Y7 Power/Other Y13 Power/Other Y19 Power/Other Y25 Power/Other AA2 Power/Other AA9 Power/Other

AA15 Power/Other AA17 Power/Other AA23 Power/Other AA30 Power/Other

AB1 Power/Other AB5 Power/Other

AB11 Power/Other AB21 Power/Other AB27 Power/Other AB31 Power/Other

AC2 Power/Other AC7 Power/Other

AC13 Power/Other AC19 Power/Other AC25 Power/Other

Signal

Buffer Type

Direction

Table 4-1. Pin Listing by Pin Name (Sheet

16 of 16)

Pin Name Pin No.

SS_SENSE

SS_SENSE2

AD3 Power/Other

AD9 Power/Other AD15 Power/Other AD17 Power/Other AD23 Power/Other

AE6 Power/Other AE11 Power/Other AE21 Power/Other AE27 Power/Other

D26 Power/Other Output

B26 Power/Other Output

A4 Power/Other B5 Power/Other

B12 Power/Other

C5 Power/Other

C10 Power/Other

D10 Power/Other

E11 Power/Other

E12 Power/Other

F10 Power/Other

W6 Power/Other W7 Power/Other W8 Power/Other

Y6 Power/Other Y10 Power/Other AA7 Power/Other

AA12 Power/Other

AC4 Power/Other

AC10 Power/Other

AD5 Power/Other

AD12 Power/Other

AE4 Power/Other AE5 Power/Other

VTT_SEL A2 Power/Other Output

Signal

Buffer Type

Direction

78 Document Number: 318080-002

Pin Listing

4.1.2 Pin Listing by Pin Number

Table 4-2. Pin Listing by Pin Number (Sheet

1 of 14)

Pin No. Pin Name

Signal

Buffer Type

A1 VID5 Power/Other Output A2 VTT_SEL Power/Other Output A3 SKTOCC# Power/Other Output A4 V A5 V

TT SS

Power/Other

Power/Other A6 A32# Source Sync Input/Output A7 A33# Source Sync Input/Output A8 V

Power/Other A9 A26# Source Sync Input/Output

A10 A20# Source Sync Input/Output A11 V

Power/Other

A12 A14# Source Sync Input/Output A13 A10# Source Sync Input/Output A14 V

Power/Other

A15 FORCEPR# Async GTL+ Input A16 TESTHI0 Power/Other Input A17 LOCK# Common Clk Input/Output A18 V

Power/Other

A19 A7# Source Sync Input/Output A20 A4# Source Sync Input/Output A21 V

Power/Other

A22 A3# Source Sync Input/Output A23 HITM# Common Clk Input/Output A24 V

Power/Other

A25 TMS TAP Input A26 V A27 V

CC_SENSE2 SS

Power/Other Output

Power/Other

A28 Reserved A29 V

Power/Other

A30 PROC_ID0 Power/Other Output A31 Reserved

B1 Reserved B2 V

Power/Other B3 VID4 Power/Other Output B4 Reserved B5 V

Power/Other B6 A38# Source Sync Input/Output B7 A31# Source Sync Input/Output B8 A27# Source Sync Input/Output B9 V

Power/Other

B10 A21# Source Sync Input/Output B11 A22# Source Sync Input/Output

Direction

Table 4-2. Pin Listing by Pin Number (Sheet

2 of 14)

Pin No. Pin Name

B12 V

B13 A13# Source Sync Input/Output B14 A12# Source Sync Input/Output B15 V

B16 A11# Source Sync Input/Output B17 V

B18 A5# Source Sync Input/Output B19 REQ0# Common Clk Input/Output B20 V

B21 REQ1# Common Clk Input/Output B22 REQ4# Common Clk Input/Output B23 V

B24 LINT0 Async GTL+ Input B25 PROCHOT# Async GTL+ Output B26 V B27 V

SS_SENSE2 CC_SENSE

B31 LL_IDO Power/Other Output B29 PROC_ID1 Power/Other Output B30 Reserved B28 LL_ID1 Power/Other Output

C1 VID6 Power/Other Output C2 TESTIN2 Power/Other Input C3 VID3 Power/Other Output C4 V C5 V

CC TT

C6 RSP# Common Clk Input C7 V

C8 A35# Source Sync Input/Output C9 A34# Source Sync Input/Output

C10 V

C11 A30# Source Sync Input/Output C12 A23# Source Sync Input/Output C13 V

C14 A16# Source Sync Input/Output C15 A15# Source Sync Input/Output C16 A39# Source Sync Input/Output C17 A8# Source Sync Input/Output C18 A6# Source Sync Input/Output C19 V

C20 REQ3# Common Clk Input/Output C21 REQ2# Common Clk Input/Output C22 V

Signal

Buffer Type

Direction

Power/Other

Power/Other Output Power/Other Output

Power/Other Power/Other

Power/Other

Document Number: 318080-002 79

Pin Listing

Table 4-2. Pin Listing by Pin Number (Sheet

3 of 14)

Pin No. Pin Name

C23 DEFER# Common Clk Input C24 TDI TAP Input C25 V

C26 IGNNE# Async GTL+ Input C27 SMI# Async GTL+ Input C28 PECI Power/Other Input/Output C29 V C30 V

SS CC

C31 Reserved

D1 TESTIN1 Power/Other Input D2 V

D3 VID2 Power/Other Output D4 STPCLK# Async GTL+ Input D5 V

D6 INIT# Async GTL+ Input D7 MCERR# Common Clk Input/Output D8 V

D9 AP1# Common Clk Input/Output D10 V D11 V

TT SS

D12 A29# Source Sync Input/Output D13 A25# Source Sync Input/Output D14 V

D15 A18# Source Sync Input/Output D16 A17# Source Sync Input/Output D17 A9# Source Sync Input/Output D18 V

D19 ADS# Common Clk Input/Output D20 BR0# Common Clk Input/Output D21 V

D22 RS1# Common Clk Input D23 BPRI# Common Clk Input D24 V

D25 COMP0 Power/Other Input D26 V

SS_SENSE

D27 Reserved D28 V

D29 Reserved D30 V D31 V

E1 V

SS CC SS

E2 Reserved

E3 VID1 Power/Other Output

E4 BPM5# Common Clk Input/Output

Signal

Buffer Type

Direction

Power/Other Input

Power/Other Power/Other

Power/Other

Power/Other Power/Other

Power/Other

Power/Other Output

Power/Other

Power/Other Power/Other Power/Other

Table 4-2. Pin Listing by Pin Number (Sheet

4 of 14)

Pin No. Pin Name

E5 IERR# Async GTL+ Output E6 V

E7 BPM2# Common Clk Input/Output E8 BPM4# Common Clk Input/Output E9 V

E10 AP0# Common Clk Input/Output E11 V E12 V

TT TT

E13 A28# Source Sync Input/Output E14 A24# Source Sync Input/Output E15 V

E16 COMP1 Power/Other Input E17 V

E18 DRDY# Common Clk Input/Output E19 TRDY# Common Clk Input E20 V

E21 RS0# Common Clk Input E22 HIT# Common Clk Input/Output E23 V

E24 TCK TAP Input E25 TDO TAP Output E26 V

E27 FERR#/PBE# Async GTL+ Output E28 V E29 V E30 V E31 V

F1 V F2 V F3 V F4 V

CC SS CC SS CC SS SS CC

F5 BPM3# Common Clk Input/Output F6 BPM0# Common Clk Input/Output F7 V

F8 BPM1# Common Clk Input/Output F9 GTLREF_ADD_END Power/Other Input

F10 V

F11 BINIT# Common Clk Input/Output F12 BR1# Common Clk Input/Output F13 V

F14 ADSTB1# Source Sync Input/Output F15 A19# Source Sync Input/Output F16 A36# Source Sync Input/Output F17 ADSTB0# Source Sync Input/Output

Signal

Buffer Type

Power/Other

Power/Other Power/Other

Power/Other

Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other

Power/Other

Direction

80 Document Number: 318080-002

Pin Listing

Table 4-2. Pin Listing by Pin Number (Sheet

5 of 14)

Pin No. Pin Name

F18 DBSY# Common Clk Input/Output F19 V

F20 BNR# Common Clk Input/Output F21 RS2# Common Clk Input F22 A37# Source Sync Input/Output F23 GTLREF_ADD_MID Power/Other Input F24 TRST# TAP Input F25 V

F26 THERMTRIP# Async GTL+ Output F27 A20M# Async GTL+ Input F28 V F29 V F30 V F31 V

G1 V G2 V G3 V G4 V G5 V G6 V G7 V G8 V G9 V

SS CC SS CC SS CC SS CC SS CC SS CC SS

G23 LINT1 Async GTL+ Input G24 V G25 V G26 V G27 V G28 V G29 V G30 V G31 V

H1 V H2 V H3 V H4 V H5 V H6 V H7 V H8 V

H9 V H23 V H24 V H25 V

CC SS CC SS CC SS CC SS CC SS CC SS CC SS CC SS CC CC SS CC

Signal

Buffer Type

Power/Other

Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other

Direction

Table 4-2. Pin Listing by Pin Number (Sheet

6 of 14)

Pin No. Pin Name

H26 V H27 V H28 V H29 V H30 V H31 V

J23 V J24 V J25 V J26 V J27 V J28 V J29 V J30 V J31 V

K1 V K2 V K3 V K4 V K5 V K6 V K7 V K8 V

K9 V K23 V K24 V K25 V K26 V K27 V K28 V K29 V K30 V K31 V

L1 V

L2 V

J1 V J2 V J3 V J4 V J5 V J6 V J7 V J8 V J9 V

SS CC SS CC SS CC SS CC SS CC SS CC SS CC SS SS CC SS CC SS CC SS CC SS CC SS CC SS CC SS CC SS CC CC SS CC SS CC SS CC SS CC SS CC

Signal

Buffer Type

Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other

Direction

Document Number: 318080-002 81

Pin Listing

Table 4-2. Pin Listing by Pin Number (Sheet

7 of 14)

Pin No. Pin Name

L3 V

L4 V

L5 V

L6 V

L7 V

L8 V

L9 V

L23 V L24 V L25 V L26 V L27 V L28 V L29 V L30 V L31 V

M1 V M2 V M3 V M4 V M5 V M6 V M7 V M8 V

M9 V M23 V M24 V M25 V M26 V M27 V M28 V M29 V M30 V M31 V

N1 V

N2 V

N3 V

N4 V

N5 V

N6 V

N7 V

N8 V

N9 V N23 V

SS CC SS CC SS CC SS CC SS CC SS CC SS CC SS CC SS CC CC SS CC SS CC SS CC SS CC CC SS CC SS CC SS CC SS CC CC

Signal

Buffer Type

Direction

Table 4-2. Pin Listing by Pin Number (Sheet

8 of 14)

Pin No. Pin Name

N24 V N25 V N26 V N27 V N28 V N29 V N30 V N31 V

P1 V P2 V P3 V P4 V P5 V P6 V P7 V P8 V

P9 V P23 V P24 V P25 V P26 V P27 V P28 V P29 V P30 V P31 V

R1 V

R2 V

R3 V

R4 V

R5 V

R6 V

R7 V

R8 V

R9 V R23 V R24 V R25 V R26 V R27 V R28 V R29 V R30 V R31 V

SS CC SS CC SS CC SS CC SS CC SS CC SS CC SS CC SS SS CC SS CC SS CC SS CC SS CC SS CC SS CC SS CC SS CC CC SS CC SS CC SS CC SS CC

Signal

Buffer Type

Direction

82 Document Number: 318080-002

Pin Listing

Table 4-2. Pin Listing by Pin Number (Sheet

9 of 14)

Pin No. Pin Name

T1 V T2 V T3 V T4 V T5 V T6 V T7 V T8 V

T9 V T23 V T24 V T25 V T26 V T27 V T28 V T29 V T30 V T31 V

U1 V

U2 V

U3 V

U4 V

U5 V

U6 V

U7 V

U8 V

U9 V U23 V U24 V U25 V U26 V U27 V U28 V U29 V U30 V U31 V

V1 V

V2 V

V3 V

V4 V

V5 V

V6 V

V7 V

V8 V

SS CC SS CC SS CC SS CC SS SS CC SS CC SS CC SS CC SS CC SS CC SS CC SS CC SS CC CC SS CC SS CC SS CC SS CC SS CC SS CC SS CC SS CC

Signal

Buffer Type

Direction

Table 4-2. Pin Listing by Pin Number (Sheet

10 of 14)

Pin No. Pin Name

V9 V V23 V V24 V V25 V V26 V V27 V V28 V V29 V V30 V V31 V W1 V W2 V

SS SS CC SS CC SS CC SS CC SS CC SS

W3 TESTHI1 Power/Other Input W4 V

W5 BCLK1 FSB Clk Input W6 V W7 V W8 V

TT TT TT

W9 GTLREF_DATA_END Power/Other Input

W23 GTLREF_DATA_MID Power/Other Input W24 V W25 V W26 V W27 V W28 V W29 V W30 V W31 V

Y1 V

Y2 V

Y3 V

SS CC SS CC SS CC SS CC SS CC SS

Y4 BCLK0 FSB Clk Input

Y5 V

Y6 V

Y7 V

SS TT SS

Y8 RESET# Common Clk Input

Y9 D62# Source Sync Input/Output Y10 V

Y11 DSTBP3# Source Sync Input/Output Y12 DSTBN3# Source Sync Input/Output Y13 V

Y14 DSTBP2# Source Sync Input/Output Y15 DSTBN2# Source Sync Input/Output Y16 V

Signal

Buffer Type

Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other

Power/Other

Power/Other Power/Other Power/Other

Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other

Power/Other Power/Other Power/Other

Power/Other

Direction

Document Number: 318080-002 83

Pin Listing

Table 4-2. Pin Listing by Pin Number (Sheet

11 of 14)

Pin No. Pin Name

Y17 DSTBP1# Source Sync Input/Output Y18 DSTBN1# Source Sync Input/Output Y19 V

Y20 DSTBP0# Source Sync Input/Output Y21 DSTBN0# Source Sync Input/Output Y22 V

Y23 D5# Source Sync Input/Output Y24 D2# Source Sync Input/Output Y25 V

Y26 D0# Source Sync Input/Output Y27 Reserved Y28 Reserved Y29 Reserved Y30 V

Y31 BSEL2 Power/Other Output AA1 V AA2 V

CC SS

AA3 BSEL0 Power/Other Output AA4 BPMb0# Common Clk Input/Output AA5 Reserved AA6 V AA7 V

CC TT

AA8 D61# Source Sync Input/Output AA9 V

AA10 D54# Source Sync Input/Output AA11 D53# Source Sync Input/Output AA12 V

AA13 D48# Source Sync Input/Output AA14 D49# Source Sync Input/Output AA15 V

AA16 D33# Source Sync Input/Output AA17 V

AA18 D24# Source Sync Input/Output AA19 D15# Source Sync Input/Output AA20 V

AA21 D11# Source Sync Input/Output AA22 D10# Source Sync Input/Output AA23 V

AA24 D6# Source Sync Input/Output AA25 D3# Source Sync Input/Output AA26 V

AA27 D1# Source Sync Input/Output AA28 Reserved AA29 SM_EP_A0 SMBus Input

Signal

Buffer Type

Power/Other

Power/Other Power/Other

Power/Other

Direction

Table 4-2. Pin Listing by Pin Number (Sheet

12 of 14)

Pin No. Pin Name

AA30 V AA31 V

AB1 V AB2 V

SS CC SS CC

AB3 BSEL1 Power/Other Output AB4 Reserved AB5 V

AB6 D63# Source Sync Input/Output AB7 PWRGOOD Async GTL+ Input AB8 V

AB9 DBI3# Source Sync Input/Output AB10 D55# Source Sync Input/Output AB11 V

AB12 D51# Source Sync Input/Output AB13 D52# Source Sync Input/Output AB14 V

AB15 D37# Source Sync Input/Output AB16 D32# Source Sync Input/Output AB17 D31# Source Sync Input/Output AB18 V

AB19 D14# Source Sync Input/Output AB20 D12# Source Sync Input/Output AB21 V

AB22 D13# Source Sync Input/Output AB23 D9# Source Sync Input/Output AB24 V

AB25 D8# Source Sync Input/Output AB26 D7# Source Sync Input/Output AB27 V

AB28 SM_EP_A2 SMBus Input AB29 SM_EP_A1 SMBus Input AB30 V AB31 V

CC SS

AC1 BPMb1# Common Clk Output

AC2 V

AC3 V

AC4 V

SS CC TT

AC5 D60# Source Sync Input/Output

AC6 D59# Source Sync Input/Output

AC7 V

AC8 D56# Source Sync Input/Output

AC9 D47# Source Sync Input/Output AC10 V

AC11 D43# Source Sync Input/Output

Signal

Buffer Type

Power/Other Power/Other Power/Other Power/Other

Power/Other

Power/Other Power/Other

Power/Other Power/Other Power/Other

Power/Other

Direction

84 Document Number: 318080-002

Pin Listing

Table 4-2. Pin Listing by Pin Number (Sheet

13 of 14)

Pin No. Pin Name

AC12 D41# Source Sync Input/Output AC13 V

AC14 D50# Source Sync Input/Output AC15 DP2# Common Clk Input/Output AC16 V

AC17 D34# Source Sync Input/Output AC18 DP0# Common Clk Input/Output AC19 V

AC20 D25# Source Sync Input/Output AC21 D26# Source Sync Input/Output AC22 V

AC23 D23# Source Sync Input/Output AC24 D20# Source Sync Input/Output AC25 V

AC26 D17# Source Sync Input/Output AC27 DBI0# Source Sync Input/Output AC28 SM _CLK SMBus Input AC29 SM _DAT SMBus Output AC30 Reserved AC31 V

AD1 V AD2 V AD3 V

CC CCPLL CC SS

AD4 Reserved AD5 V

AD6 Reserved AD7 D57# Source Sync Input/Output AD8 D46# Source Sync Input/Output AD9 V

AD10 D45# Source Sync Input/Output AD11 D40# Source Sync Input/Output AD12 V

AD13 D38# Source Sync Input/Output AD14 D39# Source Sync Input/Output AD15 V

AD16 Reserved AD17 V

AD18 D36# Source Sync Input/Output AD19 D30# Source Sync Input/Output AD20 V

Signal

Buffer Type

Direction

Power/Other

Power/Other Power/Other Input Power/Other Power/Other

Power/Other

Table 4-2. Pin Listing by Pin Number (Sheet

14 of 14)

Pin No. Pin Name

AD21 D29# Source Sync Input/Output AD22 DBI1# Source Sync Input/Output AD23 V

AD24 D21# Source Sync Input/Output AD25 D18# Source Sync Input/Output AD26 V

AD27 D4# Source Sync Input/Output AD28 Reserved AD29 SM_WP SMBus Input AD30 Reserved AD31 Reserved

AE2 BPMb2# Common Clk Output AE3 BPMb3# Common Clk Input/Output AE4 V AE5 V AE6 V

TT TT SS

AE7 D58# Source Sync Input/Output AE8 Reserved

AE9 D44# Source Sync Input/Output AE10 D42# Source Sync Input/Output AE11 V

AE12 DBI2# Source Sync Input/Output AE13 D35# Source Sync Input/Output AE14 V

AE15 COMP2 Power/Other Input AE16 COMP3 Power/Other Input AE17 DP3# Common Clk Input/Output AE18 V

AE19 DP1# Common Clk Input/Output AE20 D28# Source Sync Input/Output AE21 V

AE22 D27# Source Sync Input/Output AE23 D22# Source Sync Input/Output AE24 V

AE25 D19# Source Sync Input/Output AE26 D16# Source Sync Input/Output AE27 V

AE28 SM_VCC Power/Other AE29 SM_VCC Power/Other AE30 Reserved

Signal

Buffer Type

Direction

Power/Other

Power/Other Power/Other Power/Other Input

Power/Other

Document Number: 318080-002 85

Pin Listing

86 Document Number: 318080-002

Signal Definitions

5 Signal Definitions

5.1 Signal Definitions.

Table 5-1. Signal Definitions (Sheet 1 of 8)

Name Type Description Notes

A[39:3]# I/O A[39:3]# (Address) define a 2

A20M# I If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20

ADS# I/O ADS# (Address Strobe) is asserted to indicate the validity of the transaction address

ADSTB[1:0]# I/O Address strobes are used to latch A[39:3]# and REQ[4:0]# on their rising and falling

1 of the address phase, these pins transmit the address of a transaction. In subphase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Intel and 7300 Series FSB. A[39:3]# are protected by parity signals AP[1:0]#. A[39:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#.

On the active-to-inactive transition of RESET#, the processors sample a subset of the A[39:3]# pins to determine their power-on configuration. See Section 7.1.

(A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1 MB boundary. Assertion of A20M# is only supported in real mode.

A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O wr ite bus transaction.

on the A[39:3]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new tr ansaction. Th is signal must be connect ed to the appropriate pins on all Intel FSB agents.

edge. Strobes are associated with signals as shown below.

-byte physical memory address space. In sub-phase

Xeon® Processor 7200 Series

Xeon® Processor 7200 Series and 7300 Series

Signals Associated Strobes

REQ[4:0],

A[37:36,16:3]#

A[39:38, 35:17]# ADSTB1#

AP[1:0]# I/O AP[1:0]# (Address Parity) are driven by the requestor one common clock after

BCLK[1:0] I The differential bus clock pair BCLK[1:0] (Bus Clock) determines the FSB frequency.

ADS#, A[39:3]#, REQ[4:0]# are driven. A correct parity signal is electrically high if an even number of covered signals are electrically low and electrically low if an odd number of covered signals are electrically low. This allows parity to be electrically high when all the covered signals are electrically high. A P[1:0]# should connect the appropriate pins of all Intel agents. The following table defines the coverage for these signals.

Request Signals Subphase 1 Subphase 2

A[39:24]# AP0# AP1#

A[23:3]# AP1# AP0#

REQ[4:0]# AP1# AP0#

All processor FSB agents must receive these signals to drive their outputs and latch their inputs.

All external timing parameters are specified with respect to the rising edge of BCLK0 crossing V

CROSS

ADSTB0#

Xeon® Processor 7200 Series and 7300 Series FSB

Document Number: 318080-002 87

Signal Definitions

Table 5-1. Signal Definitions (Sheet 2 of 8)

Name Type Description Notes

BINIT# I/O BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents

BNR# I/O BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is

BPM5# BPM4# BPM3# BPM[2:1]# BPM0#

BPMb3# BPMb[2:1]# BPMb0#

BPRI# I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processo r FSB.

BR[1:0]# I/O The BR[1:0]# signals are sampled on the active-to-inactive transition of RESET#.

BSEL[2:0] O The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor

COMP[3:0] I COMP[3:0] must be terminated to VSS on the baseboard using precisio n resistors.

and if used, must connect the appropriate pins of all such agen ts. If the BINIT# driver is enabled during power on configuration, BINIT# is assert ed to s ignal an y bus condition that prevents reliable future operation.

If BINIT# observation is enabled during power-on configuration ( see Section 7.1) and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and bus request arbitration state machines. The bus agents do not reset their I/O Queue (IOQ) and transaction tracking state machines upon observation of BINIT# asse rtion. Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for the FSB and attempt completion of their bus queue and IOQ entries.

If BINIT# observation is disabled during power-on configur ation, a priority agent may handle an assertion of BINIT# as appropriate to the error handling architecture of the system.

unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any ne w transactions.

Since multiple agents might need to request a bus stall at the same time, BNR# is a wired-OR signal which must connect the appropriate pins of all processor FSB agents. In order to avoid wired-OR glitches associated with simultaneous edge transitions driven by multiple drivers, BNR# is activated on specific clock edges and sampled o n specific clock edges.

I/O

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and

programmable counters used for monitoring processor performance. BPM[5:0]#

I/O

should connect the appropriate pins of all FSB agents.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a

I/O

processor output used by debug tools to determine processor debug readiness. BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is

used by debug tools to request debug operation of the processors. BPM[5:4]# must be bussed to all bus agents. Please refer to the appropriate platfo rm

design guidelines for more detailed information.

I/O

BPMb[3:0]# (Breakpoint Monitor) are a second set of breakpoint and performance monitor signals. They are additional outputs from the processor which indicate the

status of breakpoints and programmable counters used for monitoring processor

I/O

performance. BPMb[3:0]# should connect the appropriate pins of all FSB agents.

It must connect the appropriate pins of all processor FSB agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are co mpleted, then releases the bus by deasserting BPRI#.

The signal which the agent samples asserted determines its agent ID. BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus.

These signals do not have on-die termination and must be terminated.

input clock frequency. Table 2-2 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processors, chipset, and clock synthe sizer. All FSB agents must operate at the same frequency. For more information about these signals, including termination recommendations, refer to the appropriate platform design guideline.

These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate platform design guidelines for implementation details.

88 Document Number: 318080-002

Signal Definitions

Table 5-1. Signal Definitions (Sheet 3 of 8)

Name Type Description Notes

D[63:0]# I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path

between the processor FSB agents, and must connect th e appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer.

D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to strobes and DBI#.

Data Group

D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3

Furthermore, the DBI# signals determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high.

DBI[3:0]# I/O DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of

DBSY# I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the

DEFER# I DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed

DP[3:0]# I/O DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They are

DRDY# I/O DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating

the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits, within, within a 16-bit group, would have been asserted electronically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group.

DBI[3:0] Assignment to Data Bus

Bus Signal Data Bus Signals

DBI0# D[15:0]# DBI1# D[31:16]# DBI2# D[47:32]# DBI3# D[63:48]#

processor FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on all processor FSB agents.

in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or I/O agent. This signal must connect the appropriate pins of all processor FSB agents.

driven by the agent responsible for driving D[63:0]#, and must connect the appropriate pins of all processor FSB agents.

valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of all processor FSB agents.

DSTBN#/

DSTBP#

DBI#

Document Number: 318080-002 89

Table 5-1. Signal Definitions (Sheet 4 of 8)

Name Type Description Notes

DSTBN[3:0]# I/O Data strobe used to latch in D[63:0]#.

Signals Associated Strobes

D[15:0]#, DBI0# DSTBN0# D[31:16]#, DBI1# DSTBN1# D[47:32]#, DBI2# DSTBN2# D[63:48]#, DBI3# DSTBN3#

DSTBP[3:0]# I/O Data strobe used to latch in D[63:0]#.

Signals Associated Strobes

D[15:0]#, DBI0# DSTBP0# D[31:16]#, DBI1# DSTBP1# D[47:32]#, DBI2# DSTBP2# D[63:48]#, DBI3# DSTBP3#

Signal Definitions

FERR#/PBE# O FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal and

FORCEPR# I The FORCEPR# (force power reduction) input can be used by the platform to cause

GTLREF_ADD_MID GTLREF_ADD_END

GTLREF_DATA_MID GTLREF_DATA_END

HIT# HITM#

IERR# O IERR# (Internal Error) is asserted by a processor as the result of an internal error.

its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. For additional information on the pending break event functionality, including the identification of support of the feature and enable/disable information, refer to Vol. 3 of the IA_32 Intel ®

Architecture Software Developer’s Manual and the AP-485 Intel® Processor Identification and the CPUID Instruction application note.

the Intel Control Circuit (TCC).

I GTLREF_ADD determines the signal reference level for AGTL+ address and common

clock input pins. GTLREF_ADD is used by the AGTL+ receivers to determine if a signal is a logical 0 or a logical 1. Please refer to Table 2-17 and the appropriate platform design guidelines for additional details.

I GTLREF_DATA determines the signal reference level for AGTL+ data input pins.

GTLREF_DATA is used by the AGTL+ receivers to determine if a signal is a logical 0 or a logical 1. Please refer to Table 2-17 and the appropriate platform design guidelines for additional details.

I/O

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it

I/O

requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.

Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#.

This signal does not have on-die termination.

Xeon® Processor 7200 Series and 7300 Series to activate the Thermal

90 Document Number: 318080-002

Signal Definitions

Table 5-1. Signal Definitions (Sheet 5 of 8)

Name Type Description Notes

IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a

INIT# I INIT# (Initialization), when asserted, resets integer registers inside all processors

LINT[1:0] I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all FSB agents.

LL_ID[1:0] O The LL_ID[1:0] signals are used to select the correct loadline slope for the processor.

LOCK# I/O LOCK# indicates to the system that a transaction must occur atomically. This signal

MCERR# I/O MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without

PECI I/O PECI is a proprietary one-wire bus interface that provides a communication channel

PROC_ID[1:0] O PROC_ID signals are used to identify which processor is installed.

PROCHOT# O PROCHOT# (Processor Hot) will go active when the processor’s temperature

numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O wr ite bus transaction.

without affecting their internal caches or floating-point registers. Each processo r then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropr i ate pins of all processor FSB agents.

When the APIC functionality is disabled, the LINT0/INTR signal becomes INTR, a maskable interrupt request signal, and LINT1/NMI becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium

processor. Both signals are asynchronous.

These signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration.

These signals are not connected to the pro cessor die. A logic 0 is pulled to ground and a logic 1 is a no-connect on the Intel

Xeon® Processor 7200 Series and 7300 Series

package.

must connect the appropriate pins of all processor FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction.

When the priority agent asserts BPRI# to arbitrate for ownership of the processor FSB, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock.

a bus protocol violation. It may be driven by all processor FSB agents. MCERR# assertion conditions are configurable at a system level. Assertion options

are defined by the following options:

• Enabled or disabled.

• Asserted, if configured, for internal errors along with IERR#.

• Asserted, if configured, by the request initiator of a bus transaction after it observes an error.

• Asserted by any bus agent when it observes an error in a bus transaction.

For more details regarding machine check architecture, refer to the Intel®64 and IA-

32 Architectures Software Developer’s Manual, Volume 3: System Programming Guide.

between Intel processor and chipset components to external thermal monitoring devices. See Section 6.3, “Platform Environment Control Interface (PECI)” for more on the PECI interface.

00: Intel® Xeon® Processor 7400 Series 01: Intel

Xeon® Processor 7200 Series and 7300 Series 10: Reserved 11: Reserved

monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the Thermal Control Circuit (TCC) has been activated, if enabled. The TCC will remain active until shortly after the processor deasserts PROCHOT#. See Section 6.2.5 for more details.

Document Number: 318080-002 91

Signal Definitions

Table 5-1. Signal Definitions (Sheet 6 of 8)

Name Type Description Notes

PWRGOOD I PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean

REQ[4:0]# I/O REQ[4:0]# (Request Command) must connect the appropriate pins of all processor

RESET# I Asserting the RESET# signal resets all processors to known states and invalidates

RS[2:0]# I RS[2:0]# (Response Status) are driven by the response agent (the agent responsible

RSP# I RSP# (Response Parity) is driven by the response agent (the age nt responsible for

SKTOCC# O SKTOCC# (Socket occupied) will be pul led to ground by the processor to i ndicate that

SM_CLK I/O The SM_CLK (SMBus Clock) signal is an input clock to the system management logic

SM_DAT I/O The SM_DAT (SMBus Data) signal is the data signal for the SMBus. This signal

SM_EP_A[2:0] I The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in

SM_VCC I SM_VCC provides power to the SMBus components on the Intel

SM_WP I WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch

indication that all processor clocks and power supplies are stable and within their specifications. “Clean” implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then tr ansition monotonically to a high state. Figure 2-24 illustrates the relationship of PWRGOOD to the RESET# signal. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width specification in Table 2-16, and be followed by a 1-10 ms RESET# pulse.

The PWRGOOD signal must be supplied to the processor; it is used to protec t internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation.

FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are so urce synchronous to AD STB[1:0]#. Refe r to the AP[1:0]# signal description for details on parity checking of these signals.

their internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least 1 ms after V their proper specifications. On observing active RESET#, all FSB agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted.

A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These configuration options are described in the

Section 7.1.

This signal does not have on-die termination and must be terminated on the system board.

for completion of the current transaction), and must connect the appropriate pins of all processor FSB agents.

completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins of all

CC and BCLK have reached

processor FSB agents. A correct parity signal is high if an even number of covered signals are low and low if

an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity.

the processor is present. There is no connection to the processor silicon for this signal.

which is required for operation of the system management features of theIntel

Processor 7200 Series and 7300 Series. This clock is driven by the SMBus

Xeon controller and is asynchronous to other clocks in the processor.The processor includes a 10 kΩ pull-up resistor to SM_VCC for this signal.

provides the single-bit mechanism for transferri ng data between SMBus de vices. The processor includes a 10 kΩ pull-up resistor to SM_VCC for this signal.

conjunction with the upper address bits in order to maintain unique address es on the SMBus in a system with multiple processors. To set an SM_EP_A line high, a pull-up resistor should be used that is no larger than 1 kΩ pull-down resistor to V

for each of these signals.

7200 Series and 7300 Series package.

EEPROM is write-protected when this input is pulled high to SM_VCC. The p rocessor includes a 10 kΩ pull-down resistor to V

. The processor includes a 10 kΩ

for this signal.

Xeon® Processor

92 Document Number: 318080-002

Signal Definitions

Table 5-1. Signal Definitions (Sheet 7 of 8)

Name Type Description Notes

SMI# I SMI# (System Management Interrupt) is asserted asynchronously by system logic.

STPCLK# I STPCLK# (Stop Clock), when asserted, causes processors to enter a low power Stop-

TCK I TCK (Test Clock) provides the clock input for the processor Test Bus (also known as

TDI I TDI (Test Data In) transf ers serial test data into the processor. TDI provides the serial

TDO O TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the

TESTHI[1:0] I TESTHI[1:0] must be connected to a V

TESTIN1 TESTIN2

THERMTRIP# O Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction

TMS I TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

TRDY# I TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive

TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven

CCPLL

VCC_SENSE VCC_SENSE2

On accepting a System Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.

If SMI# is asserted during the deassertion of RESET# the processor will tri-state its outputs. See Section 7.1.

Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus trans actions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processo r re starts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.

the Test Access Port).

input needed for JTAG specification support.

serial output needed for JTAG specification support.

power source through a resistor for proper

processor operation. Refer to Section 2.5 for TESTHI grouping restrictions.

TESTIN1 must be connected to a VTT power source through a resistor as well as to the TESTIN2 pin of the same socket for proper processor operation.

TESTIN2 must be connected to a VTT power source through a resistor as well as to the TESTIN1 pin of the same socket for proper processor operation.

Refer to Section 2.5 for TESTIN restrictions.

temperature has reached a temperature beyond which permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (V removed following the assertion of THERMTRIP#. See Figure 2-21 and Table 2-22 for the appropriate power down sequence and timing requirements. Intel also recommends the removal of V

when THERMTRIP# is asserted.

) must be

Driving of the THERMTRIP# signals is enabled within 10 μs of the assertion of PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated, THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-assertion of the PWRGOOD signal will de-assert THERMTRIP#, if the processor’s junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 μs of the assertion of PWRGOOD.

See the XDP: Debug Port Design Guide for Intel® 7300 Chipset Platforms for further information.

a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all FSB agents.

low during power on Reset.

IThe Intel® Xeon® Processor 7200 Series and 7300 Series implement an on-die PLL

filter solution. The V

input is used as a PLL supply voltage.

CCPLL

O VCC_SENSE and VCC_SENSE2 provides an isolated, low impedance connection to the

processor core power and ground. These signals should be used to provide feedback to the voltage regulator signals, which ensure the output voltage (that is, processor voltage) remains within specification. Please see the applicable platform design guide for implementation details.

Document Number: 318080-002 93

Signal Definitions

Table 5-1. Signal Definitions (Sheet 8 of 8)

Name Type Description Notes

VID[6:1] O VID[6:1] (Voltage ID) pins are used to support automatic selection of power supply

VSS_SENSE VSS_SENSE2

VTT P The FSB termination voltage input pins. Refer to Table 2-9 for further details. VTT_SEL O The VTT_SEL signal is used to select the correct V

voltages (V pulled up through a resistor. Conversely, the voltage regulator output must be disabled prior to the voltage supply for these pins becomes invalid. The VID pins are needed to support processor voltage s pecification variations. See Table 2- 3 for definitions of these pins. The VR must supply the voltage that is requested by these pins, or disable itself.

O VSS_SENSE and VSS_SENSE2 provides an isolated, low impedance co nnection to the

VTT_SEL is a no-connect on the Intel package.

). These are CMOS signals that are driven by the processor and must be

voltage level for the processor.

Xeon® Processor 7200 Series and 7300 Series

94 Document Number: 318080-002

Thermal Specifications

6 Thermal Specifications

6.1 Package Thermal Specifications

The Intel® Xeon® Processor 7200 Series and 7300 Series requires a thermal solution to maintain temperatures within its operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation.

A complete solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting.

This section provides data necessary for developing a complete thermal solution. For more information on designing a component level thermal solution, refer to the Dual-

Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series Thermal / Mechanical Design Guide.

6.1.1 Thermal Specifications

To allow the optimal operation and long-term reliability of Intel processor-based systems, the processor must remain within the minimum and maximum case temperature (TCASE) specifications as defined by the applicable thermal profile (see

Table 6-1 and Figure 6-1 for Quad-Core Intel® Xeon® Processor E7300 Series, Table 6-3 and Figure 6-2 for Quad-Core Intel® Xeon® X7350 Processor, Table 6-5 and Figure 6-3 for Quad-Core Intel® Xeon® L7345 Processor, Table 6-7 and Figure 6-4 for

Dual-Core Intel® Xeon® Processor 7200 Series). Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, please refer to the

Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series Thermal / Mechanical Design Guide.

The Intel managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and to assure processor reliability . Selection of the appropriate fan speed is based on the relative temperature data reported by the processor’s Platform Environment Control Interface (PECI) bus as described in

Section 6.3. The temperature reported over PECI is always a negative value and

represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT# (see Section 6.2, Processor Thermal Features). Systems that implement fan speed control should be designed to use this data. Systems that do not alter the fan speed also need to guarantee the case temperature meets the thermal profile specifications.

The Quad-Core Intel® Xeon® Processor E7300 Series (see Figure 6-1; Table 6-2), Quad-Core Intel® Xeon® L7345 Processor (see Figure 6-3; Table 6-6) and Dual-Core Intel® Xeon® Processor 7200 Series (see Figure 6-4; Table 6-8) supports a single Thermal Profile. The Thermal Profile is indicative of a constrained thermal environment (Ex: 1U form factor). Because of the reduced cooling capability represented by this solution, the probability of TCC activation and performance loss is increased.

Xeon® Processor 7200 Series and 7300 Series implement a methodology for

Document Number: 318080-002 95

Thermal Specifications

Additionally , utilization of a thermal solution that does not meet the Thermal Profile will violate the thermal specifications and may result in permanent damage to the processor. Refer to the Dual-Core Intel® Xeon® Processor 7200 Series and Quad- Core Intel® Xeon® Processor 7300 Series Thermal / Mechanical Design Guide for details on system thermal solution design, thermal profiles and environmental considerations.

For the Quad-Core Intel® Xeon® X7350 Processor, Intel has developed a thermal profile which must be met to ensure adherence to Intel reliability requirements. The Thermal Profile (see Figure 6-2; Table 6-4) is representative of a volumetrically unconstrained thermal solution (that is, industry enabled 2U heatsink). In this scenario, it is expected that the Thermal Control Circuit (TCC) would only be activated for very brief periods of time when running the most power intensive applications. Intel has developed the thermal profile to allow customers to choose the thermal solution and environmental parameters that best suit their platform implementation. Refer to the

Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series Thermal / Mechanical Design Guide for details on system

thermal solution design, thermal profiles and environmental considerations. The upper point of the thermal profile consists of the Thermal Design Power (TDP) and

the associated T Quad-Core Intel® Xeon® X7350 Processor Thermal Profile (x = TDP and y = T

value. It should be noted that the upper point associated with

CASE

CASE_MAX

P @ TDP) represents a thermal solution design point. In actuality the processor case temperature will not reach this value due to TCC activation (see Figure 6-2 for QuadCore Intel® Xeon® X7350 Processor).

Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) instead of the maximum processor power consumption. The Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period. For more details on this feature, refer to

Section 6.2. To ensure maximum flexibility for future requirements, systems should be

designed to the Flexible Motherboard (FMB) guidelines, even if a processor with lower power dissipation is currently planned. Thermal Monitor and Thermal Monitor 2

feature must be enabled for the processor to remain within its specifications.

Table 6-1. Quad-Core Intel® Xeon® E7300 Processor Thermal Specifications

Core

Frequency

Launch to FMB 80 5 See Figure 6-1;

Notes:

1. These values are specified at V the processor is not to be subjected to any static V specified I

2. Maximum Power is the highest power the processor will dissipate, regardless of its VID. Maximum P ower is measured at maximum T

3. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum T

4. These specifications are based on pre-silicon estimates and simulations. These specifications will be updated with characterized data from silicon measurements in a future release of this document.

5. Power specifications are defined at all VIDs found in Table 2-3. The Quad-Core Intel® Xeon® E7300 Processor may be shipped under multiple VIDs for each frequency.

6. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

Thermal Design

Power

(W)

. Please refer to the loadline specifications in Section 2.

CASE

Minimum

CASE

(°C)

for all processor frequencies. Systems must be designed to ensure

CC_MAX

Maximum

CASE

(°C)

Table 6-2;

and ICC combination wherein VCC exceeds V

Notes

1, 2, 3, 4, 5, 6

CASE

CC_MAX

96 Document Number: 318080-002

Thermal Specifications

Figure 6-1.Quad-Core Intel® Xeon® E7300 Processor Thermal Profile

Thermal Profile

70.0

60.0

50.0

= 0.263 x Power + 45

case

40.0

Temperature (C)

30.0

20.0 0 1020304050607080

Pow er(W)

Notes:

1. Please refer to Tab le 6-2 for discrete points that constitute the thermal profile.

2. Implementation of Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation).

3. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum T

4. These specifications are based pre-silicon estimates and simulations. These specifications will be updated with characterized data from silicon measurements in a future release of this document.

5. Power specifications are defined at all VIDs found in Table 2-3. The Quad-Core Intel® Xeon® E7300 Processor may be shipped under multiple VIDs for each frequency.

6. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

CASE

Table 6-2. Quad-Core Intel® Xeon® E7300 Processor Thermal Profile Table

Power (W) T

0 45.0 10 47.6 20 50.3 30 52.9 40 55.5 50 58.2 60 60.8 70 63.4 80 66.0

CASE_MAX

(° C)

Document Number: 318080-002 97

Thermal Specifications

Table 6-3. Quad-Core Intel® Xeon® X7350 Processor Thermal Specifications

Core

Frequency

Thermal

Design Power

(W)

Minimum

CASE

(°C)

Launch to FMB 130 5 See Figure 6-2;

Maximum

CASE

(°C)

Table 6-4;

1, 2, 3, 4, 5, 6

Notes:

1. These values are specified at V the processor is not to be subjected to any static V specified I

2. Maximum Power is the highest power the processor will dissipate, regardless of its VID. Maximum P ower is measured at maximum T

3. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum T

4. These specifications are based pre-silicon estimates and simulations. These specifications will be updated with characterized data from silicon measurements in a future release of this document.

5. Power specifications are defined at all VIDs found in Table 2-3. The Intel® Xeon® X7350 Processor may be shipped under multiple VIDs for each frequency.

6. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor

. Please refer to the loadline specifications in Section 2.

CASE

for all processor frequencies. Systems must be designed to ensure

CC_MAX

and ICC combination wherein VCC exceeds V

frequency requirements.

Figure 6-2.Quad-Core Intel® Xeon® X7350 Processor Thermal Profile

Thermal Profile

70.00

60.00

Notes

CASE

CC_MAX

50.00

40.00

= 0.162 x Power + 45

case

Temperature (C)

30.00

20.00 0 102030405060708090100110120130

Power ( W )

Notes:

1. Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 6-4 for discrete points that constitute the thermal profile.

3. Refer to the Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series Thermal / Mechanical Design Guide for system and environmental implementation details.

98 Document Number: 318080-002

Thermal Specifications

Table 6-4. Quad-Core Intel® Xeon® X7350 Processor Thermal Profile Table

Power (W) T

0 45.0 10 46.6 20 48.2 30 49.9 40 51.5 50 53.1 60 54.7 70 56.3 80 58.0 90 59.6

100 61.2 110 62.8 120 64.4 130 66.0

CASE_MAX

(° C)

Table 6-5. Quad-Core Intel® Xeon® L7345 Processor Thermal Specifications

Core

Frequency

Thermal Design

Power

(W)

Minimum

CASE

(°C)

Launch to FMB 50 5 See Figure 6-3;

Maximum

CASE

(°C)

Table 6-6

Notes

1, 2, 3, 4, 5, 6

Notes:

1. These values are specified at V the processor is not to be subjected to an y static V specified I

2. Maximum Power is the highest power the processor will dissipate, regardless of its VID. Maximum Power is measured at maximum T

3. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum T

4. These specifications are based on initial silicon characterization. These specifications may be further updated as more characterization data becomes available.

5. Power specifications are defined at all VIDs found in Table 2-3. The Quad-Core Intel® Xeon® L7345 Processor may be shipped under multiple VIDs for each frequency.

6. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements.

. Please refer to the loadline specifications in Section 2.

CASE

for all processor frequencies. Systems must be designed to ensure

CC_MAX

and ICC combination wherein VCC exceeds V

CASE

CC_MAX

Document Number: 318080-002 99

Figure 6-3. Quad-Core Intel® Xeon® L7345 Processor Thermal Profile

Thermal P ro file

70.0

65.0

60.0

55.0

50.0

45.0

40.0

Temperature (C)

35.0

30.0

25.0

20.0 0 5 10 15 20 25 30 35 40 45 50

= 0.420 x Power + 45

case

Pow er (W)

Thermal Specifications

Notes:

1. Please refer to Table 6-6 for discrete points that constitute the thermal profile.

2. Refer to the Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series Thermal / Mechanical Design Guide for system and environmental implementation details.

Table 6-6. Quad-Core Intel® Xeon® L7345 Processor Thermal Profile

Power (W) T

0 45.0

5 47.1 10 49.2 15 51.3 20 53.4 25 55.5 30 57.6 35 59.7 40 61.8 45 63.9 50 66.0

CASE_MAX

(° C)

100 Document Number: 318080-002

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