Intel Arria 10 SDI II User Manual

Intel® Arria® 10 SDI II IP Core Design Example User Guide

Updated for Intel® Quartus® Prime Design Suite: 17.0

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1.5.2 Design Limitations for Serial Loopback Design

The serial loopback design example has the following limitations:

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1 SDI II Design Example Quick Start Guide

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• You may encounter certain problems with the 12G-SDI 2160p59.94 in the serial loopback design that cannot be detected on the Omnitek Ultra 4K analyzer (software v2.1).

• Serial loopback design is mainly for image and TX clock switching demonstrations only. To get a more accurate jitter performance with the daughter card components, use the parallel loopback design and connect it to a clean video source.

• To allow segmented frame video format (1080sF30, 1080sF25) and interlaced video format (1080i60, 1080i50) to be correctly differentiated in the external analyzer, Payload ID has to be inserted in the serial loopback design.

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2 SDI II Design Example Detailed Description

The SDI II IP core includes three design examples for Arria 10 devices.

• Parallel loopback with external VCXO

• Parallel loopback without external VCXO

• Serial loopback

Features

• For HD/3G-SDI single rate and triple rate designs, you can choose either CMU or fPLL as the TX PLL.

• All designs use LED status for early debugging stage.

• The simplex serial loopback designs include RX and TX options. To use RX or TX only components, remove the irrelevant blocks from the designs.

User Requirement Preserve Remove

RX Only RX Top — TX Top

— Transceiver Arbiter

TX Only TX Top — RX Top

— Transceiver Arbiter

Note: You can directly connect the Avalon-MM pins at the RX or TX Top as shown

in the diagram below.

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

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Top

RX Top

SDI II

RX

Transceiver

PHY Reset

Controller (RX)

Transceiver Native PHY

(RX)

RX

Reconfiguration

Management

Transceiver

Arbiter

Pattern Generator Control

SDI RX System

TX Top

SDI II

TX

Transceiver

PHY Reset

C ontroller (RT)

Transceiver Native PHY

(TX)

SDI TX System

TX

PLL

Alt

Pattern Generator

Control PIO

Parallel Data Serial Data

Control/Status Avalon-MM

JTAG to Avalon

Master Bridge

Video Pattern

Generator

TX

PLL

TX

Reconfiguration

Management

TX Only Components RX Only Components Removed Blocks

2 SDI II Design Example Detailed Description

Figure 7. Components Required for TX or RX Only Design

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2.1 Parallel Loopback Design Examples

The parallel loopback design examples demonstrate simplex and duplex channel modes with and without external VCXO.

Note: For parallel loopback duplex designs, do not share the TX PLL reference clock with the

RX transceiver reference clock. The design logic tunes the TX PLL clock to match the RX recovered clock frequency. For the parallel loopback with external VCXO designs (single-rate and triple-rate), use the only 148.5 MHz on-board oscillator as the TX PLL reference clock. For the RX reference clock, use a 270 MHz clock from another onboard oscillator.

Intel® Arria® 10 SDI II IP Core Design Example User Guide 14

Top

RX Top

SDI II

RX

Transceiver

PHY Reset

Controller (RX)

Transceiver Native PHY

(RX)

RX Reconfiguration Management (3)

Transceiver

Arbiter (3)

Loopback Top

SDI RX System

TX Top

SDI II

TX

Transceiver

PHY Reset

Controller (TX)

Transceiver

Native PHY

(TX)

SDI TX System

TX PLL

Loopback

FIFO

PFD (1)

Reclock (2)

(4)

Parallel Data Serial Data

Control/Status Avalon-MM

(1) Generate up/down control signal to on-board Si516 for clock synchronization purpose. (2) Block/Connection only required for parallel loopback without external VCXO designs. (3) Block/Connection only required for triple-rate/multi-rate designs. (4) FVH video sync signals to LMH1983 for clock synchronization purpose.

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Parallel Loopback with Simplex Mode

Figure 8. Parallel Loopback with Simplex Mode Block Diagram

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Top

RX Top

SDI II

RX

Transceiver

PHY Reset

Controller (RX)

Transceiver Native PHY

(RX)

RX

Reconfiguration

Management (3)

Transceiver

Arbiter

Loopback Top

SDI RX System

TX Top

SDI II

TX

Transceiver

PHY Reset

Controller (TX)

Transceiver Native PHY

(TX)

SDI TX System

TX PLL

Loopback

FIFO

PFD (1)

Reclock (2)

TX PLL Reference Clock TX Transceiver clkout TX PLL Serial Clock RX Reference Clock RX Transceiver clkout Management Clock

RX Reference

Clock

Management

Clock

TX PLL

Reference

Clock

(1) Block/Connection only required for parallel loopback with external VCXO designs. (2) Block/Connection only required for parallel loopback without external VCXO designs. (3) Block/Connection only required for triple-rate/multi-rate designs.

2 SDI II Design Example Detailed Description

Figure 9. Parallel Loopback with Simplex Mode Clocking Scheme

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Intel® Arria® 10 SDI II IP Core Design Example User Guide 16

Top

Duplex Top

SDI II

Duplex

Transceiver

PHY Reset

Controller (RX)

Transceiver Native PHY

(Duplex)

RX

Reconfiguration

Management (3)

Transceiver

Arbiter (3)

Loopback Top

SDI Duplex System

TX PLL

Loopback

FIFO

PFD (1)

Reclock (2)

Parallel Data Serial Data

Control/Status Avalon-MM

(4)

Transceiver

PHY Reset

C ontroller (TX)

(1) Generate up/down control signal to on-board Si516 for clock synchronization purpose. (2) Block/Connection only required for parallel loopback without external VCXO designs. (3) Block/Connection only required for triple-rate/multi-rate designs. (4) FVH video sync signals to LMH1983 for clock synchronization purpose.

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Parallel Loopback with Duplex Mode

Figure 10. Parallel Loopback with Duplex Mode Block Diagram

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Top

Duplex Top

SDI II

Duplex

Transceiver

PHY Reset

Controller (RX)

Transceiver Native PHY

(Duplex)

RX

Reconfiguration

Management (3)

Transceiver

Arbiter (3)

Loopback Top

SDI Duplex System

TX PLL

Loopback

FIFO

PFD (1)

Reclock (2)

Transceiver

PHY Reset

Controller (TX)

TX PLL Reference Clock TX Transceiver clkout TX PLL Serial Clock RX Reference Clock RX Transceiver clkout Management Clock

RX Reference Clock

Management

Clock

TX PLL

Reference

Clock

(1) Block/Connection only required for parallel loopback with external VCXO designs. (2) Block/Connection only required for parallel loopback without external VCXO designs. (3) Block/Connection only required for triple-rate/multi-rate designs.

2 SDI II Design Example Detailed Description

Figure 11. Parallel Loopback with Duplex Mode Clocking Scheme

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2.2 Serial Loopback Design Examples

The serial loopback design examples demonstrate simplex and duplex channel modes.

Intel® Arria® 10 SDI II IP Core Design Example User Guide 18

Top

RX Top

SDI II

RX

Transceiver

PHY Reset

Controller (RX)

Transceiver Native PHY

(RX)

RX

Reconfiguration

Management (1)

Transceiver Arbiter

(1), (2)

Pattern Generator Control

SDI RX System

TX Top

SDI II

TX

Transceiver

PHY Reset

Controller (TX)

Transceiver Native PHY

(TX)

SDI TX System

TX

PLL

Alt (2)

Pattern Generator

Control PIO

Parallel Data Serial Data

Control/Status Avalon-MM

(1) Block/Connection only required for triple-rate/multi-rate designs. (2) Block/Connection only required for triple-rate/multi-rate for TX PLL switching designs. (3) Block/Connection only required for triple-rate/multi-rate for TX PLL reference clock switching designs.

JTAG to Avalon

Master Bridge

Video Pattern

Generator

(1) (2)

(1)

TX

PLL

TX Reconfiguration

Management

(2), (3)

(2)

(3)

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Serial Loopback with Simplex Mode

Figure 12. Serial Loopback with Simplex Mode Block Diagram

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Top

RX Top

SDI II

RX

Transceiver

PHY Reset

Controller (RX)

Transceiver Native PHY

(RX)

RX Reconfiguration Management (1)

Transceiver Arbiter

(1), (2)

Pattern Generator Control

SDI RX System

TX Top

SDI II

TX

Transceiver

PHY Reset

Controller (TX)

Transceiver Native PHY

(TX)

SDI TX System

TX

PLL

Alt (2)

Pattern Generator

Control PIO

JTAG to Avalon

Master Bridge

Video Pattern

Generator

TX

PLL

TX Reconfiguration

Management

(2), (3)

TX PLL Reference Clock TX Transceiver clkout TX PLL Serial Clock RX Reference Clock RX Transceiver clkout Management Clock

(1) Block/Connection only required for triple-rate/multi-rate designs. (2) Block/Connection only required for triple-rate/multi-rate for TX PLL switching designs. (3) Block/Connection only required for triple-rate/multi-rate for TX PLL reference clock switching designs.

Management

Clock

RX Reference

Clock

TX PLL Alt Reference

Clock (2), (3)

TX PLL

Reference

Clock

(1) (2)

(3)

2 SDI II Design Example Detailed Description

Figure 13. Serial Loopback with Simplex Mode Clocking Scheme

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Intel® Arria® 10 SDI II IP Core Design Example User Guide 20

Top

Duplex Top

SDI II

Duplex

Transceiver

PHY Reset

Controller (RX)

Transceiver

Native PHY

(Duplex)

RX Reconfiguration Management (1)

Transceiver Arbiter

(1), (2)

Pattern Generator Control

SDI Duplex System

Pattern Generator

Control PIO

Parallel Data Serial Data

Control/Status Avalon-MM

(1) Block/Connection only required for triple-rate/multi-rate designs. (2) Block/Connection only required for triple-rate/multi-rate for TX PLL switching designs. (3) Block/Connection only required for triple-rate/multi-rate for TX PLL reference clock switching designs.

JTAG to Avalon

Master Bridge

Video Pattern

Generator

Transceiver

PHY Reset

Controller (TX)

TX

PLL

Alt (2)

TX

PLL

TX Reconfiguration

Management

(2), (3)

(2)

(3)

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Serial Loopback with Duplex Mode

Figure 14. Serial Loopback with Duplex Mode Block Diagram

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Top

Duplex Top

SDI II

Duplex

Transceiver

PHY Reset

Controller (RX)

Transceiver

Native PHY

(Duplex)

RX

Reconfiguration

Management (1)

Transceiver Arbiter

(1), (2)

Pattern Generator Control

SDI Duplex System

Pattern Generator

Control PIO

JTAG to Avalon

Master Bridge

Video Pattern

Generator

Transceiver

PHY Reset

Controller (TX)

TX

PLL

Alt (2)

TX

PLL

TX Reconfiguration

Management

(2), (3)

(2)

(3)

TX PLL Reference Clock TX Transceiver clkout TX PLL Serial Clock RX Reference Clock RX Transceiver clkout Management Clock

TX PLL Alt Reference

Clock (2), (3)

TX PLL

Reference

Clock

RX

Reference

Clock

Management

Clock

(1) Block/Connection only required for triple-rate/multi-rate designs. (2) Block/Connection only required for triple-rate/multi-rate for TX PLL switching designs. (3) Block/Connection only required for triple-rate/multi-rate for TX PLL reference clock switching designs.

2 SDI II Design Example Detailed Description

Figure 15. Serial Loopback with Duplex Mode Clocking Scheme

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2.3 Design Components

The SDI II IP core design examples require the following components.

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Table 6. Device Under Test (DUT) Components

Design Component Description

SDI II IP Core • TX

— The TX core receives the video data from the top level and encodes the

necessary information, (e.g. line number (LN), cyclical redundancy check (CRC), payload ID), into the data stream(s).

— In a multi-rate design, the TX core oversamples the received data up to

11.88 Gbps data rate for every video standard. Specify the assignment of the parallel data interface (tx_parallel_data) to the transceiver based on the 11.88 Gbps data rate settings.

• RX — The RX core receives the parallel data from the Transceiver Native PHY IP

core and decodes information. This information includes descrambling, realigning data, and extracting the necessary information for user.

— For a multi-rate design, due to the difference in data widths recovered for

different video standards, rearrange rx_parallel_data from the transceiver before passing the data back to the protocol block.

Transceiver Native PHY IP Core • TX

Hard transceiver block that receives parallel data from the SDI II IP core and serializes the data before transmission.

— For HD/3G-SDI single-rate and triple-rate designs, enable the simplified

data interface option to connect parallel data directly to the tx_dataout signal of the SDI II IP core.

— For a multi-rate design, disable this option due to the limitation in the

12G-SDI transceiver PHY settings.

• RX Hard transceiver block that receives serial data from an external video

source. — For HD/3G-SDI single-rate and triple-rate designs, enable the simplified

data interface option to connect parallel data directly to the rx_datain signal of SDI II IP core.

— For a multi-rate design, disable this option due to the limitation in the

12G-SDI transceiver PHY settings.

You must connect the rx_analogreset_ack output signal from this block to the RX Reconfiguration Management module to indicate that the transceiver is in reset.

Note: For the duplex mode transceiver (SDI triple-rate parallel loopback with

external VCXO design example), generate a dummy RX only PHY (sdi_rx_phy.qsys) to get the transceiver configuration files (*_CFG0.sv, *_CFG1.sv, …) for RX reconfiguration. The generated configuration files from the duplex mode transceiver may contain some TX registers. You don't need to reconfigure the registers because only the SDI RX core requires transceiver reconfiguration.

Transceiver PHY Reset Controller • TX

— The reset input of this controller is triggered from the top level. — The controller generates the corresponding analog and digital reset signal

to the Transceiver Native PHY block, according to the reset sequencing inside the block.

—

Use the tx_ready output signal from the block as a reset signal to the TX core to indicate that the transceiver is up and running, and ready to receive data from the core.

• RX — The reset input of this controller is triggered by the SDI II IP core. — The controller generates the corresponding analog and digital reset signal

to the Transceiver Native PHY block according to the reset sequencing inside the block.

RX Reconfiguration Management RX transceiver reconfiguration management block that reconfigures the

Transceiver Native PHY block to receive different data rates from SD-SDI to 12GSDI standards.

continued...

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Design Component Description

To indicate the status of the transceiver, connect rx_cal_busy and

rx_analogreset_ack from the transceiver to this block.

TX Reconfiguration Management TX PLL or transceiver reconfiguration management block that reconfigures the TX

TX PLL/TX PLL Alt Transmitter PLL block that provides the serial fast clock to Transceiver Native

PLL or Transceiver Native PHY block to change the TX clock dynamically for switching between integer and fractional frame rates.

The block requires tx_cal_busy, pll_cal_busy, and tx_analogreset_ack from the transceiver, and the PLLs to indicate the status of the transceiver in a TX PLL switching design.

PHY.

• For TX PLL switching design, TX PLL is always configured to generate integer frame rate while TX PLL Alt is configured to generate fractional frame rate.

• For TX PLL reference clock switching design, TX PLL is configured to have reference clock 0 to generate integer frame rate and reference clock 1 to generate fractional frame rate.

• For single-rate and triple-rate designs, this PLL can be either CMU PLL or fPLL.

• For multi-rate designs, CMU PLL is not recommended for 12G data rate. Use fPLL instead.

Move the TX PLL out from the TX top if you want to merge the PLL between multiple channels.

Table 7. Loopback Components

Component Description

Loopback FIFO This block contains a dual-clock FIFO (DCFIFO) buffer to handle the data

Phase Frequency Detector (PFD) You require this soft PFD block when you use the Arria 10 GX FPGA development

Reclock The parallel loopback without external VCXO design requires this module. Similar

transmission across asynchronous clock domains—the receiver recovered clock and transmitter clock out.

• The receiver sends the decoded RX data to the transmitter through this FIFO buffer.

• When the receiver locks, the RX data is written to the FIFO buffer.

• The transmitter starts reading, encoding, and transmitting the data when half of the FIFO buffer is filled.

kit on-board Si516 VCXO for a parallel loopback design.

• This block compares the phase between the receiver and transmitter parallel clocks, and generates an up or down signal, that connects to the Si516 VCXO.

• These up/down signals control the voltage of the VCXO, so that the frequencies of both clock domains can be tuned as close as possible to each other.

Note: Applicable only for parallel loopback with external VCXO designs.

to the PFD block, this block compares the phase between the receiver and transmitter parallel clocks.

The output interfaces of this block connect to the reconfiguration Avalon Memory-Mapped (Avalon-MM) interfaces of an fPLL. If there is any difference in the frequencies between the clock domains, this module generates the necessary signals to reconfigure the fPLL to match the clock frequencies as close as possible.

Note: Applicable only for parallel loopback without external VCXO designs.

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Table 8. Video Pattern Generator Components

Component Description

Video Pattern Generator Basic video pattern generator which supports SD-SDI up to 12G-SDI video

Pattern Gen Control PIO Provides a memory-mapped interface for controlling the video pattern generator.

JTAG to Avalon Master Bridge Provides System Console host access to the Parallel I/O (PIO) IP core in the

formats with 4:2:2 YCbCr. The generator enables you to select static video with colorbar pattern or pathological pattern.

design through the JTAG interface.

Table 9. Common Block

Component Description

Transceiver Arbiter This generic functional block prevents transceivers from recalibrating

simultaneously when either RX or TX transceivers within the same physical channel require reconfiguration. The simultaneous recalibration impacts applications where RX and TX transceivers within the same channel are assigned to independent IP implementations.

This transceiver arbiter is an extension to the resolution recommended for merging simplex TX and simplex RX into the same physical channel. This transceiver arbiter also assists in merging and arbitrating the Avalon-MM RX and TX reconfiguration requests targeting simplex RX and TX transceivers within a channel as the reconfiguration interface port of the transceivers can only be accessed sequentially. The transceiver arbiter is not required when only either RX or TX transceiver is used in a channel.

The transceiver arbiter identifies the requester of a reconfiguration through its Avalon-MM reconfiguration interfaces and ensures that the corresponding

tx_reconfig_cal_busy or rx_reconfig_cal_busy is gated accordingly.

2.4 Clocking Scheme Signals

The table lists the clocking scheme signals for the SDI II IP core design examples.

Table 10. Clocking Scheme Signals

Clock Signal Name in Design Description

TX PLL Refclock

tx_pll_refclk

TX PLL reference clock, of any frequency that is divisible by the transceiver for that data rate.

continued...

Intel® Arria® 10 SDI II IP Core Design Example User Guide

25

Clock Signal Name in Design Description

TX PLL Alt Refclock

TX Transceiver Clockout

TX PLL Serial Clock

RX Refclock

tx_pll_refclk_alt

tx_vid_clkout

tx_serial_clk

rx_cdr_refclk

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Note: You must connect this clock to a dedicated

transceiver reference clock pin.

• Parallel loopback with external VCXO — Use a minimum clock frequency of 148.5 MHz

(single-rate/triple-rate) or 297 MHz (multi-rate) to meet jitter performance specification.

— Using a higher clock frequency would require a

modification of the TX PLL reference clock value in the TX PLL parameter editor.

• Parallel loopback without external VCXO — The recommended frequency is 100 MHz.

• Serial loopback — For this design, the TX PLL refclock is configured to

generate clock for integer frame rate.

— The minimum clock frequency is 148.5 MHz (single-

rate/triple-rate) or 297 MHz (multi-rate) to meet jitter performance specification.

— Using a higher clock frequency would require a

modification of the TX PLL reference clock value in TX PLL parameter editor.

Second TX PLL reference clock which can be any clock frequency that is divisible by transceiver for that data rate. This clock must be connected to a dedicated transceiver reference clock pin.

• Serial loopback — For this design example, TX PLL alt refclock is

configured to generate clock for fractional frame rate.

— The minimum clock frequency is 148.35 MHz (single-

rate/triple-rate) or 297.7 MHz (multi-rate) to meet jitter performance specification.

— Using a higher clock frequency would require a

modification of the TX PLL reference clock value in the TX PLL parameter editor.

Recovered clock from the transceiver.

• HD-SDI single rate — 74.25 MHz (default) — 74.1758 MHz (for the Dynamic TX clock switching

feature when you transmit video format with fractional frame rate)

• 3G-SDI single rate, triple rate or multi rate — 148.5 MHz (default) — 148.35 MHz (for the Dynamic TX clock switching

feature when you transmit video format with fractional frame rate)

Serial fast clock generated by TX PLL. The clock frequency is set based on the data rate.

Transceiver clock data recovery (CDR) reference clock, of any frequency that is divisible by the transceiver for that data rate. Only a single reference clock frequency is required to support both integer and fractional frame rates. It must be a free running clock connected to the transceiver clock pin.

continued...

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Clock Signal Name in Design Description

rx_core_refclk

• Parallel loopback with external VCXO — For this design example, the minimum clock

frequency of 148.5 MHz is used in the multi-rate design example. For single-rate and triple-rate design examples, a higher reference clock (270 MHz) is used instead.

— Using a higher clock frequency would require a

modification of the RX CDR reference clock value in the Arria 10 Native PHY Transceiver parameter editor. For triple or multi-rate modes, you need to modify the reference clock value for every profiles.

• Parallel loopback without external VCXO and Serial loopback

— The minimum clock frequency is 148.5 MHz. — Using a higher clock frequency would require a

modification of the RX CDR reference clock value in the Arria 10 Native PHY Transceiver parameter editor. For triple or multi-rate modes, you need to modify the reference clock value for every profiles.

Note: Do not share the TX PLL reference clock with the RX

transceiver reference clock for a parallel loopback design. In parallel loopback designs, the TX PLL clock is tuned to match the RX recovered clock frequency.

SDI RX core reference clock. The required frequency is 148.5 MHz. This clock must be a

free-running clock.

continued...

Intel® Arria® 10 SDI II IP Core Design Example User Guide

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2 SDI II Design Example Detailed Description

Clock Signal Name in Design Description

RX Transceiver Clkout

Management Clock

rx_vid_clkout

rx_rcfg_mgmt_clk

tx_rcfg_mgmt_clk

Recovered clock from the transceiver.

• SD-SDI — 148.5 MHz (default)

• HD-SDI — 74.25 MHz when receiving integer frame rate — 74.1758 MHz when receiving fractional frame rate

• 3G/6G/12-SDI — 148.5 MHz when receiving integer frame rate — 148.35 MHz when receiving fractional frame rate

A free running 100 MHz RX clock for both Avalon-MM interfaces for reconfiguration and PHY reset controller for transceiver reset sequence.

Component Required Frequency

Avalon-MM reconfiguration 100 – 125

Transceiver PHY reset controller 1 – 500

You may also connect this input clock to rx_core_refclk and change the input clock frequency option to 149 MHz in the parameter editor.

A free-running 100 MHz TX clock for both Avalon-MM interfaces for reconfiguration and PHY reset controller for transceiver reset sequence.

Component Required Frequency

Avalon-MM reconfiguration 100 – 125

Transceiver PHY reset controller 1 – 500

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(MHz)

2.5 Interface Signals

The tables list the signals for the SDI II IP core design examples.

Table 11. Top-Level Signals

Signal Direction Width Description

clk_fpga_b2_p

pcie_ob_refclk_p

refclk_dp_p

You may also connect this input clock to tx_pll_refclk (assuming this clock is not connected to a VCXO that will be tuned) and change the input clock frequency option to the correct clock frequency in the parameter editor.

On-board Oscillator Signals

Input 1 100 MHz clock for reconfiguration Avalon-MM interfaces.

Input 1 100 MHz dedicated transceiver reference clock.

Input 1 270 MHz dedicated transceiver reference clock.

continued...

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Signal Direction Width Description

refclk_sdi_p

refclk_sma_p

refclk_fmcb_p

user_pb0

cpu_resetn

user_led_g

user_led_r

On-board Si516, SDI Cable Driver and Equalizer Related Pins

sdi_rx_p

sdi_tx_p

sdi_clk148_up

sdi_clk148_down

sdi_mf0_bypass

sdi_mf1_auto_sleep

sdi_mf1_mute

sdi_tx_sd_hdn

Input 1 148.5 or 148.35 MHz dedicated transceiver reference

Input 1 302 MHz dedicated transceiver reference clock.

Input 1 625 MHz dedicated transceiver reference clock.

Input 1 Push button to power down LMK03328 after switching

Input 1 Global reset.

Output 8 Green LED display.

Output 8 Red LED display.

Input 1 On-board SDI RX serial data.

Output 1 On-board SDI TX serial data.

Output 1 Voltage control for Si516.

Output 1 On-board SDI RX Equalizer Bypass.

Output 1 On-board SDI RX Equalizer Auto Sleep.

Output 1 On-board SDI RX Equalizer Mute.

Output 1 On-board SDI TX cable driver slew rate control.

On-board Oscillator Signals

clock.

Programmable to 148.3516 MHz from the Clock Control GUI.

Programmable to 296.7033 MHz from the Clock Control GUI.

User Push Buttons and LEDs

the jumper settings.

fmcb_gbtclk_m2c_p0

fmcb_dp_m2c_p2

fmcb_la_tx_p1

fmcb_dp_c2m_p0

fmcb_la_tx_p12

fmcb_la_tx_n12

fmcb_la_tx_p14

fmcb_la_tx_n14

fmcb_la_tx_p15

Nextera SDI FMC Daughter Card Pins on FMC Port B

Input 1 297 or 296.7 MHz dedicated transceiver reference clock

from FMC port B.

Input 1 SDI RX serial data from FMC port B.

Input 1 RX cable equalizer lock status on Nextera daughter card.

Output 1 SDI TX serial data from FMC port B.

Output 1 Initialize LMH1983 on Nextera daughter card.

Output 1 F sync signal LMH1983 on Nextera daughter card.

Output 1 V sync signal LMH1983 on Nextera daughter card.

Output 1 H sync signal LMH1983 on Nextera daughter card.

Output 1 Power-down signal LMH1983 on Nextera daughter card.

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Table 12. RX/TX/DU Top Signals

Signal Direction Width Description

rx_cdr_refclk

rx_core_refclk

tx_pll_refclk

tx_pll_refclk_alt

rx_rcfg_mgmt_clk

tx_rcfg_mgmt_clk

rx_vid_clkout

tx_vid_clkout

Input 1 RX transceiver reference clock. This clock must be a free-

Input 1 SDI RX core clock. This clock must be a free-running

Input 1 TX PLL reference clock. This clock must be a free-running

Input 1 Secondary TX PLL reference clock. This clock must be a

Input 1 RX reconfiguration management clock, Avalon-MM

Input 1 TX reconfiguration management clock, and Avalon-MM

Output 1 RX transceiver recovered parallel clock for video data.

Output 1 TX transceiver recovered parallel clock for video data.

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Clocks

running clock.

clock.

free-running clock.

interface clock, and PHY reset control input clock. This clock must be a free-running clock.

tx_resetn

rx_resetn

tx_rcfg_mgmt_resetn

rx_rcfg_mgmt_resetn

sdi_rx_rst_proto_out

Video Signal Interfaces (Interface with Video Image and Processing (VIP) Components)

rx_vid_data

rx_vid_datavalid

rx_vid_std

Reset

Input 1 TX core and PHY reset signal.

Input 1 RX core and PHY reset signal.

Input 1 TX reconfiguration reset signal.

Input 1 RX reconfiguration reset signal.

Output 1 Reset signal generated to reset the receiver downstream

protocol logic. This generated reset signal is synchronous to rx_vid_clkout clock domain.

Output 20*N Receiver parallel video data out.

Note: N = 4 (multi-rate design) or 1 (triple-rate design)

Output 1 Data valid signal generated from SDI RX core. The timing

must be synchronous to rx_vid_clkout and has the following settings:

• SD-SDI: 1H 4L 1H 5L

• HD/3G/6G/12G-SDI: H

Output 3 Received video standard.

• 3'b000: SD-SDI

• 3'b001: HD-SDI

• 3'b011: 3G-SDI Level A

• 3'b010 3G-SDI Level B

• 3'b101: 6G-SDI 4 Streams Interleaved

• 3'b100: 6G-SDI 8 Streams Interleaved

• 3'b111: 12G-SDI 8 Streams Interleaved

• 3'b110: 12G-SDI16 Streams Interleaved

continued...

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Video Signal Interfaces (Interface with Video Image and Processing (VIP) Components)

rx_vid_locked

rx_vid_hsync

rx_vid_vsync

rx_vid_f

rx_vid_trs

tx_vid_data

tx_vid_datavalid

tx_vid_std

tx_vid_trs

Output 1 Frame locked indicates that the IP core has spotted

Output N Horizontal blanking interval timing signal. The receiver

Output N Vertical blanking interval timing signal. The receiver

Output N Field bit timing signal. This signal indicates which video

Output N On-board SDI TX cable driver slew rate control.

Output 20*N Receiver output signal that indicates current word is

Input 1 Transmitter parallel data valid. The timing (H: High, L:

Input 3 Indicates the desired transmit video standard.

Input 1 Transmitter TRS input.

multiple frames with the same timing.

asserts this signal when the horizontal blanking interval is active.

Note: N = 4 (multi-rate design) or 1 (triple-rate design)

asserts this signal when the vertical blanking interval is active.

Note: N = 4 (multi-rate design) or 1 (triple-rate design)

field is currently active. For interfaced frame, 0 means first field (F0) while 1 means second field (F1). For progressive frame, the value is always 0.

Note: N = 4 (multi-rate design) or 1 (triple-rate design)

timing reference signal (TRS). This signal asserts at the first word of 3FF 000 000 TRS.

Note: N = 4 (multi-rate design) or 1 (triple-rate design)

Low) must be synchronous to tx_pclk clock domain and has the following settings:

• SD-SDI = 1H 4L 1H 5L

• HD-SDI = H (for single-rate) and 1H 1L (triple-rate/ multi-rate)

• 3G/6G/12G-SDI = H

• 3'b000: SD-SDI

• 3'b001: HD-SDI

• 3'b011: 3G-SDI Level A

• 3'b010 3G-SDI Level B

• 3'b101: 6G-SDI 4 Streams Interleaved

• 3'b100: 6G-SDI 8 Streams Interleaved

• 3'b111: 12G-SDI 8 Streams Interleaved

• 3'b110: 12G-SDI16 Streams Interleaved

For use in LN, CRC, or payload ID insertion. Assert on the first word of both end of active video (EAV) TRS and start of active video (SAV) TRS.

sdi_tx_enable_crc

sdi_tx_enable_ln

sdi_tx_ln

Other SDI Video Protocol Interfaces

sdi_rx_ln

sdi_rx_ln_b

sdi_rx_crc_error_c

sdi_rx_crc_error_y

sdi_rx_crc_error_c_b

sdi_rx_crc_error_y_b

sdi_rx_line_f0

sdi_rx_line_f1

sdi_rx_vpid_byte1

sdi_rx_vpid_byte2

sdi_rx_vpid_byte3

sdi_rx_vpid_byte4

sdi_rx_vpid_checksum

Output 11*N Received line number from protocol.

Output 11*N

Output N CRC error status signal from protocol.

Output N

Output 11*N Payload ID status from protocol.

Output 11*N

Output 8*N

Output N

_error

sdi_rx_vpid_valid

sdi_rx_vpid_byte1_b

sdi_rx_vpid_byte2_b

sdi_rx_vpid_byte3_b

sdi_rx_vpid_byte4_b

sdi_rx_vpid_checksum

Output N

Output 8*N

Output N

_error_b

sdi_rx_vpid_valid_b

Output N

tx_pll_refclk_sel

tx_rcfg_cal_busy

rx_rcfg_cal_busy

gxb_rx_serial_data

gxb_tx_serial_data

gxb_rx_ready

gxb_tx_ready

gxb_rx_cal_busy

gxb_tx_cal_busy

tx_pll_locked

Transceiver Interfaces

Input 1

Input 1 Transceiver calibration status to TX PHY reset controller.

Input 1 Transceiver calibration status to RX PHY reset controller

Input 1 RX transceiver serial data.

Output 1 TX transceiver serial data.

Output 1 RX transceiver status.

Output 1 TX transceiver status.

Output 1 Calibration status signal from RX transceiver.

Output 1 Calibration status signal from TX transceiver.

Output 1 TX PLL lock status.

Indicate which of pll_locked signals to be monitored for TX PHY reset controller's reset sequencing.

Always set to 1'b0 if only one PLL is in use.

and Rx reconfiguration management module.

continued...

Intel® Arria® 10 SDI II IP Core Design Example User Guide

33

tx_pll_locked_alt

cdr_reconfig_busy

tx_reconfig_busy

gxb_du_rcfg_write

gxb_du_rcfg_read

gxb_du_rcfg_address

gxb_du_rcfg_writedat a

gxb_du_rcfg_readdata

gxb_du_rcfg_waitrequ est

gxb_rx_rcfg_write

gxb_rx_rcfg_read

gxb_rx_rcfg_address

gxb_rx_rcfg_writedat a

gxb_rx_rcfg_readdata

gxb_rx_rcfg_waitrequ est

gxb_tx_rcfg_write

gxb_tx_rcfg_read

gxb_tx_rcfg_address

gxb_tx_rcfg_writedat a

gxb_tx_rcfg_readdata

gxb_tx_rcfg_waitrequ est

rx_rcfg_readdata

rx_rcfg_waitrequest

rx_rcfg_write

rx_rcfg_read

rx_rcfg_address

rx_rcfg_writedata

tx_rcfg_readdata

tx_rcfg_waitrequest

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Transceiver Interfaces

Output 1 TX PLL alt lock status.

Output 1 RX CDR reconfiguration status.

Output 1 TX PLL/transceiver reconfiguration status.

Transceiver Reconfiguration Interfaces

Input 1 Reconfiguration interface signals from transceiver arbiter

to duplex mode transceiver.

Input 1

Input 10

Input 32

Output 32

Output 1

Input 1 Reconfiguration interface signals from transceiver arbiter

to RX transceiver.

Input 1

Input 10

Input 32

Output 32

Output 1

Input 1 Reconfiguration interface signals from transceiver arbiter

to TX transceiver.

Input 1

Input 10

Input 32

Output 32

Output 1

Input 32 Reconfiguration interface signals from RX reconfiguration

management module to transceiver arbiter.

Input 1

Output 1

Output 10

Output 32

Input 32 Reconfiguration interface signals from TX reconfiguration

management module to transceiver arbiter

Input 1

continued...

Intel® Arria® 10 SDI II IP Core Design Example User Guide 34

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Transceiver Reconfiguration Interfaces

tx_rcfg_write

tx_rcfg_read

tx_rcfg_address

tx_rcfg_writedata

tx_fpll_rcfg_write

tx_fpll_rcfg_read

tx_fpll_rcfg_writeda

Output 1

Output 10

Output 32

Input 1 Reconfiguration interface signals to fPLL Avalon-MM

Input 1

Input 32

ta

tx_fpll_rcfg_address

tx_fpll_rcfg_readdat

Input 10

Output 32

a

tx_fpll_rcfg_waitreq

Output 1

uest

Table 13. Loopback Top Signals

Signal Direction Width Description

sdi_tx_clkout

sdi_rx_clkout

sdi_reclk_sysclk

Input 1 TX transceiver recovered parallel clock for video data.

Input 1 RX transceiver recovered parallel clock for video data.

Input 1 Input clock for reclock module (without external VCXO

interface.

Clocks

solution). This clock should be the same as fPLL

reconfig_clk.

sdi_rx_rst_proto

sdi_reclk_rst

sdi_rx_dataout

sdi_rx_dataout_valid

sdi_rx_std

sdi_rx_trs

sdi_rx_trs_locked

sdi_rx_frame_locked

sdi_tx_dataout_valid

Resets

Input 1 Reset signal from SDI RX core to indicate that the

protocol is currently held in reset.

Input 1 Reset signal to reclock module (without external VCXO

solution).

SDI Related Signals

Input 20*N Receiver recovered parallel video data.

Note: N = 4 (multi-rate design) or 1 (triple-rate design)

Input 1 Data valid signal generated from SDI RX core.

Input 3 Received video standard from SDI RX core.

Input N Receiver output signal from SDI II IP core that indicates

current word is TRS.

Note: N = 4 (multi-rate design) or 1 (triple-rate design)

Input N TRS locked status signal from SDI RX core.

Note: N = 4 (multi-rate design) or 1 (triple-rate design)

Input 1 Frame locked status signal from SDI RX core.

Input 1 Data valid signal generated from SDI TX core.

continued...

Intel® Arria® 10 SDI II IP Core Design Example User Guide

35

sdi_rx_h

sdi_rx_format

sdi_rx_clkout_is_nts c_paln

sdi_tx_datain

sdi_tx_datain_valid

sdi_tx_trs

sdi_tx_std

vcoclk_up

vcoclk_down

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SDI Related Signals

Input 1 Horizontal blanking interval timing signal extracted from

SDI RX core.

Input 4 Received video transport format.

Input 1 Indication from SDI RX core that the receiver is receiving

video rate at integer or fractional frame rate.

Output 20*N Parallel video data input to SDI TX core.

Note: N = 4 (multi-rate design) or 1 (triple-rate design)

Output 1 Data valid for the transmitter parallel data to SDI TX

core.

Output 1 Transmitter TRS input to indicate that the current word is

a TRS to SDI TX core.

Output 3 Indicates the desired transmit video standard to SDI TX

core.

Voltage Control Signals for On-board Si516

Output 1 Voltage up signal to Si516 to increase the voltage.

Output 1 Voltage down signal to Si516 to decrease the voltage.

fPLL Reconfiguration Signals

pll_locked

pll_reconfig_readdat

Input 1 PLL lock status signal.

Input 32 Reconfiguration interface signals to fPLL Avalon-MM

a

pll_reconfig_waitreq

Input 1

uest

pll_reconfig_write

pll_reconfig_read

pll_reconfig_writeda

Output 1

Output 32

ta

pll_reconfig_address

Output 10

Table 14. Transceiver Arbiter Signals

Signal Direction Width Description

On-board Oscillator Signals

clk

reset

rx_rcfg_en

tx_rcfg_en

rx_rcfg_ch

Input 1 Reconfiguration clock. This clock should be sharing the

Input 1 Reset signal. This reset should be sharing the same reset

Input 1 RX reconfiguration enable signal.

Input 1 TX reconfiguration enable signal.

Input 2 Indicates which channel to be reconfigured on RX.

interface.

same clock as reconfiguration management blocks.

as reconfiguration management blocks.

Always assign to 2'b00 for SDI case.

continued...

Intel® Arria® 10 SDI II IP Core Design Example User Guide 36

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Signal Direction Width Description

tx_rcfg_ch

rx_reconfig_mgmt_wri

Input 2 Indicates which channel to be reconfigured on TX.

Input 1 Reconfiguration Avalon-MM interfaces from RX

te

rx_reconfig_mgmt_rea

Input 1

d

rx_reconfig_mgmt_add

Input 10

ress

rx_reconfig_mgmt_wri

Input 32

tedata

rx_reconfig_mgmt_rea

Output 32

ddata

rx_reconfig_mgmt_wai

Output 1

trequest

tx_reconfig_mgmt_wri

Input 1 Reconfiguration Avalon-MM interfaces from TX

te

tx_reconfig_mgmt_rea

Input 1

d

tx_reconfig_mgmt_add

Input 10

ress

tx_reconfig_mgmt_wri

Input 32

tedata

tx_reconfig_mgmt_rea

Output 32

ddata

tx_reconfig_mgmt_wai

Output 1

trequest

reconfig_write

reconfig_read

reconfig_address

reconfig_writedata

rx_reconfig_readdata

rx_reconfig_waitrequ

Output 1 Reconfiguration Avalon-MM interfaces to transceiver.

Output 1

Output 10

Output 32

Input 32

Input 1

est

tx_reconfig_readdata

tx_reconfig_waitrequ

Input 1

est

rx_cal_busy

tx_cal_busy

rx_reconfig_cal_busy

tx_reconfig_cal_busy

Input 1 Calibration status signal from RX transceiver.

Input 1 Calibration status signal from TX transceiver.

Output 1 Calibration status signal to RX transceiver PHY reset

Output 1 Calibration status signal from TX transceiver PHY reset

On-board Oscillator Signals

Always assign to 2'b00 for SDI case.

reconfiguration management.

control.

Intel® Arria® 10 SDI II IP Core Design Example User Guide

37

clk

rst

bar_100_75n

enable

patho

blank

no_color

sgmt_frame

tx_std

tx_format

dl_mapping

ntsc_paln

dout

dout_valid

trs

ln

dout_b

dout_valid_b

trs_b

ln_b

vpid_byte1

vpid_byte2

vpid_byte3

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Video Pattern Generator Signals

Input 1 Clock signal. This clock must be connected to the

tx_vid_clkout input signal on TX/Du top.

Input 1 Reset signal. This reset signal should be synchronized

Input 1 Enable this signal to generate 100% color-bar pattern.

Input 1 This signal acts as a data valid signal to this module. This

Input 1 Enable this signal to generate pathological pattern.

Input 1 Enable this signal to generate blank signal.

Input 1 Enable this signal to generate bar with no color.

Input 1 Enable this signal to generate payload ID for segmented

Input 3 Indicates the desired transmit video standard. This input

Input 4 Indicates the desired transmit video format.

Input 1 Enable this signal to generate data streams with dual-

Input 1 Enable this signal to generate payload ID for fractional

Output 20*S

Output 1 Data valid output signal to be connected to the

with the tx_vid_clkout clock signal from the TX/Du top.

Disable to generate 75% color-bar pattern.

signal should be connected to the sdi_tx_datavalid signal from the TX/Du top.

frame video format when generating 1080i50 or 1080i60 video.

signal must match tx_vid_std on the TX/Du top.

link mapping.

Note: Applicable only for HD dual link or 3G Level B

dual link video standard.

frame rate video format. Disable to generate integer frame rate video format.

Data output signal to be connected to the tx_vid_data input signal on the TX/Du top.

tx_vid_datavalid input signal on the TX/Du top.

Output 1

Output 11*S Line number output signal to be connected to the

TRS output signal to be connected to the tx_vid_trs input signal on the TX/Du top.

sdi_tx_ln input signal on the TX/Du top.

Output 20*S Data output signal for link B (HD dual link).

Output 1 Data valid output signal for link B (HD dual link).

Output 1 TRS output signal for link B (HD dual link).

Output 11*S Line number output signal to be connected to the

sdi_tx_ln_b input signal on the TX/Du top.

Input 8*N The payload ID output signal to be connected to

sdi_tx_vpid_byte1 input signal on TX/Du top.

Input 8*N The payload ID output signal to be connected to

sdi_tx_vpid_byte2 input signal on TX/Du top.

Input 8*N The payload ID output signal to be connected to

sdi_tx_vpid_byte3 input signal on TX/Du top.

continued...

Intel® Arria® 10 SDI II IP Core Design Example User Guide 38

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vpid_byte4

vpid_byte1_b

vpid_byte2_b

vpid_byte3_b

vpid_byte4_b

line_f0

line_f1

avmm_clk_in_clk

tx_clkout_in_clk

avmm_clk_reset_n

pattgen_rst_reset_in

Input 8*N The payload ID output signal to be connected to

Output 11*N The line number output signal to be inserted with the

Pattern Generator Control Module Signals

Input 1 Clock signal to Avalon-MM interface.

Input 1 Clock signal to Parallel I/O (PIO) IP. This clock must

Input 1 Reset signal to Avalon-MM interface.

Input 1 Input reset signals to a reset synchronizer which

0

pattgen_rst_reset_in

Input 1

1

pattgen_rst_reset_ou

Input 1 Output reset from the reset synchronizer. This reset

t

pattgen_ctrl_pio_out

Output 12 Output control signal from PIO to control the video

_port

Video Pattern Generator Signals

sdi_tx_vpid_byte4 input signal on TX/Du top.

sdi_tx_vpid_byte1_b input signal on TX/Du top.

sdi_tx_vpid_byte2_b input signal on TX/Du top.

sdi_tx_vpid_byte3_b input signal on TX/Du top.

sdi_tx_vpid_byte4_b input signal on TX/Du top.

payload ID. This signal must connect to

sdi_tx_line_f0 input signal on TX/Du top.

payload ID. This signal must connect to

sdi_tx_line_f1 input signal on TX/Du top.

share the same clock as video pattern generator.

synchronizes the reset to the tx_clkout_in_clk clock domain.

synchronizes to the tx_clkout_in_clk clock domain and connects to the video pattern generator’s input reset.

pattern generator.

2.6 Video Pattern Generator Parameters

Customize the video pattern generator parameters according to your design.

Intel® Arria® 10 SDI II IP Core Design Example User Guide

39

Table 15. Video Pattern Generator Parameters

D3 D4 D5 D6 D7 D8 D9 D10

Parameter Valid Value Default Value Description

OUTW_MULTP

SD_BIT_WIDTH

TEST_GEN_ANC

TEST_GEN_VPID

1, 4 1 Defines the width of the output portsh. Select 4

10, 20 10 Defines the generated SD interface bit width.

0, 1 0 Select 1 to generate the ancillary data packet in

0, 1 0 Select 1 to generate the payload ID packet in

2.7 Hardware Setup

To run the hardware test for parallel loopback designs, connect an SDI video generator to the receiver input pin.

• Connect an external video analyzer to the TX instance to verify full functionality.

• To validate if the RX core locks to the signal and receives the video data correctly, use the on-board LEDs that display the RX status.

2 SDI II Design Example Detailed Description

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for a multi-rate design, otherwise select 1.

This value must match with the SD interface bit width parameter of the SDI II TX core in the same design.

output stream. The module inserts the embedded Data ID (DID) packet with 10’h242 if

TEST_GEN_VPID is not enabled.

output streams. The module inserts the embedded Data ID (DID) packet with 10’h241.

To run the hardware test for serial loopback designs, connect the transmitter output pin directly to the receiver input pin.

• To validate if the RX core locks to the signal and receives the video data correctly, use the on-board LEDs that display the RX status.

• You may also connect an SDI signal analyzer to the transmitter output pin to view the generated image.

Figure 16. Arria 10 GX Development Board User LEDs

Table 16. On-board User LED Functions

LEDs Function

D3–D5 Indicates the receiver video standard:

• 000: SD-SDI

• 001: HD-SDI

• 010: 3G Level B

• 011: 3G Level A

• 100: 6G 8 Streams Interleaved

continued...

Intel® Arria® 10 SDI II IP Core Design Example User Guide 40

Top

RX Top

SDI II

RX

Transceiver

PHY Reset

Controller (RX)

Transceiver Native PHY

(RX)

RX

Reconfiguration

Management (1)

Transceiver Arbiter

(1), (2)

SDI RX System

TX Top

SDI II

TX

Transceiver

PHY Reset

Controller (TX)

Transceiver

Native PHY

(TX)

SDI TX System

TX

PLL

Alt (2)

Testbench Control

Parallel Data Serial Data

Control/Status Avalon-MM

Video Pattern

Generator

(1) (2)

(1)

TX

PLL

TX Reconfiguration

Management

(2), (3)

(2)

(3)

(1) Block/Connection only required for triple-rate/multi-rate designs. (2) Block/Connection only required for TX PLL switching designs. (3) Block/Connection only required for TX PLL reference clock switching designs.

TX Checker

RX Checker

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LEDs Function

• 101: 6G 4 Streams Interleaved

• 110: 12G 16 Streams Interleaved

• 111: 12G 8 Streams Interleaved

D6 Shows the slower version of the TX transceiver parallel clock

D7 Shows the slower version of the RX transceiver parallel clock

D8

D9

D10

Illuminates when align_locked asserts

Illuminates when trs_locked asserts

Illuminates when frame_locked asserts

2.8 Simulation Testbench

The simulation testbench checks for the assertion of the trs_locked signal. The testbench also detects the number of transceiver reconfiguration triggered after every video standard switching.

Figure 17. Simplex Mode Simulation Testbench Block Diagram

Intel® Arria® 10 SDI II IP Core Design Example User Guide

41

Top

Duplex Top

SDI II

Duplex

Transceiver

PHY Reset

Controller (RX)

Transceiver

Native PHY

(Duplex)

RX

Reconfiguration

Management (1)

Transceiver Arbiter

(1), (2)

SDI Duplex System

Parallel Data Serial Data

Control/Status Avalon-MM

Transceiver

PHY Reset

Controller (TX)

TX

PLL

Alt (2)

TX

PLL

TX Reconfiguration

Management

(2), (3)

(2)

(3)

(1) Block/Connection only required for triple-rate/multi-rate designs. (2) Block/Connection only required for TX PLL switching designs. (3) Block/Connection only required for TX PLL reference clock switching designs

Testbench Control

Video Pattern

Generator

TX Checker

RX Checker

(1), (2)

2 SDI II Design Example Detailed Description

Figure 18. Duplex Mode Simulation Testbench Block Diagram

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Table 17. Testbench Components

Testbench Control This block controls the test sequence of the simulation and generates the

RX Checker

TX Checker This checker verifies if the TX serial data contains a valid TRS signal.

Component Description

necessary stimulus signals to the TX and video pattern generator blocks.

This checker detects the trs_locked signal from the RX protocol and compares the actual number of transceiver reconfigurations performed versus the expected number.

Intel® Arria® 10 SDI II IP Core Design Example User Guide 42

3G

Level A

HD

3G

Level B

SD HD SD

3G

Level A

Triple-Rate Designs

12G 8 Streams

Interleaved

6G 8 Streams

Interleaved

HD SD

Multi-Rate Designs

3G

Level A

3’h3 3’h1 3’h2 3’h0 3’h1 3’h0

4’h1 4’h14’h14’h14’h1 4’h0 4’h0

2’h1 2’h12’h12’h0

2’h0

rx_std

align_locked

trs_locked

reconfig_count

expected_rcfgcount

Video standard keeps switching after obtaining lock signal

trs_locked from IP core

The actual number of transceiver reconfigurations triggered after every video standard vs. the expected number of reconfigurations

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Figure 19. Sequence of Video Standards for Triple-Rate and Multi-Rate Designs

For single-rate designs, only one video standard is tested:

• HD-SDI single-rate—HD

• 3G-SDI single-rate—3G Level A

If you turn on the Dynamic Tx Clock Switching parameter, only one video standard is being tested with 2 different TX PHY reference clocks to demonstrate the switching:

• HD-SDI single-rate—HD

• 3G-SDI single-rate/triple-rate—3G Level A

• Multi-rate—12G 8 streams interleaved

Figure 20. Simulation Waveform

A successful simulation ends with the following message:

#### TRANSMIT TEST COMPLETED SUCCESSFULLY! #### # #### Channel 1: RECEIVE TEST COMPLETED SUCCESSFULLY! ####

Intel® Arria® 10 SDI II IP Core Design Example User Guide

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A SDI II IP Core Design Example User Guide Archives

If an IP core version is not listed, the user guide for the previous IP core version applies.

IP Core Version User Guide

16.1 SDI II IP Core Design Example User Guide

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

ISO 9001:2008 Registered

UG-20076 | 2017.05.08

B Revision History for SDI II IP Core Design Example User Guide

Date Version Changes

May 2017 2017.05.08 • Rebranded as Intel.

• Changed the part number.

• Updated information about the parallel design examples and added new information about the serial design example.

• Added files designated for Quartus Prime Pro Edition.

• Added information about video pattern generator interface signals and parameters.

• Added link to archived version of the Arria 10 SDI II IP Core Design Example User Guide.

October 2016 2016.10.31 Initial release.

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Intel Arria 10 SDI II User Manual

Specifications and Main Features

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