Intel AN 860 User Manual
AN 860: Using Intel® Arria® 10 SoC
FPGA Early I/O Release
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AN-860 | 2020.10.22
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Contents
Contents
1. Introduction................................................................................................................... 3
1.1. Early I/O Release Use Cases....................................................................................3
1.2. Early I/O Release Flow........................................................................................... 5
2. Design Restrictions......................................................................................................... 6
2.1. Peripheral and Core RBF are a Matched Pair.............................................................. 6
2.2. EMIF Pin Usage Restrictions.................................................................................... 6
3. Enabling I/O Release...................................................................................................... 8
3.1. Intel Quartus Prime Project Settings.........................................................................8
Follow the steps below.........................................................................................8
3.2. Platform Designer Component Settings.....................................................................9
3.3. Creating Split RBF Images...................................................................................... 9
3.4. Configuring U-Boot to use Split RBF Files................................................................ 10
4. Debugging Early I/O Release........................................................................................ 12
A. Document Revision History for Using Intel Arria 10 SoC FPGA Early I/O Release......... 13
AN 860: Using Intel® Arria® 10 SoC FPGA Early I/O Release
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Full Configuration Sequence
User code running on HPS has “early” access to
external RAM and peripherals connected to Shared I/O
FPGA Fabric ConfigurationPart 1
I/O and HPS EMIF Configuration
AN-860 | 2020.10.22
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1. Introduction
The Intel® Arria® 10 SoC FPGA device supports Early I/O Release. This feature splits
the FPGA configuration sequence into two parts. The first part configures the FPGA
I/O, the Shared I/O and enables the HPS External Memory Interface (EMIF) if present.
The second part of the sequence configures the FPGA fabric.
Splitting the configuration sequence provides HPS access to Shared I/O and EMIF
before the FPGA fabric is configured. This allows more flexibility for designs that need
faster boot times or alternate boot sources.
Enabling Early I/O Release in an Intel Arria 10 SoC FPGA design is optional and adds
some pin and usage restrictions. Instructions for enabling and debugging the Early I/O
Release feature and usage restrictions are provided in this document.
1.1. Early I/O Release Use Cases
There are a few different reasons why you might choose to enable the Early I/O
Release feature of the Intel Arria 10 SoC FPGA device. The typical reason is to speed
up system boot and configuration time. By gaining early access to a large pool of
system RAM connected the HPS EMIF interface, the boot software can more efficiently
load the bulk of the FPGA configuration image from mass storage. Restricting boot
code to on-chip RAM typically impedes bulk transfers because of the limited code and
buffer space.
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Figure 1. Early I/O Release
BOOT LOADER
BOOT LOADER
Configure I/O and
External RAM Controller
Configure FPGA Fabric
Full Configuration Sequence
OPERATING SYSTEM BOOT
OPERATING SYSTEM BOOT
Boot OS Earlier
FPGA Fabric Configuration
Part 1
I/O and HPS EMIF Configuration
EXTERNAL STORAGE
EXTERNAL STORAGE
REMOTE STORAGE
HPS
DEDICATED I/O
HPS FPGA
SHARED I/O
HPS
DEDICATED I/O
UBOOT
HPS
FPGA
HPS
FPGA
Smaller External Storage
Secondary Storage
RAM
FULL
FPGA
CONFIG
DATA
(I/O +
CORE)
UBOOT
I/O
CONFIG
DATA
FPGA
CORE
CONFIG
DATA
ENET
1. Introduction
AN-860 | 2020.10.22
Figure 2. Early I/O Release allows FPGA fabric image to be accessed through a Shared
AN 860: Using Intel® Arria® 10 SoC FPGA Early I/O Release
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Some designers might want to boot the HPS operating system (OS) immediately. This
action can be accomplished by postponing FPGA fabric configuration until the OS has
booted. Booting the OS quickly is achieved by using the boot loader to only configure
the FPGA I/O, Shared I/O and external memory before FPGA fabric is configured, then
allowing the OS to boot and configure the FPGA fabric.
I/O Interface
Another reason to enable the Early I/O Release feature is to gain boot software access
to an interface connected to Shared I/O, such as a secondary mass storage device or
network connection. This secondary access allows the primary storage connected to
the HPS dedicated I/O pins to be smaller and possibly even write protected.
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